STM8S/A Standard Peripherals Drivers: STM8S/A Standard Peripherals Library

STM8S/A Standard Peripherals Drivers
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STM8S/A Standard Peripherals Library

STM8S/A Standard Peripherals Drivers

Copyright 2011 STMicroelectronics

The STM8S/A Standard Peripheral Drivers package, consists of device drivers for all of the standard device peripherals, for the STM8S/A 8-bit Flash microcontrollers.

These drivers contain a collection of routines, data structures and macros covering the features of STM8S/A peripherals. They allow any device to be used in the user application without the need for in-depth study of each peripheral’s specifications.

Using the Standard Peripherals drivers has two advantages: it saves significant time that would otherwise be spent in coding, while simultaneously reduces application development and integration costs.

The manual is structured as follows:

Standard Peripheral Drivers

Overview

MISRA-C 2004 Compliance

Run-time Checking

Coding rules and conventions

Acronyms

Naming conventions

Coding rules

Description of Peripherals drivers

Architecture

STM8S/A Standard Peripheral's Drivers

Supported STM8S/A devices and toolchains

Manual tab sheets description:

Modules: Lists the different modules that compose this Library.

Data Structures: Lists the variables, defines, structures, ...

Files: Lists all the files and global.

Directories: List of directories.

Release Notes for STM8S/A Standard Peripherals Drivers

License

The enclosed firmware and all the related documentation are not covered by a License Agreement, if you need such License you can contact your local STMicroelectronics office.

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

STM8 Standard Peripherals Library: Footer

For complete documentation on STM8 8-bit Microcontrollers platform visit www.st.com


STM8S/A Standard Peripherals Drivers: STM8S/A Standard Peripheral's Drivers

  • Modules
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  • Files
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STM8S/A Standard Peripheral's Drivers

src

  • stm8s_adc1.c
  • stm8s_adc2.c
  • stm8s_awu.c
  • stm8s_beep.c
  • stm8s_can.c
  • stm8s_clk.c
  • stm8s_exti.c
  • stm8s_flash.c
  • stm8s_gpio.c
  • stm8s_i2c.c
  • stm8s_itc.c
  • stm8s_iwdg.c
  • stm8s_rst.c
  • stm8s_spi.c
  • stm8s_tim1.c
  • stm8s_tim2.c
  • stm8s_tim3.c
  • stm8s_tim4.c
  • stm8s_tim5.c
  • stm8s_tim6.c
  • stm8s_uart1.c
  • stm8s_uart2.c
  • stm8s_uart3.c
  • stm8s_wwdg.c

inc

  • stm8s.h
  • stm8s_adc1.h
  • stm8s_adc2.h
  • stm8s_awu.h
  • stm8s_beep.h
  • stm8s_can.h
  • stm8s_clk.h
  • stm8s_exti.h
  • stm8s_flash.h
  • stm8s_gpio.h
  • stm8s_i2c.h
  • stm8s_itc.h
  • stm8s_iwdg.h
  • stm8s_rst.h
  • stm8s_spi.h
  • stm8s_tim1.h
  • stm8s_tim2.h
  • stm8s_tim3.h
  • stm8s_tim4.h
  • stm8s_tim5.h
  • stm8s_tim6.h
  • stm8s_uart1.h
  • stm8s_uart3.h
  • stm8s_uart2.h
  • stm8s_wwdg.h


STM8S/A Standard Peripherals Drivers: I2C_Private_Defines

  • Directories
Defines

I2C_Private_Defines

STM8S_StdPeriph_Driver

Defines

#define | FLAG_Mask ((uint16_t)0x00FF)
#define | ITEN_Mask ((uint16_t)0x0700)
#define | REGISTER_Mask ((uint16_t)0x3000)
#define | REGISTER_SR1_Index ((uint16_t)0x0100)
#define | REGISTER_SR2_Index ((uint16_t)0x0200)

Define Documentation

#define FLAG_Mask ((uint16_t)0x00FF)

Definition at line 40 of file stm8s_i2c.c.

Referenced by I2C_ClearFlag(), and I2C_ClearITPendingBit().

#define ITEN_Mask ((uint16_t)0x0700)

Definition at line 38 of file stm8s_i2c.c.

Referenced by I2C_GetITStatus().

#define REGISTER_Mask ((uint16_t)0x3000)

Definition at line 34 of file stm8s_i2c.c.

Referenced by I2C_GetITStatus().

#define REGISTER_SR1_Index ((uint16_t)0x0100)

Definition at line 35 of file stm8s_i2c.c.

Referenced by I2C_GetITStatus().

#define REGISTER_SR2_Index ((uint16_t)0x0200)

Definition at line 36 of file stm8s_i2c.c.


STM8S/A Standard Peripherals Drivers: Exported_types

Defines | Typedefs | Enumerations

Exported_types

STM8S_StdPeriph_Driver

Defines

#define | __I volatile const
IO definitions.
#define | __IO volatile
#define | __O volatile
#define | IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define | S16_MAX (32767)
#define | S16_MIN (-32768)
#define | S32_MAX (2147483647)
#define | S32_MIN (-2147483648uL)
#define | S8_MAX (127)
#define | S8_MIN (-128)
#define | U16_MAX (65535u)
#define | U32_MAX (4294967295uL)
#define | U8_MAX (255)

Typedefs

typedef enum FlagStatus | BitAction
typedef enum FlagStatus | BitStatus
typedef signed short | int16_t
typedef signed long | int32_t
typedef signed char | int8_t
typedef enum FlagStatus | ITStatus
typedef int16_t | s16
typedef int32_t | s32
typedef int8_t | s8
typedef uint16_t | u16
typedef uint32_t | u32
typedef uint8_t | u8
typedef unsigned short | uint16_t
typedef unsigned long | uint32_t
typedef unsigned char | uint8_t

Enumerations

enum | bool { FALSE = 0, TRUE = !FALSE }
enum | ErrorStatus { ERROR = 0, SUCCESS = !ERROR }
enum | FlagStatus { RESET = 0, SET = !RESET }
enum | FunctionalState { DISABLE = 0, ENABLE = !DISABLE }

Define Documentation

#define __I volatile const

IO definitions.

define access restrictions to peripheral registers defines 'read only' permissions

Definition at line 194 of file stm8s.h.

#define __IO volatile

defines 'read / write' permissions Signed integer types

Definition at line 196 of file stm8s.h.

Referenced by I2C_CheckEvent(), I2C_GetITStatus(), and I2C_GetLastEvent().

#define __O volatile

defines 'write only' permissions

Definition at line 195 of file stm8s.h.

#define IS_FUNCTIONALSTATE_OK ( STATE ) (((STATE) == DISABLE) || ((STATE) == ENABLE))

Definition at line 224 of file stm8s.h.

Referenced by ADC1_AWDChannelConfig(), ADC1_Cmd(), ADC1_DataBufferCmd(), ADC1_ExternalTriggerConfig(), ADC1_Init(), ADC1_ITConfig(), ADC1_ScanModeCmd(), ADC1_SchmittTriggerConfig(), ADC2_Cmd(), ADC2_ExternalTriggerConfig(), ADC2_Init(), ADC2_ITConfig(), ADC2_SchmittTriggerConfig(), CAN_FilterInit(), CAN_ITConfig(), CAN_TTComModeCmd(), CLK_CCOCmd(), CLK_ClockSwitchCmd(), CLK_ClockSwitchConfig(), CLK_FastHaltWakeUpCmd(), CLK_HSECmd(), CLK_HSICmd(), CLK_ITConfig(), CLK_LSICmd(), CLK_PeripheralClockConfig(), CLK_SlowActiveHaltWakeUpCmd(), FLASH_ITConfig(), GPIO_ExternalPullUpConfig(), I2C_Cmd(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_ITConfig(), I2C_SoftwareResetCmd(), I2C_StretchClockCmd(), SPI_CalculateCRCCmd(), SPI_Cmd(), SPI_ITConfig(), SPI_NSSInternalSoftwareCmd(), TIM1_ARRPreloadConfig(), TIM1_CCPreloadControl(), TIM1_CCxCmd(), TIM1_CCxNCmd(), TIM1_Cmd(), TIM1_CtrlPWMOutputs(), TIM1_ITConfig(), TIM1_OC1FastConfig(), TIM1_OC1PreloadConfig(), TIM1_OC2FastConfig(), TIM1_OC2PreloadConfig(), TIM1_OC3FastConfig(), TIM1_OC3PreloadConfig(), TIM1_OC4FastConfig(), TIM1_OC4PreloadConfig(), TIM1_SelectCOM(), TIM1_SelectHallSensor(), TIM1_SelectMasterSlaveMode(), TIM1_UpdateDisableConfig(), TIM2_ARRPreloadConfig(), TIM2_CCxCmd(), TIM2_Cmd(), TIM2_ITConfig(), TIM2_OC1PreloadConfig(), TIM2_OC2PreloadConfig(), TIM2_OC3PreloadConfig(), TIM2_UpdateDisableConfig(), TIM3_ARRPreloadConfig(), TIM3_CCxCmd(), TIM3_Cmd(), TIM3_ITConfig(), TIM3_OC1PreloadConfig(), TIM3_OC2PreloadConfig(), TIM3_UpdateDisableConfig(), TIM4_ARRPreloadConfig(), TIM4_Cmd(), TIM4_ITConfig(), TIM4_UpdateDisableConfig(), TIM5_ARRPreloadConfig(), TIM5_CCxCmd(), TIM5_Cmd(), TIM5_ITConfig(), TIM5_OC1PreloadConfig(), TIM5_OC2PreloadConfig(), TIM5_OC3PreloadConfig(), TIM5_UpdateDisableConfig(), TIM6_ARRPreloadConfig(), TIM6_Cmd(), TIM6_ITConfig(), TIM6_SelectMasterSlaveMode(), TIM6_UpdateDisableConfig(), UART1_HalfDuplexCmd(), UART1_IrDACmd(), UART1_ITConfig(), UART1_LINCmd(), UART1_ReceiverWakeUpCmd(), UART1_SmartCardCmd(), UART1_SmartCardNACKCmd(), UART2_IrDACmd(), UART2_ITConfig(), UART2_LINCmd(), UART2_ReceiverWakeUpCmd(), UART2_SmartCardCmd(), UART2_SmartCardNACKCmd(), UART3_ITConfig(), UART3_LINCmd(), and UART3_ReceiverWakeUpCmd().

#define S16_MAX (32767)

Definition at line 232 of file stm8s.h.

#define S16_MIN (-32768)

Definition at line 233 of file stm8s.h.

#define S32_MAX (2147483647)

Definition at line 235 of file stm8s.h.

#define S32_MIN (-2147483648uL)

Definition at line 236 of file stm8s.h.

#define S8_MAX (127)

Definition at line 229 of file stm8s.h.

#define S8_MIN (-128)

Definition at line 230 of file stm8s.h.

#define U16_MAX (65535u)

Definition at line 231 of file stm8s.h.

#define U32_MAX (4294967295uL)

Definition at line 234 of file stm8s.h.

#define U8_MAX (255)

Definition at line 228 of file stm8s.h.

Typedef Documentation

typedef enum FlagStatus BitAction
typedef enum FlagStatus BitStatus
typedef signed short int16_t

Definition at line 200 of file stm8s.h.

typedef signed long int32_t

Unsigned integer types

Definition at line 203 of file stm8s.h.

typedef signed char int8_t

Definition at line 199 of file stm8s.h.

typedef enum FlagStatus ITStatus
typedef int16_t s16

Definition at line 211 of file stm8s.h.

typedef int32_t s32

Definition at line 210 of file stm8s.h.

typedef int8_t s8

Definition at line 212 of file stm8s.h.

typedef uint16_t u16

Definition at line 215 of file stm8s.h.

typedef uint32_t u32

Definition at line 214 of file stm8s.h.

typedef uint8_t u8

Definition at line 216 of file stm8s.h.

typedef unsigned short uint16_t

Definition at line 205 of file stm8s.h.

typedef unsigned long uint32_t

STM8 Standard Peripheral Library old types (maintained for legacy purpose)

Definition at line 208 of file stm8s.h.

typedef unsigned char uint8_t

Definition at line 204 of file stm8s.h.

Enumeration Type Documentation

enum bool
Enumerator:
FALSE
TRUE

Definition at line 219 of file stm8s.h.

enum ErrorStatus
Enumerator:
ERROR
SUCCESS

Definition at line 226 of file stm8s.h.

enum FlagStatus
Enumerator:
RESET
SET

Definition at line 221 of file stm8s.h.

enum FunctionalState
Enumerator:
DISABLE
ENABLE

Definition at line 223 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: GPIO_Registers_Reset_Value

Defines

GPIO_Registers_Reset_Value

MAP_FILE_Exported_Types_and_Constants

Defines

#define | GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_ODR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 269 of file stm8s.h.

Referenced by GPIO_DeInit().

#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 270 of file stm8s.h.

Referenced by GPIO_DeInit().

#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)

Definition at line 268 of file stm8s.h.

Referenced by GPIO_DeInit().

#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)

Definition at line 267 of file stm8s.h.

Referenced by GPIO_DeInit().


STM8S/A Standard Peripherals Drivers: MAP_FILE_Exported_Types_and_Constants

Data Structures | Modules | Typedefs

MAP_FILE_Exported_Types_and_Constants

STM8S_StdPeriph_Driver

Data Structures

struct | GPIO_struct
General Purpose I/Os (GPIO) More...

Modules

GPIO_Registers_Reset_Value

Typedefs

typedef struct GPIO_struct | GPIO_TypeDef
General Purpose I/Os (GPIO)

Typedef Documentation

typedef struct GPIO_struct GPIO_TypeDef

General Purpose I/Os (GPIO)


STM8S/A Standard Peripherals Drivers: GPIO_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

GPIO_struct Struct Reference
MAP_FILE_Exported_Types_and_Constants

General Purpose I/Os (GPIO) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | DDR
__IO uint8_t | IDR
__IO uint8_t | ODR

Detailed Description

General Purpose I/Os (GPIO)

Definition at line 253 of file stm8s.h.

Field Documentation

__IO uint8_t GPIO_struct::CR1

Configuration Register 1

Definition at line 258 of file stm8s.h.

Referenced by GPIO_DeInit(), GPIO_ExternalPullUpConfig(), and GPIO_Init().

__IO uint8_t GPIO_struct::CR2

Configuration Register 2

Definition at line 259 of file stm8s.h.

Referenced by GPIO_DeInit(), and GPIO_Init().

__IO uint8_t GPIO_struct::DDR

Data Direction Register

Definition at line 257 of file stm8s.h.

Referenced by GPIO_DeInit(), and GPIO_Init().

__IO uint8_t GPIO_struct::IDR

Input Data Register

Definition at line 256 of file stm8s.h.

Referenced by GPIO_ReadInputData(), and GPIO_ReadInputPin().

__IO uint8_t GPIO_struct::ODR

Output Data Register

Definition at line 255 of file stm8s.h.

Referenced by GPIO_DeInit(), GPIO_Init(), GPIO_ReadOutputData(), GPIO_Write(), GPIO_WriteHigh(), GPIO_WriteLow(), and GPIO_WriteReverse().

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: IWDG_Private_Define

Defines

IWDG_Private_Define

STM8S_StdPeriph_Driver

Defines

#define | IWDG_KEY_ENABLE ((uint8_t)0xCC)
Define used to start the watchdog counter down.
#define | IWDG_KEY_REFRESH ((uint8_t)0xAA)
Define used to prevent watchdog reset.

Define Documentation

#define IWDG_KEY_ENABLE ((uint8_t)0xCC)

Define used to start the watchdog counter down.

This value written in the Key register start the watchdog counting down

Definition at line 45 of file stm8s_iwdg.h.

Referenced by IWDG_Enable().

#define IWDG_KEY_REFRESH ((uint8_t)0xAA)

Define used to prevent watchdog reset.

This value written in the Key register prevent the watchdog reset

Definition at line 40 of file stm8s_iwdg.h.

Referenced by IWDG_ReloadCounter().


STM8S/A Standard Peripherals Drivers: IWDG_Private_Macros

Defines

IWDG_Private_Macros

STM8S_StdPeriph_Driver

Defines

#define | IS_IWDG_PRESCALER_OK(VALUE)
Macro used by the assert function in order to check the different values of the prescaler.
#define | IS_IWDG_WRITEACCESS_MODE_OK(MODE) (((MODE) == IWDG_WriteAccess_Enable) || ((MODE) == IWDG_WriteAccess_Disable))
Macro used by the assert function in order to check the different values of the counter register.

Define Documentation

#define IS_IWDG_PRESCALER_OK ( VALUE )
Value:
(((VALUE) == IWDG_Prescaler_4   ) || \
                                     ((VALUE) == IWDG_Prescaler_8   ) || \
                                     ((VALUE) == IWDG_Prescaler_16  ) || \
                                     ((VALUE) == IWDG_Prescaler_32  ) || \
                                     ((VALUE) == IWDG_Prescaler_64  ) || \
                                     ((VALUE) == IWDG_Prescaler_128 ) || \
                                     ((VALUE) == IWDG_Prescaler_256))

Macro used by the assert function in order to check the different values of the prescaler.

Definition at line 59 of file stm8s_iwdg.h.

Referenced by IWDG_SetPrescaler().

#define IS_IWDG_WRITEACCESS_MODE_OK ( MODE ) (((MODE) == IWDG_WriteAccess_Enable) || ((MODE) == IWDG_WriteAccess_Disable))

Macro used by the assert function in order to check the different values of the counter register.

Definition at line 71 of file stm8s_iwdg.h.

Referenced by IWDG_WriteAccessCmd().


STM8S/A Standard Peripherals Drivers: IWDG_Exported_Types

Enumerations

IWDG_Exported_Types

STM8S_StdPeriph_Driver

Enumerations

enum IWDG_Prescaler_TypeDef {
IWDG_Prescaler_4 = (uint8_t)0x00, IWDG_Prescaler_8 = (uint8_t)0x01, IWDG_Prescaler_16 = (uint8_t)0x02, IWDG_Prescaler_32 = (uint8_t)0x03,
IWDG_Prescaler_64 = (uint8_t)0x04, IWDG_Prescaler_128 = (uint8_t)0x05, IWDG_Prescaler_256 = (uint8_t)0x06
}

IWDG prescaler enumaration.

More...
enum IWDG_WriteAccess_TypeDef { IWDG_WriteAccess_Enable = (uint8_t)0x55, IWDG_WriteAccess_Disable = (uint8_t)0x00 }

IWDG write acces enumeration.

More...

Enumeration Type Documentation

enum IWDG_Prescaler_TypeDef

IWDG prescaler enumaration.

Enumerator:
IWDG_Prescaler_4

Used to set prescaler register to 4

IWDG_Prescaler_8

Used to set prescaler register to 8

IWDG_Prescaler_16

Used to set prescaler register to 16

IWDG_Prescaler_32

Used to set prescaler register to 32

IWDG_Prescaler_64

Used to set prescaler register to 64

IWDG_Prescaler_128

Used to set prescaler register to 128

IWDG_Prescaler_256

Used to set prescaler register to 256

Definition at line 89 of file stm8s_iwdg.h.

enum IWDG_WriteAccess_TypeDef

IWDG write acces enumeration.

Enumerator:
IWDG_WriteAccess_Enable

Code 0x55 in Key register, allow write access to Prescaler and Reload registers

IWDG_WriteAccess_Disable

Code 0x00 in Key register, not allow write access to Prescaler and Reload registers

Definition at line 82 of file stm8s_iwdg.h.


STM8S/A Standard Peripherals Drivers: IWDG_Exported_Functions

Functions

IWDG_Exported_Functions

STM8S_StdPeriph_Driver

Functions

void | IWDG_Enable (void)
Enables IWDG.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter.
void | IWDG_SetPrescaler (IWDG_Prescaler_TypeDef IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint8_t IWDG_Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
Enables or disables write access to Prescaler and Reload registers.

Function Documentation

void IWDG_Enable ( void )

Enables IWDG.

Parameters:
None
Return values:
None

Definition at line 93 of file stm8s_iwdg.c.

References IWDG, and IWDG_KEY_ENABLE.

void IWDG_ReloadCounter ( void )

Reloads IWDG counter.

Note:
Write access should be enabled
Parameters:
None
Return values:
None

Definition at line 83 of file stm8s_iwdg.c.

References IWDG, and IWDG_KEY_REFRESH.

void IWDG_SetPrescaler ( IWDG_Prescaler_TypeDef IWDG_Prescaler )

Sets IWDG Prescaler value.

Note:
Write access should be enabled
Parameters:
IWDG_Prescaler : Specifies the IWDG Prescaler value. This parameter can be a value of IWDG_Prescaler_TypeDef.
Return values:
None

Definition at line 57 of file stm8s_iwdg.c.

References IS_IWDG_PRESCALER_OK, and IWDG.

void IWDG_SetReload ( uint8_t IWDG_Reload )

Sets IWDG Reload value.

Note:
Write access should be enabled
Parameters:
IWDG_Reload : Reload register value. This parameter must be a number between 0 and 0xFF.
Return values:
None

Definition at line 72 of file stm8s_iwdg.c.

References IWDG.

void IWDG_WriteAccessCmd ( IWDG_WriteAccess_TypeDef IWDG_WriteAccess )

Enables or disables write access to Prescaler and Reload registers.

Parameters:
IWDG_WriteAccess : New state of write access to Prescaler and Reload registers. This parameter can be a value of IWDG_WriteAccess_TypeDef.
Return values:
None

Definition at line 42 of file stm8s_iwdg.c.

References IS_IWDG_WRITEACCESS_MODE_OK, and IWDG.


STM8S/A Standard Peripherals Drivers: RST_Exported_Types

Enumerations

RST_Exported_Types

STM8S_StdPeriph_Driver

Enumerations

enum RST_Flag_TypeDef {
RST_FLAG_EMCF = (uint8_t)0x10, RST_FLAG_SWIMF = (uint8_t)0x08, RST_FLAG_ILLOPF = (uint8_t)0x04, RST_FLAG_IWDGF = (uint8_t)0x02,
RST_FLAG_WWDGF = (uint8_t)0x01
}

Enumeration Type Documentation

enum RST_Flag_TypeDef
Enumerator:
RST_FLAG_EMCF

EMC reset flag

RST_FLAG_SWIMF

SWIM reset flag

RST_FLAG_ILLOPF

Illigal opcode reset flag

RST_FLAG_IWDGF

Independent watchdog reset flag

RST_FLAG_WWDGF

Window watchdog reset flag

Definition at line 35 of file stm8s_rst.h.


STM8S/A Standard Peripherals Drivers: RST_Private_Macros

Defines

RST_Private_Macros

STM8S_StdPeriph_Driver

Defines

#define IS_RST_FLAG_OK(FLAG)
Macro used by the assert function to check the different functions parameters.

Define Documentation

#define IS_RST_FLAG_OK ( FLAG )
Value:
(((FLAG) == RST_FLAG_EMCF) || \
                              ((FLAG) == RST_FLAG_SWIMF)  ||\
                              ((FLAG) == RST_FLAG_ILLOPF) ||\
                              ((FLAG) == RST_FLAG_IWDGF)  ||\
                              ((FLAG) == RST_FLAG_WWDGF))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert function to check the different RST flags.

Definition at line 60 of file stm8s_rst.h.

Referenced by RST_ClearFlag(), and RST_GetFlagStatus().


STM8S/A Standard Peripherals Drivers: RST_Exported_functions

Functions

RST_Exported_functions

STM8S_StdPeriph_Driver

Functions

void | RST_ClearFlag (RST_Flag_TypeDef RST_Flag)
Clears the specified RST flag.
FlagStatus | RST_GetFlagStatus (RST_Flag_TypeDef RST_Flag)
Checks whether the specified RST flag is set or not.

Function Documentation

void RST_ClearFlag ( RST_Flag_TypeDef RST_Flag )

Clears the specified RST flag.

Parameters:
RST_Flag : specify the reset flag to clear. This parameter can be a value of RST_FLAG_TypeDef.
Return values:
None

Definition at line 64 of file stm8s_rst.c.

References IS_RST_FLAG_OK, and RST.

FlagStatus RST_GetFlagStatus ( RST_Flag_TypeDef RST_Flag )

Checks whether the specified RST flag is set or not.

Parameters:
RST_Flag : specify the reset flag to check. This parameter can be a value of RST_FLAG_TypeDef.
Return values:
FlagStatus,: status of the given RST flag.

Definition at line 48 of file stm8s_rst.c.

References IS_RST_FLAG_OK, and RST.


STM8S/A Standard Peripherals Drivers: SPI_Exported_Types

Enumerations

SPI_Exported_Types

STM8S_StdPeriph_Driver

Enumerations

enum SPI_BaudRatePrescaler_TypeDef {
SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x00, SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x08, SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x10, SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x18,
SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x20, SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x28, SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x30, SPI_BAUDRATEPRESCALER_256 = (uint8_t)0x38
}

SPI BaudRate Prescaler Warning: element values correspond to BR bits position.

More...
enum | SPI_ClockPhase_TypeDef { SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, SPI_CLOCKPHASE_2EDGE = (uint8_t)0x01 }

SPI Clock Phase Warning: element values correspond to CPHA bit position.

More...
enum | SPI_ClockPolarity_TypeDef { SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x02 }

SPI Clock Polarity Warning: element values correspond to CPOL bit position.

More...
enum | SPI_CRC_TypeDef { SPI_CRC_RX = (uint8_t)0x00, SPI_CRC_TX = (uint8_t)0x01 }

SPI CRC Transmit/Receive.

More...
enum | SPI_DataDirection_TypeDef { SPI_DATADIRECTION_2LINES_FULLDUPLEX = (uint8_t)0x00, SPI_DATADIRECTION_2LINES_RXONLY = (uint8_t)0x04, SPI_DATADIRECTION_1LINE_RX = (uint8_t)0x80, SPI_DATADIRECTION_1LINE_TX = (uint8_t)0xC0 }

SPI data direction mode Warning: element values correspond to BDM, BDOE, RXONLY bits position.

More...
enum | SPI_Direction_TypeDef { SPI_DIRECTION_RX = (uint8_t)0x00, SPI_DIRECTION_TX = (uint8_t)0x01 }

SPI direction transmit/receive.

More...
enum | SPI_FirstBit_TypeDef { SPI_FIRSTBIT_MSB = (uint8_t)0x00, SPI_FIRSTBIT_LSB = (uint8_t)0x80 }

SPI Frame Format: MSB or LSB transmitted first Warning: element values correspond to LSBFIRST bit position.

More...
enum SPI_Flag_TypeDef {
SPI_FLAG_BSY = (uint8_t)0x80, SPI_FLAG_OVR = (uint8_t)0x40, SPI_FLAG_MODF = (uint8_t)0x20, SPI_FLAG_CRCERR = (uint8_t)0x10,
SPI_FLAG_WKUP = (uint8_t)0x08, SPI_FLAG_TXE = (uint8_t)0x02, SPI_FLAG_RXNE = (uint8_t)0x01
}

SPI flags definition - Warning : FLAG value = mapping position register.

More...
enum SPI_IT_TypeDef {
SPI_IT_WKUP = (uint8_t)0x34, SPI_IT_OVR = (uint8_t)0x65, SPI_IT_MODF = (uint8_t)0x55, SPI_IT_CRCERR = (uint8_t)0x45,
SPI_IT_TXE = (uint8_t)0x17, SPI_IT_RXNE = (uint8_t)0x06, SPI_IT_ERR = (uint8_t)0x05
}

SPI_IT possible values Elements values convention: 0xYX X: Position of the corresponding Interrupt Y: ITPENDINGBIT position.

More...
enum | SPI_Mode_TypeDef { SPI_MODE_MASTER = (uint8_t)0x04, SPI_MODE_SLAVE = (uint8_t)0x00 }

SPI master/slave mode Warning: element values correspond to MSTR bit position.

More...
enum | SPI_NSS_TypeDef { SPI_NSS_SOFT = (uint8_t)0x02, SPI_NSS_HARD = (uint8_t)0x00 }

SPI Slave Select management Warning: element values correspond to LSBFIRST bit position.

More...

Enumeration Type Documentation

enum SPI_BaudRatePrescaler_TypeDef

SPI BaudRate Prescaler Warning: element values correspond to BR bits position.

Enumerator:
SPI_BAUDRATEPRESCALER_2

SPI frequency = frequency(CPU)/2

SPI_BAUDRATEPRESCALER_4

SPI frequency = frequency(CPU)/4

SPI_BAUDRATEPRESCALER_8

SPI frequency = frequency(CPU)/8

SPI_BAUDRATEPRESCALER_16

SPI frequency = frequency(CPU)/16

SPI_BAUDRATEPRESCALER_32

SPI frequency = frequency(CPU)/32

SPI_BAUDRATEPRESCALER_64

SPI frequency = frequency(CPU)/64

SPI_BAUDRATEPRESCALER_128

SPI frequency = frequency(CPU)/128

SPI_BAUDRATEPRESCALER_256

SPI frequency = frequency(CPU)/256

Definition at line 81 of file stm8s_spi.h.

enum SPI_ClockPhase_TypeDef

SPI Clock Phase Warning: element values correspond to CPHA bit position.

Enumerator:
SPI_CLOCKPHASE_1EDGE

The first clock transition is the first data capture edge

SPI_CLOCKPHASE_2EDGE

The second clock transition is the first data capture edge

Definition at line 105 of file stm8s_spi.h.

enum SPI_ClockPolarity_TypeDef

SPI Clock Polarity Warning: element values correspond to CPOL bit position.

Enumerator:
SPI_CLOCKPOLARITY_LOW

Clock to 0 when idle

SPI_CLOCKPOLARITY_HIGH

Clock to 1 when idle

Definition at line 96 of file stm8s_spi.h.

enum SPI_CRC_TypeDef

SPI CRC Transmit/Receive.

Enumerator:
SPI_CRC_RX

Select Tx CRC register

SPI_CRC_TX

Select Rx CRC register

Definition at line 122 of file stm8s_spi.h.

enum SPI_DataDirection_TypeDef

SPI data direction mode Warning: element values correspond to BDM, BDOE, RXONLY bits position.

Enumerator:
SPI_DATADIRECTION_2LINES_FULLDUPLEX

2-line uni-directional data mode enable

SPI_DATADIRECTION_2LINES_RXONLY

Receiver only in 2 line uni-directional data mode

SPI_DATADIRECTION_1LINE_RX

Receiver only in 1 line bi-directional data mode

SPI_DATADIRECTION_1LINE_TX

Transmit only in 1 line bi-directional data mode

Definition at line 41 of file stm8s_spi.h.

enum SPI_Direction_TypeDef

SPI direction transmit/receive.

Enumerator:
SPI_DIRECTION_RX

Selects Rx receive direction in bi-directional mode

SPI_DIRECTION_TX

Selects Tx transmission direction in bi-directional mode

Definition at line 63 of file stm8s_spi.h.

enum SPI_FirstBit_TypeDef

SPI Frame Format: MSB or LSB transmitted first Warning: element values correspond to LSBFIRST bit position.

Enumerator:
SPI_FIRSTBIT_MSB

MSB bit will be transmitted first

SPI_FIRSTBIT_LSB

LSB bit will be transmitted first

Definition at line 114 of file stm8s_spi.h.

enum SPI_Flag_TypeDef

SPI flags definition - Warning : FLAG value = mapping position register.

Enumerator:
SPI_FLAG_BSY

Busy flag

SPI_FLAG_OVR

Overrun flag

SPI_FLAG_MODF

Mode fault

SPI_FLAG_CRCERR

CRC error flag

SPI_FLAG_WKUP

Wake-up flag

SPI_FLAG_TXE

Transmit buffer empty

SPI_FLAG_RXNE

Receive buffer empty

Definition at line 130 of file stm8s_spi.h.

enum SPI_IT_TypeDef

SPI_IT possible values Elements values convention: 0xYX X: Position of the corresponding Interrupt Y: ITPENDINGBIT position.

Enumerator:
SPI_IT_WKUP

Wake-up interrupt

SPI_IT_OVR

Overrun interrupt

SPI_IT_MODF

Mode fault interrupt

SPI_IT_CRCERR

CRC error interrupt

SPI_IT_TXE

Transmit buffer empty interrupt

SPI_IT_RXNE

Receive buffer not empty interrupt

SPI_IT_ERR

Error interrupt

Definition at line 146 of file stm8s_spi.h.

enum SPI_Mode_TypeDef

SPI master/slave mode Warning: element values correspond to MSTR bit position.

Enumerator:
SPI_MODE_MASTER

SPI Master configuration

SPI_MODE_SLAVE

SPI Slave configuration

Definition at line 72 of file stm8s_spi.h.

enum SPI_NSS_TypeDef

SPI Slave Select management Warning: element values correspond to LSBFIRST bit position.

Enumerator:
SPI_NSS_SOFT

Software slave management disabled

SPI_NSS_HARD

Software slave management enabled

Definition at line 52 of file stm8s_spi.h.


STM8S/A Standard Peripherals Drivers: SPI_Private_Macros

Defines

SPI_Private_Macros

STM8S_StdPeriph_Driver

Macros used by the assert_param function to check the different functions parameters. More...

Defines

#define | IS_SPI_BAUDRATE_PRESCALER_OK(PRESCALER)
Macro used by the assert_param function in order to check the baudrate values.
#define | IS_SPI_CLEAR_FLAGS_OK(FLAG)
Macro used by the assert_param function in order to check the different sensitivity values for the flag that can be cleared by writing 0.
#define | IS_SPI_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert_param function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_SPI_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_SPI_CRC_OK(CRC)
Macro used by the assert_param function in order to check the CRC Transmit/Receive.
#define | IS_SPI_CRC_POLYNOMIAL_OK(POLYNOMIAL) ((POLYNOMIAL) > (uint8_t)0x00)
Macro used by the assert_param function in order to check the different sensitivity values for the CRC polynomial.
#define | IS_SPI_DATA_DIRECTION_OK(MODE)
Macro used by the assert_param function in order to check the data direction mode values.
#define | IS_SPI_DIRECTION_OK(DIRECTION)
Macro used by the assert_param function in order to check the mode half duplex data direction values.
#define | IS_SPI_FIRSTBIT_OK(BIT)
Macro used by the assert_param function in order to check the first bit to be transmited values.
#define | IS_SPI_FLAGS_OK(FLAG)
Macro used by the assert_param function in order to check the different flags values.
#define | IS_SPI_GET_IT_OK(ITPendingBit)
Macro used by the assert_param function in order to check the different sensitivity values for the pending bit.
#define | IS_SPI_MODE_OK(MODE)
Macro used by the assert_param function in order to check the SPI Mode values.
#define | IS_SPI_PHASE_OK(CLKPHA)
Macro used by the assert_param function in order to check the phase values.
#define | IS_SPI_POLARITY_OK(CLKPOL)
Macro used by the assert_param function in order to check the polarity values.
#define | IS_SPI_SLAVEMANAGEMENT_OK(NSS)
Macro used by the assert_param function in order to check the NSS management values.

Detailed Description

Macros used by the assert_param function to check the different functions parameters.

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
    ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

Macro used by the assert_param function in order to check the baudrate values.

Definition at line 206 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_CLEAR_FLAGS_OK ( FLAG )
Value:
(((FLAG) == SPI_FLAG_CRCERR) || \
                                     ((FLAG) == SPI_FLAG_WKUP))

Macro used by the assert_param function in order to check the different sensitivity values for the flag that can be cleared by writing 0.

Definition at line 258 of file stm8s_spi.h.

Referenced by SPI_ClearFlag().

#define IS_SPI_CLEAR_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == SPI_IT_CRCERR) || \
    ((ITPendingBit) == SPI_IT_WKUP))

Macro used by the assert_param function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.

Definition at line 286 of file stm8s_spi.h.

Referenced by SPI_ClearITPendingBit().

#define IS_SPI_CONFIG_IT_OK ( Interrupt )
Value:
(((Interrupt) == SPI_IT_TXE)  || \
                                        ((Interrupt) == SPI_IT_RXNE)  || \
                                        ((Interrupt) == SPI_IT_ERR) || \
                                        ((Interrupt) == SPI_IT_WKUP))

Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.

Definition at line 265 of file stm8s_spi.h.

Referenced by SPI_ITConfig().

#define IS_SPI_CRC_OK ( CRC )
Value:
(((CRC) == SPI_CRC_TX) || \
                            ((CRC) == SPI_CRC_RX))

Macro used by the assert_param function in order to check the CRC Transmit/Receive.

Definition at line 238 of file stm8s_spi.h.

Referenced by SPI_GetCRC().

#define IS_SPI_CRC_POLYNOMIAL_OK ( POLYNOMIAL ) ((POLYNOMIAL) > (uint8_t)0x00)

Macro used by the assert_param function in order to check the different sensitivity values for the CRC polynomial.

Definition at line 195 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_DATA_DIRECTION_OK ( MODE )
Value:
(((MODE) == SPI_DATADIRECTION_2LINES_FULLDUPLEX) || \
                                        ((MODE) == SPI_DATADIRECTION_2LINES_RXONLY) || \
                                        ((MODE) == SPI_DATADIRECTION_1LINE_RX) || \
                                        ((MODE) == SPI_DATADIRECTION_1LINE_TX))

Macro used by the assert_param function in order to check the data direction mode values.

Definition at line 171 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_DIRECTION_OK ( DIRECTION )
Value:
(((DIRECTION) == SPI_DIRECTION_RX) || \
                                        ((DIRECTION) == SPI_DIRECTION_TX))

Macro used by the assert_param function in order to check the mode half duplex data direction values.

Definition at line 180 of file stm8s_spi.h.

Referenced by SPI_BiDirectionalLineConfig().

#define IS_SPI_FIRSTBIT_OK ( BIT )
Value:
(((BIT) == SPI_FIRSTBIT_MSB) || \
                                 ((BIT) == SPI_FIRSTBIT_LSB))

Macro used by the assert_param function in order to check the first bit to be transmited values.

Definition at line 231 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_FLAGS_OK ( FLAG )
Value:
(((FLAG) == SPI_FLAG_OVR) || \
                               ((FLAG) == SPI_FLAG_MODF) || \
                               ((FLAG) == SPI_FLAG_CRCERR) || \
                               ((FLAG) == SPI_FLAG_WKUP) || \
                               ((FLAG) == SPI_FLAG_TXE) || \
                               ((FLAG) == SPI_FLAG_RXNE) || \
                               ((FLAG) == SPI_FLAG_BSY))

Macro used by the assert_param function in order to check the different flags values.

Definition at line 245 of file stm8s_spi.h.

Referenced by SPI_GetFlagStatus().

#define IS_SPI_GET_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == SPI_IT_OVR)  || \
                                        ((ITPendingBit) == SPI_IT_MODF) || \
                                        ((ITPendingBit) == SPI_IT_CRCERR) || \
                                        ((ITPendingBit) == SPI_IT_WKUP) || \
                                        ((ITPendingBit) == SPI_IT_TXE)  || \
                                        ((ITPendingBit) == SPI_IT_RXNE))

Macro used by the assert_param function in order to check the different sensitivity values for the pending bit.

Definition at line 274 of file stm8s_spi.h.

Referenced by SPI_GetITStatus().

#define IS_SPI_MODE_OK ( MODE )
Value:
(((MODE) == SPI_MODE_MASTER) || \
                              ((MODE) == SPI_MODE_SLAVE))

Macro used by the assert_param function in order to check the SPI Mode values.

Definition at line 200 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_PHASE_OK ( CLKPHA )
Value:
(((CLKPHA) == SPI_CLOCKPHASE_1EDGE) || \
                                 ((CLKPHA) == SPI_CLOCKPHASE_2EDGE))

Macro used by the assert_param function in order to check the phase values.

Definition at line 224 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_POLARITY_OK ( CLKPOL )
Value:
(((CLKPOL) == SPI_CLOCKPOLARITY_LOW) || \
                                    ((CLKPOL) == SPI_CLOCKPOLARITY_HIGH))

Macro used by the assert_param function in order to check the polarity values.

Definition at line 218 of file stm8s_spi.h.

Referenced by SPI_Init().

#define IS_SPI_SLAVEMANAGEMENT_OK ( NSS )
Value:
(((NSS) == SPI_NSS_SOFT) || \
                                        ((NSS) == SPI_NSS_HARD))

Macro used by the assert_param function in order to check the NSS management values.

Definition at line 187 of file stm8s_spi.h.

Referenced by SPI_Init().


STM8S/A Standard Peripherals Drivers: SPI_Exported_Functions

Functions

SPI_Exported_Functions

STM8S_StdPeriph_Driver

Functions

void | SPI_BiDirectionalLineConfig (SPI_Direction_TypeDef SPI_Direction)
Selects the data transfer direction in bi-directional mode.
void | SPI_CalculateCRCCmd (FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_ClearFlag (SPI_Flag_TypeDef SPI_FLAG)
Clears the SPI flags.
void | SPI_ClearITPendingBit (SPI_IT_TypeDef SPI_IT)
Clears the interrupt pending bits.
void | SPI_Cmd (FunctionalState NewState)
Enables or disables the SPI peripheral.
void | SPI_DeInit (void)
Deinitializes the SPI peripheral registers to their default reset values.
uint8_t | SPI_GetCRC (SPI_CRC_TypeDef SPI_CRC)
Returns the transmit or the receive CRC register value.
uint8_t | SPI_GetCRCPolynomial (void)
Returns the CRC Polynomial register value.
FlagStatus | SPI_GetFlagStatus (SPI_Flag_TypeDef SPI_FLAG)
Checks whether the specified SPI flag is set or not.
ITStatus | SPI_GetITStatus (SPI_IT_TypeDef SPI_IT)
Checks whether the specified interrupt has occurred or not.
void | SPI_Init (SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)
Initializes the SPI according to the specified parameters.
void | SPI_ITConfig (SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
Enables or disables the specified interrupts.
void | SPI_NSSInternalSoftwareCmd (FunctionalState NewState)
Configures internally by software the NSS pin.
uint8_t | SPI_ReceiveData (void)
Returns the most recent received data by the SPI peripheral.
void | SPI_ResetCRC (void)
Reset the Rx CRCR and Tx CRCR registers.
void | SPI_SendData (uint8_t Data)
Transmits a Data through the SPI peripheral.
void | SPI_TransmitCRC (void)
Enables the transmit of the CRC value.

Function Documentation

void SPI_BiDirectionalLineConfig ( SPI_Direction_TypeDef SPI_Direction )

Selects the data transfer direction in bi-directional mode.

Parameters:
SPI_Direction Specifies the data transfer direction in bi-directional mode.
Return values:
None

Definition at line 281 of file stm8s_spi.c.

References IS_SPI_DIRECTION_OK, SPI, SPI_CR2_BDOE, and SPI_DIRECTION_RX.

void SPI_CalculateCRCCmd ( FunctionalState NewState )

Enables or disables the CRC value calculation of the transferred bytes.

Parameters:
NewState Indicates the new state of the SPI CRC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 211 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR2_CRCEN.

Referenced by SPI_ResetCRC().

void SPI_ClearFlag ( SPI_Flag_TypeDef SPI_FLAG )

Clears the SPI flags.

Parameters:
SPI_FLAG : Specifies the flag to clear. This parameter can be one of the following values:

  • SPI_FLAG_CRCERR
  • SPI_FLAG_WKUP
Note:
- OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by a read operation to SPI_SR register (SPI_GetFlagStatus()).
  • MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_GetFlagStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 339 of file stm8s_spi.c.

References IS_SPI_CLEAR_FLAGS_OK, and SPI.

void SPI_ClearITPendingBit ( SPI_IT_TypeDef SPI_IT )

Clears the interrupt pending bits.

Parameters:
SPI_IT,: Specifies the interrupt pending bit to clear. This parameter can be one of the following values:

  • SPI_IT_CRCERR
  • SPI_IT_WKUP
Note:
- OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by a read operation to SPI_SR register (SPI_GetITStatus()).
  • MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_GetITStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 404 of file stm8s_spi.c.

References IS_SPI_CLEAR_IT_OK, and SPI.

void SPI_Cmd ( FunctionalState NewState )

Enables or disables the SPI peripheral.

Parameters:
NewState New state of the SPI peripheral. This parameter can be: ENABLE or DISABLE
Return values:
None

Definition at line 113 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR1_SPE.

Referenced by SPI_ResetCRC().

void SPI_DeInit ( void )

Deinitializes the SPI peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 44 of file stm8s_spi.c.

References SPI, SPI_CR1_RESET_VALUE, SPI_CR2_RESET_VALUE, SPI_CRCPR_RESET_VALUE, SPI_ICR_RESET_VALUE, and SPI_SR_RESET_VALUE.

uint8_t SPI_GetCRC ( SPI_CRC_TypeDef SPI_CRC )

Returns the transmit or the receive CRC register value.

Parameters:
SPI_CRC Specifies the CRC register to be read.
Return values:
The selected CRC register value.

Definition at line 231 of file stm8s_spi.c.

References IS_SPI_CRC_OK, SPI, and SPI_CRC_RX.

uint8_t SPI_GetCRCPolynomial ( void )

Returns the CRC Polynomial register value.

Parameters:
None
Return values:
The CRC Polynomial register value.

Definition at line 271 of file stm8s_spi.c.

References SPI.

FlagStatus SPI_GetFlagStatus ( SPI_Flag_TypeDef SPI_FLAG )

Checks whether the specified SPI flag is set or not.

Parameters:
SPI_FLAG : Specifies the flag to check. This parameter can be any of the SPI_FLAG_TypeDef enumeration.
Return values:
FlagStatus : Indicates the state of SPI_FLAG. This parameter can be any of the FlagStatus enumeration.

Definition at line 304 of file stm8s_spi.c.

References IS_SPI_FLAGS_OK, RESET, SET, and SPI.

ITStatus SPI_GetITStatus ( SPI_IT_TypeDef SPI_IT )

Checks whether the specified interrupt has occurred or not.

Parameters:
SPI_IT,: Specifies the SPI interrupt pending bit to check. This parameter can be one of the following values:

  • SPI_IT_CRCERR
  • SPI_IT_WKUP
  • SPI_IT_OVR
  • SPI_IT_MODF
  • SPI_IT_RXNE
  • SPI_IT_TXE
Return values:
ITStatus : Indicates the state of the SPI_IT. This parameter can be any of the ITStatus enumeration.

Definition at line 359 of file stm8s_spi.c.

References IS_SPI_GET_IT_OK, RESET, SET, and SPI.

void SPI_Init | ( | SPI_FirstBit_TypeDef | FirstBit,
 |  | SPI_BaudRatePrescaler_TypeDef | BaudRatePrescaler,
 |  | SPI_Mode_TypeDef | Mode,
 |  | SPI_ClockPolarity_TypeDef | ClockPolarity,
 |  | SPI_ClockPhase_TypeDef | ClockPhase,
 |  | SPI_DataDirection_TypeDef | Data_Direction,
 |  | SPI_NSS_TypeDef | Slave_Management,
 |  | uint8_t | CRCPolynomial
 | ) |  |

Initializes the SPI according to the specified parameters.

Parameters:
FirstBit | : This parameter can be any of the SPI_FirstBit_TypeDef enumeration.
BaudRatePrescaler | : This parameter can be any of the SPI_BaudRatePrescaler_TypeDef enumeration.
Mode | : This parameter can be any of the SPI_Mode_TypeDef enumeration.
ClockPolarity | : This parameter can be any of the SPI_ClockPolarity_TypeDef enumeration.
ClockPhase | : This parameter can be any of the SPI_ClockPhase_TypeDef enumeration.
Data_Direction | : This parameter can be any of the SPI_DataDirection_TypeDef enumeration.
Slave_Management | : This parameter can be any of the SPI_NSS_TypeDef enumeration.
CRCPolynomial | : Configures the CRC polynomial.
Return values:
None

Definition at line 72 of file stm8s_spi.c.

References IS_SPI_BAUDRATE_PRESCALER_OK, IS_SPI_CRC_POLYNOMIAL_OK, IS_SPI_DATA_DIRECTION_OK, IS_SPI_FIRSTBIT_OK, IS_SPI_MODE_OK, IS_SPI_PHASE_OK, IS_SPI_POLARITY_OK, IS_SPI_SLAVEMANAGEMENT_OK, SPI, SPI_CR2_SSI, and SPI_MODE_MASTER.

void SPI_ITConfig | ( | SPI_IT_TypeDef | SPI_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified interrupts.

Parameters:
SPI_IT Specifies the SPI interrupts sources to be enabled or disabled.
NewState,: The new state of the specified SPI interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 135 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_SPI_CONFIG_IT_OK, and SPI.

void SPI_NSSInternalSoftwareCmd ( FunctionalState NewState )

Configures internally by software the NSS pin.

Parameters:
NewState Indicates the new state of the SPI Software slave management. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 180 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR2_SSI.

uint8_t SPI_ReceiveData ( void )

Returns the most recent received data by the SPI peripheral.

Parameters:
None
Return values:
The value of the received data.

Definition at line 169 of file stm8s_spi.c.

References SPI.

void SPI_ResetCRC ( void )

Reset the Rx CRCR and Tx CRCR registers.

Parameters:
None
Return values:
None

Definition at line 256 of file stm8s_spi.c.

References ENABLE, SPI_CalculateCRCCmd(), and SPI_Cmd().

void SPI_SendData ( uint8_t Data )

Transmits a Data through the SPI peripheral.

Parameters:
Data : Byte to be transmitted.
Return values:
None

Definition at line 159 of file stm8s_spi.c.

References SPI.

void SPI_TransmitCRC ( void )

Enables the transmit of the CRC value.

Parameters:
None
Return values:
None

Definition at line 200 of file stm8s_spi.c.

References SPI, and SPI_CR2_CRCNEXT.


STM8S/A Standard Peripherals Drivers: TIM1_Exported_Types

Defines | Enumerations

TIM1_Exported_Types

STM8S_StdPeriph_Driver

Defines

#define | IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(STATE)
#define | IS_TIM1_BREAK_POLARITY_OK(POLARITY)
#define | IS_TIM1_BREAK_STATE_OK(STATE)
#define | IS_TIM1_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
#define | IS_TIM1_COMPLEMENTARY_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_COUNTER_MODE_OK(MODE)
#define | IS_TIM1_ENCODER_MODE_OK(MODE)
#define | IS_TIM1_EVENT_SOURCE_OK(SOURCE) ((SOURCE) != 0x00)
#define | IS_TIM1_EXT_POLARITY_OK(POLARITY)
#define | IS_TIM1_EXT_PRESCALER_OK(PRESCALER)
#define | IS_TIM1_EXT_TRG_FILTER_OK(FILTER) ((FILTER) <= 0x0F)
TIM1 External Trigger Filer Value.
#define | IS_TIM1_FORCED_ACTION_OK(ACTION)
#define | IS_TIM1_GET_FLAG_OK(FLAG)
#define | IS_TIM1_GET_IT_OK(IT)
#define | IS_TIM1_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM1 Input Capture Filer Value.
#define | IS_TIM1_IC_POLARITY_OK(POLARITY)
#define | IS_TIM1_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM1_IC_SELECTION_OK(SELECTION)
#define | IS_TIM1_IT_OK(IT) ((IT) != 0x00)
#define | IS_TIM1_LOCK_LEVEL_OK(LEVEL)
#define | IS_TIM1_OC_MODE_OK(MODE)
#define | IS_TIM1_OC_POLARITY_OK(POLARITY)
#define | IS_TIM1_OCIDLE_STATE_OK(STATE)
#define | IS_TIM1_OCM_OK(MODE)
#define | IS_TIM1_OCN_POLARITY_OK(POLARITY)
#define | IS_TIM1_OCNIDLE_STATE_OK(STATE)
#define | IS_TIM1_OPM_MODE_OK(MODE)
#define | IS_TIM1_OSSI_STATE_OK(STATE)
#define | IS_TIM1_OUTPUT_STATE_OK(STATE)
#define | IS_TIM1_OUTPUTN_STATE_OK(STATE)
#define | IS_TIM1_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM1_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_SLAVE_MODE_OK(MODE)
#define | IS_TIM1_TIX_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM1_TIXCLK_SOURCE_OK(SOURCE)
#define | IS_TIM1_TRGO_SOURCE_OK(SOURCE)
#define | IS_TIM1_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM1_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM1_AutomaticOutput_TypeDef { TIM1_AUTOMATICOUTPUT_ENABLE = ((uint8_t)0x40), TIM1_AUTOMATICOUTPUT_DISABLE = ((uint8_t)0x00) }

TIM1 AOE Bit Set/Reset.

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enum | TIM1_BreakPolarity_TypeDef { TIM1_BREAKPOLARITY_LOW = ((uint8_t)0x00), TIM1_BREAKPOLARITY_HIGH = ((uint8_t)0x20) }

TIM1 Break Polarity.

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enum | TIM1_BreakState_TypeDef { TIM1_BREAK_ENABLE = ((uint8_t)0x10), TIM1_BREAK_DISABLE = ((uint8_t)0x00) }

TIM1 Break Input enable/disable.

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enum | TIM1_Channel_TypeDef { TIM1_CHANNEL_1 = ((uint8_t)0x00), TIM1_CHANNEL_2 = ((uint8_t)0x01), TIM1_CHANNEL_3 = ((uint8_t)0x02), TIM1_CHANNEL_4 = ((uint8_t)0x03) }

TIM1 Channel.

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enum TIM1_CounterMode_TypeDef {
TIM1_COUNTERMODE_UP = ((uint8_t)0x00), TIM1_COUNTERMODE_DOWN = ((uint8_t)0x10), TIM1_COUNTERMODE_CENTERALIGNED1 = ((uint8_t)0x20), TIM1_COUNTERMODE_CENTERALIGNED2 = ((uint8_t)0x40),
TIM1_COUNTERMODE_CENTERALIGNED3 = ((uint8_t)0x60)
}

TIM1 Counter Mode.

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enum | TIM1_EncoderMode_TypeDef { TIM1_ENCODERMODE_TI1 = ((uint8_t)0x01), TIM1_ENCODERMODE_TI2 = ((uint8_t)0x02), TIM1_ENCODERMODE_TI12 = ((uint8_t)0x03) }

TIM1 Encoder Mode.

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enum TIM1_EventSource_TypeDef {
TIM1_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM1_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM1_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM1_EVENTSOURCE_CC3 = ((uint8_t)0x08),
TIM1_EVENTSOURCE_CC4 = ((uint8_t)0x10), TIM1_EVENTSOURCE_COM = ((uint8_t)0x20), TIM1_EVENTSOURCE_TRIGGER = ((uint8_t)0x40), TIM1_EVENTSOURCE_BREAK = ((uint8_t)0x80)
}

TIM1 Event Source.

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enum | TIM1_ExtTRGPolarity_TypeDef { TIM1_EXTTRGPOLARITY_INVERTED = ((uint8_t)0x80), TIM1_EXTTRGPOLARITY_NONINVERTED = ((uint8_t)0x00) }

TIM1 External Trigger Polarity.

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enum | TIM1_ExtTRGPSC_TypeDef { TIM1_EXTTRGPSC_OFF = ((uint8_t)0x00), TIM1_EXTTRGPSC_DIV2 = ((uint8_t)0x10), TIM1_EXTTRGPSC_DIV4 = ((uint8_t)0x20), TIM1_EXTTRGPSC_DIV8 = ((uint8_t)0x30) }

TIM1 External Trigger Prescaler.

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enum TIM1_FLAG_TypeDef {
TIM1_FLAG_UPDATE = ((uint16_t)0x0001), TIM1_FLAG_CC1 = ((uint16_t)0x0002), TIM1_FLAG_CC2 = ((uint16_t)0x0004), TIM1_FLAG_CC3 = ((uint16_t)0x0008),
TIM1_FLAG_CC4 = ((uint16_t)0x0010), TIM1_FLAG_COM = ((uint16_t)0x0020), TIM1_FLAG_TRIGGER = ((uint16_t)0x0040), TIM1_FLAG_BREAK = ((uint16_t)0x0080),
TIM1_FLAG_CC1OF = ((uint16_t)0x0200), TIM1_FLAG_CC2OF = ((uint16_t)0x0400), TIM1_FLAG_CC3OF = ((uint16_t)0x0800), TIM1_FLAG_CC4OF = ((uint16_t)0x1000)
}

TIM1 Flags.

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enum | TIM1_ForcedAction_TypeDef { TIM1_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM1_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }

TIM1 Forced Action.

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enum | TIM1_ICPolarity_TypeDef { TIM1_ICPOLARITY_RISING = ((uint8_t)0x00), TIM1_ICPOLARITY_FALLING = ((uint8_t)0x01) }

TIM1 Input Capture Polarity.

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enum | TIM1_ICPSC_TypeDef { TIM1_ICPSC_DIV1 = ((uint8_t)0x00), TIM1_ICPSC_DIV2 = ((uint8_t)0x04), TIM1_ICPSC_DIV4 = ((uint8_t)0x08), TIM1_ICPSC_DIV8 = ((uint8_t)0x0C) }

TIM1 Input Capture Prescaler.

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enum | TIM1_ICSelection_TypeDef { TIM1_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM1_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM1_ICSELECTION_TRGI = ((uint8_t)0x03) }

TIM1 Input Capture Selection.

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enum TIM1_IT_TypeDef {
TIM1_IT_UPDATE = ((uint8_t)0x01), TIM1_IT_CC1 = ((uint8_t)0x02), TIM1_IT_CC2 = ((uint8_t)0x04), TIM1_IT_CC3 = ((uint8_t)0x08),
TIM1_IT_CC4 = ((uint8_t)0x10), TIM1_IT_COM = ((uint8_t)0x20), TIM1_IT_TRIGGER = ((uint8_t)0x40), TIM1_IT_BREAK = ((uint8_t)0x80)
}

TIM1 interrupt sources.

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enum | TIM1_LockLevel_TypeDef { TIM1_LOCKLEVEL_OFF = ((uint8_t)0x00), TIM1_LOCKLEVEL_1 = ((uint8_t)0x01), TIM1_LOCKLEVEL_2 = ((uint8_t)0x02), TIM1_LOCKLEVEL_3 = ((uint8_t)0x03) }

TIM1 Lock levels.

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enum | TIM1_OCIdleState_TypeDef { TIM1_OCIDLESTATE_SET = ((uint8_t)0x55), TIM1_OCIDLESTATE_RESET = ((uint8_t)0x00) }

TIM1 Output Compare Idle State.

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enum TIM1_OCMode_TypeDef {
TIM1_OCMODE_TIMING = ((uint8_t)0x00), TIM1_OCMODE_ACTIVE = ((uint8_t)0x10), TIM1_OCMODE_INACTIVE = ((uint8_t)0x20), TIM1_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM1_OCMODE_PWM1 = ((uint8_t)0x60), TIM1_OCMODE_PWM2 = ((uint8_t)0x70)
}

TIM1 Output Compare and PWM modes.

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enum | TIM1_OCNIdleState_TypeDef { TIM1_OCNIDLESTATE_SET = ((uint8_t)0x2A), TIM1_OCNIDLESTATE_RESET = ((uint8_t)0x00) }

TIM1 Output Compare N Idle State.

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enum | TIM1_OCNPolarity_TypeDef { TIM1_OCNPOLARITY_HIGH = ((uint8_t)0x00), TIM1_OCNPOLARITY_LOW = ((uint8_t)0x88) }

TIM1 Output Compare N Polarity.

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enum | TIM1_OCPolarity_TypeDef { TIM1_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM1_OCPOLARITY_LOW = ((uint8_t)0x22) }

TIM1 Output Compare Polarity.

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enum | TIM1_OPMode_TypeDef { TIM1_OPMODE_SINGLE = ((uint8_t)0x01), TIM1_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM1 One Pulse Mode.

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enum | TIM1_OSSIState_TypeDef { TIM1_OSSISTATE_ENABLE = ((uint8_t)0x04), TIM1_OSSISTATE_DISABLE = ((uint8_t)0x00) }

TIM1 OSSI: Off-State Selection for Idle mode states.

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enum | TIM1_OutputNState_TypeDef { TIM1_OUTPUTNSTATE_DISABLE = ((uint8_t)0x00), TIM1_OUTPUTNSTATE_ENABLE = ((uint8_t)0x44) }

TIM1 Output Compare N States.

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enum | TIM1_OutputState_TypeDef { TIM1_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM1_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }

TIM1 Output Compare states.

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enum | TIM1_PSCReloadMode_TypeDef { TIM1_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM1_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM1 Prescaler Reload Mode.

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enum | TIM1_SlaveMode_TypeDef { TIM1_SLAVEMODE_RESET = ((uint8_t)0x04), TIM1_SLAVEMODE_GATED = ((uint8_t)0x05), TIM1_SLAVEMODE_TRIGGER = ((uint8_t)0x06), TIM1_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07) }

TIM1 Slave Mode.

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enum | TIM1_TIxExternalCLK1Source_TypeDef { TIM1_TIXEXTERNALCLK1SOURCE_TI1ED = ((uint8_t)0x40), TIM1_TIXEXTERNALCLK1SOURCE_TI1 = ((uint8_t)0x50), TIM1_TIXEXTERNALCLK1SOURCE_TI2 = ((uint8_t)0x60) }

TIM1 TIx External Clock Source.

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enum TIM1_TRGOSource_TypeDef {
TIM1_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM1_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM1_TRGOSOURCE_UPDATE = ((uint8_t)0x20), TIM1_TRGOSource_OC1 = ((uint8_t)0x30),
TIM1_TRGOSOURCE_OC1REF = ((uint8_t)0x40), TIM1_TRGOSOURCE_OC2REF = ((uint8_t)0x50), TIM1_TRGOSOURCE_OC3REF = ((uint8_t)0x60)
}

TIM1 Trigger Output Source.

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enum TIM1_TS_TypeDef {
TIM1_TS_TIM6 = ((uint8_t)0x00), TIM1_TS_TIM5 = ((uint8_t)0x30), TIM1_TS_TI1F_ED = ((uint8_t)0x40), TIM1_TS_TI1FP1 = ((uint8_t)0x50),
TIM1_TS_TI2FP2 = ((uint8_t)0x60), TIM1_TS_ETRF = ((uint8_t)0x70)
}

TIM1 Internal Trigger Selection.

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enum | TIM1_UpdateSource_TypeDef { TIM1_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM1_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM1 Update Source.

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Define Documentation

#define IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_AUTOMATICOUTPUT_ENABLE) || \
    ((STATE) == TIM1_AUTOMATICOUTPUT_DISABLE))

Definition at line 180 of file stm8s_tim1.h.

Referenced by TIM1_BDTRConfig().

#define IS_TIM1_BREAK_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM1_BREAKPOLARITY_LOW) || \
    ((POLARITY) == TIM1_BREAKPOLARITY_HIGH))

Definition at line 170 of file stm8s_tim1.h.

Referenced by TIM1_BDTRConfig().

#define IS_TIM1_BREAK_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_BREAK_ENABLE) || \
                                       ((STATE) == TIM1_BREAK_DISABLE))

Definition at line 161 of file stm8s_tim1.h.

Referenced by TIM1_BDTRConfig().

#define IS_TIM1_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM1_CHANNEL_1) || \
                                     ((CHANNEL) == TIM1_CHANNEL_2) || \
                                     ((CHANNEL) == TIM1_CHANNEL_3) || \
                                     ((CHANNEL) == TIM1_CHANNEL_4))

Definition at line 86 of file stm8s_tim1.h.

Referenced by TIM1_CCxCmd(), TIM1_ICInit(), and TIM1_SelectOCxM().

#define IS_TIM1_CLEAR_FLAG_OK ( FLAG ) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))

Definition at line 465 of file stm8s_tim1.h.

Referenced by TIM1_ClearFlag().

#define IS_TIM1_COMPLEMENTARY_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM1_CHANNEL_1) || \
    ((CHANNEL) == TIM1_CHANNEL_2) || \
    ((CHANNEL) == TIM1_CHANNEL_3))

Definition at line 94 of file stm8s_tim1.h.

Referenced by TIM1_CCxNCmd().

#define IS_TIM1_COUNTER_MODE_OK ( MODE )
Value:
(((MODE) == TIM1_COUNTERMODE_UP) || \
                                       ((MODE) == TIM1_COUNTERMODE_DOWN) || \
                                       ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED1) || \
                                       ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED2) || \
                                       ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED3))

Definition at line 109 of file stm8s_tim1.h.

Referenced by TIM1_CounterModeConfig(), and TIM1_TimeBaseInit().

#define IS_TIM1_ENCODER_MODE_OK ( MODE )
Value:
(((MODE) == TIM1_ENCODERMODE_TI1) || \
                                       ((MODE) == TIM1_ENCODERMODE_TI2) || \
                                       ((MODE) == TIM1_ENCODERMODE_TI12))

Definition at line 372 of file stm8s_tim1.h.

Referenced by TIM1_EncoderInterfaceConfig().

#define IS_TIM1_EVENT_SOURCE_OK ( SOURCE ) ((SOURCE) != 0x00)

Definition at line 389 of file stm8s_tim1.h.

Referenced by TIM1_GenerateEvent().

#define IS_TIM1_EXT_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM1_EXTTRGPOLARITY_INVERTED) || \
    ((POLARITY) == TIM1_EXTTRGPOLARITY_NONINVERTED))

Definition at line 351 of file stm8s_tim1.h.

Referenced by TIM1_ETRClockMode1Config(), and TIM1_ETRClockMode2Config().

#define IS_TIM1_EXT_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM1_EXTTRGPSC_OFF) || \
    ((PRESCALER) == TIM1_EXTTRGPSC_DIV2) || \
    ((PRESCALER) == TIM1_EXTTRGPSC_DIV4) || \
    ((PRESCALER) == TIM1_EXTTRGPSC_DIV8))

Definition at line 304 of file stm8s_tim1.h.

Referenced by TIM1_ETRClockMode1Config(), and TIM1_ETRClockMode2Config().

#define IS_TIM1_EXT_TRG_FILTER_OK ( FILTER ) ((FILTER) <= 0x0F)

TIM1 External Trigger Filer Value.

Definition at line 268 of file stm8s_tim1.h.

Referenced by TIM1_ETRConfig().

#define IS_TIM1_FORCED_ACTION_OK ( ACTION )
Value:
(((ACTION) == TIM1_FORCEDACTION_ACTIVE) || \
    ((ACTION) == TIM1_FORCEDACTION_INACTIVE))

Definition at line 474 of file stm8s_tim1.h.

Referenced by TIM1_ForcedOC1Config(), TIM1_ForcedOC2Config(), TIM1_ForcedOC3Config(), and TIM1_ForcedOC4Config().

#define IS_TIM1_GET_FLAG_OK ( FLAG )
Value:
(((FLAG) == TIM1_FLAG_UPDATE) || \
                                   ((FLAG) == TIM1_FLAG_CC1) || \
                                   ((FLAG) == TIM1_FLAG_CC2) || \
                                   ((FLAG) == TIM1_FLAG_CC3) || \
                                   ((FLAG) == TIM1_FLAG_CC4) || \
                                   ((FLAG) == TIM1_FLAG_COM) || \
                                   ((FLAG) == TIM1_FLAG_TRIGGER) || \
                                   ((FLAG) == TIM1_FLAG_BREAK) || \
                                   ((FLAG) == TIM1_FLAG_CC1OF) || \
                                   ((FLAG) == TIM1_FLAG_CC2OF) || \
                                   ((FLAG) == TIM1_FLAG_CC3OF) || \
                                   ((FLAG) == TIM1_FLAG_CC4OF))

Definition at line 452 of file stm8s_tim1.h.

Referenced by TIM1_GetFlagStatus().

#define IS_TIM1_GET_IT_OK ( IT )
Value:
(((IT) == TIM1_IT_UPDATE) || \
                               ((IT) == TIM1_IT_CC1) || \
                               ((IT) == TIM1_IT_CC2) || \
                               ((IT) == TIM1_IT_CC3) || \
                               ((IT) == TIM1_IT_CC4) || \
                               ((IT) == TIM1_IT_COM) || \
                               ((IT) == TIM1_IT_TRIGGER) || \
                               ((IT) == TIM1_IT_BREAK))

Definition at line 285 of file stm8s_tim1.h.

Referenced by TIM1_GetITStatus().

#define IS_TIM1_IC_FILTER_OK ( ICFILTER ) ((ICFILTER) <= 0x0F)

TIM1 Input Capture Filer Value.

Definition at line 265 of file stm8s_tim1.h.

Referenced by TIM1_ICInit(), and TIM1_TIxExternalClockConfig().

#define IS_TIM1_IC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM1_ICPOLARITY_RISING) || \
    ((POLARITY) == TIM1_ICPOLARITY_FALLING))

Definition at line 234 of file stm8s_tim1.h.

Referenced by TIM1_EncoderInterfaceConfig(), TIM1_ICInit(), TIM1_PWMIConfig(), and TIM1_TIxExternalClockConfig().

#define IS_TIM1_IC_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM1_ICPSC_DIV1) || \
    ((PRESCALER) == TIM1_ICPSC_DIV2) || \
    ((PRESCALER) == TIM1_ICPSC_DIV4) || \
    ((PRESCALER) == TIM1_ICPSC_DIV8))

Definition at line 258 of file stm8s_tim1.h.

Referenced by TIM1_ICInit(), TIM1_PWMIConfig(), TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), and TIM1_SetIC4Prescaler().

#define IS_TIM1_IC_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM1_ICSELECTION_DIRECTTI) || \
    ((SELECTION) == TIM1_ICSELECTION_INDIRECTTI) || \
    ((SELECTION) == TIM1_ICSELECTION_TRGI))

Definition at line 245 of file stm8s_tim1.h.

Referenced by TIM1_ICInit(), and TIM1_PWMIConfig().

#define IS_TIM1_IT_OK ( IT ) ((IT) != 0x00)

Definition at line 283 of file stm8s_tim1.h.

Referenced by TIM1_ClearITPendingBit(), and TIM1_ITConfig().

#define IS_TIM1_LOCK_LEVEL_OK ( LEVEL )
Value:
(((LEVEL) == TIM1_LOCKLEVEL_OFF) || \
                                      ((LEVEL) == TIM1_LOCKLEVEL_1) || \
                                      ((LEVEL) == TIM1_LOCKLEVEL_2) || \
                                      ((LEVEL) == TIM1_LOCKLEVEL_3))

Definition at line 192 of file stm8s_tim1.h.

Referenced by TIM1_BDTRConfig().

#define IS_TIM1_OC_MODE_OK ( MODE )
Value:
(((MODE) ==  TIM1_OCMODE_TIMING) || \
                                  ((MODE) == TIM1_OCMODE_ACTIVE) || \
                                  ((MODE) == TIM1_OCMODE_INACTIVE) || \
                                  ((MODE) == TIM1_OCMODE_TOGGLE)|| \
                                  ((MODE) == TIM1_OCMODE_PWM1) || \
                                  ((MODE) == TIM1_OCMODE_PWM2))

Definition at line 49 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC2Init(), TIM1_OC3Init(), and TIM1_OC4Init().

#define IS_TIM1_OC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM1_OCPOLARITY_HIGH) || \
    ((POLARITY) == TIM1_OCPOLARITY_LOW))

Definition at line 122 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC1PolarityConfig(), TIM1_OC2Init(), TIM1_OC2PolarityConfig(), TIM1_OC3Init(), TIM1_OC3PolarityConfig(), TIM1_OC4Init(), and TIM1_OC4PolarityConfig().

#define IS_TIM1_OCIDLE_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_OCIDLESTATE_SET) || \
                                        ((STATE) == TIM1_OCIDLESTATE_RESET))

Definition at line 214 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC2Init(), TIM1_OC3Init(), and TIM1_OC4Init().

#define IS_TIM1_OCM_OK ( MODE )
Value:
(((MODE) ==  TIM1_OCMODE_TIMING) || \
                             ((MODE) == TIM1_OCMODE_ACTIVE) || \
                             ((MODE) == TIM1_OCMODE_INACTIVE) || \
                             ((MODE) == TIM1_OCMODE_TOGGLE)|| \
                             ((MODE) == TIM1_OCMODE_PWM1) || \
                             ((MODE) == TIM1_OCMODE_PWM2) || \
                             ((MODE) == (uint8_t)TIM1_FORCEDACTION_ACTIVE) || \
                             ((MODE) == (uint8_t)TIM1_FORCEDACTION_INACTIVE))

Definition at line 56 of file stm8s_tim1.h.

Referenced by TIM1_SelectOCxM().

#define IS_TIM1_OCN_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM1_OCNPOLARITY_HIGH) || \
    ((POLARITY) == TIM1_OCNPOLARITY_LOW))

Definition at line 132 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC1NPolarityConfig(), TIM1_OC2Init(), TIM1_OC2NPolarityConfig(), TIM1_OC3Init(), and TIM1_OC3NPolarityConfig().

#define IS_TIM1_OCNIDLE_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_OCNIDLESTATE_SET) || \
    ((STATE) == TIM1_OCNIDLESTATE_RESET))

Definition at line 224 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC2Init(), and TIM1_OC3Init().

#define IS_TIM1_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM1_OPMODE_SINGLE) || \
                                   ((MODE) == TIM1_OPMODE_REPETITIVE))

Definition at line 72 of file stm8s_tim1.h.

Referenced by TIM1_SelectOnePulseMode().

#define IS_TIM1_OSSI_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_OSSISTATE_ENABLE) || \
                                      ((STATE) == TIM1_OSSISTATE_DISABLE))

Definition at line 204 of file stm8s_tim1.h.

Referenced by TIM1_BDTRConfig().

#define IS_TIM1_OUTPUT_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_OUTPUTSTATE_DISABLE) || \
                                        ((STATE) == TIM1_OUTPUTSTATE_ENABLE))

Definition at line 142 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC2Init(), TIM1_OC3Init(), and TIM1_OC4Init().

#define IS_TIM1_OUTPUTN_STATE_OK ( STATE )
Value:
(((STATE) == TIM1_OUTPUTNSTATE_DISABLE) ||\
    ((STATE) == TIM1_OUTPUTNSTATE_ENABLE))

Definition at line 152 of file stm8s_tim1.h.

Referenced by TIM1_OC1Init(), TIM1_OC2Init(), and TIM1_OC3Init().

#define IS_TIM1_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM1_PSCRELOADMODE_UPDATE) || \
    ((RELOAD) == TIM1_PSCRELOADMODE_IMMEDIATE))

Definition at line 361 of file stm8s_tim1.h.

Referenced by TIM1_PrescalerConfig().

#define IS_TIM1_PWMI_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM1_CHANNEL_1) || \
    ((CHANNEL) == TIM1_CHANNEL_2))

Definition at line 91 of file stm8s_tim1.h.

Referenced by TIM1_PWMIConfig().

#define IS_TIM1_SLAVE_MODE_OK ( MODE )
Value:
(((MODE) == TIM1_SLAVEMODE_RESET) || \
                                     ((MODE) == TIM1_SLAVEMODE_GATED) || \
                                     ((MODE) == TIM1_SLAVEMODE_TRIGGER) || \
                                     ((MODE) == TIM1_SLAVEMODE_EXTERNAL1))

Definition at line 430 of file stm8s_tim1.h.

Referenced by TIM1_SelectSlaveMode().

#define IS_TIM1_TIX_TRIGGER_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM1_TS_TI1F_ED) || \
    ((SELECTION) == TIM1_TS_TI1FP1) || \
    ((SELECTION) == TIM1_TS_TI2FP2))

Definition at line 328 of file stm8s_tim1.h.

#define IS_TIM1_TIXCLK_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1ED) || \
    ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI2) || \
    ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1))

Definition at line 340 of file stm8s_tim1.h.

Referenced by TIM1_TIxExternalClockConfig().

#define IS_TIM1_TRGO_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM1_TRGOSOURCE_RESET) || \
                                        ((SOURCE) == TIM1_TRGOSOURCE_ENABLE) || \
                                        ((SOURCE) == TIM1_TRGOSOURCE_UPDATE) || \
                                        ((SOURCE) == TIM1_TRGOSource_OC1)  || \
                                        ((SOURCE) == TIM1_TRGOSOURCE_OC1REF) || \
                                        ((SOURCE) == TIM1_TRGOSOURCE_OC2REF) || \
                                        ((SOURCE) == TIM1_TRGOSOURCE_OC3REF))

Definition at line 413 of file stm8s_tim1.h.

Referenced by TIM1_SelectOutputTrigger().

#define IS_TIM1_TRIGGER_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM1_TS_TI1F_ED) || \
    ((SELECTION) == TIM1_TS_TI1FP1) || \
    ((SELECTION) == TIM1_TS_TI2FP2) || \
    ((SELECTION) == TIM1_TS_ETRF) || \
    ((SELECTION) == TIM1_TS_TIM5) || \
    ((SELECTION) == TIM1_TS_TIM6))

Definition at line 320 of file stm8s_tim1.h.

Referenced by TIM1_SelectInputTrigger().

#define IS_TIM1_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM1_UPDATESOURCE_GLOBAL) || \
    ((SOURCE) == TIM1_UPDATESOURCE_REGULAR))

Definition at line 398 of file stm8s_tim1.h.

Referenced by TIM1_UpdateRequestConfig().

Enumeration Type Documentation

enum TIM1_AutomaticOutput_TypeDef

TIM1 AOE Bit Set/Reset.

Enumerator:
TIM1_AUTOMATICOUTPUT_ENABLE
TIM1_AUTOMATICOUTPUT_DISABLE

Definition at line 174 of file stm8s_tim1.h.

enum TIM1_BreakPolarity_TypeDef

TIM1 Break Polarity.

Enumerator:
TIM1_BREAKPOLARITY_LOW
TIM1_BREAKPOLARITY_HIGH

Definition at line 165 of file stm8s_tim1.h.

enum TIM1_BreakState_TypeDef

TIM1 Break Input enable/disable.

Enumerator:
TIM1_BREAK_ENABLE
TIM1_BREAK_DISABLE

Definition at line 156 of file stm8s_tim1.h.

enum TIM1_Channel_TypeDef

TIM1 Channel.

Enumerator:
TIM1_CHANNEL_1
TIM1_CHANNEL_2
TIM1_CHANNEL_3
TIM1_CHANNEL_4

Definition at line 77 of file stm8s_tim1.h.

enum TIM1_CounterMode_TypeDef

TIM1 Counter Mode.

Enumerator:
TIM1_COUNTERMODE_UP
TIM1_COUNTERMODE_DOWN
TIM1_COUNTERMODE_CENTERALIGNED1
TIM1_COUNTERMODE_CENTERALIGNED2
TIM1_COUNTERMODE_CENTERALIGNED3

Definition at line 100 of file stm8s_tim1.h.

enum TIM1_EncoderMode_TypeDef

TIM1 Encoder Mode.

Enumerator:
TIM1_ENCODERMODE_TI1
TIM1_ENCODERMODE_TI2
TIM1_ENCODERMODE_TI12

Definition at line 365 of file stm8s_tim1.h.

enum TIM1_EventSource_TypeDef

TIM1 Event Source.

Enumerator:
TIM1_EVENTSOURCE_UPDATE
TIM1_EVENTSOURCE_CC1
TIM1_EVENTSOURCE_CC2
TIM1_EVENTSOURCE_CC3
TIM1_EVENTSOURCE_CC4
TIM1_EVENTSOURCE_COM
TIM1_EVENTSOURCE_TRIGGER
TIM1_EVENTSOURCE_BREAK

Definition at line 377 of file stm8s_tim1.h.

enum TIM1_ExtTRGPolarity_TypeDef

TIM1 External Trigger Polarity.

Enumerator:
TIM1_EXTTRGPOLARITY_INVERTED
TIM1_EXTTRGPOLARITY_NONINVERTED

Definition at line 345 of file stm8s_tim1.h.

enum TIM1_ExtTRGPSC_TypeDef

TIM1 External Trigger Prescaler.

Enumerator:
TIM1_EXTTRGPSC_OFF
TIM1_EXTTRGPSC_DIV2
TIM1_EXTTRGPSC_DIV4
TIM1_EXTTRGPSC_DIV8

Definition at line 296 of file stm8s_tim1.h.

enum TIM1_FLAG_TypeDef

TIM1 Flags.

Enumerator:
TIM1_FLAG_UPDATE
TIM1_FLAG_CC1
TIM1_FLAG_CC2
TIM1_FLAG_CC3
TIM1_FLAG_CC4
TIM1_FLAG_COM
TIM1_FLAG_TRIGGER
TIM1_FLAG_BREAK
TIM1_FLAG_CC1OF
TIM1_FLAG_CC2OF
TIM1_FLAG_CC3OF
TIM1_FLAG_CC4OF

Definition at line 436 of file stm8s_tim1.h.

enum TIM1_ForcedAction_TypeDef

TIM1 Forced Action.

Enumerator:
TIM1_FORCEDACTION_ACTIVE
TIM1_FORCEDACTION_INACTIVE

Definition at line 468 of file stm8s_tim1.h.

enum TIM1_ICPolarity_TypeDef

TIM1 Input Capture Polarity.

Enumerator:
TIM1_ICPOLARITY_RISING
TIM1_ICPOLARITY_FALLING

Definition at line 228 of file stm8s_tim1.h.

enum TIM1_ICPSC_TypeDef

TIM1 Input Capture Prescaler.

Enumerator:
TIM1_ICPSC_DIV1
TIM1_ICPSC_DIV2
TIM1_ICPSC_DIV4
TIM1_ICPSC_DIV8

Definition at line 250 of file stm8s_tim1.h.

enum TIM1_ICSelection_TypeDef

TIM1 Input Capture Selection.

Enumerator:
TIM1_ICSELECTION_DIRECTTI
TIM1_ICSELECTION_INDIRECTTI
TIM1_ICSELECTION_TRGI

Definition at line 238 of file stm8s_tim1.h.

enum TIM1_IT_TypeDef

TIM1 interrupt sources.

Enumerator:
TIM1_IT_UPDATE
TIM1_IT_CC1
TIM1_IT_CC2
TIM1_IT_CC3
TIM1_IT_CC4
TIM1_IT_COM
TIM1_IT_TRIGGER
TIM1_IT_BREAK

Definition at line 271 of file stm8s_tim1.h.

enum TIM1_LockLevel_TypeDef

TIM1 Lock levels.

Enumerator:
TIM1_LOCKLEVEL_OFF
TIM1_LOCKLEVEL_1
TIM1_LOCKLEVEL_2
TIM1_LOCKLEVEL_3

Definition at line 184 of file stm8s_tim1.h.

enum TIM1_OCIdleState_TypeDef

TIM1 Output Compare Idle State.

Enumerator:
TIM1_OCIDLESTATE_SET
TIM1_OCIDLESTATE_RESET

Definition at line 208 of file stm8s_tim1.h.

enum TIM1_OCMode_TypeDef

TIM1 Output Compare and PWM modes.

Enumerator:
TIM1_OCMODE_TIMING
TIM1_OCMODE_ACTIVE
TIM1_OCMODE_INACTIVE
TIM1_OCMODE_TOGGLE
TIM1_OCMODE_PWM1
TIM1_OCMODE_PWM2

Definition at line 39 of file stm8s_tim1.h.

enum TIM1_OCNIdleState_TypeDef

TIM1 Output Compare N Idle State.

Enumerator:
TIM1_OCNIDLESTATE_SET
TIM1_OCNIDLESTATE_RESET

Definition at line 218 of file stm8s_tim1.h.

enum TIM1_OCNPolarity_TypeDef

TIM1 Output Compare N Polarity.

Enumerator:
TIM1_OCNPOLARITY_HIGH
TIM1_OCNPOLARITY_LOW

Definition at line 126 of file stm8s_tim1.h.

enum TIM1_OCPolarity_TypeDef

TIM1 Output Compare Polarity.

Enumerator:
TIM1_OCPOLARITY_HIGH
TIM1_OCPOLARITY_LOW

Definition at line 116 of file stm8s_tim1.h.

enum TIM1_OPMode_TypeDef

TIM1 One Pulse Mode.

Enumerator:
TIM1_OPMODE_SINGLE
TIM1_OPMODE_REPETITIVE

Definition at line 66 of file stm8s_tim1.h.

enum TIM1_OSSIState_TypeDef

TIM1 OSSI: Off-State Selection for Idle mode states.

Enumerator:
TIM1_OSSISTATE_ENABLE
TIM1_OSSISTATE_DISABLE

Definition at line 198 of file stm8s_tim1.h.

enum TIM1_OutputNState_TypeDef

TIM1 Output Compare N States.

Enumerator:
TIM1_OUTPUTNSTATE_DISABLE
TIM1_OUTPUTNSTATE_ENABLE

Definition at line 146 of file stm8s_tim1.h.

enum TIM1_OutputState_TypeDef

TIM1 Output Compare states.

Enumerator:
TIM1_OUTPUTSTATE_DISABLE
TIM1_OUTPUTSTATE_ENABLE

Definition at line 136 of file stm8s_tim1.h.

enum TIM1_PSCReloadMode_TypeDef

TIM1 Prescaler Reload Mode.

Enumerator:
TIM1_PSCRELOADMODE_UPDATE
TIM1_PSCRELOADMODE_IMMEDIATE

Definition at line 355 of file stm8s_tim1.h.

enum TIM1_SlaveMode_TypeDef

TIM1 Slave Mode.

Enumerator:
TIM1_SLAVEMODE_RESET
TIM1_SLAVEMODE_GATED
TIM1_SLAVEMODE_TRIGGER
TIM1_SLAVEMODE_EXTERNAL1

Definition at line 422 of file stm8s_tim1.h.

enum TIM1_TIxExternalCLK1Source_TypeDef

TIM1 TIx External Clock Source.

Enumerator:
TIM1_TIXEXTERNALCLK1SOURCE_TI1ED
TIM1_TIXEXTERNALCLK1SOURCE_TI1
TIM1_TIXEXTERNALCLK1SOURCE_TI2

Definition at line 333 of file stm8s_tim1.h.

enum TIM1_TRGOSource_TypeDef

TIM1 Trigger Output Source.

Enumerator:
TIM1_TRGOSOURCE_RESET
TIM1_TRGOSOURCE_ENABLE
TIM1_TRGOSOURCE_UPDATE
TIM1_TRGOSource_OC1
TIM1_TRGOSOURCE_OC1REF
TIM1_TRGOSOURCE_OC2REF
TIM1_TRGOSOURCE_OC3REF

Definition at line 402 of file stm8s_tim1.h.

enum TIM1_TS_TypeDef

TIM1 Internal Trigger Selection.

Enumerator:
TIM1_TS_TIM6

TRIG Input source = TIM6 TRIG Output

TIM1_TS_TIM5

TRIG Input source = TIM5 TRIG Output

TIM1_TS_TI1F_ED
TIM1_TS_TI1FP1
TIM1_TS_TI2FP2
TIM1_TS_ETRF

Definition at line 310 of file stm8s_tim1.h.

enum TIM1_UpdateSource_TypeDef

TIM1 Update Source.

Enumerator:
TIM1_UPDATESOURCE_GLOBAL
TIM1_UPDATESOURCE_REGULAR

Definition at line 392 of file stm8s_tim1.h.


STM8S/A Standard Peripherals Drivers: TIM1_Exported_Functions

Functions

TIM1_Exported_Functions

STM8S_StdPeriph_Driver

Functions

void | TIM1_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM1 peripheral Preload register on ARR.
void | TIM1_BDTRConfig (TIM1_OSSIState_TypeDef TIM1_OSSIState, TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime, TIM1_BreakState_TypeDef TIM1_Break, TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).
void | TIM1_CCPreloadControl (FunctionalState NewState)
Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
void | TIM1_CCxCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
void | TIM1_CCxNCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
void | TIM1_ClearFlag (TIM1_FLAG_TypeDef TIM1_FLAG)
Clears the TIM1’s pending flags.
void | TIM1_ClearITPendingBit (TIM1_IT_TypeDef TIM1_IT)
Clears the TIM1's interrupt pending bits.
void | TIM1_Cmd (FunctionalState NewState)
Enables or disables the TIM1 peripheral.
void | TIM1_CounterModeConfig (TIM1_CounterMode_TypeDef TIM1_CounterMode)
Specifies the TIM1 Counter Mode to be used.
void | TIM1_CtrlPWMOutputs (FunctionalState NewState)
Enables or disables the TIM1 peripheral Main Outputs.
void | TIM1_DeInit (void)
Deinitializes the TIM1 peripheral registers to their default reset values.
void | TIM1_EncoderInterfaceConfig (TIM1_EncoderMode_TypeDef TIM1_EncoderMode, TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
Configures the TIM1 Encoder Interface.
void | TIM1_ETRClockMode1Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode1.
void | TIM1_ETRClockMode2Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode2.
void | TIM1_ETRConfig (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External Trigger.
void | TIM1_ForcedOC1Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel1 output waveform to active or inactive level.
void | TIM1_ForcedOC2Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel2 output waveform to active or inactive level.
void | TIM1_ForcedOC3Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel3 output waveform to active or inactive level.
void | TIM1_ForcedOC4Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel4 output waveform to active or inactive level.
void | TIM1_GenerateEvent (TIM1_EventSource_TypeDef TIM1_EventSource)
Configures the TIM1 event to be generated by software.
uint16_t | TIM1_GetCapture1 (void)
Gets the TIM1 Input Capture 1 value.
uint16_t | TIM1_GetCapture2 (void)
Gets the TIM1 Input Capture 2 value.
uint16_t | TIM1_GetCapture3 (void)
Gets the TIM1 Input Capture 3 value.
uint16_t | TIM1_GetCapture4 (void)
Gets the TIM1 Input Capture 4 value.
uint16_t | TIM1_GetCounter (void)
Gets the TIM1 Counter value.
FlagStatus | TIM1_GetFlagStatus (TIM1_FLAG_TypeDef TIM1_FLAG)
Checks whether the specified TIM1 flag is set or not.
ITStatus | TIM1_GetITStatus (TIM1_IT_TypeDef TIM1_IT)
Checks whether the TIM1 interrupt has occurred or not.
uint16_t | TIM1_GetPrescaler (void)
Gets the TIM1 Prescaler value.
void | TIM1_ICInit (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Initializes the TIM1 peripheral according to the specified parameters.
void | TIM1_InternalClockConfig (void)
Configures the TIM1 internal Clock.
void | TIM1_ITConfig (TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState)
Enables or disables the specified TIM1 interrupts.
void | TIM1_OC1FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 1 Fast feature.
void | TIM1_OC1Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel1 according to the specified parameters.
void | TIM1_OC1NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 1N polarity.
void | TIM1_OC1PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 1 polarity.
void | TIM1_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR1.
void | TIM1_OC2FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 2 Fast feature.
void | TIM1_OC2Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel2 according to the specified parameters.
void | TIM1_OC2NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 2N polarity.
void | TIM1_OC2PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 2 polarity.
void | TIM1_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR2.
void | TIM1_OC3FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 3 Fast feature.
void | TIM1_OC3Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel3 according to the specified parameters.
void | TIM1_OC3NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 3N polarity.
void | TIM1_OC3PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 3 polarity.
void | TIM1_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR3.
void | TIM1_OC4FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 4 Fast feature.
void | TIM1_OC4Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
Initializes the TIM1 Channel4 according to the specified parameters.
void | TIM1_OC4PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 4 polarity.
void | TIM1_OC4PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR4.
void | TIM1_PrescalerConfig (uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
Configures the TIM1 Prescaler.
void | TIM1_PWMIConfig (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.
void | TIM1_SelectCOM (FunctionalState NewState)
Selects the TIM1 peripheral Commutation event.
void | TIM1_SelectHallSensor (FunctionalState NewState)
Enables or Disables the TIM1’s Hall sensor interface.
void | TIM1_SelectInputTrigger (TIM1_TS_TypeDef TIM1_InputTriggerSource)
Selects the TIM1 Input Trigger source.
void | TIM1_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM1 Master/Slave Mode.
void | TIM1_SelectOCxM (TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
Selects the TIM1 Output Compare Mode.
void | TIM1_SelectOnePulseMode (TIM1_OPMode_TypeDef TIM1_OPMode)
Selects the TIM1’s One Pulse Mode.
void | TIM1_SelectOutputTrigger (TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
Selects the TIM1 Trigger Output Mode.
void | TIM1_SelectSlaveMode (TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
Selects the TIM1 Slave Mode.
void | TIM1_SetAutoreload (uint16_t Autoreload)
Sets the TIM1 Autoreload Register value.
void | TIM1_SetCompare1 (uint16_t Compare1)
Sets the TIM1 Capture Compare1 Register value.
void | TIM1_SetCompare2 (uint16_t Compare2)
Sets the TIM1 Capture Compare2 Register value.
void | TIM1_SetCompare3 (uint16_t Compare3)
Sets the TIM1 Capture Compare3 Register value.
void | TIM1_SetCompare4 (uint16_t Compare4)
Sets the TIM1 Capture Compare4 Register value.
void | TIM1_SetCounter (uint16_t Counter)
Sets the TIM1 Counter Register value.
void | TIM1_SetIC1Prescaler (TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
Sets the TIM1 Input Capture 1 prescaler.
void | TIM1_SetIC2Prescaler (TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
Sets the TIM1 Input Capture 2 prescaler.
void | TIM1_SetIC3Prescaler (TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
Sets the TIM1 Input Capture 3 prescaler.
void | TIM1_SetIC4Prescaler (TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
Sets the TIM1 Input Capture 4 prescaler.
void | TIM1_TimeBaseInit (uint16_t TIM1_Prescaler, TIM1_CounterMode_TypeDef TIM1_CounterMode, uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter)
Initializes the TIM1 Time Base Unit according to the specified parameters.
void | TIM1_TIxExternalClockConfig (TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, uint8_t ICFilter)
Configures the TIM1 Trigger as External Clock.
void | TIM1_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM1 Update event.
void | TIM1_UpdateRequestConfig (TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
Selects the TIM1 Update Request Interrupt source.

Function Documentation

void TIM1_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM1 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM1 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1157 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_ARPE.

void TIM1_BDTRConfig | ( | TIM1_OSSIState_TypeDef | TIM1_OSSIState,
 |  | TIM1_LockLevel_TypeDef | TIM1_LockLevel,
 |  | uint8_t | TIM1_DeadTime,
 |  | TIM1_BreakState_TypeDef | TIM1_Break,
 |  | TIM1_BreakPolarity_TypeDef | TIM1_BreakPolarity,
 |  | TIM1_AutomaticOutput_TypeDef | TIM1_AutomaticOutput
 | ) |  |

Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).

Parameters:
TIM1_OSSIState | specifies the OSSIS State from TIM1_OSSIState_TypeDef.
TIM1_LockLevel | specifies the lock level from TIM1_LockLevel_TypeDef.
TIM1_DeadTime | specifies the dead time value.
TIM1_Break | specifies the Break state TIM1_BreakState_TypeDef.
TIM1_BreakPolarity | specifies the Break polarity from TIM1_BreakPolarity_TypeDef.
TIM1_AutomaticOutput | specifies the Automatic Output configuration from TIM1_AutomaticOutput_TypeDef.
Return values:
None

Definition at line 387 of file stm8s_tim1.c.

References IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK, IS_TIM1_BREAK_POLARITY_OK, IS_TIM1_BREAK_STATE_OK, IS_TIM1_LOCK_LEVEL_OK, IS_TIM1_OSSI_STATE_OK, and TIM1.

void TIM1_CCPreloadControl ( FunctionalState NewState )

Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.

Parameters:
NewState new state of the Capture Compare Preload Control bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1202 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_CCPC.

void TIM1_CCxCmd | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:

  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
  • TIM1_CHANNEL_4: TIM1 Channel4
NewState specifies the TIM1 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1613 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_CHANNEL_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC2E, TIM1_CCER2_CC3E, TIM1_CCER2_CC4E, TIM1_CHANNEL_1, TIM1_CHANNEL_2, and TIM1_CHANNEL_3.

void TIM1_CCxNCmd | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:

  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
NewState specifies the TIM1 Channel CCxNE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1681 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_COMPLEMENTARY_CHANNEL_OK, TIM1, TIM1_CCER1_CC1NE, TIM1_CCER1_CC2NE, TIM1_CCER2_CC3NE, TIM1_CHANNEL_1, and TIM1_CHANNEL_2.

void TIM1_ClearFlag ( TIM1_FLAG_TypeDef TIM1_FLAG )

Clears the TIM1’s pending flags.

Parameters:
TIM1_FLAG specifies the flag to clear. This parameter can be one of the following values:

  • TIM1_FLAG_UPDATE: TIM1 update Flag
  • TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
  • TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
  • TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
  • TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
  • TIM1_FLAG_COM: TIM1 Commutation Flag
  • TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
  • TIM1_FLAG_BREAK: TIM1 Break Flag
  • TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
  • TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
  • TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
  • TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
Return values:
None.

Definition at line 2137 of file stm8s_tim1.c.

References IS_TIM1_CLEAR_FLAG_OK, and TIM1.

void TIM1_ClearITPendingBit ( TIM1_IT_TypeDef TIM1_IT )

Clears the TIM1's interrupt pending bits.

Parameters:
TIM1_IT specifies the pending bit to clear. This parameter can be one of the following values:

  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_COM: TIM1 Commutation Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
Return values:
None.

Definition at line 2199 of file stm8s_tim1.c.

References IS_TIM1_IT_OK, and TIM1.

void TIM1_Cmd ( FunctionalState NewState )

Enables or disables the TIM1 peripheral.

Parameters:
NewState new state of the TIM1 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 563 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_CEN.

void TIM1_CounterModeConfig ( TIM1_CounterMode_TypeDef TIM1_CounterMode )

Specifies the TIM1 Counter Mode to be used.

Parameters:
TIM1_CounterMode specifies the Counter Mode to be used This parameter can be one of the following values:

  • TIM1_COUNTERMODE_UP: TIM1 Up Counting Mode
  • TIM1_COUNTERMODE_DOWN: TIM1 Down Counting Mode
  • TIM1_COUNTERMODE_CENTERALIGNED1: TIM1 Center Aligned Mode1
  • TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
  • TIM1_COUNTERMODE_CENTERALIGNED3: TIM1 Center Aligned Mode3
Return values:
None

Definition at line 1061 of file stm8s_tim1.c.

References IS_TIM1_COUNTER_MODE_OK, TIM1, TIM1_CR1_CMS, and TIM1_CR1_DIR.

void TIM1_CtrlPWMOutputs ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Main Outputs.

Parameters:
NewState new state of the TIM1 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 585 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_BKR_MOE.

void TIM1_DeInit ( void )

Deinitializes the TIM1 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 52 of file stm8s_tim1.c.

References TIM1, TIM1_ARRH_RESET_VALUE, TIM1_ARRL_RESET_VALUE, TIM1_BKR_RESET_VALUE, TIM1_CCER1_RESET_VALUE, TIM1_CCER2_RESET_VALUE, TIM1_CCMR1_RESET_VALUE, TIM1_CCMR2_RESET_VALUE, TIM1_CCMR3_RESET_VALUE, TIM1_CCMR4_RESET_VALUE, TIM1_CCR1H_RESET_VALUE, TIM1_CCR1L_RESET_VALUE, TIM1_CCR2H_RESET_VALUE, TIM1_CCR2L_RESET_VALUE, TIM1_CCR3H_RESET_VALUE, TIM1_CCR3L_RESET_VALUE, TIM1_CCR4H_RESET_VALUE, TIM1_CCR4L_RESET_VALUE, TIM1_CNTRH_RESET_VALUE, TIM1_CNTRL_RESET_VALUE, TIM1_CR1_RESET_VALUE, TIM1_CR2_RESET_VALUE, TIM1_DTR_RESET_VALUE, TIM1_ETR_RESET_VALUE, TIM1_IER_RESET_VALUE, TIM1_OISR_RESET_VALUE, TIM1_PSCRH_RESET_VALUE, TIM1_PSCRL_RESET_VALUE, TIM1_RCR_RESET_VALUE, TIM1_SMCR_RESET_VALUE, TIM1_SR1_RESET_VALUE, and TIM1_SR2_RESET_VALUE.

void TIM1_EncoderInterfaceConfig | ( | TIM1_EncoderMode_TypeDef | TIM1_EncoderMode,
 |  | TIM1_ICPolarity_TypeDef | TIM1_IC1Polarity,
 |  | TIM1_ICPolarity_TypeDef | TIM1_IC2Polarity
 | ) |  |

Configures the TIM1 Encoder Interface.

Parameters:
TIM1_EncoderMode specifies the TIM1 Encoder Mode. This parameter can be one of the following values

  • TIM1_ENCODERMODE_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
  • TIM1_ENCODERMODE_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
  • TIM1_ENCODERMODE_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
TIM1_IC1Polarity specifies the IC1 Polarity. This parameter can be one of the following values

  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_IC2Polarity specifies the IC2 Polarity. This parameter can be one of the following values

  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
Return values:
None

Definition at line 983 of file stm8s_tim1.c.

References CCMR_TIxDirect_Set, IS_TIM1_ENCODER_MODE_OK, IS_TIM1_IC_POLARITY_OK, TIM1, TIM1_CCER1_CC1P, TIM1_CCER1_CC2P, TIM1_CCMR_CCxS, TIM1_ICPOLARITY_RISING, TIM1_SMCR_MSM, and TIM1_SMCR_TS.

void TIM1_ETRClockMode1Config | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External clock Mode1.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:

  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:

  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 664 of file stm8s_tim1.c.

References IS_TIM1_EXT_POLARITY_OK, IS_TIM1_EXT_PRESCALER_OK, TIM1, TIM1_ETRConfig(), TIM1_SLAVEMODE_EXTERNAL1, TIM1_SMCR_SMS, TIM1_SMCR_TS, and TIM1_TS_ETRF.

void TIM1_ETRClockMode2Config | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External clock Mode2.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:

  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:

  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 696 of file stm8s_tim1.c.

References IS_TIM1_EXT_POLARITY_OK, IS_TIM1_EXT_PRESCALER_OK, TIM1, TIM1_ETR_ECE, and TIM1_ETRConfig().

void TIM1_ETRConfig | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External Trigger.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:

  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:

  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 727 of file stm8s_tim1.c.

References IS_TIM1_EXT_TRG_FILTER_OK, and TIM1.

Referenced by TIM1_ETRClockMode1Config(), and TIM1_ETRClockMode2Config().

void TIM1_ForcedOC1Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel1 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 1081 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC2Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel2 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 1100 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC3Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel3 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 1120 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC4Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel4 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC4REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC4REF.
Return values:
None

Definition at line 1140 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_GenerateEvent ( TIM1_EventSource_TypeDef TIM1_EventSource )

Configures the TIM1 event to be generated by software.

Parameters:
TIM1_EventSource specifies the event source. This parameter can be one of the following values:

  • TIM1_EVENTSOURCE_UPDATE: TIM1 update Event source
  • TIM1_EVENTSOURCE_CC1: TIM1 Capture Compare 1 Event source
  • TIM1_EVENTSOURCE_CC2: TIM1 Capture Compare 2 Event source
  • TIM1_EVENTSOURCE_CC3: TIM1 Capture Compare 3 Event source
  • TIM1_EVENTSOURCE_CC4: TIM1 Capture Compare 4 Event source
  • TIM1_EVENTSOURCE_COM: TIM1 COM Event source
  • TIM1_EVENTSOURCE_TRIGGER: TIM1 Trigger Event source
  • TIM1_EventSourceBreak: TIM1 Break Event source
Return values:
None

Definition at line 1418 of file stm8s_tim1.c.

References IS_TIM1_EVENT_SOURCE_OK, and TIM1.

uint16_t TIM1_GetCapture1 ( void )

Gets the TIM1 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 1972 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture2 ( void )

Gets the TIM1 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 1993 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture3 ( void )

Gets the TIM1 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 2014 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture4 ( void )

Gets the TIM1 Input Capture 4 value.

Parameters:
None
Return values:
Capture Compare 4 Register value.

Definition at line 2034 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCounter ( void )

Gets the TIM1 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 2054 of file stm8s_tim1.c.

References TIM1.

FlagStatus TIM1_GetFlagStatus ( TIM1_FLAG_TypeDef TIM1_FLAG )

Checks whether the specified TIM1 flag is set or not.

Parameters:
TIM1_FLAG specifies the flag to check. This parameter can be one of the following values:

  • TIM1_FLAG_UPDATE: TIM1 update Flag
  • TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
  • TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
  • TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
  • TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
  • TIM1_FLAG_COM: TIM1 Commutation Flag
  • TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
  • TIM1_FLAG_BREAK: TIM1 Break Flag
  • TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
  • TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
  • TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
  • TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
Return values:
FlagStatus The new state of TIM1_FLAG (SET or RESET).

Definition at line 2097 of file stm8s_tim1.c.

References IS_TIM1_GET_FLAG_OK, RESET, SET, and TIM1.

ITStatus TIM1_GetITStatus ( TIM1_IT_TypeDef TIM1_IT )

Checks whether the TIM1 interrupt has occurred or not.

Parameters:
TIM1_IT specifies the TIM1 interrupt source to check. This parameter can be one of the following values:

  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_COM: TIM1 Commutation Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
Return values:
ITStatus The new state of the TIM1_IT(SET or RESET).

Definition at line 2162 of file stm8s_tim1.c.

References IS_TIM1_GET_IT_OK, RESET, SET, and TIM1.

uint16_t TIM1_GetPrescaler ( void )

Gets the TIM1 Prescaler value.

Parameters:
None
Return values:
Prescaler Register value.

Definition at line 2069 of file stm8s_tim1.c.

References TIM1.

void TIM1_ICInit | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | TIM1_ICSelection_TypeDef | TIM1_ICSelection,
 |  | TIM1_ICPSC_TypeDef | TIM1_ICPrescaler,
 |  | uint8_t | TIM1_ICFilter
 | ) |  |

Initializes the TIM1 peripheral according to the specified parameters.

Parameters:
TIM1_Channel | specifies the input capture channel from TIM1_Channel_TypeDef.
TIM1_ICPolarity | specifies the Input capture polarity from TIM1_ICPolarity_TypeDef .
TIM1_ICSelection | specifies the Input capture source selection from TIM1_ICSelection_TypeDef.
TIM1_ICPrescaler | specifies the Input capture Prescaler from TIM1_ICPSC_TypeDef.
TIM1_ICFilter | specifies the Input capture filter value.
Return values:
None

Definition at line 423 of file stm8s_tim1.c.

References IS_TIM1_CHANNEL_OK, IS_TIM1_IC_FILTER_OK, IS_TIM1_IC_POLARITY_OK, IS_TIM1_IC_PRESCALER_OK, IS_TIM1_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM1_CHANNEL_1, TIM1_CHANNEL_2, TIM1_CHANNEL_3, TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), and TIM1_SetIC4Prescaler().

void TIM1_InternalClockConfig ( void )

Configures the TIM1 internal Clock.

Parameters:
None
Return values:
None

Definition at line 642 of file stm8s_tim1.c.

References TIM1, and TIM1_SMCR_SMS.

void TIM1_ITConfig | ( | TIM1_IT_TypeDef | TIM1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM1 interrupts.

Parameters:
NewState | new state of the TIM1 peripheral. This parameter can be: ENABLE or DISABLE.
TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
NewState | new state of the TIM1 peripheral.
Return values:
None

Definition at line 619 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_IT_OK, and TIM1.

void TIM1_OC1FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 1 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1317 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC1Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel1 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 150 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC1NE, TIM1_CCER1_CC1NP, TIM1_CCER1_CC1P, TIM1_CCMR_OCM, TIM1_OISR_OIS1, and TIM1_OISR_OIS1N.

void TIM1_OC1NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 1N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC1N Polarity. This parameter can be one of the following values:

  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1461 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER1_CC1NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC1PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 1 polarity.

Parameters:
TIM1_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:

  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1436 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER1_CC1P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1225 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC2FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 2 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1341 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC2Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel2 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 213 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER1_CC2E, TIM1_CCER1_CC2NE, TIM1_CCER1_CC2NP, TIM1_CCER1_CC2P, TIM1_CCMR_OCM, TIM1_OISR_OIS2, and TIM1_OISR_OIS2N.

void TIM1_OC2NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 2N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC2N Polarity. This parameter can be one of the following values:

  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1510 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER1_CC2NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC2PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 2 polarity.

Parameters:
TIM1_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:

  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1486 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER1_CC2P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1248 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC3FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 3 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1364 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC3Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel3 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 278 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER2_CC3E, TIM1_CCER2_CC3NE, TIM1_CCER2_CC3NP, TIM1_CCER2_CC3P, TIM1_CCMR_OCM, TIM1_OISR_OIS3, and TIM1_OISR_OIS3N.

void TIM1_OC3NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 3N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC3N Polarity. This parameter can be one of the following values:

  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1560 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER2_CC3NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC3PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 3 polarity.

Parameters:
TIM1_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:

  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1535 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER2_CC3P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1271 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC4FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 4 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1387 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC4Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState
 | ) |  |

Initializes the TIM1 Channel4 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 336 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, TIM1, TIM1_CCER2_CC4E, TIM1_CCER2_CC4P, TIM1_CCMR_OCM, TIM1_OCIDLESTATE_RESET, and TIM1_OISR_OIS4.

void TIM1_OC4PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 4 polarity.

Parameters:
TIM1_OCPolarity specifies the OC4 Polarity. This parameter can be one of the following values:

  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1584 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER2_CC4P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC4PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR4.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1295 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_PrescalerConfig | ( | uint16_t | Prescaler,
 |  | TIM1_PSCReloadMode_TypeDef | TIM1_PSCReloadMode
 | ) |  |

Configures the TIM1 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter must be a value between 0x0000 and 0xFFFF
TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode. This parameter can be one of the following values

  • TIM1_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM1_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 1035 of file stm8s_tim1.c.

References IS_TIM1_PRESCALER_RELOAD_OK, and TIM1.

void TIM1_PWMIConfig | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | TIM1_ICSelection_TypeDef | TIM1_ICSelection,
 |  | TIM1_ICPSC_TypeDef | TIM1_ICPrescaler,
 |  | uint8_t | TIM1_ICFilter
 | ) |  |

Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM1_Channel | specifies the input capture channel from TIM1_Channel_TypeDef.
TIM1_ICPolarity | specifies the Input capture polarity from TIM1_ICPolarity_TypeDef .
TIM1_ICSelection | specifies the Input capture source selection from TIM1_ICSelection_TypeDef.
TIM1_ICPrescaler | specifies the Input capture Prescaler from TIM1_ICPSC_TypeDef.
TIM1_ICFilter | specifies the Input capture filter value.
Return values:
None

Definition at line 490 of file stm8s_tim1.c.

References IS_TIM1_IC_POLARITY_OK, IS_TIM1_IC_PRESCALER_OK, IS_TIM1_IC_SELECTION_OK, IS_TIM1_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM1_CHANNEL_1, TIM1_ICPOLARITY_FALLING, TIM1_ICPOLARITY_RISING, TIM1_ICSELECTION_DIRECTTI, TIM1_ICSELECTION_INDIRECTTI, TIM1_SetIC1Prescaler(), and TIM1_SetIC2Prescaler().

void TIM1_SelectCOM ( FunctionalState NewState )

Selects the TIM1 peripheral Commutation event.

Parameters:
NewState new state of the Commutation event. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1180 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_COMS.

void TIM1_SelectHallSensor ( FunctionalState NewState )

Enables or Disables the TIM1’s Hall sensor interface.

Parameters:
NewState new state of the TIM1 Hall sensor interface.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 853 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_TI1S.

void TIM1_SelectInputTrigger ( TIM1_TS_TypeDef TIM1_InputTriggerSource )

Selects the TIM1 Input Trigger source.

Parameters:
TIM1_InputTriggerSource specifies Input Trigger source. This parameter can be one of the following values:

  • TIM1_TS_TI1F_ED: TI1 Edge Detector
  • TIM1_TS_TI1FP1: Filtered Timer Input 1
  • TIM1_TS_TI2FP2: Filtered Timer Input 2
  • TIM1_TS_ETRF: External Trigger input
Return values:
None

Definition at line 789 of file stm8s_tim1.c.

References IS_TIM1_TRIGGER_SELECTION_OK, TIM1, and TIM1_SMCR_TS.

Referenced by TIM1_TIxExternalClockConfig().

void TIM1_SelectMasterSlaveMode ( FunctionalState NewState )

Sets or Resets the TIM1 Master/Slave Mode.

Parameters:
NewState new state of the synchronization between TIM1 and its slaves (through TRGO). This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 947 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_SMCR_MSM.

void TIM1_SelectOCxM | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_OCMode_TypeDef | TIM1_OCMode
 | ) |  |

Selects the TIM1 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions.

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:

  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
  • TIM1_CHANNEL_4: TIM1 Channel4
TIM1_OCMode specifies the TIM1 Output Compare Mode. This paramter can be one of the following values:

  • TIM1_OCMODE_TIMING
  • TIM1_OCMODE_ACTIVE
  • TIM1_OCMODE_TOGGLE
  • TIM1_OCMODE_PWM1
  • TIM1_OCMODE_PWM2
  • TIM1_FORCEDACTION_ACTIVE
  • TIM1_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 1747 of file stm8s_tim1.c.

References IS_TIM1_CHANNEL_OK, IS_TIM1_OCM_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC2E, TIM1_CCER2_CC3E, TIM1_CCER2_CC4E, TIM1_CCMR_OCM, TIM1_CHANNEL_1, TIM1_CHANNEL_2, and TIM1_CHANNEL_3.

void TIM1_SelectOnePulseMode ( TIM1_OPMode_TypeDef TIM1_OPMode )

Selects the TIM1’s One Pulse Mode.

Parameters:
TIM1_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values

  • TIM1_OPMODE_SINGLE
  • TIM1_OPMODE_REPETITIVE
Return values:
None

Definition at line 878 of file stm8s_tim1.c.

References IS_TIM1_OPM_MODE_OK, TIM1, TIM1_CR1_OPM, and TIM1_OPMODE_REPETITIVE.

void TIM1_SelectOutputTrigger ( TIM1_TRGOSource_TypeDef TIM1_TRGOSource )

Selects the TIM1 Trigger Output Mode.

Parameters:
TIM1_TRGOSource specifies the Trigger Output source. This parameter can be one of the following values

  • TIM1_TRGOSOURCE_RESET
  • TIM1_TRGOSOURCE_ENABLE
  • TIM1_TRGOSOURCE_UPDATE
  • TIM1_TRGOSource_OC1
  • TIM1_TRGOSOURCE_OC1REF
  • TIM1_TRGOSOURCE_OC2REF
  • TIM1_TRGOSOURCE_OC3REF
Return values:
None

Definition at line 909 of file stm8s_tim1.c.

References IS_TIM1_TRGO_SOURCE_OK, TIM1, and TIM1_CR2_MMS.

void TIM1_SelectSlaveMode ( TIM1_SlaveMode_TypeDef TIM1_SlaveMode )

Selects the TIM1 Slave Mode.

Parameters:
TIM1_SlaveMode specifies the TIM1 Slave Mode. This parameter can be one of the following values

  • TIM1_SLAVEMODE_RESET
  • TIM1_SLAVEMODE_GATED
  • TIM1_SLAVEMODE_TRIGGER
  • TIM1_SLAVEMODE_EXTERNAL1
Return values:
None

Definition at line 929 of file stm8s_tim1.c.

References IS_TIM1_SLAVE_MODE_OK, TIM1, and TIM1_SMCR_SMS.

void TIM1_SetAutoreload ( uint16_t Autoreload )

Sets the TIM1 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1813 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare1 ( uint16_t Compare1 )

Sets the TIM1 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1829 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare2 ( uint16_t Compare2 )

Sets the TIM1 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1844 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare3 ( uint16_t Compare3 )

Sets the TIM1 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1859 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare4 ( uint16_t Compare4 )

Sets the TIM1 Capture Compare4 Register value.

Parameters:
Compare4 specifies the Capture Compare4 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1874 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCounter ( uint16_t Counter )

Sets the TIM1 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1798 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetIC1Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC1Prescaler )

Sets the TIM1 Input Capture 1 prescaler.

Parameters:
TIM1_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1892 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit(), and TIM1_PWMIConfig().

void TIM1_SetIC2Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC2Prescaler )

Sets the TIM1 Input Capture 2 prescaler.

Parameters:
TIM1_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1913 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit(), and TIM1_PWMIConfig().

void TIM1_SetIC3Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC3Prescaler )

Sets the TIM1 Input Capture 3 prescaler.

Parameters:
TIM1_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1935 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit().

void TIM1_SetIC4Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC4Prescaler )

Sets the TIM1 Input Capture 4 prescaler.

Parameters:
TIM1_IC4Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1956 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit().

void TIM1_TimeBaseInit | ( | uint16_t | TIM1_Prescaler,
 |  | TIM1_CounterMode_TypeDef | TIM1_CounterMode,
 |  | uint16_t | TIM1_Period,
 |  | uint8_t | TIM1_RepetitionCounter
 | ) |  |

Initializes the TIM1 Time Base Unit according to the specified parameters.

Parameters:
TIM1_Prescaler | specifies the Prescaler value.
TIM1_CounterMode | specifies the counter mode from TIM1_CounterMode_TypeDef .
TIM1_Period | specifies the Period value.
TIM1_RepetitionCounter | specifies the Repetition counter value
Return values:
None

Definition at line 105 of file stm8s_tim1.c.

References IS_TIM1_COUNTER_MODE_OK, TIM1, TIM1_CR1_CMS, and TIM1_CR1_DIR.

void TIM1_TIxExternalClockConfig | ( | TIM1_TIxExternalCLK1Source_TypeDef | TIM1_TIxExternalCLKSource,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | uint8_t | ICFilter
 | ) |  |

Configures the TIM1 Trigger as External Clock.

Parameters:
TIM1_TIxExternalCLKSource specifies Trigger source. This parameter can be one of the following values:

  • TIM1_TIXEXTERNALCLK1SOURCE_TI1: TI1 Edge Detector
  • TIM1_TIXEXTERNALCLK1SOURCE_TI2: Filtered TIM1 Input 1
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1ED: Filtered TIM1 Input 2
TIM1_ICPolarity specifies the TIx Polarity. This parameter can be:

  • TIM1_ICPOLARITY_RISING
  • TIM1_ICPOLARITY_FALLING
ICFilter specifies the filter value. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 753 of file stm8s_tim1.c.

References IS_TIM1_IC_FILTER_OK, IS_TIM1_IC_POLARITY_OK, IS_TIM1_TIXCLK_SOURCE_OK, TI1_Config(), TI2_Config(), TIM1, TIM1_ICSELECTION_DIRECTTI, TIM1_SelectInputTrigger(), TIM1_SLAVEMODE_EXTERNAL1, and TIM1_TIXEXTERNALCLK1SOURCE_TI2.

void TIM1_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM1 Update event.

Parameters:
NewState new state of the TIM1 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 806 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_UDIS.

void TIM1_UpdateRequestConfig ( TIM1_UpdateSource_TypeDef TIM1_UpdateSource )

Selects the TIM1 Update Request Interrupt source.

Parameters:
TIM1_UpdateSource specifies the Update source. This parameter can be one of the following values

  • TIM1_UPDATESOURCE_REGULAR
  • TIM1_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 830 of file stm8s_tim1.c.

References IS_TIM1_UPDATE_SOURCE_OK, TIM1, TIM1_CR1_URS, and TIM1_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM3_Exported_Types

Defines | Enumerations

TIM3_Exported_Types

STM8S_StdPeriph_Driver

Defines

#define | IS_TIM3_CHANNEL_OK(CHANNEL)
#define | IS_TIM3_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF9F8) == 0x0000) && ((uint16_t)(FLAG)!= 0x0000))
#define | IS_TIM3_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM3_FORCED_ACTION_OK(ACTION)
#define | IS_TIM3_GET_FLAG_OK(FLAG)
#define | IS_TIM3_GET_IT_OK(IT)
#define | IS_TIM3_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM3 Input Capture Filer Value.
#define | IS_TIM3_IC_POLARITY_OK(POLARITY)
#define | IS_TIM3_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM3_IC_SELECTION_OK(SELECTION)
#define | IS_TIM3_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x07))
#define | IS_TIM3_OC_MODE_OK(MODE)
#define | IS_TIM3_OC_POLARITY_OK(POLARITY)
#define | IS_TIM3_OCM_OK(MODE)
#define | IS_TIM3_OPM_MODE_OK(MODE)
#define | IS_TIM3_OUTPUT_STATE_OK(STATE)
#define | IS_TIM3_PRESCALER_OK(PRESCALER)
#define | IS_TIM3_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM3_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM3_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM3_Channel_TypeDef { TIM3_CHANNEL_1 = ((uint8_t)0x00), TIM3_CHANNEL_2 = ((uint8_t)0x01) }

TIM3 Channel.

More...
enum | TIM3_EventSource_TypeDef { TIM3_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM3_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM3_EVENTSOURCE_CC2 = ((uint8_t)0x04) }

TIM3 Event Source.

More...
enum TIM3_FLAG_TypeDef {
TIM3_FLAG_UPDATE = ((uint16_t)0x0001), TIM3_FLAG_CC1 = ((uint16_t)0x0002), TIM3_FLAG_CC2 = ((uint16_t)0x0004), TIM3_FLAG_CC1OF = ((uint16_t)0x0200),
TIM3_FLAG_CC2OF = ((uint16_t)0x0400)
}

TIM3 Flags.

More...
enum | TIM3_ForcedAction_TypeDef { TIM3_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM3_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }

TIM3 Forced Action.

More...
enum | TIM3_ICPolarity_TypeDef { TIM3_ICPOLARITY_RISING = ((uint8_t)0x00), TIM3_ICPOLARITY_FALLING = ((uint8_t)0x44) }

TIM3 Input Capture Polarity.

More...
enum | TIM3_ICPSC_TypeDef { TIM3_ICPSC_DIV1 = ((uint8_t)0x00), TIM3_ICPSC_DIV2 = ((uint8_t)0x04), TIM3_ICPSC_DIV4 = ((uint8_t)0x08), TIM3_ICPSC_DIV8 = ((uint8_t)0x0C) }

TIM3 Input Capture Prescaler.

More...
enum | TIM3_ICSelection_TypeDef { TIM3_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM3_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM3_ICSELECTION_TRGI = ((uint8_t)0x03) }

TIM3 Input Capture Selection.

More...
enum | TIM3_IT_TypeDef { TIM3_IT_UPDATE = ((uint8_t)0x01), TIM3_IT_CC1 = ((uint8_t)0x02), TIM3_IT_CC2 = ((uint8_t)0x04) }

TIM3 interrupt sources.

More...
enum TIM3_OCMode_TypeDef {
TIM3_OCMODE_TIMING = ((uint8_t)0x00), TIM3_OCMODE_ACTIVE = ((uint8_t)0x10), TIM3_OCMODE_INACTIVE = ((uint8_t)0x20), TIM3_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM3_OCMODE_PWM1 = ((uint8_t)0x60), TIM3_OCMODE_PWM2 = ((uint8_t)0x70)
}

TIM3 Output Compare and PWM modes.

More...
enum | TIM3_OCPolarity_TypeDef { TIM3_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM3_OCPOLARITY_LOW = ((uint8_t)0x22) }

TIM3 Output Compare Polarity.

More...
enum | TIM3_OPMode_TypeDef { TIM3_OPMODE_SINGLE = ((uint8_t)0x01), TIM3_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM3 One Pulse Mode.

More...
enum | TIM3_OutputState_TypeDef { TIM3_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM3_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }

TIM3 Output Compare states.

More...
enum TIM3_Prescaler_TypeDef {
TIM3_PRESCALER_1 = ((uint8_t)0x00), TIM3_PRESCALER_2 = ((uint8_t)0x01), TIM3_PRESCALER_4 = ((uint8_t)0x02), TIM3_PRESCALER_8 = ((uint8_t)0x03),
TIM3_PRESCALER_16 = ((uint8_t)0x04), TIM3_PRESCALER_32 = ((uint8_t)0x05), TIM3_PRESCALER_64 = ((uint8_t)0x06), TIM3_PRESCALER_128 = ((uint8_t)0x07),
TIM3_PRESCALER_256 = ((uint8_t)0x08), TIM3_PRESCALER_512 = ((uint8_t)0x09), TIM3_PRESCALER_1024 = ((uint8_t)0x0A), TIM3_PRESCALER_2048 = ((uint8_t)0x0B),
TIM3_PRESCALER_4096 = ((uint8_t)0x0C), TIM3_PRESCALER_8192 = ((uint8_t)0x0D), TIM3_PRESCALER_16384 = ((uint8_t)0x0E), TIM3_PRESCALER_32768 = ((uint8_t)0x0F)
}

TIM3 Prescaler.

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enum | TIM3_PSCReloadMode_TypeDef { TIM3_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM3_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM3 Prescaler Reload Mode.

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enum | TIM3_UpdateSource_TypeDef { TIM3_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM3_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM3 Update Source.

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Define Documentation

#define IS_TIM3_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM3_CHANNEL_1) || \
                                     ((CHANNEL) == TIM3_CHANNEL_2))

Definition at line 132 of file stm8s_tim3.h.

Referenced by TIM3_CCxCmd(), TIM3_ICInit(), and TIM3_SelectOCxM().

#define IS_TIM3_CLEAR_FLAG_OK ( FLAG ) ((((uint16_t)(FLAG) & 0xF9F8) == 0x0000) && ((uint16_t)(FLAG)!= 0x0000))

Definition at line 257 of file stm8s_tim3.h.

Referenced by TIM3_ClearFlag().

#define IS_TIM3_EVENT_SOURCE_OK ( SOURCE ) (((SOURCE) != 0x00))

Definition at line 229 of file stm8s_tim3.h.

Referenced by TIM3_GenerateEvent().

#define IS_TIM3_FORCED_ACTION_OK ( ACTION )
Value:
(((ACTION) == TIM3_FORCEDACTION_ACTIVE) || \
    ((ACTION) == TIM3_FORCEDACTION_INACTIVE))

Definition at line 46 of file stm8s_tim3.h.

Referenced by TIM3_ForcedOC1Config(), and TIM3_ForcedOC2Config().

#define IS_TIM3_GET_FLAG_OK ( FLAG )
Value:
(((FLAG) == TIM3_FLAG_UPDATE) || \
                                   ((FLAG) == TIM3_FLAG_CC1) || \
                                   ((FLAG) == TIM3_FLAG_CC2) || \
                                   ((FLAG) == TIM3_FLAG_CC1OF) || \
                                   ((FLAG) == TIM3_FLAG_CC2OF) )

Definition at line 251 of file stm8s_tim3.h.

Referenced by TIM3_GetFlagStatus().

#define IS_TIM3_GET_IT_OK ( IT )
Value:
(((IT) == TIM3_IT_UPDATE) || \
                               ((IT) == TIM3_IT_CC1) || \
                               ((IT) == TIM3_IT_CC2))

Definition at line 207 of file stm8s_tim3.h.

Referenced by TIM3_GetITStatus().

#define IS_TIM3_IC_FILTER_OK ( ICFILTER ) ((ICFILTER) <= 0x0F)

TIM3 Input Capture Filer Value.

Definition at line 195 of file stm8s_tim3.h.

Referenced by TIM3_ICInit().

#define IS_TIM3_IC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM3_ICPOLARITY_RISING) || \
    ((POLARITY) == TIM3_ICPOLARITY_FALLING))

Definition at line 165 of file stm8s_tim3.h.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

#define IS_TIM3_IC_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM3_ICPSC_DIV1) || \
    ((PRESCALER) == TIM3_ICPSC_DIV2) || \
    ((PRESCALER) == TIM3_ICPSC_DIV4) || \
    ((PRESCALER) == TIM3_ICPSC_DIV8))

Definition at line 189 of file stm8s_tim3.h.

Referenced by TIM3_ICInit(), TIM3_PWMIConfig(), TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

#define IS_TIM3_IC_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM3_ICSELECTION_DIRECTTI) || \
    ((SELECTION) == TIM3_ICSELECTION_INDIRECTTI) || \
    ((SELECTION) == TIM3_ICSELECTION_TRGI))

Definition at line 176 of file stm8s_tim3.h.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

#define IS_TIM3_IT_OK ( IT ) (((IT) != 0x00) && ((IT) <= 0x07))

Definition at line 205 of file stm8s_tim3.h.

Referenced by TIM3_ClearITPendingBit(), and TIM3_ITConfig().

#define IS_TIM3_OC_MODE_OK ( MODE )
Value:
(((MODE) ==  TIM3_OCMODE_TIMING) || \
                                  ((MODE) == TIM3_OCMODE_ACTIVE) || \
                                  ((MODE) == TIM3_OCMODE_INACTIVE) || \
                                  ((MODE) == TIM3_OCMODE_TOGGLE)|| \
                                  ((MODE) == TIM3_OCMODE_PWM1) || \
                                  ((MODE) == TIM3_OCMODE_PWM2))

Definition at line 98 of file stm8s_tim3.h.

Referenced by TIM3_OC1Init(), and TIM3_OC2Init().

#define IS_TIM3_OC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM3_OCPOLARITY_HIGH) || \
    ((POLARITY) == TIM3_OCPOLARITY_LOW))

Definition at line 145 of file stm8s_tim3.h.

Referenced by TIM3_OC1Init(), TIM3_OC1PolarityConfig(), TIM3_OC2Init(), and TIM3_OC2PolarityConfig().

#define IS_TIM3_OCM_OK ( MODE )
Value:
(((MODE) ==  TIM3_OCMODE_TIMING) || \
                             ((MODE) == TIM3_OCMODE_ACTIVE) || \
                             ((MODE) == TIM3_OCMODE_INACTIVE) || \
                             ((MODE) == TIM3_OCMODE_TOGGLE)|| \
                             ((MODE) == TIM3_OCMODE_PWM1) || \
                             ((MODE) == TIM3_OCMODE_PWM2) || \
                             ((MODE) == (uint8_t)TIM3_FORCEDACTION_ACTIVE) || \
                             ((MODE) == (uint8_t)TIM3_FORCEDACTION_INACTIVE))

Definition at line 105 of file stm8s_tim3.h.

Referenced by TIM3_SelectOCxM().

#define IS_TIM3_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM3_OPMODE_SINGLE) || \
                                   ((MODE) == TIM3_OPMODE_REPETITIVE))

Definition at line 121 of file stm8s_tim3.h.

Referenced by TIM3_SelectOnePulseMode().

#define IS_TIM3_OUTPUT_STATE_OK ( STATE )
Value:
(((STATE) == TIM3_OUTPUTSTATE_DISABLE) || \
                                        ((STATE) == TIM3_OUTPUTSTATE_ENABLE))

Definition at line 155 of file stm8s_tim3.h.

Referenced by TIM3_OC1Init(), and TIM3_OC2Init().

#define IS_TIM3_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM3_PRESCALER_1  ) || \
    ((PRESCALER) == TIM3_PRESCALER_2    ) || \
    ((PRESCALER) == TIM3_PRESCALER_4    ) || \
    ((PRESCALER) == TIM3_PRESCALER_8  ) || \
    ((PRESCALER) == TIM3_PRESCALER_16   ) || \
    ((PRESCALER) == TIM3_PRESCALER_32     ) || \
    ((PRESCALER) == TIM3_PRESCALER_64    ) || \
    ((PRESCALER) == TIM3_PRESCALER_128   ) || \
    ((PRESCALER) == TIM3_PRESCALER_256   ) || \
    ((PRESCALER) == TIM3_PRESCALER_512   ) || \
    ((PRESCALER) == TIM3_PRESCALER_1024  ) || \
    ((PRESCALER) == TIM3_PRESCALER_2048 ) || \
    ((PRESCALER) == TIM3_PRESCALER_4096 ) || \
    ((PRESCALER) == TIM3_PRESCALER_8192 ) || \
    ((PRESCALER) == TIM3_PRESCALER_16384 ) || \
    ((PRESCALER) == TIM3_PRESCALER_32768 ))

Definition at line 70 of file stm8s_tim3.h.

Referenced by TIM3_PrescalerConfig().

#define IS_TIM3_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM3_PSCRELOADMODE_UPDATE) || \
    ((RELOAD) == TIM3_PSCRELOADMODE_IMMEDIATE))

Definition at line 218 of file stm8s_tim3.h.

Referenced by TIM3_PrescalerConfig().

#define IS_TIM3_PWMI_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM3_CHANNEL_1) || \
    ((CHANNEL) == TIM3_CHANNEL_2))

Definition at line 135 of file stm8s_tim3.h.

Referenced by TIM3_PWMIConfig().

#define IS_TIM3_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM3_UPDATESOURCE_GLOBAL) || \
    ((SOURCE) == TIM3_UPDATESOURCE_REGULAR))

Definition at line 238 of file stm8s_tim3.h.

Referenced by TIM3_UpdateRequestConfig().

Enumeration Type Documentation

enum TIM3_Channel_TypeDef

TIM3 Channel.

Enumerator:
TIM3_CHANNEL_1
TIM3_CHANNEL_2

Definition at line 126 of file stm8s_tim3.h.

enum TIM3_EventSource_TypeDef

TIM3 Event Source.

Enumerator:
TIM3_EVENTSOURCE_UPDATE
TIM3_EVENTSOURCE_CC1
TIM3_EVENTSOURCE_CC2

Definition at line 222 of file stm8s_tim3.h.

enum TIM3_FLAG_TypeDef

TIM3 Flags.

Enumerator:
TIM3_FLAG_UPDATE
TIM3_FLAG_CC1
TIM3_FLAG_CC2
TIM3_FLAG_CC1OF
TIM3_FLAG_CC2OF

Definition at line 242 of file stm8s_tim3.h.

enum TIM3_ForcedAction_TypeDef

TIM3 Forced Action.

Enumerator:
TIM3_FORCEDACTION_ACTIVE
TIM3_FORCEDACTION_INACTIVE

Definition at line 40 of file stm8s_tim3.h.

enum TIM3_ICPolarity_TypeDef

TIM3 Input Capture Polarity.

Enumerator:
TIM3_ICPOLARITY_RISING
TIM3_ICPOLARITY_FALLING

Definition at line 159 of file stm8s_tim3.h.

enum TIM3_ICPSC_TypeDef

TIM3 Input Capture Prescaler.

Enumerator:
TIM3_ICPSC_DIV1
TIM3_ICPSC_DIV2
TIM3_ICPSC_DIV4
TIM3_ICPSC_DIV8

Definition at line 181 of file stm8s_tim3.h.

enum TIM3_ICSelection_TypeDef

TIM3 Input Capture Selection.

Enumerator:
TIM3_ICSELECTION_DIRECTTI
TIM3_ICSELECTION_INDIRECTTI
TIM3_ICSELECTION_TRGI

Definition at line 169 of file stm8s_tim3.h.

enum TIM3_IT_TypeDef

TIM3 interrupt sources.

Enumerator:
TIM3_IT_UPDATE
TIM3_IT_CC1
TIM3_IT_CC2

Definition at line 198 of file stm8s_tim3.h.

enum TIM3_OCMode_TypeDef

TIM3 Output Compare and PWM modes.

Enumerator:
TIM3_OCMODE_TIMING
TIM3_OCMODE_ACTIVE
TIM3_OCMODE_INACTIVE
TIM3_OCMODE_TOGGLE
TIM3_OCMODE_PWM1
TIM3_OCMODE_PWM2

Definition at line 88 of file stm8s_tim3.h.

enum TIM3_OCPolarity_TypeDef

TIM3 Output Compare Polarity.

Enumerator:
TIM3_OCPOLARITY_HIGH
TIM3_OCPOLARITY_LOW

Definition at line 139 of file stm8s_tim3.h.

enum TIM3_OPMode_TypeDef

TIM3 One Pulse Mode.

Enumerator:
TIM3_OPMODE_SINGLE
TIM3_OPMODE_REPETITIVE

Definition at line 115 of file stm8s_tim3.h.

enum TIM3_OutputState_TypeDef

TIM3 Output Compare states.

Enumerator:
TIM3_OUTPUTSTATE_DISABLE
TIM3_OUTPUTSTATE_ENABLE

Definition at line 149 of file stm8s_tim3.h.

enum TIM3_Prescaler_TypeDef

TIM3 Prescaler.

Enumerator:
TIM3_PRESCALER_1
TIM3_PRESCALER_2
TIM3_PRESCALER_4
TIM3_PRESCALER_8
TIM3_PRESCALER_16
TIM3_PRESCALER_32
TIM3_PRESCALER_64
TIM3_PRESCALER_128
TIM3_PRESCALER_256
TIM3_PRESCALER_512
TIM3_PRESCALER_1024
TIM3_PRESCALER_2048
TIM3_PRESCALER_4096
TIM3_PRESCALER_8192
TIM3_PRESCALER_16384
TIM3_PRESCALER_32768

Definition at line 50 of file stm8s_tim3.h.

enum TIM3_PSCReloadMode_TypeDef

TIM3 Prescaler Reload Mode.

Enumerator:
TIM3_PSCRELOADMODE_UPDATE
TIM3_PSCRELOADMODE_IMMEDIATE

Definition at line 212 of file stm8s_tim3.h.

enum TIM3_UpdateSource_TypeDef

TIM3 Update Source.

Enumerator:
TIM3_UPDATESOURCE_GLOBAL
TIM3_UPDATESOURCE_REGULAR

Definition at line 232 of file stm8s_tim3.h.


STM8S/A Standard Peripherals Drivers: TIM3_Exported_Functions

Functions

TIM3_Exported_Functions

STM8S_StdPeriph_Driver

Functions

void | TIM3_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM3 peripheral Preload register on ARR.
void | TIM3_CCPreloadControl (FunctionalState NewState)
void | TIM3_CCxCmd (TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
Enables or disables the TIM3 Capture Compare Channel x.
void | TIM3_ClearFlag (TIM3_FLAG_TypeDef TIM3_FLAG)
Clears the TIM3’s pending flags.
void | TIM3_ClearITPendingBit (TIM3_IT_TypeDef TIM3_IT)
Clears the TIM3's interrupt pending bits.
void | TIM3_Cmd (FunctionalState NewState)
Enables or disables the TIM3 peripheral.
void | TIM3_DeInit (void)
Deinitializes the TIM3 peripheral registers to their default reset values.
void | TIM3_ForcedOC1Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel1 output waveform to active or inactive level.
void | TIM3_ForcedOC2Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel2 output waveform to active or inactive level.
void | TIM3_GenerateEvent (TIM3_EventSource_TypeDef TIM3_EventSource)
Configures the TIM3 event to be generated by software.
uint16_t | TIM3_GetCapture1 (void)
Gets the TIM3 Input Capture 1 value.
uint16_t | TIM3_GetCapture2 (void)
Gets the TIM3 Input Capture 2 value.
uint16_t | TIM3_GetCounter (void)
Gets the TIM3 Counter value.
FlagStatus | TIM3_GetFlagStatus (TIM3_FLAG_TypeDef TIM3_FLAG)
Checks whether the specified TIM3 flag is set or not.
ITStatus | TIM3_GetITStatus (TIM3_IT_TypeDef TIM3_IT)
Checks whether the TIM3 interrupt has occurred or not.
TIM3_Prescaler_TypeDef | TIM3_GetPrescaler (void)
Gets the TIM3 Prescaler value.
void | TIM3_ICInit (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Initializes the TIM3 peripheral according to the specified parameters.
void | TIM3_InternalClockConfig (void)
void | TIM3_ITConfig (TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
Enables or disables the specified TIM3 interrupts.
void | TIM3_OC1Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel1 according to the specified parameters.
void | TIM3_OC1PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 1 polarity.
void | TIM3_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR1.
void | TIM3_OC2Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel2 according to the specified parameters.
void | TIM3_OC2PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 2 polarity.
void | TIM3_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR2.
void | TIM3_PrescalerConfig (TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
Configures the TIM3 Prescaler.
void | TIM3_PWMIConfig (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.
void | TIM3_SelectOCxM (TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
Selects the TIM3 Output Compare Mode.
void | TIM3_SelectOnePulseMode (TIM3_OPMode_TypeDef TIM3_OPMode)
Selects the TIM3’s One Pulse Mode.
void | TIM3_SetAutoreload (uint16_t Autoreload)
Sets the TIM3 Autoreload Register value.
void | TIM3_SetCompare1 (uint16_t Compare1)
Sets the TIM3 Capture Compare1 Register value.
void | TIM3_SetCompare2 (uint16_t Compare2)
Sets the TIM3 Capture Compare2 Register value.
void | TIM3_SetCounter (uint16_t Counter)
Sets the TIM3 Counter Register value.
void | TIM3_SetIC1Prescaler (TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
Sets the TIM3 Input Capture 1 prescaler.
void | TIM3_SetIC2Prescaler (TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
Sets the TIM3 Input Capture 2 prescaler.
void | TIM3_TimeBaseInit (TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period)
Initializes the TIM3 Time Base Unit according to the specified parameters.
void | TIM3_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM3 Update event.
void | TIM3_UpdateRequestConfig (TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
Selects the TIM3 Update Request Interrupt source.

Function Documentation

void TIM3_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM3 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM3 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 486 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_ARPE.

void TIM3_CCPreloadControl ( FunctionalState NewState )
void TIM3_CCxCmd | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM3 Capture Compare Channel x.

Parameters:
TIM3_Channel specifies the TIM3 Channel. This parameter can be one of the following values:

  • TIM3_CHANNEL_1: TIM3 Channel1
  • TIM3_CHANNEL_2: TIM3 Channel2
NewState specifies the TIM3 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 627 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM3_CHANNEL_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC2E, and TIM3_CHANNEL_1.

void TIM3_ClearFlag ( TIM3_FLAG_TypeDef TIM3_FLAG )

Clears the TIM3’s pending flags.

Parameters:
TIM3_FLAG specifies the flag to clear. This parameter can be one of the following values:

  • TIM3_FLAG_UPDATE: TIM3 update Flag
  • TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
  • TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
  • TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
  • TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
Return values:
None.

Definition at line 911 of file stm8s_tim3.c.

References IS_TIM3_CLEAR_FLAG_OK.

void TIM3_ClearITPendingBit ( TIM3_IT_TypeDef TIM3_IT )

Clears the TIM3's interrupt pending bits.

Parameters:
TIM3_IT specifies the pending bit to clear. This parameter can be one of the following values:

  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
Return values:
None.

Definition at line 965 of file stm8s_tim3.c.

References IS_TIM3_IT_OK.

void TIM3_Cmd ( FunctionalState NewState )

Enables or disables the TIM3 peripheral.

Parameters:
NewState new state of the TIM3 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 280 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_CEN.

void TIM3_DeInit ( void )

Deinitializes the TIM3 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 45 of file stm8s_tim3.c.

References TIM3_ARRH_RESET_VALUE, TIM3_ARRL_RESET_VALUE, TIM3_CCER1_RESET_VALUE, TIM3_CCMR1_RESET_VALUE, TIM3_CCMR2_RESET_VALUE, TIM3_CCR1H_RESET_VALUE, TIM3_CCR1L_RESET_VALUE, TIM3_CCR2H_RESET_VALUE, TIM3_CCR2L_RESET_VALUE, TIM3_CNTRH_RESET_VALUE, TIM3_CNTRL_RESET_VALUE, TIM3_CR1_RESET_VALUE, TIM3_IER_RESET_VALUE, TIM3_PSCR_RESET_VALUE, TIM3_SR1_RESET_VALUE, and TIM3_SR2_RESET_VALUE.

void TIM3_ForcedOC1Config ( TIM3_ForcedAction_TypeDef TIM3_ForcedAction )

Forces the TIM3 Channel1 output waveform to active or inactive level.

Parameters:
TIM3_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM3_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM3_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 452 of file stm8s_tim3.c.

References IS_TIM3_FORCED_ACTION_OK, and TIM3_CCMR_OCM.

void TIM3_ForcedOC2Config ( TIM3_ForcedAction_TypeDef TIM3_ForcedAction )

Forces the TIM3 Channel2 output waveform to active or inactive level.

Parameters:
TIM3_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM3_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM3_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 470 of file stm8s_tim3.c.

References IS_TIM3_FORCED_ACTION_OK, and TIM3_CCMR_OCM.

void TIM3_GenerateEvent ( TIM3_EventSource_TypeDef TIM3_EventSource )

Configures the TIM3 event to be generated by software.

Parameters:
TIM3_EventSource specifies the event source. This parameter can be one of the following values:

  • TIM3_EVENTSOURCE_UPDATE: TIM3 update Event source
  • TIM3_EVENTSOURCE_CC1: TIM3 Capture Compare 1 Event source
  • TIM3_EVENTSOURCE_CC2: TIM3 Capture Compare 2 Event source
Return values:
None

Definition at line 557 of file stm8s_tim3.c.

References IS_TIM3_EVENT_SOURCE_OK.

uint16_t TIM3_GetCapture1 ( void )

Gets the TIM3 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 804 of file stm8s_tim3.c.

uint16_t TIM3_GetCapture2 ( void )

Gets the TIM3 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 824 of file stm8s_tim3.c.

uint16_t TIM3_GetCounter ( void )

Gets the TIM3 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 844 of file stm8s_tim3.c.

FlagStatus TIM3_GetFlagStatus ( TIM3_FLAG_TypeDef TIM3_FLAG )

Checks whether the specified TIM3 flag is set or not.

Parameters:
TIM3_FLAG specifies the flag to check. This parameter can be one of the following values:

  • TIM3_FLAG_UPDATE: TIM3 update Flag
  • TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
  • TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
  • TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
  • TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
Return values:
FlagStatus The new state of TIM3_FLAG (SET or RESET).

Definition at line 877 of file stm8s_tim3.c.

References IS_TIM3_GET_FLAG_OK, RESET, and SET.

ITStatus TIM3_GetITStatus ( TIM3_IT_TypeDef TIM3_IT )

Checks whether the TIM3 interrupt has occurred or not.

Parameters:
TIM3_IT specifies the TIM3 interrupt source to check. This parameter can be one of the following values:

  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
Return values:
ITStatus The new state of the TIM3_IT(SET or RESET).

Definition at line 932 of file stm8s_tim3.c.

References IS_TIM3_GET_IT_OK, RESET, and SET.

TIM3_Prescaler_TypeDef TIM3_GetPrescaler ( void )

Gets the TIM3 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM3_Prescaler_TypeDef.

Definition at line 859 of file stm8s_tim3.c.

void TIM3_ICInit | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_ICPolarity_TypeDef | TIM3_ICPolarity,
 |  | TIM3_ICSelection_TypeDef | TIM3_ICSelection,
 |  | TIM3_ICPSC_TypeDef | TIM3_ICPrescaler,
 |  | uint8_t | TIM3_ICFilter
 | ) |  |

Initializes the TIM3 peripheral according to the specified parameters.

Parameters:
TIM3_Channel | specifies the Input Capture Channel from TIM3_Channel_TypeDef.
TIM3_ICPolarity | specifies the Input Capture Polarity from TIM3_ICPolarity_TypeDef.
TIM3_ICSelection | specifies the Input Capture Selection from TIM3_ICSelection_TypeDef.
TIM3_ICPrescaler | specifies the Input Capture Prescaler from TIM3_ICPSC_TypeDef.
TIM3_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 163 of file stm8s_tim3.c.

References IS_TIM3_CHANNEL_OK, IS_TIM3_IC_FILTER_OK, IS_TIM3_IC_POLARITY_OK, IS_TIM3_IC_PRESCALER_OK, IS_TIM3_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TIM3_CHANNEL_2, TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

void TIM3_InternalClockConfig ( void )
void TIM3_ITConfig | ( | TIM3_IT_TypeDef | TIM3_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM3 interrupts.

Parameters:
NewState | new state of the TIM3 peripheral. This parameter can be: ENABLE or DISABLE.
TIM3_IT specifies the TIM3 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
  • TIM3_IT_CC3: TIM3 Capture Compare 3 Interrupt source
NewState | new state of the TIM3 peripheral. *
Return values:
None

Definition at line 309 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM3_IT_OK.

void TIM3_OC1Init | ( | TIM3_OCMode_TypeDef | TIM3_OCMode,
 |  | TIM3_OutputState_TypeDef | TIM3_OutputState,
 |  | uint16_t | TIM3_Pulse,
 |  | TIM3_OCPolarity_TypeDef | TIM3_OCPolarity
 | ) |  |

Initializes the TIM3 Channel1 according to the specified parameters.

Parameters:
TIM3_OCMode | specifies the Output Compare mode from TIM3_OCMode_TypeDef.
TIM3_OutputState | specifies the Output State from TIM3_OutputState_TypeDef.
TIM3_Pulse | specifies the Pulse width value.
TIM3_OCPolarity | specifies the Output Compare Polarity from TIM3_OCPolarity_TypeDef.
Return values:
None

Definition at line 96 of file stm8s_tim3.c.

References IS_TIM3_OC_MODE_OK, IS_TIM3_OC_POLARITY_OK, IS_TIM3_OUTPUT_STATE_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC1P, and TIM3_CCMR_OCM.

void TIM3_OC1PolarityConfig ( TIM3_OCPolarity_TypeDef TIM3_OCPolarity )

Configures the TIM3 Channel 1 polarity.

Parameters:
TIM3_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:

  • TIM3_OCPOLARITY_LOW: Output Compare active low
  • TIM3_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 575 of file stm8s_tim3.c.

References IS_TIM3_OC_POLARITY_OK, TIM3_CCER1_CC1P, and TIM3_OCPOLARITY_HIGH.

void TIM3_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM3 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 509 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CCMR_OCxPE.

void TIM3_OC2Init | ( | TIM3_OCMode_TypeDef | TIM3_OCMode,
 |  | TIM3_OutputState_TypeDef | TIM3_OutputState,
 |  | uint16_t | TIM3_Pulse,
 |  | TIM3_OCPolarity_TypeDef | TIM3_OCPolarity
 | ) |  |

Initializes the TIM3 Channel2 according to the specified parameters.

Parameters:
TIM3_OCMode | specifies the Output Compare mode from TIM3_OCMode_TypeDef.
TIM3_OutputState | specifies the Output State from TIM3_OutputState_TypeDef.
TIM3_Pulse | specifies the Pulse width value.
TIM3_OCPolarity | specifies the Output Compare Polarity from TIM3_OCPolarity_TypeDef.
Return values:
None

Definition at line 128 of file stm8s_tim3.c.

References IS_TIM3_OC_MODE_OK, IS_TIM3_OC_POLARITY_OK, IS_TIM3_OUTPUT_STATE_OK, TIM3_CCER1_CC2E, TIM3_CCER1_CC2P, and TIM3_CCMR_OCM.

void TIM3_OC2PolarityConfig ( TIM3_OCPolarity_TypeDef TIM3_OCPolarity )

Configures the TIM3 Channel 2 polarity.

Parameters:
TIM3_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:

  • TIM3_OCPOLARITY_LOW: Output Compare active low
  • TIM3_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 600 of file stm8s_tim3.c.

References IS_TIM3_OC_POLARITY_OK, TIM3_CCER1_CC2P, and TIM3_OCPOLARITY_HIGH.

void TIM3_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM3 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 532 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CCMR_OCxPE.

void TIM3_PrescalerConfig | ( | TIM3_Prescaler_TypeDef | Prescaler,
 |  | TIM3_PSCReloadMode_TypeDef | TIM3_PSCReloadMode
 | ) |  |

Configures the TIM3 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values

  • TIM3_PRESCALER_1
  • TIM3_PRESCALER_2
  • TIM3_PRESCALER_4
  • TIM3_PRESCALER_8
  • TIM3_PRESCALER_16
  • TIM3_PRESCALER_32
  • TIM3_PRESCALER_64
  • TIM3_PRESCALER_128
  • TIM3_PRESCALER_256
  • TIM3_PRESCALER_512
  • TIM3_PRESCALER_1024
  • TIM3_PRESCALER_2048
  • TIM3_PRESCALER_4096
  • TIM3_PRESCALER_8192
  • TIM3_PRESCALER_16384
  • TIM3_PRESCALER_32768
TIM3_PSCReloadMode specifies the TIM3 Prescaler Reload mode. This parameter can be one of the following values

  • TIM3_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediatly.
  • TIM3_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 429 of file stm8s_tim3.c.

References IS_TIM3_PRESCALER_OK, and IS_TIM3_PRESCALER_RELOAD_OK.

void TIM3_PWMIConfig | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_ICPolarity_TypeDef | TIM3_ICPolarity,
 |  | TIM3_ICSelection_TypeDef | TIM3_ICSelection,
 |  | TIM3_ICPSC_TypeDef | TIM3_ICPrescaler,
 |  | uint8_t | TIM3_ICFilter
 | ) |  |

Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM3_Channel | specifies the Input Capture Channel from TIM3_Channel_TypeDef.
TIM3_ICPolarity | specifies the Input Capture Polarity from TIM3_ICPolarity_TypeDef.
TIM3_ICSelection | specifies the Input Capture Selection from TIM3_ICSelection_TypeDef.
TIM3_ICPrescaler | specifies the Input Capture Prescaler from TIM3_ICPSC_TypeDef.
TIM3_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 206 of file stm8s_tim3.c.

References IS_TIM3_IC_POLARITY_OK, IS_TIM3_IC_PRESCALER_OK, IS_TIM3_IC_SELECTION_OK, IS_TIM3_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM3_CHANNEL_2, TIM3_ICPOLARITY_FALLING, TIM3_ICPOLARITY_RISING, TIM3_ICSELECTION_DIRECTTI, TIM3_ICSELECTION_INDIRECTTI, TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

void TIM3_SelectOCxM | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_OCMode_TypeDef | TIM3_OCMode
 | ) |  |

Selects the TIM3 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM3_CCxCmd and TIM3_CCxNCmd functions.

Parameters:
TIM3_Channel specifies the TIM3 Channel. This parameter can be one of the following values:

  • TIM3_CHANNEL_1: TIM3 Channel1
  • TIM3_CHANNEL_2: TIM3 Channel2
TIM3_OCMode specifies the TIM3 Output Compare Mode. This paramter can be one of the following values:

  • TIM3_OCMODE_TIMING
  • TIM3_OCMODE_ACTIVE
  • TIM3_OCMODE_TOGGLE
  • TIM3_OCMODE_PWM1
  • TIM3_OCMODE_PWM2
  • TIM3_FORCEDACTION_ACTIVE
  • TIM3_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 680 of file stm8s_tim3.c.

References IS_TIM3_CHANNEL_OK, IS_TIM3_OCM_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC2E, TIM3_CCMR_OCM, and TIM3_CHANNEL_1.

void TIM3_SelectOnePulseMode ( TIM3_OPMode_TypeDef TIM3_OPMode )

Selects the TIM3’s One Pulse Mode.

Parameters:
TIM3_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values

  • TIM3_OPMODE_SINGLE
  • TIM3_OPMODE_REPETITIVE
Return values:
None

Definition at line 383 of file stm8s_tim3.c.

References IS_TIM3_OPM_MODE_OK, TIM3_CR1_OPM, and TIM3_OPMODE_REPETITIVE.

void TIM3_SetAutoreload ( uint16_t Autoreload )

Sets the TIM3 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 726 of file stm8s_tim3.c.

void TIM3_SetCompare1 ( uint16_t Compare1 )

Sets the TIM3 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 740 of file stm8s_tim3.c.

void TIM3_SetCompare2 ( uint16_t Compare2 )

Sets the TIM3 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 754 of file stm8s_tim3.c.

void TIM3_SetCounter ( uint16_t Counter )

Sets the TIM3 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 711 of file stm8s_tim3.c.

void TIM3_SetIC1Prescaler ( TIM3_ICPSC_TypeDef TIM3_IC1Prescaler )

Sets the TIM3 Input Capture 1 prescaler.

Parameters:
TIM3_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM3_ICPSC_DIV1: no prescaler
  • TIM3_ICPSC_DIV2: capture is done once every 2 events
  • TIM3_ICPSC_DIV4: capture is done once every 4 events
  • TIM3_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 772 of file stm8s_tim3.c.

References IS_TIM3_IC_PRESCALER_OK, and TIM3_CCMR_ICxPSC.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

void TIM3_SetIC2Prescaler ( TIM3_ICPSC_TypeDef TIM3_IC2Prescaler )

Sets the TIM3 Input Capture 2 prescaler.

Parameters:
TIM3_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM3_ICPSC_DIV1: no prescaler
  • TIM3_ICPSC_DIV2: capture is done once every 2 events
  • TIM3_ICPSC_DIV4: capture is done once every 4 events
  • TIM3_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 791 of file stm8s_tim3.c.

References IS_TIM3_IC_PRESCALER_OK, and TIM3_CCMR_ICxPSC.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

void TIM3_TimeBaseInit | ( | TIM3_Prescaler_TypeDef | TIM3_Prescaler,
 |  | uint16_t | TIM3_Period
 | ) |  |

Initializes the TIM3 Time Base Unit according to the specified parameters.

Parameters:
TIM3_Prescaler | specifies the Prescaler from TIM3_Prescaler_TypeDef.
TIM3_Period | specifies the Period value.
Return values:
None

Definition at line 78 of file stm8s_tim3.c.

void TIM3_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM3 Update event.

Parameters:
NewState new state of the TIM3 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 334 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_UDIS.

void TIM3_UpdateRequestConfig ( TIM3_UpdateSource_TypeDef TIM3_UpdateSource )

Selects the TIM3 Update Request Interrupt source.

Parameters:
TIM3_UpdateSource specifies the Update source. This parameter can be one of the following values

  • TIM3_UPDATESOURCE_REGULAR
  • TIM3_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 358 of file stm8s_tim3.c.

References IS_TIM3_UPDATE_SOURCE_OK, TIM3_CR1_URS, and TIM3_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM4_Exported_Types

Defines | Enumerations

TIM4_Exported_Types

STM8S_StdPeriph_Driver

Defines

#define | IS_TIM4_EVENT_SOURCE_OK(SOURCE) (((SOURCE) == 0x01))
#define | IS_TIM4_GET_FLAG_OK(FLAG) ((FLAG) == TIM4_FLAG_UPDATE)
#define | IS_TIM4_IT_OK(IT) ((IT) == TIM4_IT_UPDATE)
#define | IS_TIM4_OPM_MODE_OK(MODE)
#define | IS_TIM4_PRESCALER_OK(PRESCALER)
#define | IS_TIM4_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM4_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM4_EventSource_TypeDef { TIM4_EVENTSOURCE_UPDATE = ((uint8_t)0x01) }

TIM4 Event Source.

More...
enum | TIM4_FLAG_TypeDef { TIM4_FLAG_UPDATE = ((uint8_t)0x01) }

TIM4 Flags.

More...
enum | TIM4_IT_TypeDef { TIM4_IT_UPDATE = ((uint8_t)0x01) }

TIM4 interrupt sources.

More...
enum | TIM4_OPMode_TypeDef { TIM4_OPMODE_SINGLE = ((uint8_t)0x01), TIM4_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM4 One Pulse Mode.

More...
enum TIM4_Prescaler_TypeDef {
TIM4_PRESCALER_1 = ((uint8_t)0x00), TIM4_PRESCALER_2 = ((uint8_t)0x01), TIM4_PRESCALER_4 = ((uint8_t)0x02), TIM4_PRESCALER_8 = ((uint8_t)0x03),
TIM4_PRESCALER_16 = ((uint8_t)0x04), TIM4_PRESCALER_32 = ((uint8_t)0x05), TIM4_PRESCALER_64 = ((uint8_t)0x06), TIM4_PRESCALER_128 = ((uint8_t)0x07)
}

TIM4 Prescaler.

More...
enum | TIM4_PSCReloadMode_TypeDef { TIM4_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM4_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM4 Prescaler Reload Mode.

More...
enum | TIM4_UpdateSource_TypeDef { TIM4_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM4_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM4 Update Source.

More...

Define Documentation

#define IS_TIM4_EVENT_SOURCE_OK ( SOURCE ) (((SOURCE) == 0x01))

Definition at line 99 of file stm8s_tim4.h.

Referenced by TIM4_GenerateEvent().

#define IS_TIM4_GET_FLAG_OK ( FLAG ) ((FLAG) == TIM4_FLAG_UPDATE)

Definition at line 107 of file stm8s_tim4.h.

Referenced by TIM4_ClearFlag(), and TIM4_GetFlagStatus().

#define IS_TIM4_IT_OK ( IT ) ((IT) == TIM4_IT_UPDATE)

Definition at line 117 of file stm8s_tim4.h.

Referenced by TIM4_ClearITPendingBit(), TIM4_GetITStatus(), and TIM4_ITConfig().

#define IS_TIM4_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM4_OPMODE_SINGLE) || \
                                   ((MODE) == TIM4_OPMODE_REPETITIVE))

Definition at line 70 of file stm8s_tim4.h.

Referenced by TIM4_SelectOnePulseMode().

#define IS_TIM4_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM4_PRESCALER_1  ) || \
    ((PRESCALER) == TIM4_PRESCALER_2    ) || \
    ((PRESCALER) == TIM4_PRESCALER_4    ) || \
    ((PRESCALER) == TIM4_PRESCALER_8  ) || \
    ((PRESCALER) == TIM4_PRESCALER_16   ) || \
    ((PRESCALER) == TIM4_PRESCALER_32     ) || \
    ((PRESCALER) == TIM4_PRESCALER_64    ) || \
    ((PRESCALER) == TIM4_PRESCALER_128   ) )

Definition at line 54 of file stm8s_tim4.h.

Referenced by TIM4_PrescalerConfig(), and TIM4_TimeBaseInit().

#define IS_TIM4_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM4_PSCRELOADMODE_UPDATE) || \
    ((RELOAD) == TIM4_PSCRELOADMODE_IMMEDIATE))

Definition at line 80 of file stm8s_tim4.h.

Referenced by TIM4_PrescalerConfig().

#define IS_TIM4_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM4_UPDATESOURCE_GLOBAL) || \
    ((SOURCE) == TIM4_UPDATESOURCE_REGULAR))

Definition at line 90 of file stm8s_tim4.h.

Referenced by TIM4_UpdateRequestConfig().

Enumeration Type Documentation

enum TIM4_EventSource_TypeDef

TIM4 Event Source.

Enumerator:
TIM4_EVENTSOURCE_UPDATE

Definition at line 94 of file stm8s_tim4.h.

enum TIM4_FLAG_TypeDef

TIM4 Flags.

Enumerator:
TIM4_FLAG_UPDATE

Definition at line 102 of file stm8s_tim4.h.

enum TIM4_IT_TypeDef

TIM4 interrupt sources.

Enumerator:
TIM4_IT_UPDATE

Definition at line 112 of file stm8s_tim4.h.

enum TIM4_OPMode_TypeDef

TIM4 One Pulse Mode.

Enumerator:
TIM4_OPMODE_SINGLE
TIM4_OPMODE_REPETITIVE

Definition at line 64 of file stm8s_tim4.h.

enum TIM4_Prescaler_TypeDef

TIM4 Prescaler.

Enumerator:
TIM4_PRESCALER_1
TIM4_PRESCALER_2
TIM4_PRESCALER_4
TIM4_PRESCALER_8
TIM4_PRESCALER_16
TIM4_PRESCALER_32
TIM4_PRESCALER_64
TIM4_PRESCALER_128

Definition at line 42 of file stm8s_tim4.h.

enum TIM4_PSCReloadMode_TypeDef

TIM4 Prescaler Reload Mode.

Enumerator:
TIM4_PSCRELOADMODE_UPDATE
TIM4_PSCRELOADMODE_IMMEDIATE

Definition at line 74 of file stm8s_tim4.h.

enum TIM4_UpdateSource_TypeDef

TIM4 Update Source.

Enumerator:
TIM4_UPDATESOURCE_GLOBAL
TIM4_UPDATESOURCE_REGULAR

Definition at line 84 of file stm8s_tim4.h.


STM8S/A Standard Peripherals Drivers: TIM4_Exported_Functions

Functions

TIM4_Exported_Functions

STM8S_StdPeriph_Driver

Functions

void | TIM4_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM4 peripheral Preload register on ARR.
void | TIM4_ClearFlag (TIM4_FLAG_TypeDef TIM4_FLAG)
Clears the TIM4’s pending flags.
void | TIM4_ClearITPendingBit (TIM4_IT_TypeDef TIM4_IT)
Clears the TIM4's interrupt pending bits.
void | TIM4_Cmd (FunctionalState NewState)
Enables or disables the TIM4 peripheral.
void | TIM4_DeInit (void)
Deinitializes the TIM4 peripheral registers to their default reset values.
void | TIM4_GenerateEvent (TIM4_EventSource_TypeDef TIM4_EventSource)
Configures the TIM4 event to be generated by software.
uint8_t | TIM4_GetCounter (void)
Gets the TIM4 Counter value.
FlagStatus | TIM4_GetFlagStatus (TIM4_FLAG_TypeDef TIM4_FLAG)
Checks whether the specified TIM4 flag is set or not.
ITStatus | TIM4_GetITStatus (TIM4_IT_TypeDef TIM4_IT)
Checks whether the TIM4 interrupt has occurred or not.
TIM4_Prescaler_TypeDef | TIM4_GetPrescaler (void)
Gets the TIM4 Prescaler value.
void | TIM4_ITConfig (TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
Enables or disables the specified TIM4 interrupts.
void | TIM4_PrescalerConfig (TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
Configures the TIM4 Prescaler.
void | TIM4_SelectOnePulseMode (TIM4_OPMode_TypeDef TIM4_OPMode)
Selects the TIM4’s One Pulse Mode.
void | TIM4_SetAutoreload (uint8_t Autoreload)
Sets the TIM4 Autoreload Register value.
void | TIM4_SetCounter (uint8_t Counter)
Sets the TIM4 Counter Register value.
void | TIM4_TimeBaseInit (TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)
Initializes the TIM4 Time Base Unit according to the specified parameters.
void | TIM4_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM4 Update event.
void | TIM4_UpdateRequestConfig (TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
Selects the TIM4 Update Request Interrupt source.

Function Documentation

void TIM4_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM4 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM4 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 231 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_ARPE.

void TIM4_ClearFlag ( TIM4_FLAG_TypeDef TIM4_FLAG )

Clears the TIM4’s pending flags.

Parameters:
TIM4_FLAG specifies the flag to clear. This parameter can be one of the following values:

  • TIM4_FLAG_UPDATE: TIM4 update Flag
Return values:
None.

Definition at line 343 of file stm8s_tim4.c.

References IS_TIM4_GET_FLAG_OK.

void TIM4_ClearITPendingBit ( TIM4_IT_TypeDef TIM4_IT )

Clears the TIM4's interrupt pending bits.

Parameters:
TIM4_IT specifies the pending bit to clear. This parameter can be one of the following values:

  • TIM4_IT_UPDATE: TIM4 update Interrupt source
Return values:
None.

Definition at line 391 of file stm8s_tim4.c.

References IS_TIM4_IT_OK.

void TIM4_Cmd ( FunctionalState NewState )

Enables or disables the TIM4 peripheral.

Parameters:
NewState new state of the TIM4 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 77 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_CEN.

void TIM4_DeInit ( void )

Deinitializes the TIM4 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 43 of file stm8s_tim4.c.

References TIM4_ARR_RESET_VALUE, TIM4_CNTR_RESET_VALUE, TIM4_CR1_RESET_VALUE, TIM4_IER_RESET_VALUE, TIM4_PSCR_RESET_VALUE, and TIM4_SR1_RESET_VALUE.

void TIM4_GenerateEvent ( TIM4_EventSource_TypeDef TIM4_EventSource )

Configures the TIM4 event to be generated by software.

Parameters:
TIM4_EventSource specifies the event source. This parameter can be one of the following values:

  • TIM4_EVENTSOURCE_UPDATE: TIM4 update Event source
Return values:
None

Definition at line 254 of file stm8s_tim4.c.

References IS_TIM4_EVENT_SOURCE_OK.

uint8_t TIM4_GetCounter ( void )

Gets the TIM4 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 294 of file stm8s_tim4.c.

FlagStatus TIM4_GetFlagStatus ( TIM4_FLAG_TypeDef TIM4_FLAG )

Checks whether the specified TIM4 flag is set or not.

Parameters:
TIM4_FLAG specifies the flag to check. This parameter can be one of the following values:

  • TIM4_FLAG_UPDATE: TIM4 update Flag
Return values:
FlagStatus The new state of TIM4_FLAG (SET or RESET).

Definition at line 318 of file stm8s_tim4.c.

References IS_TIM4_GET_FLAG_OK, RESET, and SET.

ITStatus TIM4_GetITStatus ( TIM4_IT_TypeDef TIM4_IT )

Checks whether the TIM4 interrupt has occurred or not.

Parameters:
TIM4_IT specifies the TIM4 interrupt source to check. This parameter can be one of the following values:

  • TIM4_IT_UPDATE: TIM4 update Interrupt source
Return values:
ITStatus The new state of the TIM4_IT (SET or RESET).

Definition at line 360 of file stm8s_tim4.c.

References IS_TIM4_IT_OK, RESET, and SET.

TIM4_Prescaler_TypeDef TIM4_GetPrescaler ( void )

Gets the TIM4 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value.

Definition at line 305 of file stm8s_tim4.c.

void TIM4_ITConfig | ( | TIM4_IT_TypeDef | TIM4_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM4 interrupts.

Parameters:
NewState | new state of the TIM4 peripheral. This parameter can be: ENABLE or DISABLE.
TIM4_IT specifies the TIM4 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM4_IT_UPDATE: TIM4 update Interrupt source
NewState | new state of the TIM4 peripheral.
Return values:
None

Definition at line 103 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM4_IT_OK.

void TIM4_PrescalerConfig | ( | TIM4_Prescaler_TypeDef | Prescaler,
 |  | TIM4_PSCReloadMode_TypeDef | TIM4_PSCReloadMode
 | ) |  |

Configures the TIM4 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values

  • TIM4_PRESCALER_1
  • TIM4_PRESCALER_2
  • TIM4_PRESCALER_4
  • TIM4_PRESCALER_8
  • TIM4_PRESCALER_16
  • TIM4_PRESCALER_32
  • TIM4_PRESCALER_64
  • TIM4_PRESCALER_128
TIM4_PSCReloadMode specifies the TIM4 Prescaler Reload mode. This parameter can be one of the following values

  • TIM4_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediatly.
  • TIM4_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 212 of file stm8s_tim4.c.

References IS_TIM4_PRESCALER_OK, and IS_TIM4_PRESCALER_RELOAD_OK.

void TIM4_SelectOnePulseMode ( TIM4_OPMode_TypeDef TIM4_OPMode )

Selects the TIM4’s One Pulse Mode.

Parameters:
TIM4_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values

  • TIM4_OPMODE_SINGLE
  • TIM4_OPMODE_REPETITIVE
Return values:
None

Definition at line 175 of file stm8s_tim4.c.

References IS_TIM4_OPM_MODE_OK, TIM4_CR1_OPM, and TIM4_OPMODE_REPETITIVE.

void TIM4_SetAutoreload ( uint8_t Autoreload )

Sets the TIM4 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 283 of file stm8s_tim4.c.

void TIM4_SetCounter ( uint8_t Counter )

Sets the TIM4 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 270 of file stm8s_tim4.c.

void TIM4_TimeBaseInit | ( | TIM4_Prescaler_TypeDef | TIM4_Prescaler,
 |  | uint8_t | TIM4_Period
 | ) |  |

Initializes the TIM4 Time Base Unit according to the specified parameters.

Parameters:
TIM4_Prescaler | specifies the Prescaler from TIM4_Prescaler_TypeDef.
TIM4_Period | specifies the Period value.
Return values:
None

Definition at line 59 of file stm8s_tim4.c.

References IS_TIM4_PRESCALER_OK.

void TIM4_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM4 Update event.

Parameters:
NewState new state of the TIM4 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 127 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_UDIS.

void TIM4_UpdateRequestConfig ( TIM4_UpdateSource_TypeDef TIM4_UpdateSource )

Selects the TIM4 Update Request Interrupt source.

Parameters:
TIM4_UpdateSource specifies the Update source. This parameter can be one of the following values

  • TIM4_UPDATESOURCE_REGULAR
  • TIM4_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 151 of file stm8s_tim4.c.

References IS_TIM4_UPDATE_SOURCE_OK, TIM4_CR1_URS, and TIM4_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM6_Exported_Types

Enumerations

TIM6_Exported_Types

STM8S_StdPeriph_Driver

Enumerations

enum | TIM6_EventSource_TypeDef { TIM6_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM6_EVENTSOURCE_TRIGGER = ((uint8_t)0x40) }

TIM6 Event Source.

More...
enum | TIM6_FLAG_TypeDef { TIM6_FLAG_UPDATE = ((uint8_t)0x01), TIM6_FLAG_TRIGGER = ((uint8_t)0x40) }

TIM6 Flags.

More...
enum | TIM6_IT_TypeDef { TIM6_IT_UPDATE = ((uint8_t)0x01), TIM6_IT_TRIGGER = ((uint8_t)0x40) }

TIM6 interrupt sources.

More...
enum | TIM6_OPMode_TypeDef { TIM6_OPMODE_SINGLE = ((uint8_t)0x01), TIM6_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM6 One Pulse Mode.

More...
enum TIM6_Prescaler_TypeDef {
TIM6_PRESCALER_1 = ((uint8_t)0x00), TIM6_PRESCALER_2 = ((uint8_t)0x01), TIM6_PRESCALER_4 = ((uint8_t)0x02), TIM6_PRESCALER_8 = ((uint8_t)0x03),
TIM6_PRESCALER_16 = ((uint8_t)0x04), TIM6_PRESCALER_32 = ((uint8_t)0x05), TIM6_PRESCALER_64 = ((uint8_t)0x06), TIM6_PRESCALER_128 = ((uint8_t)0x07)
}

TIM6 Prescaler.

More...
enum | TIM6_PSCReloadMode_TypeDef { TIM6_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM6_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM6 Prescaler Reload Mode.

More...
enum TIM6_SlaveMode_TypeDef {
TIM6_SLAVEMODE_DISABLE = ((uint8_t)0x00), TIM6_SLAVEMODE_RESET = ((uint8_t)0x04), TIM6_SLAVEMODE_GATED = ((uint8_t)0x05), TIM6_SLAVEMODE_TRIGGER = ((uint8_t)0x06),
TIM6_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07)
}

TIM6 Slave Mode.

More...
enum | TIM6_TRGOSource_TypeDef { TIM6_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM6_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM6_TRGOSOURCE_UPDATE = ((uint8_t)0x20) }

TIM6 Trigger Output Source.

More...
enum | TIM6_TS_TypeDef { TIM6_TS_TIM1 = ((uint8_t)0x20), TIM6_TS_TIM5 = ((uint8_t)0x30) }

TIM6 Internal Trigger Selection.

More...
enum | TIM6_UpdateSource_TypeDef { TIM6_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM6_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM6 Update Source.

More...

Enumeration Type Documentation

enum TIM6_EventSource_TypeDef

TIM6 Event Source.

Enumerator:
TIM6_EVENTSOURCE_UPDATE

Update Event

TIM6_EVENTSOURCE_TRIGGER

Trigger Event

Definition at line 86 of file stm8s_tim6.h.

enum TIM6_FLAG_TypeDef

TIM6 Flags.

Enumerator:
TIM6_FLAG_UPDATE

Update Flag

TIM6_FLAG_TRIGGER

Trigger Flag

Definition at line 117 of file stm8s_tim6.h.

enum TIM6_IT_TypeDef

TIM6 interrupt sources.

Enumerator:
TIM6_IT_UPDATE

Update Interrupt

TIM6_IT_TRIGGER

Trigger Interrupt

Definition at line 126 of file stm8s_tim6.h.

enum TIM6_OPMode_TypeDef

TIM6 One Pulse Mode.

Enumerator:
TIM6_OPMODE_SINGLE

Single one Pulse mode (OPM Active)

TIM6_OPMODE_REPETITIVE

Repetitive Pulse mode (OPM inactive)

Definition at line 59 of file stm8s_tim6.h.

enum TIM6_Prescaler_TypeDef

TIM6 Prescaler.

Enumerator:
TIM6_PRESCALER_1

Time base Prescaler = 1 (No effect)

TIM6_PRESCALER_2

Time base Prescaler = 2

TIM6_PRESCALER_4

Time base Prescaler = 4

TIM6_PRESCALER_8

Time base Prescaler = 8

TIM6_PRESCALER_16

Time base Prescaler = 16

TIM6_PRESCALER_32

Time base Prescaler = 32

TIM6_PRESCALER_64

Time base Prescaler = 64

TIM6_PRESCALER_128

Time base Prescaler = 128

Definition at line 44 of file stm8s_tim6.h.

enum TIM6_PSCReloadMode_TypeDef

TIM6 Prescaler Reload Mode.

Enumerator:
TIM6_PSCRELOADMODE_UPDATE

Prescaler value is reloaded at every update

TIM6_PSCRELOADMODE_IMMEDIATE

Prescaler value is reloaded immediatly

Definition at line 68 of file stm8s_tim6.h.

enum TIM6_SlaveMode_TypeDef

TIM6 Slave Mode.

Enumerator:
TIM6_SLAVEMODE_DISABLE

Disable slave mode to clock the prescaler directly with the internal clock

TIM6_SLAVEMODE_RESET

Slave Mode Selection = Reset

TIM6_SLAVEMODE_GATED

Slave Mode Selection = Gated

TIM6_SLAVEMODE_TRIGGER

Slave Mode Selection = Trigger

TIM6_SLAVEMODE_EXTERNAL1

Slave Mode Selection = External 1

Definition at line 105 of file stm8s_tim6.h.

enum TIM6_TRGOSource_TypeDef

TIM6 Trigger Output Source.

Enumerator:
TIM6_TRGOSOURCE_RESET

Trigger Output source = Reset

TIM6_TRGOSOURCE_ENABLE

Trigger Output source = TIM5 is enabled

TIM6_TRGOSOURCE_UPDATE

Trigger Output source = Update event

Definition at line 95 of file stm8s_tim6.h.

enum TIM6_TS_TypeDef

TIM6 Internal Trigger Selection.

Enumerator:
TIM6_TS_TIM1

TRIG Input source = TIM1 TRIG Output

TIM6_TS_TIM5

TRIG Input source = TIM5 TRIG Output

Definition at line 135 of file stm8s_tim6.h.

enum TIM6_UpdateSource_TypeDef

TIM6 Update Source.

Enumerator:
TIM6_UPDATESOURCE_GLOBAL

Global Update request source

TIM6_UPDATESOURCE_REGULAR

Regular Update request source

Definition at line 77 of file stm8s_tim6.h.


STM8S/A Standard Peripherals Drivers: TIM6_Private_Macros

Defines

TIM6_Private_Macros

STM8S_StdPeriph_Driver

Defines

#define | IS_TIM6_CLEAR_FLAG_OK(FLAG) ((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))
#define | IS_TIM6_EVENT_SOURCE_OK(SOURCE)
Macro TIM6 Event source.
#define | IS_TIM6_GET_FLAG_OK(FLAG)
Macro TIM6 Flags.
#define | IS_TIM6_GET_IT_OK(IT)
#define | IS_TIM6_IT_OK(IT)
Macro TIM6 interrupts.
#define | IS_TIM6_OPM_MODE_OK(MODE)
Macro TIM6 One Pulse Mode.
#define | IS_TIM6_PRESCALER_OK(PRESCALER)
Macro used by the assert function to check the different functions parameters.
#define | IS_TIM6_PRESCALER_RELOAD_OK(RELOAD)
Macro TIM6 Prescaler reload.
#define | IS_TIM6_SLAVE_MODE_OK(MODE)
Macro TIM6 Slave mode.
#define | IS_TIM6_TRGO_SOURCE_OK(SOURCE)
Macro TIM6 TRGO source.
#define | IS_TIM6_TRIGGER_SELECTION_OK(SELECTION)
Macro TIM6 Trigger selection.
#define | IS_TIM6_UPDATE_SOURCE_OK(SOURCE)
Macro TIM6 Update source.

Define Documentation

#define IS_TIM6_CLEAR_FLAG_OK ( FLAG ) ((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))

Definition at line 218 of file stm8s_tim6.h.

Referenced by TIM6_ClearFlag().

#define IS_TIM6_EVENT_SOURCE_OK ( SOURCE )
Value:
((((SOURCE) & (uint8_t)0xBE) == 0x00) && \
    ((SOURCE) != 0x00))

Macro TIM6 Event source.

Definition at line 191 of file stm8s_tim6.h.

Referenced by TIM6_GenerateEvent().

#define IS_TIM6_GET_FLAG_OK ( FLAG )
Value:
(((FLAG) == TIM6_FLAG_UPDATE) || \
    ((FLAG) == TIM6_FLAG_TRIGGER))

Macro TIM6 Flags.

Definition at line 214 of file stm8s_tim6.h.

Referenced by TIM6_GetFlagStatus().

#define IS_TIM6_GET_IT_OK ( IT )
Value:
(((IT) == TIM6_IT_UPDATE) || \
    ((IT) == TIM6_IT_TRIGGER))

Definition at line 227 of file stm8s_tim6.h.

Referenced by TIM6_GetITStatus().

#define IS_TIM6_IT_OK ( IT )
Value:
(((IT) != 0x00) && \
    (((IT) & (uint8_t)(~(uint8_t)(0x41)))== 0x00))

Macro TIM6 interrupts.

Definition at line 223 of file stm8s_tim6.h.

Referenced by TIM6_ClearITPendingBit(), and TIM6_ITConfig().

#define IS_TIM6_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM6_OPMODE_SINGLE) || \
    ((MODE) == TIM6_OPMODE_REPETITIVE))

Macro TIM6 One Pulse Mode.

Definition at line 172 of file stm8s_tim6.h.

Referenced by TIM6_SelectOnePulseMode().

#define IS_TIM6_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM6_PRESCALER_1)    || \
    ((PRESCALER) == TIM6_PRESCALER_2)    || \
    ((PRESCALER) == TIM6_PRESCALER_4)    || \
    ((PRESCALER) == TIM6_PRESCALER_8)    || \
    ((PRESCALER) == TIM6_PRESCALER_16)   || \
    ((PRESCALER) == TIM6_PRESCALER_32)   || \
    ((PRESCALER) == TIM6_PRESCALER_64)   || \
    ((PRESCALER) == TIM6_PRESCALER_128))

Macro used by the assert function to check the different functions parameters.

Macro TIM6 Prescaler

Definition at line 160 of file stm8s_tim6.h.

Referenced by TIM6_PrescalerConfig(), and TIM6_TimeBaseInit().

#define IS_TIM6_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM6_PSCRELOADMODE_UPDATE) || \
    ((RELOAD) == TIM6_PSCRELOADMODE_IMMEDIATE))

Macro TIM6 Prescaler reload.

Definition at line 179 of file stm8s_tim6.h.

Referenced by TIM6_PrescalerConfig().

#define IS_TIM6_SLAVE_MODE_OK ( MODE )
Value:
(((MODE) == TIM6_SLAVEMODE_DISABLE) || \
    ((MODE) == TIM6_SLAVEMODE_RESET)   || \
    ((MODE) == TIM6_SLAVEMODE_GATED)   || \
    ((MODE) == TIM6_SLAVEMODE_TRIGGER) || \
    ((MODE) == TIM6_SLAVEMODE_EXTERNAL1))

Macro TIM6 Slave mode.

Definition at line 205 of file stm8s_tim6.h.

Referenced by TIM6_SelectSlaveMode().

#define IS_TIM6_TRGO_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM6_TRGOSOURCE_RESET) || \
    ((SOURCE) == TIM6_TRGOSOURCE_ENABLE)|| \
    ((SOURCE) == TIM6_TRGOSOURCE_UPDATE))

Macro TIM6 TRGO source.

Definition at line 198 of file stm8s_tim6.h.

Referenced by TIM6_SelectOutputTrigger().

#define IS_TIM6_TRIGGER_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM6_TS_TIM5) || \
    ((SELECTION) == TIM6_TS_TIM1))

Macro TIM6 Trigger selection.

Definition at line 233 of file stm8s_tim6.h.

Referenced by TIM6_SelectInputTrigger().

#define IS_TIM6_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM6_UPDATESOURCE_GLOBAL) || \
    ((SOURCE) == TIM6_UPDATESOURCE_REGULAR))

Macro TIM6 Update source.

Definition at line 185 of file stm8s_tim6.h.

Referenced by TIM6_UpdateRequestConfig().


STM8S/A Standard Peripherals Drivers: TIM6_Exported_Functions

Functions

TIM6_Exported_Functions

STM8S_StdPeriph_Driver

Functions

void | TIM6_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM6 peripheral Preload register on ARR.
void | TIM6_ClearFlag (TIM6_FLAG_TypeDef TIM6_FLAG)
Clears the TIM’s pending flags.
void | TIM6_ClearITPendingBit (TIM6_IT_TypeDef TIM6_IT)
Clears the TIM6's interrupt pending bits.
void | TIM6_Cmd (FunctionalState NewState)
Enables or disables the TIM6 peripheral.
void | TIM6_DeInit (void)
Deinitializes the TIM6 peripheral registers to their default reset values.
void | TIM6_GenerateEvent (TIM6_EventSource_TypeDef TIM6_EventSource)
Configures the TIM6 event to be generated by software.
uint8_t | TIM6_GetCounter (void)
Gets the TIM6 Counter value.
FlagStatus | TIM6_GetFlagStatus (TIM6_FLAG_TypeDef TIM6_FLAG)
Checks whether the specified TIM6 flag is set or not.
ITStatus | TIM6_GetITStatus (TIM6_IT_TypeDef TIM6_IT)
Checks whether the TIM6 interrupt has occurred or not.
TIM6_Prescaler_TypeDef | TIM6_GetPrescaler (void)
Gets the TIM6 Prescaler value.
void | TIM6_InternalClockConfig (void)
Enables the TIM6 internal Clock.
void | TIM6_ITConfig (TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)
Enables or disables the specified TIM6 interrupts.
void | TIM6_PrescalerConfig (TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)
Configures the TIM6 Prescaler.
void | TIM6_SelectInputTrigger (TIM6_TS_TypeDef TIM6_InputTriggerSource)
Selects the TIM6 Input Trigger source.
void | TIM6_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM6 Master/Slave Mode.
void | TIM6_SelectOnePulseMode (TIM6_OPMode_TypeDef TIM6_OPMode)
Selects the TIM6’s One Pulse Mode.
void | TIM6_SelectOutputTrigger (TIM6_TRGOSource_TypeDef TIM6_TRGOSource)
Selects the TIM6 Trigger Output Mode.
void | TIM6_SelectSlaveMode (TIM6_SlaveMode_TypeDef TIM6_SlaveMode)
Selects the TIM6 Slave Mode.
void | TIM6_SetAutoreload (uint8_t Autoreload)
Sets the TIM6 Autoreload Register value.
void | TIM6_SetCounter (uint8_t Counter)
Sets the TIM6 Counter Register value.
void | TIM6_TimeBaseInit (TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period)
Initializes the TIM6 Time Base Unit according to the specified parameters.
void | TIM6_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM6 Update event.
void | TIM6_UpdateRequestConfig (TIM6_UpdateSource_TypeDef TIM6_UpdateSource)
Selects the TIM6 Update Request Interrupt source.

Function Documentation

void TIM6_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM6 peripheral Preload register on ARR.

Parameters:
NewState : The new state of the TIM6 peripheral Preload register. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 205 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_ARPE.

void TIM6_ClearFlag ( TIM6_FLAG_TypeDef TIM6_FLAG )

Clears the TIM’s pending flags.

Parameters:
TIM6_FLAG : Specifies the flag to clear. This parameter can be one of the TIM6_FLAG_TypeDef enumeration.
Return values:
None

Definition at line 305 of file stm8s_tim6.c.

References IS_TIM6_CLEAR_FLAG_OK.

void TIM6_ClearITPendingBit ( TIM6_IT_TypeDef TIM6_IT )

Clears the TIM6's interrupt pending bits.

Parameters:
TIM6_IT : Specifies the pending bit to clear. This parameter can be one of the TIM6_IT_TypeDef enumeration.
Return values:
None

Definition at line 390 of file stm8s_tim6.c.

References IS_TIM6_IT_OK.

void TIM6_Cmd ( FunctionalState NewState )

Enables or disables the TIM6 peripheral.

Parameters:
NewState : The new state of the TIM6 peripheral. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 87 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_CEN.

void TIM6_DeInit ( void )

Deinitializes the TIM6 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 51 of file stm8s_tim6.c.

References TIM6_ARR_RESET_VALUE, TIM6_CNTR_RESET_VALUE, TIM6_CR1_RESET_VALUE, TIM6_CR2_RESET_VALUE, TIM6_IER_RESET_VALUE, TIM6_PSCR_RESET_VALUE, TIM6_SMCR_RESET_VALUE, and TIM6_SR1_RESET_VALUE.

void TIM6_GenerateEvent ( TIM6_EventSource_TypeDef TIM6_EventSource )

Configures the TIM6 event to be generated by software.

Parameters:
TIM6_EventSource : Specifies the event source. This parameter can be one of the TIM6_EventSource_TypeDef enumeration.
Return values:
None

Definition at line 350 of file stm8s_tim6.c.

References IS_TIM6_EVENT_SOURCE_OK.

uint8_t TIM6_GetCounter ( void )

Gets the TIM6 Counter value.

Parameters:
None
Return values:
uint8_t,: Counter Register value.

Definition at line 251 of file stm8s_tim6.c.

FlagStatus TIM6_GetFlagStatus ( TIM6_FLAG_TypeDef TIM6_FLAG )

Checks whether the specified TIM6 flag is set or not.

Parameters:
TIM6_FLAG : Specifies the flag to check. This parameter can be one of the TIM6_FLAG_TypeDef enumeration.
Return values:
FlagStatus : The new state of TIM6_FLAG. This parameter can be any of the FlagStatus enumeration.

Definition at line 366 of file stm8s_tim6.c.

References IS_TIM6_GET_FLAG_OK, RESET, and SET.

ITStatus TIM6_GetITStatus ( TIM6_IT_TypeDef TIM6_IT )

Checks whether the TIM6 interrupt has occurred or not.

Parameters:
TIM6_IT : Specifies the TIM6 interrupt source to check. This parameter can be one of the TIM6_IT_TypeDef enumeration.
Return values:
ITStatus : The new state of the TIM6_IT. This parameter can be any of the ITStatus enumeration.

Definition at line 321 of file stm8s_tim6.c.

References IS_TIM6_GET_IT_OK, RESET, and SET.

TIM6_Prescaler_TypeDef TIM6_GetPrescaler ( void )

Gets the TIM6 Prescaler value.

Parameters:
None
Return values:
TIM6_Prescaler_TypeDef : Prescaler Register configuration value.

Definition at line 264 of file stm8s_tim6.c.

void TIM6_InternalClockConfig ( void )

Enables the TIM6 internal Clock.

Parameters:
None
Return values:
None

Definition at line 473 of file stm8s_tim6.c.

References TIM6_SMCR_SMS.

void TIM6_ITConfig | ( | TIM6_IT_TypeDef | TIM6_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM6 interrupts.

Parameters:
TIM6_IT | : Specifies the TIM6 interrupts sources to be enabled or disabled. This parameter can be any combination of the TIM6_IT_TypeDef enumeration.
NewState | : The new state of the TIM6 peripheral. This parameter can be any of the FunctionalState enumeration.
Return values:
None
Required preconditions:
If QST option bit is enabled, the TIM6 Interrupt vector will be mapped on IRQ number 2 (irq0). Otherwise, it will be mapped on IRQ number 27 (irq25).

Definition at line 281 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM6_IT_OK.

void TIM6_PrescalerConfig | ( | TIM6_Prescaler_TypeDef | Prescaler,
 |  | TIM6_PSCReloadMode_TypeDef | TIM6_PSCReloadMode
 | ) |  |

Configures the TIM6 Prescaler.

Parameters:
Prescaler | : Specifies the Prescaler Register value This parameter can be one of the TIM6_Prescaler_TypeDef enumeration.
TIM6_PSCReloadMode | : Specifies the TIM6 Prescaler Reload mode. This parameter can be one of the TIM6_PSCReloadMode_TypeDef enumeration.
Return values:
None

Definition at line 178 of file stm8s_tim6.c.

References IS_TIM6_PRESCALER_OK, IS_TIM6_PRESCALER_RELOAD_OK, TIM6_EGR_UG, and TIM6_PSCRELOADMODE_IMMEDIATE.

void TIM6_SelectInputTrigger ( TIM6_TS_TypeDef TIM6_InputTriggerSource )

Selects the TIM6 Input Trigger source.

Parameters:
TIM6_InputTriggerSource : Specifies Input Trigger source. This parameter can be one of the TIM6_TS_TypeDef enumeration.
Return values:
None

Definition at line 452 of file stm8s_tim6.c.

References IS_TIM6_TRIGGER_SELECTION_OK, and TIM6_SMCR_TS.

void TIM6_SelectMasterSlaveMode ( FunctionalState NewState )

Sets or Resets the TIM6 Master/Slave Mode.

Parameters:
NewState : The new state of the synchronization between TIM6 and its slaves (through TRGO). This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 430 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_SMCR_MSM.

void TIM6_SelectOnePulseMode ( TIM6_OPMode_TypeDef TIM6_OPMode )

Selects the TIM6’s One Pulse Mode.

Parameters:
TIM6_OPMode : Specifies the OPM Mode to be used. This parameter can be one of the TIM6_OPMode_TypeDef enumeration.
Return values:
None

Definition at line 153 of file stm8s_tim6.c.

References IS_TIM6_OPM_MODE_OK, TIM6_CR1_OPM, and TIM6_OPMODE_SINGLE.

void TIM6_SelectOutputTrigger ( TIM6_TRGOSource_TypeDef TIM6_TRGOSource )

Selects the TIM6 Trigger Output Mode.

Parameters:
TIM6_TRGOSource : Specifies the Trigger Output source. This parameter can be one of the TIM6_TRGOSource_TypeDef enumeration.
Return values:
None

Definition at line 405 of file stm8s_tim6.c.

References IS_TIM6_TRGO_SOURCE_OK, and TIM6_CR2_MMS.

void TIM6_SelectSlaveMode ( TIM6_SlaveMode_TypeDef TIM6_SlaveMode )

Selects the TIM6 Slave Mode.

Parameters:
TIM6_SlaveMode : Specifies the TIM6 Slave Mode. This parameter can be one of the TIM6_SlaveMode_TypeDef enumeration.
Return values:
None

Definition at line 485 of file stm8s_tim6.c.

References IS_TIM6_SLAVE_MODE_OK, and TIM6_SMCR_SMS.

void TIM6_SetAutoreload ( uint8_t Autoreload )

Sets the TIM6 Autoreload Register value.

Parameters:
Autoreload : Specifies the Autoreload register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 239 of file stm8s_tim6.c.

void TIM6_SetCounter ( uint8_t Counter )

Sets the TIM6 Counter Register value.

Parameters:
Counter : Specifies the Counter register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 227 of file stm8s_tim6.c.

void TIM6_TimeBaseInit | ( | TIM6_Prescaler_TypeDef | TIM6_Prescaler,
 |  | uint8_t | TIM6_Period
 | ) |  |

Initializes the TIM6 Time Base Unit according to the specified parameters.

Parameters:
TIM6_Prescaler | : This parameter can be any of the TIM5_Prescaler_TypeDef enumeration.
TIM6_Period | : This parameter must be a value between 0x00 and 0xFF.
Return values:
None

Definition at line 70 of file stm8s_tim6.c.

References IS_TIM6_PRESCALER_OK.

void TIM6_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM6 Update event.

Parameters:
NewState : The new state of the TIM6 peripheral Preload register. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 109 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_UDIS.

void TIM6_UpdateRequestConfig ( TIM6_UpdateSource_TypeDef TIM6_UpdateSource )

Selects the TIM6 Update Request Interrupt source.

Parameters:
TIM6_UpdateSource : Specifies the Update source. This parameter can be one of the TIM6_UpdateSource_TypeDef enumeration.
Return values:
None

Definition at line 131 of file stm8s_tim6.c.

References IS_TIM6_UPDATE_SOURCE_OK, TIM6_CR1_URS, and TIM6_UPDATESOURCE_REGULAR.


STM8S/A Standard Peripherals Drivers: UART1_Exported_Types

Enumerations

UART1_Exported_Types

STM8S_StdPeriph_Driver

Enumerations

enum UART1_Flag_TypeDef {
UART1_FLAG_TXE = (uint16_t)0x0080, UART1_FLAG_TC = (uint16_t)0x0040, UART1_FLAG_RXNE = (uint16_t)0x0020, UART1_FLAG_IDLE = (uint16_t)0x0010,
UART1_FLAG_OR = (uint16_t)0x0008, UART1_FLAG_NF = (uint16_t)0x0004, UART1_FLAG_FE = (uint16_t)0x0002, UART1_FLAG_PE = (uint16_t)0x0001,
UART1_FLAG_LBDF = (uint16_t)0x0210, UART1_FLAG_SBK = (uint16_t)0x0101
}

UART1 Flag possible values.

More...
enum | UART1_IrDAMode_TypeDef { UART1_IRDAMODE_NORMAL = (uint8_t)0x00, UART1_IRDAMODE_LOWPOWER = (uint8_t)0x01 }

UART1 Irda Modes.

More...
enum UART1_IT_TypeDef {
UART1_IT_TXE = (uint16_t)0x0277, UART1_IT_TC = (uint16_t)0x0266, UART1_IT_RXNE = (uint16_t)0x0255, UART1_IT_IDLE = (uint16_t)0x0244,
UART1_IT_OR = (uint16_t)0x0235, UART1_IT_PE = (uint16_t)0x0100, UART1_IT_LBDF = (uint16_t)0x0346, UART1_IT_RXNE_OR = (uint16_t)0x0205
}

UART1 Interrupt definition UART1_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt

  • For the following values, X means the interrupt position in the CR2 register.
More...
enum | UART1_LINBreakDetectionLength_TypeDef { UART1_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART1_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }

UART1 LIN Break detection length possible values.

More...
enum UART1_Mode_TypeDef {
UART1_MODE_RX_ENABLE = (uint8_t)0x08, UART1_MODE_TX_ENABLE = (uint8_t)0x04, UART1_MODE_TX_DISABLE = (uint8_t)0x80, UART1_MODE_RX_DISABLE = (uint8_t)0x40,
UART1_MODE_TXRX_ENABLE = (uint8_t)0x0C
}

UART1 Mode possible values.

More...
enum | UART1_Parity_TypeDef { UART1_PARITY_NO = (uint8_t)0x00, UART1_PARITY_EVEN = (uint8_t)0x04, UART1_PARITY_ODD = (uint8_t)0x06 }

UART1 parity possible values.

More...
enum | UART1_StopBits_TypeDef { UART1_STOPBITS_1 = (uint8_t)0x00, UART1_STOPBITS_0_5 = (uint8_t)0x10, UART1_STOPBITS_2 = (uint8_t)0x20, UART1_STOPBITS_1_5 = (uint8_t)0x30 }

UART1 stop bits possible values.

More...
enum UART1_SyncMode_TypeDef {
UART1_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, UART1_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, UART1_SYNCMODE_CPOL_LOW = (uint8_t)0x40, UART1_SYNCMODE_CPOL_HIGH = (uint8_t)0x04,
UART1_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, UART1_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, UART1_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, UART1_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01
}

UART1 Synchrone modes.

More...
enum | UART1_WakeUp_TypeDef { UART1_WAKEUP_IDLELINE = (uint8_t)0x00, UART1_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }

UART1 WakeUP Modes.

More...
enum | UART1_WordLength_TypeDef { UART1_WORDLENGTH_8D = (uint8_t)0x00, UART1_WORDLENGTH_9D = (uint8_t)0x10 }

UART1 Word length possible values.

More...

Enumeration Type Documentation

enum UART1_Flag_TypeDef

UART1 Flag possible values.

Enumerator:
UART1_FLAG_TXE

Transmit Data Register Empty flag

UART1_FLAG_TC

Transmission Complete flag

UART1_FLAG_RXNE

Read Data Register Not Empty flag

UART1_FLAG_IDLE

Idle line detected flag

UART1_FLAG_OR

OverRun error flag

UART1_FLAG_NF

Noise error flag

UART1_FLAG_FE

Framing Error flag

UART1_FLAG_PE

Parity Error flag

UART1_FLAG_LBDF

Line Break Detection Flag

UART1_FLAG_SBK

Send Break characters Flag

Definition at line 113 of file stm8s_uart1.h.

enum UART1_IrDAMode_TypeDef

UART1 Irda Modes.

Enumerator:
UART1_IRDAMODE_NORMAL

0x00 Irda Normal Mode

UART1_IRDAMODE_LOWPOWER

0x01 Irda Low Power Mode

Definition at line 44 of file stm8s_uart1.h.

enum UART1_IT_TypeDef

UART1 Interrupt definition UART1_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt

  • For the following values, X means the interrupt position in the CR2 register.

UART1_IT_TXE UART1_IT_TC UART1_IT_RXNE UART1_IT_IDLE UART1_IT_OR

  • For the UART1_IT_PE value, X means the flag position in the CR1 register.
  • For the UART1_IT_LBDF value, X means the flag position in the CR4 register. Y: Flag position

For the following values, Y means the flag (pending bit) position in the SR register. UART1_IT_TXE UART1_IT_TC UART1_IT_RXNE UART1_IT_IDLE UART1_IT_OR UART1_IT_PE

  • For the UART1_IT_LBDF value, Y means the flag position in the CR4 register. Z: Register index: indicate in which register the dedicated interrupt source is:
  • 1==> CR1 register
  • 2==> CR2 register
  • 3==> CR4 register
Enumerator:
UART1_IT_TXE

Transmit interrupt

UART1_IT_TC

Transmission Complete interrupt

UART1_IT_RXNE

Receive interrupt

UART1_IT_IDLE

IDLE line interrupt

UART1_IT_OR

Overrun Error interrupt

UART1_IT_PE

Parity Error interrupt

UART1_IT_LBDF

LIN break detection interrupt.

UART1_IT_RXNE_OR

Receive/Overrun interrupt

Definition at line 152 of file stm8s_uart1.h.

enum UART1_LINBreakDetectionLength_TypeDef

UART1 LIN Break detection length possible values.

Enumerator:
UART1_LINBREAKDETECTIONLENGTH_10BITS

0x01 10 bits Lin Break detection

UART1_LINBREAKDETECTIONLENGTH_11BITS

0x02 11 bits Lin Break detection

Definition at line 58 of file stm8s_uart1.h.

enum UART1_Mode_TypeDef

UART1 Mode possible values.

Enumerator:
UART1_MODE_RX_ENABLE

0x08 Receive Enable

UART1_MODE_TX_ENABLE

0x04 Transmit Enable

UART1_MODE_TX_DISABLE

0x80 Transmit Disable

UART1_MODE_RX_DISABLE

0x40 Single-wire Half-duplex mode

UART1_MODE_TXRX_ENABLE

0x0C Transmit Enable and Receive Enable

Definition at line 103 of file stm8s_uart1.h.

enum UART1_Parity_TypeDef

UART1 parity possible values.

Enumerator:
UART1_PARITY_NO

No Parity.

UART1_PARITY_EVEN

Even Parity.

UART1_PARITY_ODD

Odd Parity.

Definition at line 75 of file stm8s_uart1.h.

enum UART1_StopBits_TypeDef

UART1 stop bits possible values.

Enumerator:
UART1_STOPBITS_1

One stop bit is transmitted at the end of frame.

UART1_STOPBITS_0_5

Half stop bits is transmitted at the end of frame.

UART1_STOPBITS_2

Two stop bits are transmitted at the end of frame.

UART1_STOPBITS_1_5

One and half stop bits.

Definition at line 66 of file stm8s_uart1.h.

enum UART1_SyncMode_TypeDef

UART1 Synchrone modes.

Enumerator:
UART1_SYNCMODE_CLOCK_DISABLE

0x80 Sync mode Disable, SLK pin Disable

UART1_SYNCMODE_CLOCK_ENABLE

0x08 Sync mode Enable, SLK pin Enable

UART1_SYNCMODE_CPOL_LOW

0x40 Steady low value on SCLK pin outside transmission window

UART1_SYNCMODE_CPOL_HIGH

0x04 Steady high value on SCLK pin outside transmission window

UART1_SYNCMODE_CPHA_MIDDLE

0x20 SCLK clock line activated in middle of data bit

UART1_SYNCMODE_CPHA_BEGINING

0x02 SCLK clock line activated at beginning of data bit

UART1_SYNCMODE_LASTBIT_DISABLE

0x10 The clock pulse of the last data bit is not output to the SCLK pin

UART1_SYNCMODE_LASTBIT_ENABLE

0x01 The clock pulse of the last data bit is output to the SCLK pin

Definition at line 83 of file stm8s_uart1.h.

enum UART1_WakeUp_TypeDef

UART1 WakeUP Modes.

Enumerator:
UART1_WAKEUP_IDLELINE

0x01 Idle Line wake up

UART1_WAKEUP_ADDRESSMARK

0x02 Address Mark wake up

Definition at line 51 of file stm8s_uart1.h.

enum UART1_WordLength_TypeDef

UART1 Word length possible values.

Enumerator:
UART1_WORDLENGTH_8D

0x00 8 bits Data

UART1_WORDLENGTH_9D

0x10 9 bits Data

Definition at line 96 of file stm8s_uart1.h.


STM8S/A Standard Peripherals Drivers: UART1_Private_Macros

Defines

UART1_Private_Macros

STM8S_StdPeriph_Driver

Defines

#define | IS_UART1_ADDRESS_OK(node) ((node) < UART1_ADDRESS_MAX )
#define | IS_UART1_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART1_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART1_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART1_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART1_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART1_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART1_IRDAMODE_OK(IrDAMode)
Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.
#define | IS_UART1_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART1_MODE_OK(Mode)
Macro used by the assert function to check the different functions parameters.
#define | IS_UART1_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.
#define | IS_UART1_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART1_StopBits.
#define | IS_UART1_SYNCMODE_OK(SyncMode)
Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART1_CLOCK_ENABLE|UART1_CLOCK_DISABLE.
#define | IS_UART1_WAKEUP_OK(WakeUp)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART1_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART1_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART1 or UART node.

Define Documentation

#define IS_UART1_ADDRESS_OK ( node ) ((node) < UART1_ADDRESS_MAX )

Definition at line 327 of file stm8s_uart1.h.

Referenced by UART1_SetAddress().

#define IS_UART1_BAUDRATE_OK ( NUM ) ((NUM) <= (uint32_t)625000)

Macro used by the assert_param function in order to check the maximum baudrate value.

Definition at line 319 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define IS_UART1_CLEAR_FLAG_OK ( Flag )
Value:
(((Flag) == UART1_FLAG_RXNE) || \
   ((Flag) == UART1_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.

Definition at line 233 of file stm8s_uart1.h.

Referenced by UART1_ClearFlag().

#define IS_UART1_CLEAR_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART1_IT_RXNE) || \
   ((ITPendingBit) == UART1_IT_LBDF))

Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.

Definition at line 269 of file stm8s_uart1.h.

Referenced by UART1_ClearITPendingBit().

#define IS_UART1_CONFIG_IT_OK ( Interrupt )
Value:
(((Interrupt) == UART1_IT_PE) || \
   ((Interrupt) == UART1_IT_TXE) || \
   ((Interrupt) == UART1_IT_TC) || \
   ((Interrupt) == UART1_IT_RXNE_OR ) || \
   ((Interrupt) == UART1_IT_IDLE) || \
   ((Interrupt) == UART1_IT_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.

Definition at line 244 of file stm8s_uart1.h.

Referenced by UART1_ITConfig().

#define IS_UART1_FLAG_OK ( Flag )
Value:
(((Flag) == UART1_FLAG_TXE) || \
   ((Flag) == UART1_FLAG_TC)  || \
   ((Flag) == UART1_FLAG_RXNE) || \
   ((Flag) == UART1_FLAG_IDLE) || \
   ((Flag) == UART1_FLAG_OR) || \
   ((Flag) == UART1_FLAG_NF) || \
   ((Flag) == UART1_FLAG_FE) || \
   ((Flag) == UART1_FLAG_PE) || \
   ((Flag) == UART1_FLAG_SBK) || \
   ((Flag) == UART1_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.

Definition at line 218 of file stm8s_uart1.h.

Referenced by UART1_GetFlagStatus().

#define IS_UART1_GET_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART1_IT_TXE)  || \
   ((ITPendingBit) == UART1_IT_TC)   || \
   ((ITPendingBit) == UART1_IT_RXNE) || \
   ((ITPendingBit) == UART1_IT_IDLE) || \
   ((ITPendingBit) == UART1_IT_OR)  || \
   ((ITPendingBit) == UART1_IT_LBDF)  || \
   ((ITPendingBit) == UART1_IT_PE))

Macro used by the assert function in order to check the different sensitivity values for the pending bit.

Definition at line 256 of file stm8s_uart1.h.

Referenced by UART1_GetITStatus().

#define IS_UART1_IRDAMODE_OK ( IrDAMode )
Value:
(((IrDAMode) == UART1_IRDAMODE_LOWPOWER) || \
   ((IrDAMode) == UART1_IRDAMODE_NORMAL))

Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.

Definition at line 278 of file stm8s_uart1.h.

Referenced by UART1_IrDAConfig().

#define IS_UART1_LINBREAKDETECTIONLENGTH_OK ( LINBreakDetectionLength )
Value:
(((LINBreakDetectionLength) == UART1_LINBREAKDETECTIONLENGTH_10BITS) || \
   ((LINBreakDetectionLength) == UART1_LINBREAKDETECTIONLENGTH_11BITS))

Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.

Definition at line 294 of file stm8s_uart1.h.

Referenced by UART1_LINBreakDetectionConfig().

#define IS_UART1_MODE_OK ( Mode )
Value:
(((Mode) == (uint8_t)UART1_MODE_RX_ENABLE) || \
   ((Mode) == (uint8_t)UART1_MODE_RX_DISABLE) || \
   ((Mode) == (uint8_t)UART1_MODE_TX_ENABLE) || \
   ((Mode) == (uint8_t)UART1_MODE_TX_DISABLE) || \
   ((Mode) == (uint8_t)UART1_MODE_TXRX_ENABLE) || \
   ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_ENABLE|(uint8_t)UART1_MODE_RX_ENABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_ENABLE|(uint8_t)UART1_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_DISABLE|(uint8_t)UART1_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_DISABLE|(uint8_t)UART1_MODE_RX_ENABLE)))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert_param function in order to check the different sensitivity values for the MODEs possible combination should be one of the following

Definition at line 184 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define IS_UART1_PARITY_OK ( Parity )
Value:
(((Parity) == UART1_PARITY_NO) || \
                                    ((Parity) == UART1_PARITY_EVEN) || \
                                    ((Parity) == UART1_PARITY_ODD ))

Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.

Definition at line 311 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define IS_UART1_STOPBITS_OK ( StopBit )
Value:
(((StopBit) == UART1_STOPBITS_1) || \
                                       ((StopBit) == UART1_STOPBITS_0_5) || \
                                       ((StopBit) == UART1_STOPBITS_2) || \
                                       ((StopBit) == UART1_STOPBITS_1_5 ))

Macro used by the assert_param function in order to check the different sensitivity values for the UART1_StopBits.

Definition at line 302 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define IS_UART1_SYNCMODE_OK ( SyncMode )
Value:
(!((((SyncMode)&(((uint8_t)UART1_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART1_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART1_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART1_SYNCMODE_CLOCK_DISABLE))) \
    || (((SyncMode)&(((uint8_t)UART1_SYNCMODE_CPOL_LOW )|((uint8_t)UART1_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART1_SYNCMODE_CPOL_LOW )|((uint8_t)UART1_SYNCMODE_CPOL_HIGH))) \
    ||(((SyncMode)&(((uint8_t)UART1_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART1_SYNCMODE_CPHA_BEGINING))) ==  (((uint8_t)UART1_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART1_SYNCMODE_CPHA_BEGINING))) \
    || (((SyncMode)&(((uint8_t)UART1_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART1_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART1_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART1_SYNCMODE_LASTBIT_ENABLE)))))

Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART1_CLOCK_ENABLE|UART1_CLOCK_DISABLE.

Definition at line 208 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define IS_UART1_WAKEUP_OK ( WakeUp )
Value:
(((WakeUp) == UART1_WAKEUP_IDLELINE) || \
   ((WakeUp) == UART1_WAKEUP_ADDRESSMARK))

Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.

Definition at line 286 of file stm8s_uart1.h.

Referenced by UART1_WakeUpConfig().

#define IS_UART1_WORDLENGTH_OK ( WordLength )
Value:
(((WordLength) == UART1_WORDLENGTH_8D) || \
   ((WordLength) == UART1_WORDLENGTH_9D))

Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.

Definition at line 199 of file stm8s_uart1.h.

Referenced by UART1_Init().

#define UART1_ADDRESS_MAX ((uint8_t)16)

Macro used by the assert_param function in order to check the address of the UART1 or UART node.

Definition at line 326 of file stm8s_uart1.h.


STM8S/A Standard Peripherals Drivers: UART1_Exported_Functions

Functions

UART1_Exported_Functions

STM8S_StdPeriph_Driver

Functions

void | UART1_ClearFlag (UART1_Flag_TypeDef UART1_FLAG)
Clears the UART1 flags.
void | UART1_ClearITPendingBit (UART1_IT_TypeDef UART1_IT)
Clears the UART1 pending flags.
void | UART1_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART1_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART1_GetFlagStatus (UART1_Flag_TypeDef UART1_FLAG)
Checks whether the specified UART1 flag is set or not.
ITStatus | UART1_GetITStatus (UART1_IT_TypeDef UART1_IT)
Checks whether the specified UART1 interrupt has occurred or not.
void | UART1_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART1_Init (uint32_t BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
Initializes the UART1 according to the specified parameters.
void | UART1_IrDACmd (FunctionalState NewState)
Enables or disables the UART’s IrDA interface.
void | UART1_IrDAConfig (UART1_IrDAMode_TypeDef UART1_IrDAMode)
Configures the UART’s IrDA interface.
void | UART1_ITConfig (UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | UART1_LINBreakDetectionConfig (UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
Sets the UART1 LIN Break detection length.
void | UART1_LINCmd (FunctionalState NewState)
Enables or disables the UART1’s LIN mode.
uint8_t | UART1_ReceiveData8 (void)
Returns the most recent received data by the UART1 peripheral.
uint16_t | UART1_ReceiveData9 (void)
Returns the most recent received data by the UART1 peripheral.
void | UART1_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART1 is in mute mode or not.
void | UART1_SendBreak (void)
Transmits break characters.
void | UART1_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART1 peripheral.
void | UART1_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART peripheral.
void | UART1_SetAddress (uint8_t UART1_Address)
Sets the address of the UART1 node.
void | UART1_SetGuardTime (uint8_t UART1_GuardTime)
Sets the specified UART guard time.
void | UART1_SetPrescaler (uint8_t UART1_Prescaler)
Sets the system clock prescaler.
void | UART1_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART1 Smart Card mode.
void | UART1_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART1_WakeUpConfig (UART1_WakeUp_TypeDef UART1_WakeUp)
Selects the UART1 WakeUp method.

Function Documentation

void UART1_ClearFlag ( UART1_Flag_TypeDef UART1_FLAG )

Clears the UART1 flags.

Parameters:
UART1_FLAG specifies the flag to clear This parameter can be any combination of the following values:

  • UART1_FLAG_LBDF: LIN Break detection flag.
  • UART1_FLAG_RXNE: Receive data register not empty flag.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART1_SR register (UART1_GetFlagStatus())followed by a read operation to UART1_DR register(UART1_ReceiveData8() or UART1_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART1_DR register (UART1_ReceiveData8()or UART1_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART1_SR register (UART1_GetFlagStatus()) followed by a write operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • TXE flag is cleared only by a write to the UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 639 of file stm8s_uart1.c.

References IS_UART1_CLEAR_FLAG_OK, UART1_CR4_LBDF, UART1_FLAG_RXNE, and UART1_SR_RXNE.

void UART1_ClearITPendingBit ( UART1_IT_TypeDef UART1_IT )

Clears the UART1 pending flags.

Parameters:
UART1_IT specifies the pending bit to clear This parameter can be one of the following values:

  • UART1_IT_LBDF: LIN Break detection interrupt
  • UART1_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART1_SR register (UART1_GetITStatus()) followed by a read operation to UART1_DR register (UART1_ReceiveData8() or UART1_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART1_DR register (UART1_ReceiveData8() or UART1_ReceiveData9()).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART1_SR register (UART1_GetITStatus()) followed by a write operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • TXE pending bit is cleared only by a write to the UART1_DR register (UART1_SendData8() or UART1_SendData9()).
    Return values:
    None

Definition at line 768 of file stm8s_uart1.c.

References IS_UART1_CLEAR_IT_OK, UART1_CR4_LBDF, UART1_IT_RXNE, and UART1_SR_RXNE.

void UART1_Cmd ( FunctionalState NewState )

Enable the UART1 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 177 of file stm8s_uart1.c.

References DISABLE, and UART1_CR1_UARTD.

void UART1_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 46 of file stm8s_uart1.c.

References UART1_BRR1_RESET_VALUE, UART1_BRR2_RESET_VALUE, UART1_CR1_RESET_VALUE, UART1_CR2_RESET_VALUE, UART1_CR3_RESET_VALUE, UART1_CR4_RESET_VALUE, UART1_CR5_RESET_VALUE, UART1_GTR_RESET_VALUE, and UART1_PSCR_RESET_VALUE.

FlagStatus UART1_GetFlagStatus ( UART1_Flag_TypeDef UART1_FLAG )

Checks whether the specified UART1 flag is set or not.

Parameters:
UART1_FLAG specifies the flag to check. This parameter can be any of the UART1_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 560 of file stm8s_uart1.c.

References IS_UART1_FLAG_OK, RESET, SET, UART1_FLAG_LBDF, and UART1_FLAG_SBK.

ITStatus UART1_GetITStatus ( UART1_IT_TypeDef UART1_IT )

Checks whether the specified UART1 interrupt has occurred or not.

Parameters:
UART1_IT,: Specifies the UART1 interrupt pending bit to check. This parameter can be one of the following values:

  • UART1_IT_LBDF: LIN Break detection interrupt
  • UART1_IT_TXE: Tansmit Data Register empty interrupt
  • UART1_IT_TC: Transmission complete interrupt
  • UART1_IT_RXNE: Receive Data register not empty interrupt
  • UART1_IT_IDLE: Idle line detection interrupt
  • UART1_IT_OR: OverRun Error interrupt
  • UART1_IT_PE: Parity Error interrupt
Return values:
The new state of UART1_IT (SET or RESET).

Definition at line 668 of file stm8s_uart1.c.

References IS_UART1_GET_IT_OK, RESET, SET, UART1_IT_LBDF, and UART1_IT_PE.

void UART1_HalfDuplexCmd ( FunctionalState NewState )

Enables or disables the UART’s Half Duplex communication.

Parameters:
NewState new state of the UART Communication. This parameter can be: ENABLE or DISABLE.
Return values:
None

< UART1 Half Duplex Enable

< UART1 Half Duplex Disable

Definition at line 258 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_HDSEL.

void UART1_Init | ( | uint32_t | BaudRate,
 |  | UART1_WordLength_TypeDef | WordLength,
 |  | UART1_StopBits_TypeDef | StopBits,
 |  | UART1_Parity_TypeDef | Parity,
 |  | UART1_SyncMode_TypeDef | SyncMode,
 |  | UART1_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART1 according to the specified parameters.

Note:
Configure in Push Pull or Open Drain mode the Tx pin by setting the correct I/O Port register according the product package and line configuration
Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART1_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART1_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART1_Parity_TypeDef enumeration.
SyncMode,: This parameter can be any of the UART1_SyncMode_TypeDef values.
Mode,: This parameter can be any of the UART1_Mode_TypeDef values
Return values:
None

Definition at line 83 of file stm8s_uart1.c.

References CLK_GetClockFreq(), IS_UART1_BAUDRATE_OK, IS_UART1_MODE_OK, IS_UART1_PARITY_OK, IS_UART1_STOPBITS_OK, IS_UART1_SYNCMODE_OK, IS_UART1_WORDLENGTH_OK, UART1_BRR1_DIVM, UART1_BRR2_DIVF, UART1_BRR2_DIVM, UART1_CR1_M, UART1_CR1_PCEN, UART1_CR1_PS, UART1_CR2_REN, UART1_CR2_TEN, UART1_CR3_CKEN, UART1_CR3_CPHA, UART1_CR3_CPOL, UART1_CR3_LBCL, UART1_CR3_STOP, UART1_MODE_RX_ENABLE, UART1_MODE_TX_ENABLE, and UART1_SYNCMODE_CLOCK_DISABLE.

void UART1_IrDACmd ( FunctionalState NewState )

Enables or disables the UART’s IrDA interface.

Parameters:
NewState new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 298 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_IREN.

void UART1_IrDAConfig ( UART1_IrDAMode_TypeDef UART1_IrDAMode )

Configures the UART’s IrDA interface.

Parameters:
UART1_IrDAMode specifies the IrDA mode. This parameter can be any of the UART1_IrDAMode_TypeDef values.
Return values:
None

Definition at line 278 of file stm8s_uart1.c.

References IS_UART1_IRDAMODE_OK, UART1_CR5_IRLP, and UART1_IRDAMODE_NORMAL.

void UART1_ITConfig | ( | UART1_IT_TypeDef | UART1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART interrupts.

Parameters:
UART1_IT specifies the USART interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • UART1_IT_TXE: Tansmit Data Register empty interrupt
  • UART1_IT_TC: Transmission complete interrupt
  • UART1_IT_RXNE: Receive Data register not empty interrupt
  • UART1_IT_OR: Overrun error interrupt
  • UART1_IT_IDLE: Idle line detection interrupt
  • USRT1_IT_ERR: Error interrupt
NewState new state of the specified USART interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

< Enable the Interrupt bits according to UART1_IT mask

< Disable the interrupt bits according to UART1_IT mask

Definition at line 205 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART1_CONFIG_IT_OK.

void UART1_LINBreakDetectionConfig ( UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength )

Sets the UART1 LIN Break detection length.

Parameters:
UART1_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART1_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 323 of file stm8s_uart1.c.

References IS_UART1_LINBREAKDETECTIONLENGTH_OK, UART1_CR4_LBDL, and UART1_LINBREAKDETECTIONLENGTH_10BITS.

void UART1_LINCmd ( FunctionalState NewState )

Enables or disables the UART1’s LIN mode.

Parameters:
NewState is new state of the UART1 LIN mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 343 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR3_LINEN.

uint8_t UART1_ReceiveData8 ( void )

Returns the most recent received data by the UART1 peripheral.

Parameters:
None
Return values:
The received data.

Definition at line 443 of file stm8s_uart1.c.

uint16_t UART1_ReceiveData9 ( void )

Returns the most recent received data by the UART1 peripheral.

Parameters:
None
Return values:
The received data.

Definition at line 453 of file stm8s_uart1.c.

References UART1_CR1_R8.

void UART1_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART1 is in mute mode or not.

Parameters:
NewState,: new state of the UART1 mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 422 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR2_RWU.

void UART1_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 493 of file stm8s_uart1.c.

References UART1_CR2_SBK.

void UART1_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART1 peripheral.

Parameters:
Data,: The data to transmit.
Return values:
None

Definition at line 466 of file stm8s_uart1.c.

void UART1_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART peripheral.

Parameters:
Data : The data to transmit. This parameter should be lower than 0x1FF.
Return values:
None

< Clear the transmit data bit 8 [8]

< Write the transmit data bit [8]

< Write the transmit data bit [0:7]

Definition at line 478 of file stm8s_uart1.c.

References UART1_CR1_T8.

void UART1_SetAddress ( uint8_t UART1_Address )

Sets the address of the UART1 node.

Parameters:
UART1_Address,: Indicates the address of the UART1 node.
Return values:
None

Definition at line 503 of file stm8s_uart1.c.

References IS_UART1_ADDRESS_OK, and UART1_CR4_ADD.

void UART1_SetGuardTime ( uint8_t UART1_GuardTime )

Sets the specified UART guard time.

Note:
SmartCard Mode should be Enabled
Parameters:
UART1_GuardTime,: specifies the guard time.
Return values:
None

Definition at line 520 of file stm8s_uart1.c.

void UART1_SetPrescaler ( uint8_t UART1_Prescaler )

Sets the system clock prescaler.

Note:
IrDA Low Power mode or smartcard mode should be enabled
This function is related to SmartCard and IrDa mode.
Parameters:
UART1_Prescaler,: specifies the prescaler clock. This parameter can be one of the following values:
IrDA Low Power Mode
The clock source is divided by the value given in the register (8 bits)
  • 0000 0000 Reserved
  • 0000 0001 divides the clock source by 1
  • 0000 0010 divides the clock source by 2
  • ...........................................................
Smart Card Mode
The clock source is divided by the value given in the register (5 significant bits) multiplied by 2
  • 0 0000 Reserved
  • 0 0001 divides the clock source by 2
  • 0 0010 divides the clock source by 4
  • 0 0011 divides the clock source by 6
  • ...........................................................
Return values:
None

Definition at line 548 of file stm8s_uart1.c.

void UART1_SmartCardCmd ( FunctionalState NewState )

Enables or disables the UART1 Smart Card mode.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 364 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_SCEN.

void UART1_SmartCardNACKCmd ( FunctionalState NewState )

Enables or disables NACK transmission.

Note:
This function is valid only for UART1 because is related to SmartCard mode.
Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 387 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_NACK.

void UART1_WakeUpConfig ( UART1_WakeUp_TypeDef UART1_WakeUp )

Selects the UART1 WakeUp method.

Parameters:
UART1_WakeUp,: specifies the UART1 wakeup method. This parameter can be any of the UART1_WakeUp_TypeDef values.
Return values:
None

Definition at line 409 of file stm8s_uart1.c.

References IS_UART1_WAKEUP_OK, and UART1_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: UART2_Exported_Types

Enumerations

UART2_Exported_Types

STM8S_StdPeriph_Driver

Enumerations

enum UART2_Flag_TypeDef {
UART2_FLAG_TXE = (uint16_t)0x0080, UART2_FLAG_TC = (uint16_t)0x0040, UART2_FLAG_RXNE = (uint16_t)0x0020, UART2_FLAG_IDLE = (uint16_t)0x0010,
UART2_FLAG_OR_LHE = (uint16_t)0x0008, UART2_FLAG_NF = (uint16_t)0x0004, UART2_FLAG_FE = (uint16_t)0x0002, UART2_FLAG_PE = (uint16_t)0x0001,
UART2_FLAG_SBK = (uint16_t)0x0101, UART2_FLAG_LBDF = (uint16_t)0x0210, UART2_FLAG_LHDF = (uint16_t)0x0302, UART2_FLAG_LSF = (uint16_t)0x0301
}

UART2 Flag possible values.

More...
enum | UART2_IrDAMode_TypeDef { UART2_IRDAMODE_NORMAL = (uint8_t)0x00, UART2_IRDAMODE_LOWPOWER = (uint8_t)0x01 }

UART2 Irda Modes.

More...
enum UART2_IT_TypeDef {
UART2_IT_TXE = (uint16_t)0x0277, UART2_IT_TC = (uint16_t)0x0266, UART2_IT_RXNE = (uint16_t)0x0255, UART2_IT_IDLE = (uint16_t)0x0244,
UART2_IT_OR = (uint16_t)0x0235, UART2_IT_PE = (uint16_t)0x0100, UART2_IT_LBDF = (uint16_t)0x0346, UART2_IT_LHDF = (uint16_t)0x0412,
UART2_IT_RXNE_OR = (uint16_t)0x0205
}

UART2 Interrupt definition UART2_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt

  • For the following values, X means the interrupt position in the CR2 register.
More...
enum | UART2_LinAutosync_TypeDef { UART2_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, UART2_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 }

UART2 automatic resynchronisation possible values.

More...
enum | UART2_LINBreakDetectionLength_TypeDef { UART2_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART2_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }

UART2 LIN Break detection length possible values.

More...
enum | UART2_LinDivUp_TypeDef { UART2_LIN_DIVUP_LBRR1 = (uint8_t)0x00, UART2_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 }

UART2 Divider Update Method possible values.

More...
enum | UART2_LinMode_TypeDef { UART2_LIN_MODE_MASTER = (uint8_t)0x00, UART2_LIN_MODE_SLAVE = (uint8_t)0x01 }

UART2 Mode possible values.

More...
enum UART2_Mode_TypeDef {
UART2_MODE_RX_ENABLE = (uint8_t)0x08, UART2_MODE_TX_ENABLE = (uint8_t)0x04, UART2_MODE_TX_DISABLE = (uint8_t)0x80, UART2_MODE_RX_DISABLE = (uint8_t)0x40,
UART2_MODE_TXRX_ENABLE = (uint8_t)0x0C
}

UART2 Mode possible values.

More...
enum | UART2_Parity_TypeDef { UART2_PARITY_NO = (uint8_t)0x00, UART2_PARITY_EVEN = (uint8_t)0x04, UART2_PARITY_ODD = (uint8_t)0x06 }

UART2 parity possible values.

More...
enum | UART2_StopBits_TypeDef { UART2_STOPBITS_1 = (uint8_t)0x00, UART2_STOPBITS_0_5 = (uint8_t)0x10, UART2_STOPBITS_2 = (uint8_t)0x20, UART2_STOPBITS_1_5 = (uint8_t)0x30 }

UART2 stop bits possible values.

More...
enum UART2_SyncMode_TypeDef {
UART2_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, UART2_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, UART2_SYNCMODE_CPOL_LOW = (uint8_t)0x40, UART2_SYNCMODE_CPOL_HIGH = (uint8_t)0x04,
UART2_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, UART2_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, UART2_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, UART2_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01
}

UART2 Synchrone modes.

More...
enum | UART2_WakeUp_TypeDef { UART2_WAKEUP_IDLELINE = (uint8_t)0x00, UART2_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }

UART2 WakeUP Modes.

More...
enum | UART2_WordLength_TypeDef { UART2_WORDLENGTH_8D = (uint8_t)0x00, UART2_WORDLENGTH_9D = (uint8_t)0x10 }

UART2 Word length possible values.

More...

Enumeration Type Documentation

enum UART2_Flag_TypeDef

UART2 Flag possible values.

Enumerator:
UART2_FLAG_TXE

Transmit Data Register Empty flag

UART2_FLAG_TC

Transmission Complete flag

UART2_FLAG_RXNE

Read Data Register Not Empty flag

UART2_FLAG_IDLE

Idle line detected flag

UART2_FLAG_OR_LHE

OverRun error flag

UART2_FLAG_NF

Noise error flag

UART2_FLAG_FE

Framing Error flag

UART2_FLAG_PE

Parity Error flag

UART2_FLAG_SBK

Send Break Complete interrupt flag.

UART2_FLAG_LBDF

LIN Break Detection Flag.

UART2_FLAG_LHDF

LIN Header Detection Flag.

UART2_FLAG_LSF

LIN Sync Field Flag.

Definition at line 133 of file stm8s_uart2.h.

enum UART2_IrDAMode_TypeDef

UART2 Irda Modes.

Enumerator:
UART2_IRDAMODE_NORMAL

0x00 Irda Normal Mode

UART2_IRDAMODE_LOWPOWER

0x01 Irda Low Power Mode

Definition at line 43 of file stm8s_uart2.h.

enum UART2_IT_TypeDef

UART2 Interrupt definition UART2_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt

  • For the following values, X means the interrupt position in the CR2 register.

UART2_IT_TXE UART2_IT_TC UART2_IT_RXNE UART2_IT_IDLE UART2_IT_OR

  • For the UART2_IT_PE value, X means the flag position in the CR1 register.
  • For the UART2_IT_LBDF value, X means the flag position in the CR4 register.
  • For the UART2_IT_LHDF value, X means the flag position in the CR6 register. Y: Flag position

For the following values, Y means the flag (pending bit) position in the SR register. UART2_IT_TXE UART2_IT_TC UART2_IT_RXNE UART2_IT_IDLE UART2_IT_OR UART2_IT_PE

  • For the UART2_IT_LBDF value, Y means the flag position in the CR4 register.
  • For the UART2_IT_LHDF value, Y means the flag position in the CR6 register. Z: Register index: indicate in which register the dedicated interrupt source is:
  • 1==> CR1 register
  • 2==> CR2 register
  • 3==> CR4 register
  • 4==> CR6 register
Enumerator:
UART2_IT_TXE

Transmit interrupt.

UART2_IT_TC

Transmission Complete interrupt.

UART2_IT_RXNE

Data Register Not Empty interrupt.

UART2_IT_IDLE

Idle line detected interrupt.

UART2_IT_OR

OverRun error interrupt.

UART2_IT_PE

Parity Error interrupt.

UART2_IT_LBDF

LIN Break Detection interrupt.

UART2_IT_LHDF

LIN Header Detection interrupt.

UART2_IT_RXNE_OR

Receive/Overrun interrupt

Definition at line 179 of file stm8s_uart2.h.

enum UART2_LinAutosync_TypeDef

UART2 automatic resynchronisation possible values.

Enumerator:
UART2_LIN_AUTOSYNC_DISABLE

LIN Autosynchronization Disable.

UART2_LIN_AUTOSYNC_ENABLE

LIN Autosynchronization Enable.

Definition at line 91 of file stm8s_uart2.h.

enum UART2_LINBreakDetectionLength_TypeDef

UART2 LIN Break detection length possible values.

Enumerator:
UART2_LINBREAKDETECTIONLENGTH_10BITS

0x01 10 bits Lin Break detection

UART2_LINBREAKDETECTIONLENGTH_11BITS

0x02 11 bits Lin Break detection

Definition at line 60 of file stm8s_uart2.h.

enum UART2_LinDivUp_TypeDef

UART2 Divider Update Method possible values.

Enumerator:
UART2_LIN_DIVUP_LBRR1

LIN LDIV is updated as soon as LBRR1 is written.

UART2_LIN_DIVUP_NEXTRXNE

LIN LDIV is updated at the next received character.

Definition at line 97 of file stm8s_uart2.h.

enum UART2_LinMode_TypeDef

UART2 Mode possible values.

Enumerator:
UART2_LIN_MODE_MASTER

LIN Master Mode.

UART2_LIN_MODE_SLAVE

LIN Slave Mode.

Definition at line 85 of file stm8s_uart2.h.

enum UART2_Mode_TypeDef

UART2 Mode possible values.

Enumerator:
UART2_MODE_RX_ENABLE

0x08 Receive Enable

UART2_MODE_TX_ENABLE

0x04 Transmit Enable

UART2_MODE_TX_DISABLE

0x80 Transmit Disable

UART2_MODE_RX_DISABLE

0x40 Single-wire Half-duplex mode

UART2_MODE_TXRX_ENABLE

0x0C Transmit Enable and Receive Enable

Definition at line 124 of file stm8s_uart2.h.

enum UART2_Parity_TypeDef

UART2 parity possible values.

Enumerator:
UART2_PARITY_NO

No Parity.

UART2_PARITY_EVEN

Even Parity.

UART2_PARITY_ODD

Odd Parity.

Definition at line 78 of file stm8s_uart2.h.

enum UART2_StopBits_TypeDef

UART2 stop bits possible values.

Enumerator:
UART2_STOPBITS_1

One stop bit is transmitted at the end of frame.

UART2_STOPBITS_0_5

Half stop bits is transmitted at the end of frame.

UART2_STOPBITS_2

Two stop bits are transmitted at the end of frame.

UART2_STOPBITS_1_5

One and half stop bits.

Definition at line 68 of file stm8s_uart2.h.

enum UART2_SyncMode_TypeDef

UART2 Synchrone modes.

Enumerator:
UART2_SYNCMODE_CLOCK_DISABLE

0x80 Sync mode Disable, SLK pin Disable

UART2_SYNCMODE_CLOCK_ENABLE

0x08 Sync mode Enable, SLK pin Enable

UART2_SYNCMODE_CPOL_LOW

0x40 Steady low value on SCLK pin outside transmission window

UART2_SYNCMODE_CPOL_HIGH

0x04 Steady high value on SCLK pin outside transmission window

UART2_SYNCMODE_CPHA_MIDDLE

0x20 SCLK clock line activated in middle of data bit

UART2_SYNCMODE_CPHA_BEGINING

0x02 SCLK clock line activated at beginning of data bit

UART2_SYNCMODE_LASTBIT_DISABLE

0x10 The clock pulse of the last data bit is not output to the SCLK pin

UART2_SYNCMODE_LASTBIT_ENABLE

0x01 The clock pulse of the last data bit is output to the SCLK pin

Definition at line 104 of file stm8s_uart2.h.

enum UART2_WakeUp_TypeDef

UART2 WakeUP Modes.

Enumerator:
UART2_WAKEUP_IDLELINE

0x01 Idle Line wake up

UART2_WAKEUP_ADDRESSMARK

0x02 Address Mark wake up

Definition at line 52 of file stm8s_uart2.h.

enum UART2_WordLength_TypeDef

UART2 Word length possible values.

Enumerator:
UART2_WORDLENGTH_8D

0x00 8 bits Data

UART2_WORDLENGTH_9D

0x10 9 bits Data

Definition at line 117 of file stm8s_uart2.h.


STM8S/A Standard Peripherals Drivers: UART2_Private_Macros

Defines

UART2_Private_Macros

STM8S_StdPeriph_Driver

Defines

#define | IS_UART2_ADDRESS_OK(node) ((node) < UART2_ADDRESS_MAX )
#define | IS_UART2_AUTOSYNC_OK(AutosyncMode)
Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.
#define | IS_UART2_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART2_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART2_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART2_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART2_DIVUP_OK(DivupMethode)
Macro used by the assert_param function in order to check the LIN divider update method.
#define | IS_UART2_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART2_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART2_IRDAMODE_OK(IrDAMode)
Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.
#define | IS_UART2_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART2_MODE_OK(Mode)
Macro used by the assert function to check the different functions parameters.
#define | IS_UART2_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.
#define | IS_UART2_SLAVE_OK(Mode)
Macro used by the assert_param function in order to check the LIN mode.
#define | IS_UART2_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART2_StopBits.
#define | IS_UART2_SYNCMODE_OK(SyncMode)
Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART2_CLOCK_ENABLE|UART2_CLOCK_DISABLE.
#define | IS_UART2_WAKEUP_OK(WakeUp)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART2_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART2_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART2 or UART node.

Define Documentation

#define IS_UART2_ADDRESS_OK ( node ) ((node) < UART2_ADDRESS_MAX )

Definition at line 363 of file stm8s_uart2.h.

Referenced by UART2_SetAddress().

#define IS_UART2_AUTOSYNC_OK ( AutosyncMode )
Value:
(((AutosyncMode) ==  UART2_LIN_AUTOSYNC_ENABLE) || \
   ((AutosyncMode) == UART2_LIN_AUTOSYNC_DISABLE))

Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.

Definition at line 376 of file stm8s_uart2.h.

Referenced by UART2_LINConfig().

#define IS_UART2_BAUDRATE_OK ( NUM ) ((NUM) <= (uint32_t)625000)

Macro used by the assert_param function in order to check the maximum baudrate value.

Definition at line 355 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define IS_UART2_CLEAR_FLAG_OK ( Flag )
Value:
(((Flag) == UART2_FLAG_RXNE) || \
   ((Flag) == UART2_FLAG_LHDF) || \
   ((Flag) == UART2_FLAG_LSF) || \
   ((Flag) == UART2_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.

Definition at line 266 of file stm8s_uart2.h.

Referenced by UART2_ClearFlag().

#define IS_UART2_CLEAR_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART2_IT_RXNE) || \
   ((ITPendingBit) == UART2_IT_LHDF) || \
   ((ITPendingBit) == UART2_IT_LBDF))

Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.

Definition at line 304 of file stm8s_uart2.h.

Referenced by UART2_ClearITPendingBit().

#define IS_UART2_CONFIG_IT_OK ( Interrupt )
Value:
(((Interrupt) == UART2_IT_PE) || \
   ((Interrupt) == UART2_IT_TXE) || \
   ((Interrupt) == UART2_IT_TC) || \
   ((Interrupt) == UART2_IT_RXNE_OR ) || \
   ((Interrupt) == UART2_IT_IDLE) || \
   ((Interrupt) == UART2_IT_LHDF) || \
   ((Interrupt) == UART2_IT_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.

Definition at line 277 of file stm8s_uart2.h.

Referenced by UART2_ITConfig().

#define IS_UART2_DIVUP_OK ( DivupMethode )
Value:
(((DivupMethode) == UART2_LIN_DIVUP_LBRR1) || \
   ((DivupMethode) == UART2_LIN_DIVUP_NEXTRXNE))

Macro used by the assert_param function in order to check the LIN divider update method.

Definition at line 383 of file stm8s_uart2.h.

Referenced by UART2_LINConfig().

#define IS_UART2_FLAG_OK ( Flag )
Value:
(((Flag) == UART2_FLAG_TXE) || \
   ((Flag) == UART2_FLAG_TC)  || \
   ((Flag) == UART2_FLAG_RXNE) || \
   ((Flag) == UART2_FLAG_IDLE) || \
   ((Flag) == UART2_FLAG_OR_LHE) || \
   ((Flag) == UART2_FLAG_NF) || \
   ((Flag) == UART2_FLAG_FE) || \
   ((Flag) == UART2_FLAG_PE) || \
   ((Flag) == UART2_FLAG_SBK) || \
   ((Flag) == UART2_FLAG_LSF) || \
   ((Flag) == UART2_FLAG_LHDF) || \
   ((Flag) == UART2_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.

Definition at line 247 of file stm8s_uart2.h.

Referenced by UART2_GetFlagStatus().

#define IS_UART2_GET_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART2_IT_TXE)  || \
   ((ITPendingBit) == UART2_IT_TC)   || \
   ((ITPendingBit) == UART2_IT_RXNE) || \
   ((ITPendingBit) == UART2_IT_IDLE) || \
   ((ITPendingBit) == UART2_IT_OR)  || \
   ((ITPendingBit) == UART2_IT_LBDF)  || \
   ((ITPendingBit) == UART2_IT_LHDF)  || \
   ((ITPendingBit) == UART2_IT_PE))

Macro used by the assert function in order to check the different sensitivity values for the pending bit.

Definition at line 290 of file stm8s_uart2.h.

Referenced by UART2_GetITStatus().

#define IS_UART2_IRDAMODE_OK ( IrDAMode )
Value:
(((IrDAMode) == UART2_IRDAMODE_LOWPOWER) || \
   ((IrDAMode) == UART2_IRDAMODE_NORMAL))

Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.

Definition at line 314 of file stm8s_uart2.h.

Referenced by UART2_IrDAConfig().

#define IS_UART2_LINBREAKDETECTIONLENGTH_OK ( LINBreakDetectionLength )
Value:
(((LINBreakDetectionLength) == UART2_LINBREAKDETECTIONLENGTH_10BITS) || \
   ((LINBreakDetectionLength) == UART2_LINBREAKDETECTIONLENGTH_11BITS))

Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.

Definition at line 330 of file stm8s_uart2.h.

Referenced by UART2_LINBreakDetectionConfig().

#define IS_UART2_MODE_OK ( Mode )
Value:
(((Mode) == (uint8_t)UART2_MODE_RX_ENABLE) || \
   ((Mode) == (uint8_t)UART2_MODE_RX_DISABLE) || \
   ((Mode) == (uint8_t)UART2_MODE_TX_ENABLE) || \
   ((Mode) == (uint8_t)UART2_MODE_TX_DISABLE) || \
   ((Mode) == (uint8_t)UART2_MODE_TXRX_ENABLE) || \
   ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_ENABLE|(uint8_t)UART2_MODE_RX_ENABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_ENABLE|(uint8_t)UART2_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_DISABLE|(uint8_t)UART2_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_DISABLE|(uint8_t)UART2_MODE_RX_ENABLE)))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert_param function in order to check the different sensitivity values for the MODEs possible combination should be one of the following.

Definition at line 213 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define IS_UART2_PARITY_OK ( Parity )
Value:
(((Parity) == UART2_PARITY_NO) || \
                                    ((Parity) == UART2_PARITY_EVEN) || \
                                    ((Parity) == UART2_PARITY_ODD ))

Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.

Definition at line 347 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define IS_UART2_SLAVE_OK ( Mode )
Value:
(((Mode) == UART2_LIN_MODE_MASTER) || \
   ((Mode) == UART2_LIN_MODE_SLAVE))

Macro used by the assert_param function in order to check the LIN mode.

Definition at line 368 of file stm8s_uart2.h.

Referenced by UART2_LINConfig().

#define IS_UART2_STOPBITS_OK ( StopBit )
Value:
(((StopBit) == UART2_STOPBITS_1) || \
                                       ((StopBit) == UART2_STOPBITS_0_5) || \
                                       ((StopBit) == UART2_STOPBITS_2) || \
                                       ((StopBit) == UART2_STOPBITS_1_5 ))

Macro used by the assert_param function in order to check the different sensitivity values for the UART2_StopBits.

Definition at line 338 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define IS_UART2_SYNCMODE_OK ( SyncMode )
Value:
(!((((SyncMode)&(((uint8_t)UART2_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART2_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART2_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART2_SYNCMODE_CLOCK_DISABLE))) || \
     (((SyncMode)&(((uint8_t)UART2_SYNCMODE_CPOL_LOW )|((uint8_t)UART2_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART2_SYNCMODE_CPOL_LOW )|((uint8_t)UART2_SYNCMODE_CPOL_HIGH))) || \
     (((SyncMode)&(((uint8_t)UART2_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART2_SYNCMODE_CPHA_BEGINING))) == (((uint8_t)UART2_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART2_SYNCMODE_CPHA_BEGINING))) || \
     (((SyncMode)&(((uint8_t)UART2_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART2_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART2_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART2_SYNCMODE_LASTBIT_ENABLE)))))

Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART2_CLOCK_ENABLE|UART2_CLOCK_DISABLE.

Definition at line 237 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define IS_UART2_WAKEUP_OK ( WakeUp )
Value:
(((WakeUp) == UART2_WAKEUP_IDLELINE) || \
   ((WakeUp) == UART2_WAKEUP_ADDRESSMARK))

Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.

Definition at line 322 of file stm8s_uart2.h.

Referenced by UART2_WakeUpConfig().

#define IS_UART2_WORDLENGTH_OK ( WordLength )
Value:
(((WordLength) == UART2_WORDLENGTH_8D) || \
   ((WordLength) == UART2_WORDLENGTH_9D))

Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.

Definition at line 228 of file stm8s_uart2.h.

Referenced by UART2_Init().

#define UART2_ADDRESS_MAX ((uint8_t)16)

Macro used by the assert_param function in order to check the address of the UART2 or UART node.

Definition at line 362 of file stm8s_uart2.h.


STM8S/A Standard Peripherals Drivers: UART2_Exported_Functions

Functions

UART2_Exported_Functions

STM8S_StdPeriph_Driver

Functions

void | UART2_ClearFlag (UART2_Flag_TypeDef UART2_FLAG)
Clears the UART2 flags.
void | UART2_ClearITPendingBit (UART2_IT_TypeDef UART2_IT)
Clears the UART2 pending flags.
void | UART2_Cmd (FunctionalState NewState)
Enable the UART2 peripheral.
void | UART2_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART2_GetFlagStatus (UART2_Flag_TypeDef UART2_FLAG)
Checks whether the specified UART2 flag is set or not.
ITStatus | UART2_GetITStatus (UART2_IT_TypeDef UART2_IT)
Checks whether the specified UART2 interrupt has occurred or not.
void | UART2_HalfDuplexCmd (FunctionalState NewState)
void | UART2_Init (uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
Initializes the UART2 according to the specified parameters.
void | UART2_IrDACmd (FunctionalState NewState)
Enables or disables the UART2’s IrDA interface.
void | UART2_IrDAConfig (UART2_IrDAMode_TypeDef UART2_IrDAMode)
Configures the UART2’s IrDA interface.
void | UART2_ITConfig (UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
Enables or disables the specified UART2 interrupts.
void | UART2_LINBreakDetectionConfig (UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
Sets the UART2 LIN Break detection length.
void | UART2_LINCmd (FunctionalState NewState)
Enables or disables the UART2 LIN mode.
void | UART2_LINConfig (UART2_LinMode_TypeDef UART2_Mode, UART2_LinAutosync_TypeDef UART2_Autosync, UART2_LinDivUp_TypeDef UART2_DivUp)
Configure the UART2 peripheral.
uint8_t | UART2_ReceiveData8 (void)
Returns the most recent received data by the UART2 peripheral.
uint16_t | UART2_ReceiveData9 (void)
Returns the most recent received data by the UART2 peripheral.
void | UART2_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART2 is in mute mode or not.
void | UART2_SendBreak (void)
Transmits break characters.
void | UART2_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART2 peripheral.
void | UART2_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART2 peripheral.
void | UART2_SetAddress (uint8_t UART2_Address)
Sets the address of the UART2 node.
void | UART2_SetGuardTime (uint8_t UART2_GuardTime)
Sets the specified UART2 guard time.
void | UART2_SetPrescaler (uint8_t UART2_Prescaler)
Sets the system clock prescaler.
void | UART2_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART2 Smart Card mode.
void | UART2_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART2_WakeUpConfig (UART2_WakeUp_TypeDef UART2_WakeUp)
Selects the UART2 WakeUp method.

Function Documentation

void UART2_ClearFlag ( UART2_Flag_TypeDef UART2_FLAG )

Clears the UART2 flags.

Parameters:
UART2_FLAG specifies the flag to clear This parameter can be any combination of the following values:

  • UART2_FLAG_LBDF: LIN Break detection flag.
  • UART2_FLAG_LHDF: LIN Header detection flag.
  • UART2_FLAG_LSF: LIN synchrone field flag.
  • UART2_FLAG_RXNE: Receive data register not empty flag.
Note:
:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART2_SR register (UART2_GetFlagStatus())followed by a read operation to UART2_DR register(UART2_ReceiveData8() or UART2_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART2_DR register (UART2_ReceiveData8()or UART2_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART2_SR register (UART2_GetFlagStatus()) followed by a write operation to UART2_DR register (UART2_SendData8() or UART2_SendData9()).
  • TXE flag is cleared only by a write to the UART2_DR register (UART2_SendData8() or UART2_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 693 of file stm8s_uart2.c.

References IS_UART2_CLEAR_FLAG_OK, UART2_CR4_LBDF, UART2_CR6_LHDF, UART2_CR6_LSF, UART2_FLAG_LBDF, UART2_FLAG_LHDF, UART2_FLAG_RXNE, and UART2_SR_RXNE.

void UART2_ClearITPendingBit ( UART2_IT_TypeDef UART2_IT )

Clears the UART2 pending flags.

Parameters:
UART2_IT specifies the pending bit to clear This parameter can be one of the following values:

  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_LHDF: LIN Header detection interrupt
  • UART2_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART2_SR register (UART2_GetITStatus()) followed by a read operation to UART2_DR register (UART2_ReceiveData8() or UART2_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART2_DR register (UART2_ReceiveData8() or UART2_ReceiveData9()).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART2_SR register (UART2_GetITStatus()) followed by a write operation to UART2_DR register (UART2_SendData8()or UART2_SendData9()).
  • TXE pending bit is cleared only by a write to the UART2_DR register (UART2_SendData8() or UART2_SendData9()).
    Return values:
    None

Definition at line 846 of file stm8s_uart2.c.

References IS_UART2_CLEAR_IT_OK, UART2_CR4_LBDF, UART2_CR6_LHDF, UART2_IT_LBDF, UART2_IT_RXNE, and UART2_SR_RXNE.

void UART2_Cmd ( FunctionalState NewState )

Enable the UART2 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 176 of file stm8s_uart2.c.

References DISABLE, and UART2_CR1_UARTD.

void UART2_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 47 of file stm8s_uart2.c.

References UART2_BRR1_RESET_VALUE, UART2_BRR2_RESET_VALUE, UART2_CR1_RESET_VALUE, UART2_CR2_RESET_VALUE, UART2_CR3_RESET_VALUE, UART2_CR4_RESET_VALUE, UART2_CR5_RESET_VALUE, and UART2_CR6_RESET_VALUE.

FlagStatus UART2_GetFlagStatus ( UART2_Flag_TypeDef UART2_FLAG )

Checks whether the specified UART2 flag is set or not.

Parameters:
UART2_FLAG specifies the flag to check. This parameter can be any of the UART2_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 601 of file stm8s_uart2.c.

References IS_UART2_FLAG_OK, RESET, SET, UART2_FLAG_LBDF, UART2_FLAG_LHDF, UART2_FLAG_LSF, and UART2_FLAG_SBK.

ITStatus UART2_GetITStatus ( UART2_IT_TypeDef UART2_IT )

Checks whether the specified UART2 interrupt has occurred or not.

Parameters:
UART2_IT,: Specifies the UART2 interrupt pending bit to check. This parameter can be one of the following values:

  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_TXE: Tansmit Data Register empty interrupt
  • UART2_IT_TC: Transmission complete interrupt
  • UART2_IT_RXNE: Receive Data register not empty interrupt
  • UART2_IT_IDLE: Idle line detection interrupt
  • UART2_IT_OR: OverRun Error interrupt
  • UART2_IT_PE: Parity Error interrupt
Return values:
The state of UART2_IT (SET or RESET).

Definition at line 732 of file stm8s_uart2.c.

References IS_UART2_GET_IT_OK, RESET, SET, UART2_IT_LBDF, UART2_IT_LHDF, and UART2_IT_PE.

void UART2_HalfDuplexCmd ( FunctionalState NewState )
void UART2_Init | ( | uint32_t | BaudRate,
 |  | UART2_WordLength_TypeDef | WordLength,
 |  | UART2_StopBits_TypeDef | StopBits,
 |  | UART2_Parity_TypeDef | Parity,
 |  | UART2_SyncMode_TypeDef | SyncMode,
 |  | UART2_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART2 according to the specified parameters.

Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART2_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART2_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART2_Parity_TypeDef enumeration.
SyncMode,: This parameter can be any of the UART2_SyncMode_TypeDef values.
Mode,: This parameter can be any of the UART2_Mode_TypeDef values
Return values:
None

Definition at line 80 of file stm8s_uart2.c.

References CLK_GetClockFreq(), IS_UART2_BAUDRATE_OK, IS_UART2_MODE_OK, IS_UART2_PARITY_OK, IS_UART2_STOPBITS_OK, IS_UART2_SYNCMODE_OK, IS_UART2_WORDLENGTH_OK, UART2_BRR1_DIVM, UART2_BRR2_DIVF, UART2_BRR2_DIVM, UART2_CR1_M, UART2_CR1_PCEN, UART2_CR1_PS, UART2_CR2_REN, UART2_CR2_TEN, UART2_CR3_CKEN, UART2_CR3_CPHA, UART2_CR3_CPOL, UART2_CR3_LBCL, UART2_CR3_STOP, UART2_MODE_RX_ENABLE, UART2_MODE_TX_ENABLE, and UART2_SYNCMODE_CLOCK_DISABLE.

void UART2_IrDACmd ( FunctionalState NewState )

Enables or disables the UART2’s IrDA interface.

Parameters:
NewState new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 287 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_IREN.

void UART2_IrDAConfig ( UART2_IrDAMode_TypeDef UART2_IrDAMode )

Configures the UART2’s IrDA interface.

Parameters:
UART2_IrDAMode specifies the IrDA mode. This parameter can be any of the UART2_IrDAMode_TypeDef values.
Return values:
None

Definition at line 267 of file stm8s_uart2.c.

References IS_UART2_IRDAMODE_OK, UART2_CR5_IRLP, and UART2_IRDAMODE_NORMAL.

void UART2_ITConfig | ( | UART2_IT_TypeDef | UART2_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified UART2 interrupts.

Parameters:
UART2_IT specifies the UART2 interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_LHDF: LIN Break detection interrupt
  • UART2_IT_TXE: Tansmit Data Register empty interrupt
  • UART2_IT_TC: Transmission complete interrupt
  • UART2_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
  • UART2_IT_IDLE: Idle line detection interrupt
  • UART2_IT_PE: Parity Error interrupt
NewState new state of the specified UART2 interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 206 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART2_CONFIG_IT_OK.

void UART2_LINBreakDetectionConfig ( UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength )

Sets the UART2 LIN Break detection length.

Parameters:
UART2_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART2_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 311 of file stm8s_uart2.c.

References IS_UART2_LINBREAKDETECTIONLENGTH_OK, UART2_CR4_LBDL, and UART2_LINBREAKDETECTIONLENGTH_10BITS.

void UART2_LINCmd ( FunctionalState NewState )

Enables or disables the UART2 LIN mode.

Parameters:
NewState is new state of the UART2 LIN mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 379 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR3_LINEN.

void UART2_LINConfig | ( | UART2_LinMode_TypeDef | UART2_Mode,
 |  | UART2_LinAutosync_TypeDef | UART2_Autosync,
 |  | UART2_LinDivUp_TypeDef | UART2_DivUp
 | ) |  |

Configure the UART2 peripheral.

Parameters:
UART2_Mode | specifies the LIN mode. This parameter can be any of the UART2_LinMode_TypeDef values.
UART2_Autosync | specifies the LIN automatic resynchronization mode. This parameter can be any of the UART2_LinAutosync_TypeDef values.
UART2_DivUp | specifies the LIN divider update method. This parameter can be any of the UART2_LinDivUp_TypeDef values.
Return values:
None

Definition at line 336 of file stm8s_uart2.c.

References IS_UART2_AUTOSYNC_OK, IS_UART2_DIVUP_OK, IS_UART2_SLAVE_OK, UART2_CR6_LASE, UART2_CR6_LDUM, UART2_CR6_LSLV, UART2_LIN_AUTOSYNC_DISABLE, UART2_LIN_DIVUP_LBRR1, and UART2_LIN_MODE_MASTER.

uint8_t UART2_ReceiveData8 ( void )

Returns the most recent received data by the UART2 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 481 of file stm8s_uart2.c.

uint16_t UART2_ReceiveData9 ( void )

Returns the most recent received data by the UART2 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 491 of file stm8s_uart2.c.

References UART2_CR1_R8.

void UART2_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART2 is in mute mode or not.

Parameters:
NewState,: new state of the UART2 mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 460 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR2_RWU.

void UART2_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 534 of file stm8s_uart2.c.

References UART2_CR2_SBK.

void UART2_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART2 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 505 of file stm8s_uart2.c.

void UART2_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART2 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 516 of file stm8s_uart2.c.

References UART2_CR1_T8.

void UART2_SetAddress ( uint8_t UART2_Address )

Sets the address of the UART2 node.

Parameters:
UART2_Address,: Indicates the address of the UART2 node.
Return values:
None

Definition at line 544 of file stm8s_uart2.c.

References IS_UART2_ADDRESS_OK, and UART2_CR4_ADD.

void UART2_SetGuardTime ( uint8_t UART2_GuardTime )

Sets the specified UART2 guard time.

Note:
SmartCard Mode should be Enabled
Parameters:
UART2_GuardTime,: specifies the guard time.
Return values:
None

Definition at line 561 of file stm8s_uart2.c.

void UART2_SetPrescaler ( uint8_t UART2_Prescaler )

Sets the system clock prescaler.

Note:
IrDA Low Power mode or smartcard mode should be enabled
This function is related to SmartCard and IrDa mode.
Parameters:
UART2_Prescaler,: specifies the prescaler clock. This parameter can be one of the following values:
IrDA Low Power Mode
The clock source is divided by the value given in the register (8 bits)
  • 0000 0000 Reserved
  • 0000 0001 divides the clock source by 1
  • 0000 0010 divides the clock source by 2
  • ...........................................................
Smart Card Mode
The clock source is divided by the value given in the register (5 significant bits) multiped by 2
  • 0 0000 Reserved
  • 0 0001 divides the clock source by 2
  • 0 0010 divides the clock source by 4
  • 0 0011 divides the clock source by 6
  • ...........................................................
Return values:
None

Definition at line 589 of file stm8s_uart2.c.

void UART2_SmartCardCmd ( FunctionalState NewState )

Enables or disables the UART2 Smart Card mode.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 400 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_SCEN.

void UART2_SmartCardNACKCmd ( FunctionalState NewState )

Enables or disables NACK transmission.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 423 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_NACK.

void UART2_WakeUpConfig ( UART2_WakeUp_TypeDef UART2_WakeUp )

Selects the UART2 WakeUp method.

Parameters:
UART2_WakeUp,: specifies the UART2 wakeup method. This parameter can be any of the UART2_WakeUp_TypeDef values.
Return values:
None

Definition at line 446 of file stm8s_uart2.c.

References IS_UART2_WAKEUP_OK, and UART2_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: UART3_Exported_Types

Enumerations

UART3_Exported_Types

STM8S_StdPeriph_Driver

Enumerations

enum UART3_Flag_TypeDef {
UART3_FLAG_TXE = (uint16_t)0x0080, UART3_FLAG_TC = (uint16_t)0x0040, UART3_FLAG_RXNE = (uint16_t)0x0020, UART3_FLAG_IDLE = (uint16_t)0x0010,
UART3_FLAG_OR_LHE = (uint16_t)0x0008, UART3_FLAG_NF = (uint16_t)0x0004, UART3_FLAG_FE = (uint16_t)0x0002, UART3_FLAG_PE = (uint16_t)0x0001,
UART3_FLAG_SBK = (uint16_t)0x0101, UART3_FLAG_LBDF = (uint16_t)0x0210, UART3_FLAG_LHDF = (uint16_t)0x0302, UART3_FLAG_LSF = (uint16_t)0x0301
}

UART3 Flag possible values.

More...
enum UART3_IT_TypeDef {
UART3_IT_TXE = (uint16_t)0x0277, UART3_IT_TC = (uint16_t)0x0266, UART3_IT_RXNE = (uint16_t)0x0255, UART3_IT_IDLE = (uint16_t)0x0244,
UART3_IT_OR = (uint16_t)0x0235, UART3_IT_PE = (uint16_t)0x0100, UART3_IT_LBDF = (uint16_t)0x0346, UART3_IT_LHDF = (uint16_t)0x0412,
UART3_IT_RXNE_OR = (uint16_t)0x0205
}

UART3 Interrupt definition UART3_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt

  • For the following values, X means the interrupt position in the CR2 register.
More...
enum | UART3_LinAutosync_TypeDef { UART3_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, UART3_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 }

UART3 automatic resynchronisation possible values.

More...
enum | UART3_LINBreakDetectionLength_TypeDef { UART3_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART3_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }

UART3 LIN Break detection length possible values.

More...
enum | UART3_LinDivUp_TypeDef { UART3_LIN_DIVUP_LBRR1 = (uint8_t)0x00, UART3_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 }

UART3 Divider Update Method possible values.

More...
enum | UART3_LinMode_TypeDef { UART3_LIN_MODE_MASTER = (uint8_t)0x00, UART3_LIN_MODE_SLAVE = (uint8_t)0x01 }

UART3 Mode possible values.

More...
enum UART3_Mode_TypeDef {
UART3_MODE_RX_ENABLE = (uint8_t)0x08, UART3_MODE_TX_ENABLE = (uint8_t)0x04, UART3_MODE_TX_DISABLE = (uint8_t)0x80, UART3_MODE_RX_DISABLE = (uint8_t)0x40,
UART3_MODE_TXRX_ENABLE = (uint8_t)0x0C
}

UART3 Mode Transmit/Receive possible values.

More...
enum | UART3_Parity_TypeDef { UART3_PARITY_NO = (uint8_t)0x00, UART3_PARITY_EVEN = (uint8_t)0x04, UART3_PARITY_ODD = (uint8_t)0x06 }

UART3 parity possible values.

More...
enum | UART3_StopBits_TypeDef { UART3_STOPBITS_1 = (uint8_t)0x00, UART3_STOPBITS_2 = (uint8_t)0x20 }

UART3 stop bits possible values.

More...
enum | UART3_WakeUp_TypeDef { UART3_WAKEUP_IDLELINE = (uint8_t)0x00, UART3_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }

UART3 WakeUP Modes.

More...
enum | UART3_WordLength_TypeDef { UART3_WORDLENGTH_8D = (uint8_t)0x00, UART3_WORDLENGTH_9D = (uint8_t)0x10 }

UART3 Word length possible values.

More...

Enumeration Type Documentation

enum UART3_Flag_TypeDef

UART3 Flag possible values.

Enumerator:
UART3_FLAG_TXE

Transmit Data Register Empty flag

UART3_FLAG_TC

Transmission Complete flag

UART3_FLAG_RXNE

Read Data Register Not Empty flag

UART3_FLAG_IDLE

Idle line detected flag

UART3_FLAG_OR_LHE

OverRun error flag

UART3_FLAG_NF

Noise error flag

UART3_FLAG_FE

Framing Error flag

UART3_FLAG_PE

Parity Error flag

UART3_FLAG_SBK

Send Break Complete interrupt flag.

UART3_FLAG_LBDF

LIN Break Detection Flag.

UART3_FLAG_LHDF

LIN Header Detection Flag.

UART3_FLAG_LSF

LIN Sync Field Flag.

Definition at line 109 of file stm8s_uart3.h.

enum UART3_IT_TypeDef

UART3 Interrupt definition UART3_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt

  • For the following values, X means the interrupt position in the CR2 register.

UART3_IT_TXE UART3_IT_TC UART3_IT_RXNE UART3_IT_IDLE UART3_IT_OR

  • For the UART3_IT_PE value, X means the flag position in the CR1 register.
  • For the UART3_IT_LBDF value, X means the flag position in the CR4 register.
  • For the UART3_IT_LHDF value, X means the flag position in the CR6 register. Y: Flag position

For the following values, Y means the flag (pending bit) position in the SR register. UART3_IT_TXE UART3_IT_TC UART3_IT_RXNE UART3_IT_IDLE UART3_IT_OR UART3_IT_PE

  • For the UART3_IT_LBDF value, Y means the flag position in the CR4 register.
  • For the UART3_IT_LHDF value, Y means the flag position in the CR6 register. Z: Register index: indicate in which register the dedicated interrupt source is:
  • 1==> CR1 register
  • 2==> CR2 register
  • 3==> CR4 register
  • 4==> CR6 register
Enumerator:
UART3_IT_TXE

Transmit interrupt.

UART3_IT_TC

Transmission Complete interrupt.

UART3_IT_RXNE

Data Register Not Empty interrupt.

UART3_IT_IDLE

Idle line detected interrupt.

UART3_IT_OR

OverRun error interrupt.

UART3_IT_PE

Parity Error interrupt.

UART3_IT_LBDF

LIN Break Detection interrupt.

UART3_IT_LHDF

LIN Header Detection interrupt.

UART3_IT_RXNE_OR

Receive/Overrun interrupt

Definition at line 155 of file stm8s_uart3.h.

enum UART3_LinAutosync_TypeDef

UART3 automatic resynchronisation possible values.

Enumerator:
UART3_LIN_AUTOSYNC_DISABLE

LIN Autosynchronization Disable.

UART3_LIN_AUTOSYNC_ENABLE

LIN Autosynchronization Enable.

Definition at line 95 of file stm8s_uart3.h.

enum UART3_LINBreakDetectionLength_TypeDef

UART3 LIN Break detection length possible values.

Enumerator:
UART3_LINBREAKDETECTIONLENGTH_10BITS

10 bits Lin Break detection

UART3_LINBREAKDETECTIONLENGTH_11BITS

11 bits Lin Break detection

Definition at line 49 of file stm8s_uart3.h.

enum UART3_LinDivUp_TypeDef

UART3 Divider Update Method possible values.

Enumerator:
UART3_LIN_DIVUP_LBRR1

LIN LDIV is updated as soon as LBRR1 is written.

UART3_LIN_DIVUP_NEXTRXNE

LIN LDIV is updated at the next received character.

Definition at line 101 of file stm8s_uart3.h.

enum UART3_LinMode_TypeDef

UART3 Mode possible values.

Enumerator:
UART3_LIN_MODE_MASTER

LIN Master Mode.

UART3_LIN_MODE_SLAVE

LIN Slave Mode.

Definition at line 89 of file stm8s_uart3.h.

enum UART3_Mode_TypeDef

UART3 Mode Transmit/Receive possible values.

Enumerator:
UART3_MODE_RX_ENABLE

0x08 Receive Enable

UART3_MODE_TX_ENABLE

0x04 Transmit Enable

UART3_MODE_TX_DISABLE

0x80 Receive Enable

UART3_MODE_RX_DISABLE

0x40 Single-wire Half-duplex mode

UART3_MODE_TXRX_ENABLE

0x0C Receive Enable and Transmit enable

Definition at line 79 of file stm8s_uart3.h.

enum UART3_Parity_TypeDef

UART3 parity possible values.

Enumerator:
UART3_PARITY_NO

No Parity.

UART3_PARITY_EVEN

Even Parity.

UART3_PARITY_ODD

Odd Parity.

Definition at line 64 of file stm8s_uart3.h.

enum UART3_StopBits_TypeDef

UART3 stop bits possible values.

Enumerator:
UART3_STOPBITS_1

One stop bit is transmitted at the end of frame.

UART3_STOPBITS_2

Two stop bits are transmitted at the end of frame.

Definition at line 57 of file stm8s_uart3.h.

enum UART3_WakeUp_TypeDef

UART3 WakeUP Modes.

Enumerator:
UART3_WAKEUP_IDLELINE

0x01 Idle Line wake up

UART3_WAKEUP_ADDRESSMARK

0x02 Address Mark wake up

Definition at line 42 of file stm8s_uart3.h.

enum UART3_WordLength_TypeDef

UART3 Word length possible values.

Enumerator:
UART3_WORDLENGTH_8D

0x00 8 bits Data

UART3_WORDLENGTH_9D

0x10 9 bits Data

Definition at line 72 of file stm8s_uart3.h.


STM8S/A Standard Peripherals Drivers: UART3_Private_Macros

Defines

UART3_Private_Macros

STM8S_StdPeriph_Driver

Defines

#define | IS_UART3_ADDRESS_OK(Node) ((Node) < UART3_ADDRESS_MAX)
#define | IS_UART3_AUTOSYNC_OK(AutosyncMode)
Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.
#define | IS_UART3_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART3_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART3_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART3_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART3_DIVUP_OK(DivupMethode)
Macro used by the assert_param function in order to check the LIN divider update method.
#define | IS_UART3_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART3_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART3_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLengths)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART3_MODE_OK(Mode)
Macro used by the assert_param function in order to check the different sensitivity values for the MODEs.
#define | IS_UART3_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Parity.
#define | IS_UART3_SLAVE_OK(Mode)
Macro used by the assert_param function in order to check the LIN mode.
#define | IS_UART3_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART3_StopBits.
#define | IS_UART3_WAKEUP_OK(WakeUpMode)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART3_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART3_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART3 or UART node.

Define Documentation

#define IS_UART3_ADDRESS_OK ( Node ) ((Node) < UART3_ADDRESS_MAX)

Definition at line 314 of file stm8s_uart3.h.

Referenced by UART3_SetAddress().

#define IS_UART3_AUTOSYNC_OK ( AutosyncMode )
Value:
(((AutosyncMode) ==  UART3_LIN_AUTOSYNC_ENABLE) || \
   ((AutosyncMode) == UART3_LIN_AUTOSYNC_DISABLE))

Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.

Definition at line 327 of file stm8s_uart3.h.

Referenced by UART3_LINConfig().

#define IS_UART3_BAUDRATE_OK ( NUM ) ((NUM) <= (uint32_t)625000)

Macro used by the assert_param function in order to check the maximum baudrate value.

Definition at line 307 of file stm8s_uart3.h.

Referenced by UART3_Init().

#define IS_UART3_CLEAR_FLAG_OK ( Flag )
Value:
(((Flag) == UART3_FLAG_RXNE) || \
   ((Flag) == UART3_FLAG_LHDF) || \
   ((Flag) == UART3_FLAG_LSF) || \
   ((Flag) == UART3_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.

Definition at line 203 of file stm8s_uart3.h.

Referenced by UART3_ClearFlag().

#define IS_UART3_CLEAR_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART3_IT_RXNE) || \
   ((ITPendingBit) == UART3_IT_LHDF) || \
   ((ITPendingBit) == UART3_IT_LBDF))

Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.

Definition at line 241 of file stm8s_uart3.h.

Referenced by UART3_ClearITPendingBit().

#define IS_UART3_CONFIG_IT_OK ( Interrupt )
Value:
(((Interrupt) == UART3_IT_PE) || \
   ((Interrupt) == UART3_IT_TXE) || \
   ((Interrupt) == UART3_IT_TC) || \
   ((Interrupt) == UART3_IT_RXNE_OR ) || \
   ((Interrupt) == UART3_IT_IDLE) || \
   ((Interrupt) == UART3_IT_LHDF) || \
   ((Interrupt) == UART3_IT_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.

Definition at line 214 of file stm8s_uart3.h.

Referenced by UART3_ITConfig().

#define IS_UART3_DIVUP_OK ( DivupMethode )
Value:
(((DivupMethode) == UART3_LIN_DIVUP_LBRR1) || \
   ((DivupMethode) == UART3_LIN_DIVUP_NEXTRXNE))

Macro used by the assert_param function in order to check the LIN divider update method.

Definition at line 335 of file stm8s_uart3.h.

Referenced by UART3_LINConfig().

#define IS_UART3_FLAG_OK ( Flag )
Value:
(((Flag) == UART3_FLAG_TXE) || \
   ((Flag) == UART3_FLAG_TC)  || \
   ((Flag) == UART3_FLAG_RXNE) || \
   ((Flag) == UART3_FLAG_IDLE) || \
   ((Flag) == UART3_FLAG_OR_LHE) || \
   ((Flag) == UART3_FLAG_NF) || \
   ((Flag) == UART3_FLAG_FE) || \
   ((Flag) == UART3_FLAG_PE) || \
   ((Flag) == UART3_FLAG_SBK) || \
   ((Flag) == UART3_FLAG_LSF) || \
   ((Flag) == UART3_FLAG_LHDF) || \
   ((Flag) == UART3_FLAG_LBDF))

Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.

Definition at line 184 of file stm8s_uart3.h.

Referenced by UART3_GetFlagStatus().

#define IS_UART3_GET_IT_OK ( ITPendingBit )
Value:
(((ITPendingBit) == UART3_IT_TXE)  || \
   ((ITPendingBit) == UART3_IT_TC)   || \
   ((ITPendingBit) == UART3_IT_RXNE) || \
   ((ITPendingBit) == UART3_IT_IDLE) || \
   ((ITPendingBit) == UART3_IT_OR)  || \
   ((ITPendingBit) == UART3_IT_LBDF)  || \
   ((ITPendingBit) == UART3_IT_LHDF)  || \
   ((ITPendingBit) == UART3_IT_PE))

Macro used by the assert function in order to check the different sensitivity values for the pending bit.

Definition at line 227 of file stm8s_uart3.h.

Referenced by UART3_GetITStatus().

#define IS_UART3_LINBREAKDETECTIONLENGTH_OK ( LINBreakDetectionLengths )
Value:
(((LINBreakDetectionLengths) == UART3_LINBREAKDETECTIONLENGTH_10BITS) || \
   ((LINBreakDetectionLengths) == UART3_LINBREAKDETECTIONLENGTH_11BITS))

Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.

Definition at line 282 of file stm8s_uart3.h.

Referenced by UART3_LINBreakDetectionConfig().

#define IS_UART3_MODE_OK ( Mode )
Value:
(((Mode) == (uint8_t)UART3_MODE_RX_ENABLE) || \
   ((Mode) == (uint8_t)UART3_MODE_RX_DISABLE) || \
   ((Mode) == (uint8_t)UART3_MODE_TX_ENABLE) || \
   ((Mode) == (uint8_t)UART3_MODE_TX_DISABLE) || \
   ((Mode) == (uint8_t)UART3_MODE_TXRX_ENABLE) || \
   ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_ENABLE|(uint8_t)UART3_MODE_RX_ENABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_ENABLE|(uint8_t)UART3_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_DISABLE|(uint8_t)UART3_MODE_RX_DISABLE)) || \
   ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_DISABLE|(uint8_t)UART3_MODE_RX_ENABLE)))

Macro used by the assert_param function in order to check the different sensitivity values for the MODEs.

Definition at line 250 of file stm8s_uart3.h.

Referenced by UART3_Init().

#define IS_UART3_PARITY_OK ( Parity )
Value:
(((Parity) == UART3_PARITY_NO) || \
   ((Parity) == UART3_PARITY_EVEN) || \
   ((Parity) == UART3_PARITY_ODD ))

Macro used by the assert_param function in order to check the different sensitivity values for the Parity.

Definition at line 298 of file stm8s_uart3.h.

Referenced by UART3_Init().

#define IS_UART3_SLAVE_OK ( Mode )
Value:
(((Mode) == UART3_LIN_MODE_MASTER) || \
   ((Mode) == UART3_LIN_MODE_SLAVE))

Macro used by the assert_param function in order to check the LIN mode.

Definition at line 319 of file stm8s_uart3.h.

Referenced by UART3_LINConfig().

#define IS_UART3_STOPBITS_OK ( StopBit )
Value:
(((StopBit) == UART3_STOPBITS_1) || \
   ((StopBit) == UART3_STOPBITS_2))

Macro used by the assert_param function in order to check the different sensitivity values for the UART3_StopBits.

Definition at line 290 of file stm8s_uart3.h.

Referenced by UART3_Init().

#define IS_UART3_WAKEUP_OK ( WakeUpMode )
Value:
(((WakeUpMode) == UART3_WAKEUP_IDLELINE) || \
   ((WakeUpMode) == UART3_WAKEUP_ADDRESSMARK))

Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.

Definition at line 274 of file stm8s_uart3.h.

Referenced by UART3_WakeUpConfig().

#define IS_UART3_WORDLENGTH_OK ( WordLength )
Value:
(((WordLength) == UART3_WORDLENGTH_8D) || \
   ((WordLength) == UART3_WORDLENGTH_9D))

Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.

Definition at line 265 of file stm8s_uart3.h.

Referenced by UART3_Init().

#define UART3_ADDRESS_MAX ((uint8_t)16)

Macro used by the assert_param function in order to check the address of the UART3 or UART node.

Definition at line 313 of file stm8s_uart3.h.


STM8S/A Standard Peripherals Drivers: UART3_Exported_Functions

Functions

UART3_Exported_Functions

STM8S_StdPeriph_Driver

Functions

void | UART3_ClearFlag (UART3_Flag_TypeDef UART3_FLAG)
Clears the UART3 flags.
void | UART3_ClearITPendingBit (UART3_IT_TypeDef UART3_IT)
Clears the UART3 pending flags.
void | UART3_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART3_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART3_GetFlagStatus (UART3_Flag_TypeDef UART3_FLAG)
Checks whether the specified UART3 flag is set or not.
ITStatus | UART3_GetITStatus (UART3_IT_TypeDef UART3_IT)
Checks whether the specified UART3 interrupt has occurred or not.
void | UART3_Init (uint32_t BaudRate, UART3_WordLength_TypeDef WordLength, UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, UART3_Mode_TypeDef Mode)
Initializes the UART3 according to the specified parameters.
void | UART3_ITConfig (UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
Enables or disables the specified UART3 interrupts.
void | UART3_LINBreakDetectionConfig (UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
Sets the UART3 LIN Break detection length.
void | UART3_LINCmd (FunctionalState NewState)
Enables or disables the UART3 LIN mode.
void | UART3_LINConfig (UART3_LinMode_TypeDef UART3_Mode, UART3_LinAutosync_TypeDef UART3_Autosync, UART3_LinDivUp_TypeDef UART3_DivUp)
Configure the UART3 peripheral.
uint8_t | UART3_ReceiveData8 (void)
Returns the most recent received data by the UART3 peripheral.
uint16_t | UART3_ReceiveData9 (void)
Returns the most recent received data by the UART3 peripheral.
void | UART3_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART3 is in mute mode or not.
void | UART3_SendBreak (void)
Transmits break characters.
void | UART3_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART3 peripheral.
void | UART3_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART3 peripheral.
void | UART3_SetAddress (uint8_t UART3_Address)
Sets the address of the UART3 node.
void | UART3_WakeUpConfig (UART3_WakeUp_TypeDef UART3_WakeUp)
Selects the UART3 WakeUp method.

Function Documentation

void UART3_ClearFlag ( UART3_Flag_TypeDef UART3_FLAG )

Clears the UART3 flags.

Parameters:
UART3_FLAG specifies the flag to clear This parameter can be any combination of the following values:

  • UART3_FLAG_LBDF: LIN Break detection flag.
  • UART3_FLAG_LHDF: LIN Header detection flag.
  • UART3_FLAG_LSF: LIN synchrone field flag.
  • UART3_FLAG_RXNE: Receive data register not empty flag.
Note:
  • PE (Parity error), FE (Framing error), NF (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART3_SR register (UART3_GetFlagStatus())followed by a read operation to UART3_DR register(UART3_ReceiveData8() or UART3_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART3_DR register (UART3_ReceiveData8()or UART3_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART3_SR register (UART3_GetFlagStatus()) followed by a write operation to UART3_DR register (UART3_SendData8() or UART3_SendData9()).
  • TXE flag is cleared only by a write to the UART3_DR register (UART3_SendData8() or UART3_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 546 of file stm8s_uart3.c.

References IS_UART3_CLEAR_FLAG_OK, UART3_CR4_LBDF, UART3_CR6_LHDF, UART3_CR6_LSF, UART3_FLAG_LBDF, UART3_FLAG_LHDF, UART3_FLAG_RXNE, and UART3_SR_RXNE.

void UART3_ClearITPendingBit ( UART3_IT_TypeDef UART3_IT )

Clears the UART3 pending flags.

Parameters:
UART3_IT specifies the pending bit to clear This parameter can be one of the following values:

  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_LHDF: LIN Header detection interrupt
  • UART3_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NF (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART3_SR register (UART3_GetITStatus()) followed by a read operation to UART3_DR register (UART3_ReceiveData8() or UART3_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART3_DR register (UART3_ReceiveData8() or UART3_ReceiveData9() ).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART3_SR register (UART3_GetITStatus()) followed by a write operation to UART3_DR register (UART3_SendData8()or UART3_SendData9()).
  • TXE pending bit is cleared only by a write to the UART3_DR register (UART3_SendData8() or UART3_SendData9()).
    Return values:
    None

Definition at line 701 of file stm8s_uart3.c.

References IS_UART3_CLEAR_IT_OK, UART3_CR4_LBDF, UART3_CR6_LHDF, UART3_IT_LBDF, UART3_IT_RXNE, and UART3_SR_RXNE.

void UART3_Cmd ( FunctionalState NewState )

Enable the UART1 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 155 of file stm8s_uart3.c.

References DISABLE, and UART3_CR1_UARTD.

void UART3_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 48 of file stm8s_uart3.c.

References UART3_BRR1_RESET_VALUE, UART3_BRR2_RESET_VALUE, UART3_CR1_RESET_VALUE, UART3_CR2_RESET_VALUE, UART3_CR3_RESET_VALUE, UART3_CR4_RESET_VALUE, and UART3_CR6_RESET_VALUE.

FlagStatus UART3_GetFlagStatus ( UART3_Flag_TypeDef UART3_FLAG )

Checks whether the specified UART3 flag is set or not.

Parameters:
UART3_FLAG specifies the flag to check. This parameter can be any of the UART3_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 454 of file stm8s_uart3.c.

References IS_UART3_FLAG_OK, RESET, SET, UART3_FLAG_LBDF, UART3_FLAG_LHDF, UART3_FLAG_LSF, and UART3_FLAG_SBK.

ITStatus UART3_GetITStatus ( UART3_IT_TypeDef UART3_IT )

Checks whether the specified UART3 interrupt has occurred or not.

Parameters:
UART3_IT,: Specifies the UART3 interrupt pending bit to check. This parameter can be one of the following values:

  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_TXE: Tansmit Data Register empty interrupt
  • UART3_IT_TC: Transmission complete interrupt
  • UART3_IT_RXNE: Receive Data register not empty interrupt
  • UART3_IT_IDLE: Idle line detection interrupt
  • UART3_IT_OR: OverRun Error interrupt
  • UART3_IT_PE: Parity Error interrupt
Return values:
The state of UART3_IT (SET or RESET).

Definition at line 586 of file stm8s_uart3.c.

References IS_UART3_GET_IT_OK, RESET, SET, UART3_IT_LBDF, UART3_IT_LHDF, and UART3_IT_PE.

void UART3_Init | ( | uint32_t | BaudRate,
 |  | UART3_WordLength_TypeDef | WordLength,
 |  | UART3_StopBits_TypeDef | StopBits,
 |  | UART3_Parity_TypeDef | Parity,
 |  | UART3_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART3 according to the specified parameters.

Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART3_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART3_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART3_Parity_TypeDef enumeration.
Mode,: This parameter can be any of the UART3_Mode_TypeDef values
Return values:
None

Definition at line 78 of file stm8s_uart3.c.

References CLK_GetClockFreq(), IS_UART3_BAUDRATE_OK, IS_UART3_MODE_OK, IS_UART3_PARITY_OK, IS_UART3_STOPBITS_OK, IS_UART3_WORDLENGTH_OK, UART3_BRR1_DIVM, UART3_BRR2_DIVF, UART3_BRR2_DIVM, UART3_CR1_M, UART3_CR1_PCEN, UART3_CR1_PS, UART3_CR2_REN, UART3_CR2_TEN, UART3_CR3_STOP, UART3_MODE_RX_ENABLE, and UART3_MODE_TX_ENABLE.

void UART3_ITConfig | ( | UART3_IT_TypeDef | UART3_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified UART3 interrupts.

Parameters:
UART3_IT specifies the UART3 interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_LHDF: LIN Break detection interrupt
  • UART3_IT_TXE: Tansmit Data Register empty interrupt
  • UART3_IT_TC: Transmission complete interrupt
  • UART3_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
  • UART3_IT_IDLE: Idle line detection interrupt
  • UART3_IT_PE: Parity Error interrupt
NewState new state of the specified UART3 interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 185 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART3_CONFIG_IT_OK.

void UART3_LINBreakDetectionConfig ( UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength )

Sets the UART3 LIN Break detection length.

Parameters:
UART3_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART3_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 248 of file stm8s_uart3.c.

References IS_UART3_LINBREAKDETECTIONLENGTH_OK, UART3_CR4_LBDL, and UART3_LINBREAKDETECTIONLENGTH_10BITS.

void UART3_LINCmd ( FunctionalState NewState )

Enables or disables the UART3 LIN mode.

Parameters:
NewState is new state of the UART3 LIN mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 316 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART3_CR3_LINEN.

void UART3_LINConfig | ( | UART3_LinMode_TypeDef | UART3_Mode,
 |  | UART3_LinAutosync_TypeDef | UART3_Autosync,
 |  | UART3_LinDivUp_TypeDef | UART3_DivUp
 | ) |  |

Configure the UART3 peripheral.

Parameters:
UART3_Mode | specifies the LIN mode. This parameter can be any of the UART3_LinMode_TypeDef values.
UART3_Autosync | specifies the LIN automatic resynchronization mode. This parameter can be any of the UART3_LinAutosync_TypeDef values.
UART3_DivUp | specifies the LIN divider update method. This parameter can be any of the UART3_LinDivUp_TypeDef values.
Return values:
None

Definition at line 273 of file stm8s_uart3.c.

References IS_UART3_AUTOSYNC_OK, IS_UART3_DIVUP_OK, IS_UART3_SLAVE_OK, UART3_CR6_LASE, UART3_CR6_LDUM, UART3_CR6_LSLV, UART3_LIN_AUTOSYNC_DISABLE, UART3_LIN_DIVUP_LBRR1, and UART3_LIN_MODE_MASTER.

uint8_t UART3_ReceiveData8 ( void )

Returns the most recent received data by the UART3 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 376 of file stm8s_uart3.c.

uint16_t UART3_ReceiveData9 ( void )

Returns the most recent received data by the UART3 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 386 of file stm8s_uart3.c.

References UART3_CR1_R8.

void UART3_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART3 is in mute mode or not.

Parameters:
NewState,: new state of the UART3 mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 354 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART3_CR2_RWU.

void UART3_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 427 of file stm8s_uart3.c.

References UART3_CR2_SBK.

void UART3_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART3 peripheral.

Parameters:
Data the data to transmit.
Return values:
None

Definition at line 399 of file stm8s_uart3.c.

void UART3_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART3 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 410 of file stm8s_uart3.c.

References UART3_CR1_T8.

void UART3_SetAddress ( uint8_t UART3_Address )

Sets the address of the UART3 node.

Parameters:
UART3_Address,: Indicates the address of the UART3 node.
Return values:
None

Definition at line 437 of file stm8s_uart3.c.

References IS_UART3_ADDRESS_OK, and UART3_CR4_ADD.

void UART3_WakeUpConfig ( UART3_WakeUp_TypeDef UART3_WakeUp )

Selects the UART3 WakeUp method.

Parameters:
UART3_WakeUp,: specifies the UART3 wakeup method. This parameter can be any of the UART3_WakeUp_TypeDef values.
Return values:
None

Definition at line 339 of file stm8s_uart3.c.

References IS_UART3_WAKEUP_OK, and UART3_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: WWDG_Private_Macros

Defines

WWDG_Private_Macros

STM8S_StdPeriph_Driver

Defines

#define | IS_WWDG_COUNTERVALUE_OK(CounterValue) ((CounterValue) <= 0x7F)
Macro used by the assert function in order to check the different values of the counter register.
#define | IS_WWDG_WINDOWLIMITVALUE_OK(WindowLimitValue) ((WindowLimitValue) <= 0x7F)
Macro used by the assert function in order to check the values of the window register.

Define Documentation

#define IS_WWDG_COUNTERVALUE_OK ( CounterValue ) ((CounterValue) <= 0x7F)

Macro used by the assert function in order to check the different values of the counter register.

Definition at line 49 of file stm8s_wwdg.h.

Referenced by WWDG_SetCounter().

#define IS_WWDG_WINDOWLIMITVALUE_OK ( WindowLimitValue ) ((WindowLimitValue) <= 0x7F)

Macro used by the assert function in order to check the values of the window register.

Definition at line 43 of file stm8s_wwdg.h.

Referenced by WWDG_Init(), and WWDG_SetWindowValue().


STM8S/A Standard Peripherals Drivers: WWDG_Exported_Functions

Functions

WWDG_Exported_Functions

STM8S_StdPeriph_Driver

Functions

uint8_t | WWDG_GetCounter (void)
Gets the WWDG Counter Value.
void | WWDG_Init (uint8_t Counter, uint8_t WindowValue)
Initializes the WWDG peripheral.
void | WWDG_SetCounter (uint8_t Counter)
Refreshes the WWDG peripheral.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.
void | WWDG_SWReset (void)
Generates immediate WWDG RESET.

Function Documentation

uint8_t WWDG_GetCounter ( void )

Gets the WWDG Counter Value.

This value could be used to check if WWDG is in the window, where refresh is allowed.

Parameters:
None
Return values:
WWDG Counter Value

Definition at line 82 of file stm8s_wwdg.c.

References WWDG.

void WWDG_Init | ( | uint8_t | Counter,
 |  | uint8_t | WindowValue
 | ) |  |

Initializes the WWDG peripheral.

This function set Window Register = WindowValue, Counter Register according to Counter and ENABLE WWDG

Parameters:
Counter | : WWDG counter value
WindowValue | : specifies the WWDG Window Register, range is 0x00 to 0x7F.
Return values:
None

Definition at line 47 of file stm8s_wwdg.c.

References IS_WWDG_WINDOWLIMITVALUE_OK, WWDG, WWDG_CR_T6, WWDG_CR_WDGA, and WWDG_WR_RESET_VALUE.

void WWDG_SetCounter ( uint8_t Counter )

Refreshes the WWDG peripheral.

Parameters:
Counter : WWDG Counter Value This parameter must be a number between 0x40 and 0x7F.
Return values:
None

Definition at line 63 of file stm8s_wwdg.c.

References BIT_MASK, IS_WWDG_COUNTERVALUE_OK, and WWDG.

void WWDG_SetWindowValue ( uint8_t WindowValue )

Sets the WWDG window value.

Parameters:
WindowValue,: specifies the window value to be compared to the downcounter. This parameter value must be lower than 0x80.
Return values:
None

Definition at line 104 of file stm8s_wwdg.c.

References IS_WWDG_WINDOWLIMITVALUE_OK, WWDG, WWDG_CR_T6, and WWDG_CR_WDGA.

void WWDG_SWReset ( void )

Generates immediate WWDG RESET.

Parameters:
None
Return values:
None

Definition at line 92 of file stm8s_wwdg.c.

References WWDG, and WWDG_CR_WDGA.


STM8S/A Standard Peripherals Drivers: ADC1_Public_Functions

Functions

ADC1_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | ADC1_AWDChannelConfig (ADC1_Channel_TypeDef Channel, FunctionalState NewState)
Enables or disables the analog watchdog for the given channel.
void | ADC1_ClearFlag (ADC1_Flag_TypeDef Flag)
Clear the specified ADC1 Flag.
void | ADC1_ClearITPendingBit (ADC1_IT_TypeDef ITPendingBit)
Clear the ADC1 End of Conversion pending bit.
void | ADC1_Cmd (FunctionalState NewState)
Enables or Disables the ADC1 peripheral.
void | ADC1_ConversionConfig (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)
Configure the ADC1 conversion on selected channel.
void | ADC1_DataBufferCmd (FunctionalState NewState)
Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.
void | ADC1_DeInit (void)
Deinitializes the ADC1 peripheral registers to their default reset values.
void | ADC1_ExternalTriggerConfig (ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
Configure the ADC1 conversion on external trigger event.
FlagStatus | ADC1_GetAWDChannelStatus (ADC1_Channel_TypeDef Channel)
Checks the specified analog watchdog channel status.
uint16_t | ADC1_GetBufferValue (uint8_t Buffer)
Get one sample of measured signal.
uint16_t | ADC1_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC1_GetFlagStatus (ADC1_Flag_TypeDef Flag)
Checks the specified ADC1 flag status.
ITStatus | ADC1_GetITStatus (ADC1_IT_TypeDef ITPendingBit)
Returns the specified pending bit status.
void | ADC1_Init (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)
Initializes the ADC1 peripheral according to the specified parameters.
void | ADC1_ITConfig (ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)
Enables or disables the ADC1 interrupt.
void | ADC1_PrescalerConfig (ADC1_PresSel_TypeDef ADC1_Prescaler)
Configure the ADC1 prescaler division factor.
void | ADC1_ScanModeCmd (FunctionalState NewState)
Enables or Disables the ADC1 scan mode.
void | ADC1_SchmittTriggerConfig (ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC1 Schmitt Trigger on a selected channel.
void | ADC1_SetHighThreshold (uint16_t Threshold)
Sets the high threshold of the analog watchdog.
void | ADC1_SetLowThreshold (uint16_t Threshold)
Sets the low threshold of the analog watchdog.
void | ADC1_StartConversion (void)
Start ADC1 conversion.

Function Documentation

void ADC1_AWDChannelConfig | ( | ADC1_Channel_TypeDef | Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the analog watchdog for the given channel.

Parameters:
Channel | specifies the desired Channel. It can be set of the values of ADC1_Channel_TypeDef.
NewState | specifies the analog watchdog new state. can have one of the values of FunctionalState.
Return values:
None

Definition at line 427 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_CHANNEL_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_ClearFlag ( ADC1_Flag_TypeDef Flag )

Clear the specified ADC1 Flag.

Parameters:
Flag,: ADC1 flag. can be one of the values of ADC1_Flag_TypeDef.
Return values:
None

Definition at line 591 of file stm8s_adc1.c.

References IS_ADC1_FLAG_OK.

void ADC1_ClearITPendingBit ( ADC1_IT_TypeDef ITPendingBit )

Clear the ADC1 End of Conversion pending bit.

Parameters:
ITPendingBit : the IT pending bit to clear. This parameter can be one of the following values:

  • ADC1_IT_AWD : Analog WDG IT status
  • ADC1_IT_AWS0 : Analog channel 0 IT status
  • ADC1_IT_AWS1 : Analog channel 1 IT status
  • ADC1_IT_AWS2 : Analog channel 2 IT status
  • ADC1_IT_AWS3 : Analog channel 3 IT status
  • ADC1_IT_AWS4 : Analog channel 4 IT status
  • ADC1_IT_AWS5 : Analog channel 5 IT status
  • ADC1_IT_AWS6 : Analog channel 6 IT status
  • ADC1_IT_AWS7 : Analog channel 7 IT status
  • ADC1_IT_AWS8 : Analog channel 8 IT status
  • ADC1_IT_AWS9 : Analog channel 9 IT status
  • ADC1_IT_EOC : EOC pending bit
Return values:
None

Definition at line 687 of file stm8s_adc1.c.

References IS_ADC1_ITPENDINGBIT_OK.

void ADC1_Cmd ( FunctionalState NewState )

Enables or Disables the ADC1 peripheral.

Parameters:
NewState,: specifies the peripheral enabled or disabled state.
Return values:
None

Definition at line 126 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_ConversionConfig | ( | ADC1_ConvMode_TypeDef | ADC1_ConversionMode,
 |  | ADC1_Channel_TypeDef | ADC1_Channel,
 |  | ADC1_Align_TypeDef | ADC1_Align
 | ) |  |

Configure the ADC1 conversion on selected channel.

Parameters:
ADC1_ConversionMode | Specifies the conversion type. It can be set of the values of ADC1_ConvMode_TypeDef
ADC1_Channel | specifies the ADC1 Channel. It can be set of the values of ADC1_Channel_TypeDef
ADC1_Align | specifies the conerted data alignment. It can be set of the values of ADC1_Align_TypeDef
Return values:
None

Definition at line 300 of file stm8s_adc1.c.

References ADC1_CONVERSIONMODE_CONTINUOUS, IS_ADC1_ALIGN_OK, IS_ADC1_CHANNEL_OK, and IS_ADC1_CONVERSIONMODE_OK.

Referenced by ADC1_Init().

void ADC1_DataBufferCmd ( FunctionalState NewState )

Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.

Parameters:
NewState,: specifies the selected mode enabled or disabled state.
Return values:
None

Definition at line 170 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_DeInit ( void )

Deinitializes the ADC1 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 48 of file stm8s_adc1.c.

void ADC1_ExternalTriggerConfig | ( | ADC1_ExtTrig_TypeDef | ADC1_ExtTrigger,
 |  | FunctionalState | NewState
 | ) |  |

Configure the ADC1 conversion on external trigger event.

Full description:
The selected external trigger evant can be enabled or disabled.
Parameters:
ADC1_ExtTrigger | to select the External trigger event. can have one of the values of ADC1_ExtTrig_TypeDef.
NewState | to enable/disable the selected external trigger can have one of the values of FunctionalState.
Return values:
None

Definition at line 342 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_EXTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC1_Init().

FlagStatus ADC1_GetAWDChannelStatus ( ADC1_Channel_TypeDef Channel )

Checks the specified analog watchdog channel status.

Parameters:
Channel,: specify the channel of which to check the analog watchdog can be one of the values of ADC1_Channel_TypeDef.
Return values:
FlagStatus Status of the analog watchdog.

Definition at line 526 of file stm8s_adc1.c.

References IS_ADC1_CHANNEL_OK.

uint16_t ADC1_GetBufferValue ( uint8_t Buffer )

Get one sample of measured signal.

Parameters:
Buffer specifies the buffer to read.
Return values:
BufferValue,: value read from the given buffer.
Required preconditions:
ADC1 conversion finished.

Definition at line 488 of file stm8s_adc1.c.

References ADC1_BaseAddress, and IS_ADC1_BUFFER_OK.

uint16_t ADC1_GetConversionValue ( void )

Get one sample of measured signal.

Parameters:
None
Return values:
ConversionValue,: value of the measured signal.
Required preconditions:
ADC1 conversion finished.

Definition at line 390 of file stm8s_adc1.c.

FlagStatus ADC1_GetFlagStatus ( ADC1_Flag_TypeDef Flag )

Checks the specified ADC1 flag status.

Parameters:
Flag,: ADC1 flag. can be one of the values of ADC1_Flag_TypeDef.
Return values:
FlagStatus Status of the ADC1 flag.

Definition at line 551 of file stm8s_adc1.c.

References IS_ADC1_FLAG_OK.

ITStatus ADC1_GetITStatus ( ADC1_IT_TypeDef ITPendingBit )

Returns the specified pending bit status.

Parameters:
ITPendingBit : the IT pending bit to check. This parameter can be one of the following values:

  • ADC1_IT_AWD : Analog WDG IT status
  • ADC1_IT_AWS0 : Analog channel 0 IT status
  • ADC1_IT_AWS1 : Analog channel 1 IT status
  • ADC1_IT_AWS2 : Analog channel 2 IT status
  • ADC1_IT_AWS3 : Analog channel 3 IT status
  • ADC1_IT_AWS4 : Analog channel 4 IT status
  • ADC1_IT_AWS5 : Analog channel 5 IT status
  • ADC1_IT_AWS6 : Analog channel 6 IT status
  • ADC1_IT_AWS7 : Analog channel 7 IT status
  • ADC1_IT_AWS8 : Analog channel 8 IT status
  • ADC1_IT_AWS9 : Analog channel 9 IT status
  • ADC1_IT_EOC : EOC pending bit
Return values:
ITStatus,: status of the specified pending bit.

Definition at line 640 of file stm8s_adc1.c.

References IS_ADC1_ITPENDINGBIT_OK, and RESET.

void ADC1_Init | ( | ADC1_ConvMode_TypeDef | ADC1_ConversionMode,
 |  | ADC1_Channel_TypeDef | ADC1_Channel,
 |  | ADC1_PresSel_TypeDef | ADC1_PrescalerSelection,
 |  | ADC1_ExtTrig_TypeDef | ADC1_ExtTrigger,
 |  | FunctionalState | ADC1_ExtTriggerState,
 |  | ADC1_Align_TypeDef | ADC1_Align,
 |  | ADC1_SchmittTrigg_TypeDef | ADC1_SchmittTriggerChannel,
 |  | FunctionalState | ADC1_SchmittTriggerState
 | ) |  |

Initializes the ADC1 peripheral according to the specified parameters.

Parameters:
ADC1_ConversionMode,: specifies the conversion mode can be one of the values of ADC1_ConvMode_TypeDef.
ADC1_Channel,: specifies the channel to convert can be one of the values of ADC1_Channel_TypeDef.
ADC1_PrescalerSelection,: specifies the ADC1 prescaler can be one of the values of ADC1_PresSel_TypeDef.
ADC1_ExtTrigger,: specifies the external trigger can be one of the values of ADC1_ExtTrig_TypeDef.
ADC1_ExtTriggerState,: specifies the external trigger new state can be one of the values of FunctionalState.
ADC1_Align,: specifies the converted data alignment can be one of the values of ADC1_Align_TypeDef.
ADC1_SchmittTriggerChannel,: specifies the schmitt trigger channel can be one of the values of ADC1_SchmittTrigg_TypeDef.
ADC1_SchmittTriggerState,: specifies the schmitt trigger state can be one of the values of FunctionalState.
Return values:
None

Definition at line 85 of file stm8s_adc1.c.

References ADC1_ConversionConfig(), ADC1_ExternalTriggerConfig(), ADC1_PrescalerConfig(), ADC1_SchmittTriggerConfig(), IS_ADC1_ALIGN_OK, IS_ADC1_CHANNEL_OK, IS_ADC1_CONVERSIONMODE_OK, IS_ADC1_EXTTRIG_OK, IS_ADC1_PRESSEL_OK, IS_ADC1_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_ITConfig | ( | ADC1_IT_TypeDef | ADC1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC1 interrupt.

Parameters:
ADC1_IT specifies the name of the interrupt to enable or disable. This parameter can be one of the following values:

  • ADC1_IT_AWDITEN : Analog WDG interrupt enable
  • ADC1_IT_EOCITEN : EOC iterrupt enable
NewState specifies the state of the interrupt to apply.
Return values:
None

Definition at line 196 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_IT_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_PrescalerConfig ( ADC1_PresSel_TypeDef ADC1_Prescaler )

Configure the ADC1 prescaler division factor.

Parameters:
ADC1_Prescaler,: the selected precaler. It can be one of the values of ADC1_PresSel_TypeDef.
Return values:
None

Definition at line 222 of file stm8s_adc1.c.

References IS_ADC1_PRESSEL_OK.

Referenced by ADC1_Init().

void ADC1_ScanModeCmd ( FunctionalState NewState )

Enables or Disables the ADC1 scan mode.

Parameters:
NewState,: specifies the selected mode enabled or disabled state.
Return values:
None

Definition at line 148 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_SchmittTriggerConfig | ( | ADC1_SchmittTrigg_TypeDef | ADC1_SchmittTriggerChannel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC1 Schmitt Trigger on a selected channel.

Parameters:
ADC1_SchmittTriggerChannel | specifies the desired Channel. It can be set of the values of ADC1_SchmittTrigg_TypeDef.
NewState | specifies Channel new status. can have one of the values of FunctionalState.
Return values:
None

Definition at line 244 of file stm8s_adc1.c.

References ADC1_SCHMITTTRIG_ALL, ADC1_SCHMITTTRIG_CHANNEL8, DISABLE, IS_ADC1_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC1_Init().

void ADC1_SetHighThreshold ( uint16_t Threshold )

Sets the high threshold of the analog watchdog.

Parameters:
Threshold specifies the high threshold value. this value depends on the reference voltage range.
Return values:
None

Definition at line 463 of file stm8s_adc1.c.

void ADC1_SetLowThreshold ( uint16_t Threshold )

Sets the low threshold of the analog watchdog.

Parameters:
Threshold specifies the low threshold value. this value depends on the reference voltage range.
Return values:
None

Definition at line 475 of file stm8s_adc1.c.

void ADC1_StartConversion ( void )

Start ADC1 conversion.

Full description:
This function triggers the start of conversion, after ADC1 configuration.
Parameters:
None
Return values:
None
Required preconditions:
Enable the ADC1 peripheral before calling this function

Definition at line 378 of file stm8s_adc1.c.


STM8S/A Standard Peripherals Drivers: ADC2_Public_Functions

Functions

ADC2_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | ADC2_ClearFlag (void)
Clear the ADC2 EOC Flag.
void | ADC2_ClearITPendingBit (void)
Clear the ADC2 End of Conversion pending bit.
void | ADC2_Cmd (FunctionalState NewState)
Enables or Disables the ADC2 peripheral.
void | ADC2_ConversionConfig (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)
Configure the ADC2 conversion on selected channel.
void | ADC2_DeInit (void)
Deinitializes the ADC2 peripheral registers to their default reset values.
void | ADC2_ExternalTriggerConfig (ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)
Configure the ADC2 conversion on external trigger event.
uint16_t | ADC2_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC2_GetFlagStatus (void)
Checks the ADC2 EOC flag status.
ITStatus | ADC2_GetITStatus (void)
Returns the EOC pending bit status.
void | ADC2_Init (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)
Initializes the ADC2 peripheral according to the specified parameters.
void | ADC2_ITConfig (FunctionalState NewState)
Enables or disables the ADC2 interrupt.
void | ADC2_PrescalerConfig (ADC2_PresSel_TypeDef ADC2_Prescaler)
Configure the ADC2 prescaler division factor.
void | ADC2_SchmittTriggerConfig (ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC2 Schmitt Trigger on a selected channel.
void | ADC2_StartConversion (void)
Start ADC2 conversion.

Function Documentation

void ADC2_ClearFlag ( void )

Clear the ADC2 EOC Flag.

Parameters:
None
Return values:
None

Definition at line 378 of file stm8s_adc2.c.

void ADC2_ClearITPendingBit ( void )

Clear the ADC2 End of Conversion pending bit.

Parameters:
None
Return values:
None

Definition at line 399 of file stm8s_adc2.c.

void ADC2_Cmd ( FunctionalState NewState )

Enables or Disables the ADC2 peripheral.

Parameters:
NewState,: specifies the peripheral enabled or disabled state.
Return values:
None

Definition at line 118 of file stm8s_adc2.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC2_ConversionConfig | ( | ADC2_ConvMode_TypeDef | ADC2_ConversionMode,
 |  | ADC2_Channel_TypeDef | ADC2_Channel,
 |  | ADC2_Align_TypeDef | ADC2_Align
 | ) |  |

Configure the ADC2 conversion on selected channel.

Parameters:
ADC2_ConversionMode | Specifies the conversion type. It can be set of the values of ADC2_ConvMode_TypeDef
ADC2_Channel | specifies the ADC2 Channel. It can be set of the values of ADC2_Channel_TypeDef
ADC2_Align | specifies the converted data alignment. It can be set of the values of ADC2_Align_TypeDef
Return values:
None

Definition at line 242 of file stm8s_adc2.c.

References ADC2_CONVERSIONMODE_CONTINUOUS, IS_ADC2_ALIGN_OK, IS_ADC2_CHANNEL_OK, and IS_ADC2_CONVERSIONMODE_OK.

Referenced by ADC2_Init().

void ADC2_DeInit ( void )

Deinitializes the ADC2 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 48 of file stm8s_adc2.c.

void ADC2_ExternalTriggerConfig | ( | ADC2_ExtTrig_TypeDef | ADC2_ExtTrigger,
 |  | FunctionalState | NewState
 | ) |  |

Configure the ADC2 conversion on external trigger event.

Full description:
The selected external trigger event can be enabled or disabled.
Parameters:
ADC2_ExtTrigger | to select the External trigger event. can have one of the values of ADC2_ExtTrig_TypeDef.
NewState | to enable/disable the selected external trigger can have one of the values of FunctionalState.
Return values:
None

Definition at line 284 of file stm8s_adc2.c.

References DISABLE, IS_ADC2_EXTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC2_Init().

uint16_t ADC2_GetConversionValue ( void )

Get one sample of measured signal.

Parameters:
None
Return values:
ConversionValue,: value of the measured signal.
Required preconditions:
ADC2 conversion finished.

Definition at line 332 of file stm8s_adc2.c.

FlagStatus ADC2_GetFlagStatus ( void )

Checks the ADC2 EOC flag status.

Parameters:
None
Return values:
FlagStatus Status of the ADC2 EOC flag.

Definition at line 366 of file stm8s_adc2.c.

ITStatus ADC2_GetITStatus ( void )

Returns the EOC pending bit status.

Parameters:
None
Return values:
FlagStatus,: status of the EOC pending bit.

Definition at line 389 of file stm8s_adc2.c.

void ADC2_Init | ( | ADC2_ConvMode_TypeDef | ADC2_ConversionMode,
 |  | ADC2_Channel_TypeDef | ADC2_Channel,
 |  | ADC2_PresSel_TypeDef | ADC2_PrescalerSelection,
 |  | ADC2_ExtTrig_TypeDef | ADC2_ExtTrigger,
 |  | FunctionalState | ADC2_ExtTriggerState,
 |  | ADC2_Align_TypeDef | ADC2_Align,
 |  | ADC2_SchmittTrigg_TypeDef | ADC2_SchmittTriggerChannel,
 |  | FunctionalState | ADC2_SchmittTriggerState
 | ) |  |

Initializes the ADC2 peripheral according to the specified parameters.

Parameters:
ADC2_ConversionMode,: specifies the conversion mode can be one of the values of ADC2_ConvMode_TypeDef.
ADC2_Channel,: specifies the channel to convert can be one of the values of ADC2_Channel_TypeDef.
ADC2_PrescalerSelection,: specifies the ADC2 prescaler can be one of the values of ADC2_PresSel_TypeDef.
ADC2_ExtTrigger,: specifies the external trigger can be one of the values of ADC2_ExtTrig_TypeDef.
ADC2_ExtTriggerState,: specifies the external trigger new state can be one of the values of FunctionalState.
ADC2_Align,: specifies the converted data alignment can be one of the values of ADC2_Align_TypeDef.
ADC2_SchmittTriggerChannel,: specifies the schmitt trigger channel can be one of the values of ADC2_SchmittTrigg_TypeDef.
ADC2_SchmittTriggerState,: specifies the schmitt trigger state can be one of the values of FunctionalState.
Return values:
None

Definition at line 77 of file stm8s_adc2.c.

References ADC2_ConversionConfig(), ADC2_ExternalTriggerConfig(), ADC2_PrescalerConfig(), ADC2_SchmittTriggerConfig(), IS_ADC2_ALIGN_OK, IS_ADC2_CHANNEL_OK, IS_ADC2_CONVERSIONMODE_OK, IS_ADC2_EXTTRIG_OK, IS_ADC2_PRESSEL_OK, IS_ADC2_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

void ADC2_ITConfig ( FunctionalState NewState )

Enables or disables the ADC2 interrupt.

Parameters:
NewState specifies the state of ADC2 interrupt.
Return values:
None

Definition at line 140 of file stm8s_adc2.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC2_PrescalerConfig ( ADC2_PresSel_TypeDef ADC2_Prescaler )

Configure the ADC2 prescaler division factor.

Parameters:
ADC2_Prescaler,: the selected prescaler. It can be one of the values of ADC2_PresSel_TypeDef.
Return values:
None

Definition at line 165 of file stm8s_adc2.c.

References IS_ADC2_PRESSEL_OK.

Referenced by ADC2_Init().

void ADC2_SchmittTriggerConfig | ( | ADC2_SchmittTrigg_TypeDef | ADC2_SchmittTriggerChannel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC2 Schmitt Trigger on a selected channel.

Parameters:
ADC2_SchmittTriggerChannel | specifies the desired Channel. It can be set of the values of ADC2_SchmittTrigg_TypeDef.
NewState | specifies the Channel ADC2 Schmitt Trigger new status. can have one of the values of FunctionalState.
Return values:
None

Definition at line 187 of file stm8s_adc2.c.

References ADC2_SCHMITTTRIG_ALL, ADC2_SCHMITTTRIG_CHANNEL8, DISABLE, IS_ADC2_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC2_Init().

void ADC2_StartConversion ( void )

Start ADC2 conversion.

Full description:
This function triggers the start of conversion, after ADC2 configuration.
Parameters:
None
Return values:
None
Required preconditions:
Enable the ADC2 peripheral before calling this function

Definition at line 320 of file stm8s_adc2.c.


STM8S/A Standard Peripherals Drivers: AWU_Public_Functions

Functions

AWU_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | AWU_Cmd (FunctionalState NewState)
Enable or disable the AWU peripheral.
void | AWU_DeInit (void)
Deinitializes the AWU peripheral registers to their default reset values.
FlagStatus | AWU_GetFlagStatus (void)
Returns status of the AWU peripheral flag.
void | AWU_IdleModeEnable (void)
Configures AWU in Idle mode to reduce power consumption.
void | AWU_Init (AWU_Timebase_TypeDef AWU_TimeBase)
Initializes the AWU peripheral according to the specified parameters.
void | AWU_LSICalibrationConfig (uint32_t LSIFreqHz)
Update APR register with the measured LSI frequency.

Function Documentation

void AWU_Cmd ( FunctionalState NewState )

Enable or disable the AWU peripheral.

Parameters:
NewState Indicates the new state of the AWU peripheral.
Return values:
None
Required preconditions:
Initialisation of AWU and LS RC calibration must be done before.

Definition at line 108 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUEN, and DISABLE.

void AWU_DeInit ( void )

Deinitializes the AWU peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 67 of file stm8s_awu.c.

References AWU, AWU_APR_RESET_VALUE, AWU_CSR_RESET_VALUE, and AWU_TBR_RESET_VALUE.

FlagStatus AWU_GetFlagStatus ( void )

Returns status of the AWU peripheral flag.

Parameters:
None
Return values:
FlagStatus : Status of the AWU flag. This parameter can be any of the FlagStatus enumeration.

Definition at line 180 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUF, RESET, and SET.

void AWU_IdleModeEnable ( void )

Configures AWU in Idle mode to reduce power consumption.

Parameters:
None
Return values:
None

Definition at line 165 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUEN, and AWU_TBR_AWUTB.

void AWU_Init ( AWU_Timebase_TypeDef AWU_TimeBase )

Initializes the AWU peripheral according to the specified parameters.

Parameters:
AWU_TimeBase : Time base selection (interval between AWU interrupts). can be one of the values of AWU_Timebase_TypeDef.
Return values:
None
Required preconditions:
The LS RC calibration must be performed before calling this function.

Definition at line 82 of file stm8s_awu.c.

References APR_Array, AWU, AWU_APR_APR, AWU_CSR_AWUEN, AWU_TBR_AWUTB, IS_AWU_TIMEBASE_OK, and TBR_Array.

void AWU_LSICalibrationConfig ( uint32_t LSIFreqHz )

Update APR register with the measured LSI frequency.

Note on the APR calculation:
A is the integer part of lsifreqkhz/4 and x the decimal part. x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1] but we know that A + x = lsifreqkhz/4 ==> 4x = lsifreqkhz-4A so [F1] can be written : 4A >= (lsifreqkhz-4A)(1+2A)
Parameters:
LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
Return values:
None
Required preconditions:
  • AWU must be disabled to avoid unwanted interrupts.

Definition at line 135 of file stm8s_awu.c.

References AWU, and IS_LSI_FREQUENCY_OK.


STM8S/A Standard Peripherals Drivers: BEEP_Public_Functions

Functions

BEEP_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | BEEP_Cmd (FunctionalState NewState)
Enable or disable the BEEP function.
void | BEEP_DeInit (void)
Deinitializes the BEEP peripheral registers to their default reset values.
void | BEEP_Init (BEEP_Frequency_TypeDef BEEP_Frequency)
Initializes the BEEP function according to the specified parameters.
void | BEEP_LSICalibrationConfig (uint32_t LSIFreqHz)
Update CSR register with the measured LSI frequency.

Function Documentation

void BEEP_Cmd ( FunctionalState NewState )

Enable or disable the BEEP function.

Parameters:
NewState Indicates the new state of the BEEP function.
Return values:
None
Required preconditions:
Initialisation of BEEP and LS RC calibration must be done before.

Definition at line 87 of file stm8s_beep.c.

References BEEP, BEEP_CSR_BEEPEN, and DISABLE.

void BEEP_DeInit ( void )

Deinitializes the BEEP peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 48 of file stm8s_beep.c.

References BEEP, and BEEP_CSR_RESET_VALUE.

void BEEP_Init ( BEEP_Frequency_TypeDef BEEP_Frequency )

Initializes the BEEP function according to the specified parameters.

Parameters:
BEEP_Frequency Frequency selection. can be one of the values of BEEP_Frequency_TypeDef.
Return values:
None
Required preconditions:
The LS RC calibration must be performed before calling this function.

Definition at line 61 of file stm8s_beep.c.

References BEEP, BEEP_CALIBRATION_DEFAULT, BEEP_CSR_BEEPDIV, BEEP_CSR_BEEPSEL, and IS_BEEP_FREQUENCY_OK.

void BEEP_LSICalibrationConfig ( uint32_t LSIFreqHz )

Update CSR register with the measured LSI frequency.

Note on the APR calculation:
A is the integer part of LSIFreqkHz/4 and x the decimal part. x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1] but we know that A + x = LSIFreqkHz/4 ==> 4x = LSIFreqkHz-4A so [F1] can be written : 4A >= (LSIFreqkHz-4A)(1+2A)
Parameters:
LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
Return values:
None
Required preconditions:
  • BEEP must be disabled to avoid unwanted interrupts.

Definition at line 114 of file stm8s_beep.c.

References BEEP, BEEP_CSR_BEEPDIV, and IS_LSI_FREQUENCY_OK.


STM8S/A Standard Peripherals Drivers: CAN_Public_Functions

Functions

CAN_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | CAN_CancelTransmit (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_FLAG_TypeDef CAN_Flag)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_IT_TypeDef CAN_IT)
Clears the CAN’s interrupt pending bits.
void | CAN_DeInit (void)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (void)
Releases the CAN FIFO.
void | CAN_FilterInit (CAN_FilterNumber_TypeDef CAN_FilterNumber, FunctionalState CAN_FilterActivation, CAN_FilterMode_TypeDef CAN_FilterMode, CAN_FilterScale_TypeDef CAN_FilterScale, uint8_t CAN_FilterID1, uint8_t CAN_FilterID2, uint8_t CAN_FilterID3, uint8_t CAN_FilterID4, uint8_t CAN_FilterIDMask1, uint8_t CAN_FilterIDMask2, uint8_t CAN_FilterIDMask3, uint8_t CAN_FilterIDMask4)
Initializes the CAN peripheral Filter according to the specified parameters.
FlagStatus | CAN_GetFlagStatus (CAN_FLAG_TypeDef CAN_Flag)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_IT_TypeDef CAN_IT)
Checks whether the specified CAN interrupt has occurred or not.
CAN_ErrorCode_TypeDef | CAN_GetLastErrorCode (void)
Gets the Last Error Code.
uint16_t | CAN_GetMessageTimeStamp (void)
Returns the Received time stamp.
uint8_t | CAN_GetReceivedData (uint8_t CAN_DataIndex)
Gets the CAN Data of the received message.
uint8_t | CAN_GetReceivedDLC (void)
Gets the CAN DLC of the received message.
uint8_t | CAN_GetReceivedFMI (void)
Gets the CAN FMI of the received message.
uint32_t | CAN_GetReceivedId (void)
Gets the CAN Id of the received message.
CAN_Id_TypeDef | CAN_GetReceivedIDE (void)
Gets the CAN IDE of the received message.
CAN_RTR_TypeDef | CAN_GetReceivedRTR (void)
Gets the CAN RTR of the received message.
CAN_Page_TypeDef | CAN_GetSelectedPage (void)
Gets the selected registers page.
CAN_InitStatus_TypeDef | CAN_Init (CAN_MasterCtrl_TypeDef CAN_MasterCtrl, CAN_Mode_TypeDef CAN_Mode, CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth, CAN_BitSeg1_TypeDef CAN_BitSeg1, CAN_BitSeg2_TypeDef CAN_BitSeg2, uint8_t CAN_Prescaler)
Initializes the CAN peripheral according to the specified parameters.
void | CAN_ITConfig (CAN_IT_TypeDef CAN_IT, FunctionalState NewState)
Enables or disables the specified CAN interrupts.
CAN_NbrPendingMessage_TypeDef | CAN_MessagePending (void)
Returns the number of pending messages.
CAN_ModeStatus_TypeDef | CAN_OperatingModeRequest (CAN_OperatingMode_TypeDef CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (void)
Receives a message which contains CAN Id, IDE, RTR DLC, datas and FMI number.
void | CAN_SelectPage (CAN_Page_TypeDef CAN_Page)
Sets the registers page to be selected.
CAN_Sleep_TypeDef | CAN_Sleep (void)
Enters the Sleep low power mode.
void | CAN_ST7CompatibilityCmd (CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)
Enables or Disables the ST7 CAN Compatibility.
CAN_TxStatus_TypeDef | CAN_Transmit (uint32_t CAN_Id, CAN_Id_TypeDef CAN_IDE, CAN_RTR_TypeDef CAN_RTR, uint8_t CAN_DLC, uint8_t *CAN_Data)
Initiates the transmission of a message.
CAN_TxStatus_TypeDef | CAN_TransmitStatus (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
CAN_WakeUp_TypeDef | CAN_WakeUp (void)
Wakes the CAN up.
static ITStatus | CheckITStatus (uint8_t CAN_Reg, uint8_t It_Bit)
Checks whether the CAN interrupt has occurred or not.

Function Documentation

void CAN_CancelTransmit ( CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox )

Cancels a transmit request.

Parameters:
TransmitMailbox : the Transmission mailbox, can be one of CAN_TransmitMailBox_TypeDef
Return values:
None

Definition at line 718 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_MCSR_ABRQ, CAN_SelectPage(), and IS_CAN_TRANSMITMAILBOX_OK.

void CAN_ClearFlag ( CAN_FLAG_TypeDef CAN_Flag )

Clears the CAN's pending flags.

Parameters:
CAN_FLAG : Flag to be cleared, can be one of the following parameters: CAN_FLAG_RQCP0 Request MailBox0 Flag CAN_FLAG_RQCP1 Request MailBox1 Flag CAN_FLAG_RQCP2 Request MailBox2 Flag CAN_FLAG_FF FIFO Full Flag CAN_FLAG_FOV FIFO Overrun Flag CAN_FLAG_WKU wake up Flag CAN_FLAG_LEC Last error code Flag
Return values:
None

Definition at line 1073 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), IS_CAN_FLAG_CLEAR_OK, and RESET.

void CAN_ClearITPendingBit ( CAN_IT_TypeDef CAN_IT )

Clears the CAN’s interrupt pending bits.

Parameters:
CAN_IT,: specifies the interrupt pending bit to clear, can be one of the following parameters: CAN_IT_TME = Transmit mailbox empty interrupt CAN_IT_FF =FIFO full interrupt CAN_IT_FOV =FIFO overrun interrupt CAN_IT_WKU =Wake-up interrupt CAN_IT_ERR =General Error interrupt CAN_IT_EWG =Error warning interrupt CAN_IT_EPV =Error passive interrupt CAN_IT_BOF = Bus-off interrupt CAN_IT_LEC =Last error code interrupt
Return values:
None

Definition at line 1344 of file stm8s_can.c.

References CAN_ESR_RESET_VALUE, CAN_GetSelectedPage(), CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF, CAN_IT_FOV, CAN_IT_LEC, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_ERRI, CAN_MSR_WKUI, CAN_Page_Config, CAN_RFR_FOVR, CAN_RFR_FULL, CAN_SelectPage(), CAN_TSR_RQCP012, and IS_CAN_IT_PENDING_BIT_OK.

void CAN_DeInit ( void )

Deinitializes the CAN peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 56 of file stm8s_can.c.

References CAN_BTR1_RESET_VALUE, CAN_BTR2_RESET_VALUE, CAN_DGR_RESET_VALUE, CAN_EIER_RESET_VALUE, CAN_ESR_RESET_VALUE, CAN_FCR_RESET_VALUE, CAN_FMR1_RESET_VALUE, CAN_FMR2_RESET_VALUE, CAN_IER_RESET_VALUE, CAN_MCR_INRQ, CAN_MCR_RESET_VALUE, CAN_MDLC_RESET_VALUE, CAN_MSR_RESET_VALUE, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingModeRequest(), CAN_Page_Config, CAN_Page_RxFifo, CAN_Page_TxMailBox0, CAN_Page_TxMailBox1, CAN_Page_TxMailBox2, CAN_PSR_RESET_VALUE, CAN_RFR_RESET_VALUE, and CAN_TSR_RESET_VALUE.

void CAN_FIFORelease ( void )

Releases the CAN FIFO.

Parameters:
None
Return values:
None

Definition at line 736 of file stm8s_can.c.

References CAN_RFR_RFOM.

Referenced by CAN_Receive().

void CAN_FilterInit | ( | CAN_FilterNumber_TypeDef | CAN_FilterNumber,
 |  | FunctionalState | CAN_FilterActivation,
 |  | CAN_FilterMode_TypeDef | CAN_FilterMode,
 |  | CAN_FilterScale_TypeDef | CAN_FilterScale,
 |  | uint8_t | CAN_FilterID1,
 |  | uint8_t | CAN_FilterID2,
 |  | uint8_t | CAN_FilterID3,
 |  | uint8_t | CAN_FilterID4,
 |  | uint8_t | CAN_FilterIDMask1,
 |  | uint8_t | CAN_FilterIDMask2,
 |  | uint8_t | CAN_FilterIDMask3,
 |  | uint8_t | CAN_FilterIDMask4
 | ) |  |

Initializes the CAN peripheral Filter according to the specified parameters.

Parameters:
CAN_FilterNumber | : CAN Filter number , can be one of CAN_FilterNumber_TypeDef
CAN_FilterActivation | : CAN Filter Activation state , can be one of FunctionalState
CAN_FilterMode | : CAN Filter Mode , can be one of CAN_FilterMode_TypeDef
CAN_FilterScale | : CAN Filter Scale , can be one of CAN_FilterScale_TypeDef
CAN_FilterID1 | : CAN Filter ID 1 , can be a value from 0x00 to 0xFF
CAN_FilterID2 | : CAN Filter ID 2 , can be a value from 0x00 to 0xFF
CAN_FilterID3 | : CAN Filter ID 3 , can be a value from 0x00 to 0xFF
CAN_FilterID4 | : CAN Filter ID 4 , can be a value from 0x00 to 0xFF
CAN_FilterIDMask1 | : CAN Filter ID 1/ Mask 1 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask2 | : CAN Filter ID 2/ Mask 2 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask3 | : CAN Filter ID 3/ Mask 3 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask4 | : CAN Filter ID 4/ Mask 4 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
Return values:
None

Definition at line 188 of file stm8s_can.c.

References CAN_FCR1_FSC00, CAN_FCR1_FSC01, CAN_FilterMode_IdList, CAN_FilterMode_IdList_IdMask, CAN_FilterMode_IdMask, CAN_FilterNumber_0, CAN_FilterNumber_1, CAN_FilterNumber_2, CAN_FilterNumber_3, CAN_FilterNumber_4, CAN_FilterScale_16_8Bit, CAN_FilterScale_16Bit, CAN_FilterScale_32Bit, CAN_FilterScale_8Bit, CAN_GetSelectedPage(), CAN_IDLIST_IDMASK_MASK, CAN_IDMASK_IDLIST_MASK, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingModeRequest(), CAN_Page_Config, CAN_Page_Filter01, CAN_Page_Filter23, CAN_Page_Filter45, CAN_SelectPage(), DISABLE, IS_CAN_FILTER_MODE_OK, IS_CAN_FILTER_NUMBER_OK, IS_CAN_FILTER_SCALE_OK, and IS_FUNCTIONALSTATE_OK.

FlagStatus CAN_GetFlagStatus ( CAN_FLAG_TypeDef CAN_Flag )

Checks whether the specified CAN flag is set or not.

Parameters:
CAN_FLAG,: specifies the flag to check, can be one of CAN_FLAG_TypeDef enumeration.
Return values:
The new state of CAN_FLAG which can be one of FlagStatus.

Definition at line 1115 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), IS_CAN_FLAG_STATUS_OK, RESET, and SET.

ITStatus CAN_GetITStatus ( CAN_IT_TypeDef CAN_IT )

Checks whether the specified CAN interrupt has occurred or not.

Parameters:
CAN_IT,: specifies the CAN interrupt source to check, can be one of CAN_IT_TypeDef.
Return values:
The new state of CAN_IT, which can be one of ITStatus.

Definition at line 1199 of file stm8s_can.c.

References CAN_EIER_BOFIE, CAN_EIER_EPVIE, CAN_EIER_ERRIE, CAN_EIER_EWGIE, CAN_EIER_LECIE, CAN_ESR_BOFF, CAN_ESR_EPVF, CAN_ESR_EWGF, CAN_ESR_LEC, CAN_GetSelectedPage(), CAN_IER_FFIE, CAN_IER_FMPIE, CAN_IER_FOVIE, CAN_IER_TMEIE, CAN_IER_WKUIE, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF, CAN_IT_FMP, CAN_IT_FOV, CAN_IT_LEC, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_WKUI, CAN_Page_Config, CAN_RFR_FMP01, CAN_RFR_FOVR, CAN_RFR_FULL, CAN_SelectPage(), CAN_TSR_RQCP012, CheckITStatus(), IS_CAN_IT_STATUS_OK, and RESET.

CAN_ErrorCode_TypeDef CAN_GetLastErrorCode ( void )

Gets the Last Error Code.

Parameters:
None
Return values:
Error Code.

Definition at line 1047 of file stm8s_can.c.

References CAN_ErrorCode_NoErr, CAN_ESR_LEC, CAN_GetSelectedPage(), CAN_Page_Config, and CAN_SelectPage().

uint16_t CAN_GetMessageTimeStamp ( void )

Returns the Received time stamp.

Parameters:
None
Return values:
uint16_t the received time stamp.

Definition at line 896 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_RxFifo, and CAN_SelectPage().

uint8_t CAN_GetReceivedData ( uint8_t CAN_DataIndex )

Gets the CAN Data of the received message.

Parameters:
CAN_DataIndexe : number of the received Data, it can be an integer between 0 to 7.
Return values:
the received CAN message ith Data.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 872 of file stm8s_can.c.

References _Data, and IS_CAN_DLC_OK.

uint8_t CAN_GetReceivedDLC ( void )

Gets the CAN DLC of the received message.

Parameters:
None
Return values:
the received CAN message DLC.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 858 of file stm8s_can.c.

References _DLC.

uint8_t CAN_GetReceivedFMI ( void )

Gets the CAN FMI of the received message.

Parameters:
None
Return values:
the received CAN message FMI.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 886 of file stm8s_can.c.

References _FMI.

uint32_t CAN_GetReceivedId ( void )

Gets the CAN Id of the received message.

Parameters:
None
Return values:
the received CAN message Id.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 819 of file stm8s_can.c.

References _Id.

CAN_Id_TypeDef CAN_GetReceivedIDE ( void )

Gets the CAN IDE of the received message.

Parameters:
None
Return values:
the received CAN message IDE.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 832 of file stm8s_can.c.

References _IDE.

CAN_RTR_TypeDef CAN_GetReceivedRTR ( void )

Gets the CAN RTR of the received message.

Parameters:
None
Return values:
the received CAN message RTR.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 845 of file stm8s_can.c.

References _RTR.

CAN_Page_TypeDef CAN_GetSelectedPage ( void )

Gets the selected registers page.

Parameters:
None
Return values:
the selected page which can be one of the CAN_Page_TypeDef.

Definition at line 1405 of file stm8s_can.c.

Referenced by CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_FilterInit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetMessageTimeStamp(), CAN_Init(), CAN_ITConfig(), CAN_Receive(), CAN_Transmit(), and CAN_TTComModeCmd().

CAN_InitStatus_TypeDef CAN_Init | ( | CAN_MasterCtrl_TypeDef | CAN_MasterCtrl,
 |  | CAN_Mode_TypeDef | CAN_Mode,
 |  | CAN_SynJumpWidth_TypeDef | CAN_SynJumpWidth,
 |  | CAN_BitSeg1_TypeDef | CAN_BitSeg1,
 |  | CAN_BitSeg2_TypeDef | CAN_BitSeg2,
 |  | uint8_t | CAN_Prescaler
 | ) |  |

Initializes the CAN peripheral according to the specified parameters.

Parameters:
CAN_MasterCtrl | : Master control option, can be one or a combination of CAN_MasterCtrl_TypeDef.
CAN_Mode | : CAN mode , can be one of CAN_Mode_TypeDef.
CAN_SynJumpWidth | : CAN Synchronisation Jump Width , can be one of CAN_SynJumpWidth_TypeDef.
CAN_BitSeg1 | : CAN bit segment 1 , can be one of CAN_BitSeg1_TypeDef.
CAN_BitSeg2 | : CAN bit segment 2 , can be one of CAN_BitSeg2_TypeDef.
CAN_Prescaler | : CAN Baud Rate Prescaler , can be a value from 0x01 to 0xFF.
Return values:
Indicates if initialization is succeed. it can be one of CAN_InitStatus_TypeDef enumeration.

Definition at line 100 of file stm8s_can.c.

References CAN_ACKNOWLEDGE_TIMEOUT, CAN_GetSelectedPage(), CAN_InitStatus_Failed, CAN_InitStatus_Success, CAN_MCR_INRQ, CAN_MSR_INAK, CAN_Page_Config, CAN_SelectPage(), IS_CAN_BITSEG1_OK, IS_CAN_BITSEG2_OK, IS_CAN_MASTERCTRL_OK, IS_CAN_MODE_OK, IS_CAN_PRESCALER_OK, and IS_CAN_SYNJUMPWIDTH_OK.

void CAN_ITConfig | ( | CAN_IT_TypeDef | CAN_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified CAN interrupts.

Parameters:
CAN_IT,: specifies the CAN interrupt sources to be enabled or disabled.
NewState : CAN_IT new state , can be one of FunctionalState
Return values:
None

Definition at line 481 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), DISABLE, IS_CAN_IT_CONFIG_OK, and IS_FUNCTIONALSTATE_OK.

CAN_NbrPendingMessage_TypeDef CAN_MessagePending ( void )

Returns the number of pending messages.

Return values:
Number of pending messages.

Definition at line 746 of file stm8s_can.c.

References CAN_NbrPendingMessage_0, and CAN_RFR_FMP01.

CAN_ModeStatus_TypeDef CAN_OperatingModeRequest ( CAN_OperatingMode_TypeDef CAN_OperatingMode )

Select the CAN Operation mode.

Parameters:
CAN_OperatingMode CAN Operating Mode , this parameter can be one of CAN_OperatingMode_TypeDef enumeration.
Return values:
the status of the requested mode which can be

  • CAN_ModeStatus_Failed CAN failed entring the specific mode
  • CAN_ModeStatus_Success CAN Succeed entring the specific mode

Definition at line 969 of file stm8s_can.c.

References CAN_ACKNOWLEDGE_TIMEOUT, CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MODE_MASK, CAN_ModeStatus_Failed, CAN_ModeStatus_Success, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingMode_Sleep, and IS_CAN_OPERATINGMODE_OK.

Referenced by CAN_DeInit(), and CAN_FilterInit().

void CAN_Receive ( void )

Receives a message which contains CAN Id, IDE, RTR DLC, datas and FMI number.

In order to get these data, use CAN_GetReceivedId(), CAN_GetReceivedIDE(), CAN_GetReceivedRTR(), CAN_GetReceivedDLC(), CAN_GetReceivedFMI() and CAN_GetReceivedData() functions.

Parameters:
None
Return values:
None

Definition at line 761 of file stm8s_can.c.

References _Data, _DLC, _FMI, _Id, _IDE, _RTR, CAN_EXTID_SIZE, CAN_FIFORelease(), CAN_GetSelectedPage(), CAN_Id_Extended, CAN_Id_Standard, CAN_Page_RxFifo, CAN_SelectPage(), and CAN_STDID_SIZE.

void CAN_SelectPage ( CAN_Page_TypeDef CAN_Page )

Sets the registers page to be selected.

Parameters:
the selected page which can be one of the CAN_Page_TypeDef.
Return values:
None

Definition at line 1415 of file stm8s_can.c.

Referenced by CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_FilterInit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetMessageTimeStamp(), CAN_Init(), CAN_ITConfig(), CAN_Receive(), CAN_Transmit(), and CAN_TTComModeCmd().

CAN_Sleep_TypeDef CAN_Sleep ( void )

Enters the Sleep low power mode.

Parameters:
None
Return values:
CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an other case.

Definition at line 918 of file stm8s_can.c.

References CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_Sleep_Failed, and CAN_Sleep_Ok.

void CAN_ST7CompatibilityCmd ( CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility )

Enables or Disables the ST7 CAN Compatibility.

if the ST7 compatibility is Enabled, CAN provides only 2 mailboxes. if the ST7 compatibility is Disabled, CAN provides 3 mailboxes.

Parameters:
CAN_ST7Compatibility : CAN ST7 Compatibility , this parameter can be one of CAN_ST7Compatibility_TypeDef enumeration.
Return values:
None

Definition at line 519 of file stm8s_can.c.

References CAN_DGR_TXM2E, and IS_CAN_ST7_COMPATIBILITY_OK.

CAN_TxStatus_TypeDef CAN_Transmit | ( | uint32_t | CAN_Id,
 |  | CAN_Id_TypeDef | CAN_IDE,
 |  | CAN_RTR_TypeDef | CAN_RTR,
 |  | uint8_t | CAN_DLC,
 |  | uint8_t * | CAN_Data
 | ) |  |

Initiates the transmission of a message.

Parameters:
CAN_Id | the ID number of the message, its size depends on CAN_IDE value.
[in] | CAN_IDE | the ID type of the message, this parameter can be one of the CAN_Id_TypeDef enumeration.
[in] | CAN_RTR | the message type, this parameter can be one of the CAN_RTR_TypeDef enumeration.
[in] | CAN_DLC | the number of data in the message type, this parameter can be a value between 0 to 7.
[in] | CAN_Data | pointer to a the uint8_t table which contains data to sent.
Return values:
Transmit Status, this returned value can be one of the CAN_TxStatus_TypeDef enumeration.

Definition at line 581 of file stm8s_can.c.

References CAN_EXTID_SIZE, CAN_GetSelectedPage(), CAN_Id_Standard, CAN_MCSR_TXRQ, CAN_SelectPage(), CAN_STDID_SIZE, CAN_TPR_TME0, CAN_TPR_TME1, CAN_TPR_TME2, CAN_TxStatus_MailBox0Ok, CAN_TxStatus_MailBox1Ok, CAN_TxStatus_MailBox2Ok, CAN_TxStatus_NoMailBox, IS_CAN_DLC_OK, IS_CAN_EXTID_OK, IS_CAN_IDTYPE_OK, IS_CAN_RTR_OK, and IS_CAN_STDID_OK.

CAN_TxStatus_TypeDef CAN_TransmitStatus ( CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox )

Checks the transmission of a message.

Parameters:
TransmitMailbox,: the number of the mailbox that is used for transmission, can be on of CAN_TransmitMailBox_TypeDef.
Return values:
CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.

Definition at line 666 of file stm8s_can.c.

References CAN_TPR_TME0, CAN_TPR_TME1, CAN_TPR_TME2, CAN_TransmitMailBox_0, CAN_TransmitMailBox_1, CAN_TransmitMailBox_2, CAN_TSR_RQCP0, CAN_TSR_RQCP1, CAN_TSR_RQCP2, CAN_TSR_TXOK0, CAN_TSR_TXOK1, CAN_TSR_TXOK2, CAN_TxStatus_Failed, CAN_TxStatus_MailBoxEmpty, CAN_TxStatus_Ok, CAN_TxStatus_Pending, and IS_CAN_TRANSMITMAILBOX_OK.

void CAN_TTComModeCmd ( FunctionalState NewState )

Enables or disables the CAN Time TriggerOperation communication mode.

Parameters:
NewState : Mode new state , can be one of FunctionalState
Return values:
None

Definition at line 535 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_MCR_TTCM, CAN_MDLCR_TGT, CAN_Page_RxFifo, CAN_Page_TxMailBox0, CAN_Page_TxMailBox1, CAN_Page_TxMailBox2, CAN_SelectPage(), DISABLE, and IS_FUNCTIONALSTATE_OK.

CAN_WakeUp_TypeDef CAN_WakeUp ( void )

Wakes the CAN up.

Parameters:
None
Return values:
CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an other case.

Definition at line 942 of file stm8s_can.c.

References CAN_MCR_SLEEP, CAN_MSR_SLAK, CAN_WakeUp_Failed, and CAN_WakeUp_Ok.

static ITStatus CheckITStatus | ( | uint8_t | CAN_Reg,
 |  | uint8_t | It_Bit
 | ) |  | [static]

Checks whether the CAN interrupt has occurred or not.

Parameters:
CAN_Reg,: specifies the CAN interrupt register to check.
It_Bit,: specifies the interrupt source bit to check.
Return values:
The new state of the CAN Interrupt, which can be one of ITStatus.

Definition at line 1426 of file stm8s_can.c.

References RESET, and SET.

Referenced by CAN_GetITStatus().


STM8S/A Standard Peripherals Drivers: CLK_Private_Constants

Variables

CLK_Private_Constants

STM8S_StdPeriph_Driver

Variables

CONST uint8_t | CLKPrescTable [8] = {1, 2, 4, 8, 10, 16, 20, 40}
CONST uint8_t | HSIDivFactor [4] = {1, 2, 4, 8}

Variable Documentation

CONST uint8_t CLKPrescTable[8] = {1, 2, 4, 8, 10, 16, 20, 40}

Holds the different CLK prescaler values

Definition at line 43 of file stm8s_clk.c.

CONST uint8_t HSIDivFactor[4] = {1, 2, 4, 8}

Holds the different HSI Divider factors

Definition at line 42 of file stm8s_clk.c.

Referenced by CLK_GetClockFreq().


STM8S/A Standard Peripherals Drivers: CLK_Public_Functions

Functions

CLK_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | CLK_AdjustHSICalibrationValue (CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | CLK_CCOCmd (FunctionalState NewState)
Enables or disablle the Configurable Clock Output (CCO).
void | CLK_CCOConfig (CLK_Output_TypeDef CLK_CCO)
Output the selected clock on a dedicated I/O pin.
void | CLK_ClearITPendingBit (CLK_IT_TypeDef CLK_IT)
Clears the CLK’s interrupt pending bits.
void | CLK_ClockSecuritySystemEnable (void)
Enables the Clock Security System.
void | CLK_ClockSwitchCmd (FunctionalState NewState)
Starts or Stops manually the clock switch execution.
ErrorStatus | CLK_ClockSwitchConfig (CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
configures the Switch from one clock to another
void | CLK_DeInit (void)
Deinitializes the CLK peripheral registers to their default reset values.
void | CLK_FastHaltWakeUpCmd (FunctionalState NewState)
Configures the High Speed Internal oscillator (HSI).
uint32_t | CLK_GetClockFreq (void)
This function returns the frequencies of different on chip clocks.
FlagStatus | CLK_GetFlagStatus (CLK_Flag_TypeDef CLK_FLAG)
Checks whether the specified CLK flag is set or not.
ITStatus | CLK_GetITStatus (CLK_IT_TypeDef CLK_IT)
Checks whether the specified CLK interrupt has is enabled or not.
CLK_Source_TypeDef | CLK_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | CLK_HSECmd (FunctionalState NewState)
Enable or Disable the External High Speed oscillator (HSE).
void | CLK_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | CLK_HSIPrescalerConfig (CLK_Prescaler_TypeDef HSIPrescaler)
Configures the HSI clock dividers.
void | CLK_ITConfig (CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
Enables or disables the specified CLK interrupts.
void | CLK_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | CLK_PeripheralClockConfig (CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
Enables or disables the specified peripheral CLK.
void | CLK_SlowActiveHaltWakeUpCmd (FunctionalState NewState)
Configures the slow active halt wake up.
void | CLK_SWIMConfig (CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
Configures the SWIM clock frequency on the fly.
void | CLK_SYSCLKConfig (CLK_Prescaler_TypeDef CLK_Prescaler)
Configures the HSI and CPU clock dividers.
void | CLK_SYSCLKEmergencyClear (void)
Reset the SWBSY flag (SWICR Reister)

Function Documentation

void CLK_AdjustHSICalibrationValue ( CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue )

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Full description:
Parameters:
CLK_HSICalibrationValue calibration trimming value. can be one of the values of CLK_HSITrimValue_TypeDef
Return values:
None

Definition at line 616 of file stm8s_clk.c.

References CLK, CLK_HSITRIMR_HSITRIM, and IS_CLK_HSITRIMVALUE_OK.

void CLK_CCOCmd ( FunctionalState NewState )

Enables or disablle the Configurable Clock Output (CCO).

Parameters:
NewState : New state of CCEN bit (CCO register). This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 192 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_CCOConfig ( CLK_Output_TypeDef CLK_CCO )

Output the selected clock on a dedicated I/O pin.

Parameters:
CLK_CCO : Specifies the clock source. This parameter can be any of the CLK_Output_TypeDef enumeration.
Return values:
None
Required preconditions:
The dedicated I/O pin must be set at 1 in the corresponding Px_CR1 register
to be set as input with pull-up or push-pull output.

Definition at line 439 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, CLK_CCOR_CCOSEL, and IS_CLK_OUTPUT_OK.

void CLK_ClearITPendingBit ( CLK_IT_TypeDef CLK_IT )

Clears the CLK’s interrupt pending bits.

Parameters:
CLK_IT specifies the interrupt pending bits. can be one of the values of CLK_IT_TypeDef
Return values:
None

Definition at line 747 of file stm8s_clk.c.

References CLK, CLK_CSSR_CSSD, CLK_IT_CSSD, CLK_SWCR_SWIF, and IS_CLK_IT_OK.

void CLK_ClockSecuritySystemEnable ( void )

Enables the Clock Security System.

Full description:
once CSS is enabled it cannot be disabled until the next reset.
Parameters:
None
Return values:
None

Definition at line 557 of file stm8s_clk.c.

References CLK, and CLK_CSSR_CSSEN.

void CLK_ClockSwitchCmd ( FunctionalState NewState )

Starts or Stops manually the clock switch execution.

Full description:
NewState parameter set the SWEN.
Parameters:
NewState new state of SWEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 218 of file stm8s_clk.c.

References CLK, CLK_SWCR_SWEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

ErrorStatus CLK_ClockSwitchConfig | ( | CLK_SwitchMode_TypeDef | CLK_SwitchMode,
 |  | CLK_Source_TypeDef | CLK_NewClock,
 |  | FunctionalState | ITState,
 |  | CLK_CurrentClockState_TypeDef | CLK_CurrentClockState
 | ) |  |

configures the Switch from one clock to another

Parameters:
CLK_SwitchMode | select the clock switch mode. It can be set of the values of CLK_SwitchMode_TypeDef
CLK_NewClock | choice of the future clock. It can be set of the values of CLK_Source_TypeDef
NewState | Enable or Disable the Clock Switch interrupt.
CLK_CurrentClockState | current clock to switch OFF or to keep ON. It can be set of the values of CLK_CurrentClockState_TypeDef
Return values:
ErrorStatus this shows the clock switch status (ERROR/SUCCESS).

Definition at line 319 of file stm8s_clk.c.

References CLK, CLK_CURRENTCLOCKSTATE_DISABLE, CLK_ECKR_HSEEN, CLK_ICKR_HSIEN, CLK_ICKR_LSIEN, CLK_SOURCE_HSE, CLK_SOURCE_HSI, CLK_SOURCE_LSI, CLK_SWCR_SWBSY, CLK_SWCR_SWEN, CLK_SWCR_SWIEN, CLK_SWITCHMODE_AUTO, CLK_TIMEOUT, DISABLE, ERROR, IS_CLK_CURRENTCLOCKSTATE_OK, IS_CLK_SOURCE_OK, IS_CLK_SWITCHMODE_OK, IS_FUNCTIONALSTATE_OK, and SUCCESS.

void CLK_DeInit ( void )

Deinitializes the CLK peripheral registers to their default reset values.

Parameters:
None
Return values:
None
Warning:
Resetting the CCOR register:
When the CCOEN bit is set, the reset of the CCOR register require two consecutive write instructions in order to reset first the CCOEN bit and the second one is to reset the CCOSEL bits.

Definition at line 66 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, CLK_CCOR_RESET_VALUE, CLK_CKDIVR_RESET_VALUE, CLK_CSSR_RESET_VALUE, CLK_ECKR_RESET_VALUE, CLK_HSITRIMR_RESET_VALUE, CLK_ICKR_RESET_VALUE, CLK_PCKENR1_RESET_VALUE, CLK_PCKENR2_RESET_VALUE, CLK_SWCR_RESET_VALUE, CLK_SWIMCCR_RESET_VALUE, and CLK_SWR_RESET_VALUE.

void CLK_FastHaltWakeUpCmd ( FunctionalState NewState )

Configures the High Speed Internal oscillator (HSI).

Full description:
If CLK_FastHaltWakeup is enabled, HSI oscillator is automatically switched-on (HSIEN=1) and selected as next clock master (CKM=SWI=HSI) when resuming from HALT/ActiveHalt modes.
Parameters:
NewState this parameter is the Wake-up Mode state.
Return values:
None

Definition at line 95 of file stm8s_clk.c.

References CLK, CLK_ICKR_FHWU, DISABLE, and IS_FUNCTIONALSTATE_OK.

uint32_t CLK_GetClockFreq ( void )

This function returns the frequencies of different on chip clocks.

Parameters:
None
Return values:
the master clock frequency

Definition at line 579 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_HSIDIV, CLK_SOURCE_HSI, CLK_SOURCE_LSI, HSE_VALUE, HSI_VALUE, HSIDivFactor, and LSI_VALUE.

Referenced by UART1_Init(), UART2_Init(), and UART3_Init().

FlagStatus CLK_GetFlagStatus ( CLK_Flag_TypeDef CLK_FLAG )

Checks whether the specified CLK flag is set or not.

Full description:
Parameters:
CLK_FLAG Flag to check. can be one of the values of CLK_Flag_TypeDef
Return values:
FlagStatus,status of the checked flag

Definition at line 648 of file stm8s_clk.c.

References CLK, IS_CLK_FLAG_OK, RESET, and SET.

ITStatus CLK_GetITStatus ( CLK_IT_TypeDef CLK_IT )

Checks whether the specified CLK interrupt has is enabled or not.

Parameters:
CLK_IT specifies the CLK interrupt. can be one of the values of CLK_IT_TypeDef
Return values:
ITStatus,new state of CLK_IT (SET or RESET).

Definition at line 703 of file stm8s_clk.c.

References CLK, CLK_IT_SWIF, IS_CLK_IT_OK, RESET, and SET.

CLK_Source_TypeDef CLK_GetSYSCLKSource ( void )

Returns the clock source used as system clock.

Parameters:
None
Return values:
Clock source used. can be one of the values of CLK_Source_TypeDef

Definition at line 569 of file stm8s_clk.c.

References CLK.

void CLK_HSECmd ( FunctionalState NewState )

Enable or Disable the External High Speed oscillator (HSE).

Parameters:
NewState new state of HSEEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 119 of file stm8s_clk.c.

References CLK, CLK_ECKR_HSEEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_HSICmd ( FunctionalState NewState )

Enables or disables the Internal High Speed oscillator (HSI).

Parameters:
NewState new state of HSIEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 143 of file stm8s_clk.c.

References CLK, CLK_ICKR_HSIEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_HSIPrescalerConfig ( CLK_Prescaler_TypeDef HSIPrescaler )

Configures the HSI clock dividers.

Parameters:
HSIPrescaler : Specifies the HSI clock divider to apply. This parameter can be any of the CLK_Prescaler_TypeDef enumeration.
Return values:
None

Definition at line 416 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_HSIDIV, and IS_CLK_HSIPRESCALER_OK.

void CLK_ITConfig | ( | CLK_IT_TypeDef | CLK_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified CLK interrupts.

Parameters:
CLK_IT | This parameter specifies the interrupt sources. It can be one of the values of CLK_IT_TypeDef.
NewState | New state of the Interrupt. Value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 464 of file stm8s_clk.c.

References CLK, CLK_CSSR_CSSDIE, CLK_IT_CSSD, CLK_IT_SWIF, CLK_SWCR_SWIEN, DISABLE, IS_CLK_IT_OK, and IS_FUNCTIONALSTATE_OK.

void CLK_LSICmd ( FunctionalState NewState )

Enables or disables the Internal Low Speed oscillator (LSI).

Parameters:
NewState new state of LSIEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 167 of file stm8s_clk.c.

References CLK, CLK_ICKR_LSIEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_PeripheralClockConfig | ( | CLK_Peripheral_TypeDef | CLK_Peripheral,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified peripheral CLK.

Parameters:
CLK_Peripheral | : This parameter specifies the peripheral clock to gate. This parameter can be any of the CLK_Peripheral_TypeDef enumeration.
NewState | : New state of specified peripheral clock. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 272 of file stm8s_clk.c.

References CLK, DISABLE, IS_CLK_PERIPHERAL_OK, and IS_FUNCTIONALSTATE_OK.

void CLK_SlowActiveHaltWakeUpCmd ( FunctionalState NewState )

Configures the slow active halt wake up.

Parameters:
NewState,: specifies the Slow Active Halt wake up state. can be set of the following values:

  • DISABLE: Slow Active Halt mode disabled;
  • ENABLE: Slow Active Halt mode enabled.
Return values:
None

Definition at line 245 of file stm8s_clk.c.

References CLK, CLK_ICKR_SWUAH, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_SWIMConfig ( CLK_SWIMDivider_TypeDef CLK_SWIMDivider )

Configures the SWIM clock frequency on the fly.

Parameters:
CLK_SWIMDivider Specifies the SWIM clock divider to apply. can be one of the value of CLK_SWIMDivider_TypeDef
Return values:
None

Definition at line 531 of file stm8s_clk.c.

References CLK, CLK_SWIMCCR_SWIMDIV, CLK_SWIMDIVIDER_2, and IS_CLK_SWIMDIVIDER_OK.

void CLK_SYSCLKConfig ( CLK_Prescaler_TypeDef CLK_Prescaler )

Configures the HSI and CPU clock dividers.

Parameters:
ClockPrescaler Specifies the HSI or CPU clock divider to apply.
Return values:
None

Definition at line 507 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_CPUDIV, CLK_CKDIVR_HSIDIV, and IS_CLK_PRESCALER_OK.

void CLK_SYSCLKEmergencyClear ( void )

Reset the SWBSY flag (SWICR Reister)

Full description:
This function reset SWBSY flag in order to reset clock switch operations (target oscillator is broken, stabilization is longing too much, etc.). If at the same time
software attempts to set SWEN and clear SWBSY, SWBSY action takes precedence.
Parameters:
None
Return values:
None

Definition at line 636 of file stm8s_clk.c.

References CLK, and CLK_SWCR_SWBSY.


STM8S/A Standard Peripherals Drivers: EXTI_Public_Functions

Functions

EXTI_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | EXTI_DeInit (void)
Deinitializes the external interrupt control registers to their default reset value.
EXTI_Sensitivity_TypeDef | EXTI_GetExtIntSensitivity (EXTI_Port_TypeDef Port)
Get the external interrupt sensitivity of the selected port.
EXTI_TLISensitivity_TypeDef | EXTI_GetTLISensitivity (void)
Get the TLI interrupt sensitivity.
void | EXTI_SetExtIntSensitivity (EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)
Set the external interrupt sensitivity of the selected port.
void | EXTI_SetTLISensitivity (EXTI_TLISensitivity_TypeDef SensitivityValue)
Set the TLI interrupt sensitivity.

Function Documentation

void EXTI_DeInit ( void )

Deinitializes the external interrupt control registers to their default reset value.

Parameters:
None
Return values:
None

Definition at line 47 of file stm8s_exti.c.

References EXTI, EXTI_CR1_RESET_VALUE, and EXTI_CR2_RESET_VALUE.

EXTI_Sensitivity_TypeDef EXTI_GetExtIntSensitivity ( EXTI_Port_TypeDef Port )

Get the external interrupt sensitivity of the selected port.

Parameters:
Port The port number to access.
Return values:
EXTI_Sensitivity_TypeDef The external interrupt sensitivity of the selected port.

Definition at line 121 of file stm8s_exti.c.

References EXTI, EXTI_CR1_PAIS, EXTI_CR1_PBIS, EXTI_CR1_PCIS, EXTI_CR1_PDIS, EXTI_CR2_PEIS, EXTI_PORT_GPIOA, EXTI_PORT_GPIOB, EXTI_PORT_GPIOC, EXTI_PORT_GPIOD, EXTI_PORT_GPIOE, and IS_EXTI_PORT_OK.

EXTI_TLISensitivity_TypeDef EXTI_GetTLISensitivity ( void )

Get the TLI interrupt sensitivity.

Parameters:
None
Return values:
EXTI_TLISensitivity_TypeDef The TLI interrupt sensitivity read.

Definition at line 157 of file stm8s_exti.c.

References EXTI, and EXTI_CR2_TLIS.

void EXTI_SetExtIntSensitivity | ( | EXTI_Port_TypeDef | Port,
 |  | EXTI_Sensitivity_TypeDef | SensitivityValue
 | ) |  |

Set the external interrupt sensitivity of the selected port.

Warning:
  • The modification of external interrupt sensitivity is only possible when the interrupts are disabled.
  • The normal behavior is to disable the interrupts before calling this function, and re-enable them after.
Parameters:
Port | The port number to access.
SensitivityValue | The external interrupt sensitivity value to set.
Return values:
None
Required preconditions:
Global interrupts must be disabled before calling this function.

Definition at line 64 of file stm8s_exti.c.

References EXTI, EXTI_CR1_PAIS, EXTI_CR1_PBIS, EXTI_CR1_PCIS, EXTI_CR1_PDIS, EXTI_CR2_PEIS, EXTI_PORT_GPIOA, EXTI_PORT_GPIOB, EXTI_PORT_GPIOC, EXTI_PORT_GPIOD, EXTI_PORT_GPIOE, IS_EXTI_PORT_OK, and IS_EXTI_SENSITIVITY_OK.

void EXTI_SetTLISensitivity ( EXTI_TLISensitivity_TypeDef SensitivityValue )

Set the TLI interrupt sensitivity.

Parameters:
SensitivityValue The TLI interrupt sensitivity value.
Return values:
None
Required preconditions:
Global interrupts must be disabled before calling this function.

Definition at line 106 of file stm8s_exti.c.

References EXTI, EXTI_CR2_TLIS, and IS_EXTI_TLISENSITIVITY_OK.


STM8S/A Standard Peripherals Drivers: FLASH_Public_functions

Functions

FLASH_Public_functions

STM8S_StdPeriph_Driver

Functions

void | FLASH_DeInit (void)
Deinitializes the FLASH registers to their default reset values.
void | FLASH_EraseByte (uint32_t Address)
Erases one byte in the program or data EEPROM memory.
void | FLASH_EraseOptionByte (uint16_t Address)
Erases option byte.
uint32_t | FLASH_GetBootSize (void)
Returns the Boot memory size in bytes.
FlagStatus | FLASH_GetFlagStatus (FLASH_Flag_TypeDef FLASH_FLAG)
Checks whether the specified SPI flag is set or not.
FLASH_LPMode_TypeDef | FLASH_GetLowPowerMode (void)
Returns the Flash behaviour type in low power mode.
FLASH_ProgramTime_TypeDef | FLASH_GetProgrammingTime (void)
Returns the fixed programming time.
void | FLASH_ITConfig (FunctionalState NewState)
Enables or Disables the Flash interrupt mode.
void | FLASH_Lock (FLASH_MemType_TypeDef FLASH_MemType)
Locks the program or data EEPROM memory.
void | FLASH_ProgramByte (uint32_t Address, uint8_t Data)
Programs one byte in program or data EEPROM memory.
void | FLASH_ProgramOptionByte (uint16_t Address, uint8_t Data)
Programs option byte.
void | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs one word (4 bytes) in program or data EEPROM memory.
uint8_t | FLASH_ReadByte (uint32_t Address)
Reads any byte from flash memory.
uint16_t | FLASH_ReadOptionByte (uint16_t Address)
Reads one option byte.
void | FLASH_SetLowPowerMode (FLASH_LPMode_TypeDef FLASH_LPMode)
Select the Flash behaviour in low power mode.
void | FLASH_SetProgrammingTime (FLASH_ProgramTime_TypeDef FLASH_ProgTime)
Sets the fixed programming time.
void | FLASH_Unlock (FLASH_MemType_TypeDef FLASH_MemType)
Unlocks the program or data EEPROM memory.

Function Documentation

void FLASH_DeInit ( void )

Deinitializes the FLASH registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 120 of file stm8s_flash.c.

References FLASH, FLASH_CR1_RESET_VALUE, FLASH_CR2_RESET_VALUE, FLASH_IAPSR_DUL, FLASH_IAPSR_PUL, and FLASH_NCR2_RESET_VALUE.

void FLASH_EraseByte ( uint32_t Address )

Erases one byte in the program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address : Address of the byte to erase
Return values:
None

Definition at line 158 of file stm8s_flash.c.

References FLASH_CLEAR_BYTE, IS_FLASH_ADDRESS_OK, and PointerAttr.

void FLASH_EraseOptionByte ( uint16_t Address )

Erases option byte.

Parameters:
Address : Option byte address to erase
Return values:
None

Definition at line 265 of file stm8s_flash.c.

References FLASH, FLASH_CLEAR_BYTE, FLASH_CR2_OPT, FLASH_MEMTYPE_PROG, FLASH_NCR2_NOPT, FLASH_SET_BYTE, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

uint32_t FLASH_GetBootSize ( void )

Returns the Boot memory size in bytes.

Parameters:
None
Return values:
Boot memory size in bytes

Definition at line 387 of file stm8s_flash.c.

References FLASH.

FlagStatus FLASH_GetFlagStatus ( FLASH_Flag_TypeDef FLASH_FLAG )

Checks whether the specified SPI flag is set or not.

Parameters:
FLASH_FLAG : Specifies the flag to check. This parameter can be any of the FLASH_Flag_TypeDef enumeration.
Return values:
FlagStatus : Indicates the state of FLASH_FLAG. This parameter can be any of the FlagStatus enumeration.
Note:
This function can clear the EOP, WR_PG_DIS flags in the IAPSR register.

Definition at line 412 of file stm8s_flash.c.

References FLASH, IS_FLASH_FLAGS_OK, RESET, and SET.

FLASH_LPMode_TypeDef FLASH_GetLowPowerMode ( void )

Returns the Flash behaviour type in low power mode.

Parameters:
None
Return values:
FLASH_LPMode_TypeDef Flash behaviour type in low power mode

Definition at line 367 of file stm8s_flash.c.

References FLASH, FLASH_CR1_AHALT, and FLASH_CR1_HALT.

FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime ( void )

Returns the fixed programming time.

Parameters:
None
Return values:
FLASH_ProgramTime_TypeDef Fixed programming time value

Definition at line 377 of file stm8s_flash.c.

References FLASH, and FLASH_CR1_FIX.

void FLASH_ITConfig ( FunctionalState NewState )

Enables or Disables the Flash interrupt mode.

Parameters:
NewState : The new state of the flash interrupt mode This parameter can be a value of FunctionalState enumeration.
Return values:
None

Definition at line 136 of file stm8s_flash.c.

References DISABLE, FLASH, FLASH_CR1_IE, and IS_FUNCTIONALSTATE_OK.

void FLASH_Lock ( FLASH_MemType_TypeDef FLASH_MemType )

Locks the program or data EEPROM memory.

Parameters:
FLASH_MemType : Memory type This parameter can be a value of FLASH_MemType_TypeDef
Return values:
None

Definition at line 106 of file stm8s_flash.c.

References FLASH, and IS_MEMORY_TYPE_OK.

void FLASH_ProgramByte | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  |

Programs one byte in program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address | : Address where the byte will be programmed
Data | : Value to be programmed
Return values:
None

Definition at line 176 of file stm8s_flash.c.

References IS_FLASH_ADDRESS_OK, and PointerAttr.

void FLASH_ProgramOptionByte | ( | uint16_t | Address,
 |  | uint8_t | Data
 | ) |  |

Programs option byte.

Parameters:
Address | : option byte address to program
Data | : Value to write
Return values:
None

Definition at line 232 of file stm8s_flash.c.

References FLASH, FLASH_CR2_OPT, FLASH_MEMTYPE_PROG, FLASH_NCR2_NOPT, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

void FLASH_ProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs one word (4 bytes) in program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address | : The address where the data will be programmed
Data | : Value to be programmed
Return values:
None

Definition at line 207 of file stm8s_flash.c.

References FLASH, FLASH_CR2_WPRG, FLASH_NCR2_NWPRG, IS_FLASH_ADDRESS_OK, and PointerAttr.

uint8_t FLASH_ReadByte ( uint32_t Address )

Reads any byte from flash memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address : Address to read
Return values:
Value of the byte

Definition at line 190 of file stm8s_flash.c.

References IS_FLASH_ADDRESS_OK, and PointerAttr.

uint16_t FLASH_ReadOptionByte ( uint16_t Address )

Reads one option byte.

Parameters:
Address option byte address to read.
Return values:
Option byte read value + its complement

Definition at line 297 of file stm8s_flash.c.

References FLASH_OPTIONBYTE_ERROR, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

void FLASH_SetLowPowerMode ( FLASH_LPMode_TypeDef FLASH_LPMode )

Select the Flash behaviour in low power mode.

Parameters:
FLASH_LPMode Low power mode selection This parameter can be any of the FLASH_LPMode_TypeDef values.
Return values:
None

Definition at line 335 of file stm8s_flash.c.

References FLASH, FLASH_CR1_AHALT, FLASH_CR1_HALT, and IS_FLASH_LOW_POWER_MODE_OK.

void FLASH_SetProgrammingTime ( FLASH_ProgramTime_TypeDef FLASH_ProgTime )

Sets the fixed programming time.

Parameters:
FLASH_ProgTime Indicates the programming time to be fixed This parameter can be any of the FLASH_ProgramTime_TypeDef values.
Return values:
None

Definition at line 353 of file stm8s_flash.c.

References FLASH, FLASH_CR1_FIX, and IS_FLASH_PROGRAM_TIME_OK.

void FLASH_Unlock ( FLASH_MemType_TypeDef FLASH_MemType )

Unlocks the program or data EEPROM memory.

Parameters:
FLASH_MemType : Memory type to unlock This parameter can be a value of FLASH_MemType_TypeDef
Return values:
None

Definition at line 81 of file stm8s_flash.c.

References FLASH, FLASH_MEMTYPE_PROG, FLASH_RASS_KEY1, FLASH_RASS_KEY2, and IS_MEMORY_TYPE_OK.


STM8S/A Standard Peripherals Drivers: GPIO_Public_Functions

Functions

GPIO_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ExternalPullUpConfig (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
Configures the external pull-up on GPIOx pins.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
Initializes the GPIOx according to the specified parameters.
uint8_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
BitStatus | GPIO_ReadInputPin (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
Reads the specified GPIO input data pin.
uint8_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint8_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteHigh (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes high level to the specified GPIO pins.
void | GPIO_WriteLow (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes low level to the specified GPIO pins.
void | GPIO_WriteReverse (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes reverse level to the specified GPIO pins.

Function Documentation

void GPIO_DeInit ( GPIO_TypeDef * GPIOx )

Deinitializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: Select the GPIO peripheral number (x = A to I).
Return values:
None

Definition at line 47 of file stm8s_gpio.c.

References GPIO_struct::CR1, GPIO_struct::CR2, GPIO_struct::DDR, GPIO_CR1_RESET_VALUE, GPIO_CR2_RESET_VALUE, GPIO_DDR_RESET_VALUE, GPIO_ODR_RESET_VALUE, and GPIO_struct::ODR.

void GPIO_ExternalPullUpConfig | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin,
 |  | FunctionalState | NewState
 | ) |  |

Configures the external pull-up on GPIOx pins.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : Specifies the pin number
NewState | : The new state of the pull up pin.
Return values:
None

Definition at line 219 of file stm8s_gpio.c.

References GPIO_struct::CR1, DISABLE, IS_FUNCTIONALSTATE_OK, and IS_GPIO_PIN_OK.

void GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin,
 |  | GPIO_Mode_TypeDef | GPIO_Mode
 | ) |  |

Initializes the GPIOx according to the specified parameters.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : This parameter contains the pin number, it can be any value of the GPIO_Pin_TypeDef enumeration.
GPIO_Mode | : This parameter can be a value of the GPIO_Mode_TypeDef enumeration.
Return values:
None

Definition at line 65 of file stm8s_gpio.c.

References GPIO_struct::CR1, GPIO_struct::CR2, GPIO_struct::DDR, IS_GPIO_MODE_OK, IS_GPIO_PIN_OK, and GPIO_struct::ODR.

uint8_t GPIO_ReadInputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO input data port.

Note:
The port must be configured in input mode.
Parameters:
GPIOx : Select the GPIO peripheral number (x = A to I).
Return values:
GPIO input data port value.

Definition at line 196 of file stm8s_gpio.c.

References GPIO_struct::IDR.

BitStatus GPIO_ReadInputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin
 | ) |  |

Reads the specified GPIO input data pin.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : Specifies the pin number.
Return values:
BitStatus : GPIO input pin status.

Definition at line 207 of file stm8s_gpio.c.

References GPIO_struct::IDR.

uint8_t GPIO_ReadOutputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO output data port.

Note:
The port must be configured in input mode.
Parameters:
GPIOx : Select the GPIO peripheral number (x = A to I).
Return values:
GPIO output data port value.

Definition at line 185 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_Write | ( | GPIO_TypeDef * | GPIOx,
 |  | uint8_t | PortVal
 | ) |  |

Writes data to the specified GPIO data port.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_PortVal | : Specifies the value to be written to the port output data register.
Return values:
None

Definition at line 135 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteHigh | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes high level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be turned high to the port output. data register.
Return values:
None

Definition at line 148 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteLow | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes low level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be turned low to the port output. data register.
Return values:
None

Definition at line 161 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteReverse | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes reverse level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be reversed to the port output. data register.
Return values:
None

Definition at line 174 of file stm8s_gpio.c.

References GPIO_struct::ODR.


STM8S/A Standard Peripherals Drivers: I2C_Public_Functions

Functions

I2C_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | I2C_AcknowledgeConfig (I2C_Ack_TypeDef Ack)
Enable or Disable the I2C acknowledge and position acknowledge feature.
ErrorStatus | I2C_CheckEvent (I2C_Event_TypeDef I2C_Event)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_Flag_TypeDef I2C_FLAG)
Clear flags.
void | I2C_ClearITPendingBit (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Clear IT pending bit.
void | I2C_Cmd (FunctionalState NewState)
Enables or disables the I2C peripheral.
void | I2C_DeInit (void)
Deinitializes the I2C peripheral registers to their default reset values.
void | I2C_FastModeDutyCycleConfig (I2C_DutyCycle_TypeDef I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (FunctionalState NewState)
Enables or disables the I2C General Call feature.
void | I2C_GenerateSTART (FunctionalState NewState)
Generates I2C communication START condition.
void | I2C_GenerateSTOP (FunctionalState NewState)
Generates I2C communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_Flag_TypeDef I2C_Flag)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Checks whether the specified I2C interrupt has occurred or not.
I2C_Event_TypeDef | I2C_GetLastEvent (void)
2) Advanced state monitoring
void | I2C_Init (uint32_t OutputClockFrequencyHz, uint16_t OwnAddress, I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack, I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz)
Initializes the I2C according to the specified parameters in standard or fast mode.
void | I2C_ITConfig (I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupt.
uint8_t | I2C_ReceiveData (void)
Returns the most recent received data.
void | I2C_Send7bitAddress (uint8_t Address, I2C_Direction_TypeDef Direction)
Transmits the 7-bit address (to select the) slave device.
void | I2C_SendData (uint8_t Data)
Send a byte by writing in the DR register.
void | I2C_SoftwareResetCmd (FunctionalState NewState)
Enables or disables I2C software reset.
void | I2C_StretchClockCmd (FunctionalState NewState)
Enables or disables the I2C clock stretching.

Function Documentation

void I2C_AcknowledgeConfig ( I2C_Ack_TypeDef Ack )

Enable or Disable the I2C acknowledge and position acknowledge feature.

Note:
This function must be called before data reception start
Parameters:
Ack : Specifies the acknowledge mode to apply. This parameter can be any of the I2C_Ack_TypeDef enumeration.
Return values:
None

Definition at line 343 of file stm8s_i2c.c.

References I2C, I2C_ACK_CURR, I2C_ACK_NONE, I2C_CR2_ACK, I2C_CR2_POS, and IS_I2C_ACK_OK.

Referenced by I2C_Init().

ErrorStatus I2C_CheckEvent ( I2C_Event_TypeDef I2C_Event )

I2C State Monitoring Functions.

This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints:

1) Basic state monitoring: Using I2C_CheckEvent() function: It compares the status registers (SR1, SR2 and SR3) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status.

  • When to use:
    • This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0016).
    • It is also suitable for users who need to define their own events.
  • Limitations:
    • If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler.
Note:
For error management, it is advised to use the following functions:
  • I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  • I2C_IRQHandler() which is called when the I2C interurpts occur.
  • I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2C_IRQHandler() function in order to determine which error occured.
  • I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status.

2) Advanced state monitoring: Using the function I2C_GetLastEvent() which returns the image of both SR1 & SR3 status registers in a single word (uint16_t) (Status Register 3 value is shifted left by 8 bits and concatenated to Status Register 1).

  • When to use:
    • This function is suitable for the same applications above but it allows to overcome the limitations of I2C_GetFlagStatus() function (see below). The returned value could be compared to events already defined in the library (stm8s_i2c.h) or to custom values defined by user.
    • This function is suitable when multiple flags are monitored at the same time.
    • At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function).
  • Limitations:
    • User may need to define his own events.
    • Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags).

3) Flag-based state monitoring: Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...).

  • When to use:
    • This function could be used for specific applications or in debug phase.
    • It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags).
  • Limitations:
    • When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones.
    • Function may need to be called twice or more in order to monitor one single event.

For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.

1) Basic state monitoring Checks whether the last I2C Event is equal to the one passed as parameter.

Parameters:
I2C_EVENT,: specifies the event to be checked. This parameter can be one of the following values:

  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
  • I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
  • I2C_EVENT_SLAVE_STOP_DETECTED : EV4
  • I2C_EVENT_MASTER_MODE_SELECT : EV5
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
Note:
: For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Last event is equal to the I2C_EVENT
  • ERROR: Last event is different from the I2C_EVENT

Definition at line 579 of file stm8s_i2c.c.

References __IO, ERROR, I2C, I2C_EVENT_SLAVE_ACK_FAILURE, I2C_SR2_AF, IS_I2C_EVENT_OK, and SUCCESS.

void I2C_ClearFlag ( I2C_Flag_TypeDef I2C_FLAG )

Clear flags.

Parameters:
I2C_Flag : Specifies the flag to clear This parameter can be any combination of the following values:

  • I2C_FLAG_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_FLAG_BUSERROR: Bus error flag.
Note:
Notes:
  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_CR2 register.
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the second byte of the address in DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to I2C_SR3 register ((void)(I2C->SR3)).
  • SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 760 of file stm8s_i2c.c.

References FLAG_Mask, I2C, and IS_I2C_CLEAR_FLAG_OK.

void I2C_ClearITPendingBit ( I2C_ITPendingBit_TypeDef I2C_ITPendingBit )

Clear IT pending bit.

Parameters:
I2C_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun interrupt (Slave mode)
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure interrupt
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost interrupt (Master mode)
  • I2C_ITPENDINGBIT_BUSERROR: Bus error interrupt

Notes:

  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_CR2 register (I2C_AcknowledgeConfig() to configure the I2C peripheral Acknowledge).
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second byte of the address in I2C_DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to I2C_SR3 register ((void)(I2C->SR3)).
  • SB (Start Bit) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
    Return values:
    None

Definition at line 873 of file stm8s_i2c.c.

References FLAG_Mask, I2C, and IS_I2C_CLEAR_ITPENDINGBIT_OK.

void I2C_Cmd ( FunctionalState NewState )

Enables or disables the I2C peripheral.

Parameters:
NewState : Indicate the new I2C peripheral state. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 196 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_PE, and IS_FUNCTIONALSTATE_OK.

void I2C_DeInit ( void )

Deinitializes the I2C peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 61 of file stm8s_i2c.c.

References I2C, I2C_CCRH_RESET_VALUE, I2C_CCRL_RESET_VALUE, I2C_CR1_RESET_VALUE, I2C_CR2_RESET_VALUE, I2C_FREQR_RESET_VALUE, I2C_ITR_RESET_VALUE, I2C_OARH_RESET_VALUE, I2C_OARL_RESET_VALUE, and I2C_TRISER_RESET_VALUE.

void I2C_FastModeDutyCycleConfig ( I2C_DutyCycle_TypeDef I2C_DutyCycle )

Selects the specified I2C fast mode duty cycle.

Parameters:
I2C_DutyCycle : Specifies the duty cycle to apply. This parameter can be any of the I2C_DutyCycle_TypeDef enumeration.
Return values:
None

Definition at line 405 of file stm8s_i2c.c.

References I2C, I2C_CCRH_DUTY, I2C_DUTYCYCLE_16_9, and IS_I2C_DUTYCYCLE_OK.

void I2C_GeneralCallCmd ( FunctionalState NewState )

Enables or disables the I2C General Call feature.

Parameters:
NewState : State of the General Call feature. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 220 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_ENGC, and IS_FUNCTIONALSTATE_OK.

void I2C_GenerateSTART ( FunctionalState NewState )

Generates I2C communication START condition.

Note:
CCR must be programmed, i.e. I2C_Init function must have been called with a valid I2C_ClockSpeed
Parameters:
NewState : Enable or disable the start condition. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 246 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_START, and IS_FUNCTIONALSTATE_OK.

void I2C_GenerateSTOP ( FunctionalState NewState )

Generates I2C communication STOP condition.

Parameters:
NewState : Enable or disable the stop condition. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 270 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_STOP, and IS_FUNCTIONALSTATE_OK.

FlagStatus I2C_GetFlagStatus ( I2C_Flag_TypeDef I2C_Flag )

3) Flag-based state monitoring

Checks whether the specified I2C flag is set or not.

Parameters:
I2C_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • I2C_FLAG_GENERALCALL: General call header flag (Slave mode)
  • I2C_FLAG_TRANSMITTERRECEIVER: Transmitter/Receiver flag
  • I2C_FLAG_BUSBUSY: Bus busy flag
  • I2C_FLAG_MASTERSLAVE: Master/Slave flag
  • I2C_FLAG_WAKEUPFROMHALT: Wake up from HALT flag
  • I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_FLAG_BUSERROR: Bus error flag
  • I2C_FLAG_TXEMPTY: Data register empty flag (Transmitter)
  • I2C_FLAG_RXNOTEMPTY: Data register not empty (Receiver) flag
  • I2C_FLAG_STOPDETECTION: Stop detection flag (Slave mode)
  • I2C_FLAG_HEADERSENT: 10-bit header sent flag (Master mode)
  • I2C_FLAG_TRANSFERFINISHED: Byte transfer finished flag
  • I2C_FLAG_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL” Address matched flag (Slave mode)”ENDAD”
  • I2C_FLAG_STARTDETECTION: Start bit flag (Master mode)
Return values:
The new state of I2C_FLAG (SET or RESET).

Definition at line 680 of file stm8s_i2c.c.

References I2C, IS_I2C_FLAG_OK, RESET, and SET.

ITStatus I2C_GetITStatus ( I2C_ITPendingBit_TypeDef I2C_ITPendingBit )

Checks whether the specified I2C interrupt has occurred or not.

Parameters:
I2C_ITPendingBit,: specifies the interrupt source to check. This parameter can be one of the following values:

  • I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_ITPENDINGBIT_BUSERROR: Bus error flag
  • I2C_ITPENDINGBIT_TXEMPTY: Data register empty flag (Transmitter)
  • I2C_ITPENDINGBIT_RXNOTEMPTY: Data register not empty (Receiver) flag
  • I2C_ITPENDINGBIT_STOPDETECTION: Stop detection flag (Slave mode)
  • I2C_ITPENDINGBIT_HEADERSENT: 10-bit header sent flag (Master mode)
  • I2C_ITPENDINGBIT_TRANSFERFINISHED: Byte transfer finished flag
  • I2C_ITPENDINGBIT_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL” Address matched flag (Slave mode)“ENDAD”
  • I2C_ITPENDINGBIT_STARTDETECTION: Start bit flag (Master mode)
Return values:
The new state of I2C_ITPendingBit This parameter can be any of the ITStatus enumeration.

Definition at line 792 of file stm8s_i2c.c.

References __IO, I2C, IS_I2C_ITPENDINGBIT_OK, ITEN_Mask, REGISTER_Mask, REGISTER_SR1_Index, RESET, and SET.

I2C_Event_TypeDef I2C_GetLastEvent ( void )

2) Advanced state monitoring

Returns the last I2C Event.

Note:
: For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.
Return values:
The last event This parameter can be any of the I2C_Event_TypeDef enumeration.

Definition at line 629 of file stm8s_i2c.c.

References __IO, I2C, I2C_EVENT_SLAVE_ACK_FAILURE, and I2C_SR2_AF.

void I2C_Init | ( | uint32_t | OutputClockFrequencyHz,
 |  | uint16_t | OwnAddress,
 |  | I2C_DutyCycle_TypeDef | I2C_DutyCycle,
 |  | I2C_Ack_TypeDef | Ack,
 |  | I2C_AddMode_TypeDef | AddMode,
 |  | uint8_t | InputClockFrequencyMHz
 | ) |  |

Initializes the I2C according to the specified parameters in standard or fast mode.

Parameters:
OutputClockFrequencyHz | : Specifies the output clock frequency in Hz.
OwnAddress | : Specifies the own address.
I2C_DutyCycle | : Specifies the duty cycle to apply in fast mode. This parameter can be any of the I2C_DutyCycle_TypeDef enumeration.
Note:
This parameter don't have impact when the OutputClockFrequency lower than 100KHz.
Parameters:
Ack | : Specifies the acknowledge mode to apply. This parameter can be any of the I2C_Ack_TypeDef enumeration.
AddMode | : Specifies the acknowledge address to apply. This parameter can be any of the I2C_AddMode_TypeDef enumeration.
InputClockFrequencyMHz | : Specifies the input clock frequency in MHz.
Return values:
None

Definition at line 90 of file stm8s_i2c.c.

References I2C, I2C_AcknowledgeConfig(), I2C_CCRH_CCR, I2C_CCRH_DUTY, I2C_CCRH_FS, I2C_CCRL_CCR, I2C_CR1_PE, I2C_DUTYCYCLE_2, I2C_FREQR_FREQ, I2C_MAX_STANDARD_FREQ, I2C_OARH_ADDCONF, IS_I2C_ACK_OK, IS_I2C_ADDMODE_OK, IS_I2C_DUTYCYCLE_OK, IS_I2C_INPUT_CLOCK_FREQ_OK, IS_I2C_OUTPUT_CLOCK_FREQ_OK, and IS_I2C_OWN_ADDRESS_OK.

void I2C_ITConfig | ( | I2C_IT_TypeDef | I2C_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C interrupt.

Parameters:
ITName | : Name of the interrupt to enable or disable. This parameter can be any of the I2C_IT_TypeDef enumeration.
NewState | : State of the interrupt to apply. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 380 of file stm8s_i2c.c.

References DISABLE, I2C, IS_FUNCTIONALSTATE_OK, and IS_I2C_INTERRUPT_OK.

uint8_t I2C_ReceiveData ( void )

Returns the most recent received data.

Parameters:
None
Return values:
uint8_t : The value of the received byte data.

Definition at line 428 of file stm8s_i2c.c.

References I2C.

void I2C_Send7bitAddress | ( | uint8_t | Address,
 |  | I2C_Direction_TypeDef | Direction
 | ) |  |

Transmits the 7-bit address (to select the) slave device.

Parameters:
Address | : Specifies the slave address which will be transmitted.
Direction | : Specifies whether the I2C device will be a Transmitter or a Receiver. This parameter can be any of the I2C_Direction_TypeDef enumeration.
Return values:
None

Definition at line 441 of file stm8s_i2c.c.

References I2C, IS_I2C_ADDRESS_OK, and IS_I2C_DIRECTION_OK.

void I2C_SendData ( uint8_t Data )

Send a byte by writing in the DR register.

Parameters:
Data : Byte to be sent.
Return values:
None

Definition at line 459 of file stm8s_i2c.c.

References I2C.

void I2C_SoftwareResetCmd ( FunctionalState NewState )

Enables or disables I2C software reset.

Parameters:
NewState : Specifies the new state of the I2C software reset. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 294 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_SWRST, and IS_FUNCTIONALSTATE_OK.

void I2C_StretchClockCmd ( FunctionalState NewState )

Enables or disables the I2C clock stretching.

Parameters:
NewState : Specifies the new state of the I2C Clock stretching. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 318 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_NOSTRETCH, and IS_FUNCTIONALSTATE_OK.


STM8S/A Standard Peripherals Drivers: ITC_Private_Functions

Functions

ITC_Private_Functions

STM8S_StdPeriph_Driver

Functions

uint8_t ITC_GetCPUCC (void)
Utility function used to read CC register.

Function Documentation

uint8_t ITC_GetCPUCC ( void )

Utility function used to read CC register.

Parameters:
None
Return values:
CPU CC register value

Definition at line 44 of file stm8s_itc.c.

Referenced by ITC_GetSoftIntStatus().


STM8S/A Standard Peripherals Drivers: ITC_Public_Functions

Functions

ITC_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | ITC_DeInit (void)
Deinitializes the ITC registers to their default reset value.
uint8_t | ITC_GetSoftIntStatus (void)
Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
ITC_PriorityLevel_TypeDef | ITC_GetSoftwarePriority (ITC_Irq_TypeDef IrqNum)
Gets the software priority of the specified interrupt source.
void | ITC_SetSoftwarePriority (ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
Sets the software priority of the specified interrupt source.

Function Documentation

void ITC_DeInit ( void )

Deinitializes the ITC registers to their default reset value.

Parameters:
None
Return values:
None

Definition at line 74 of file stm8s_itc.c.

References ITC, and ITC_SPRX_RESET_VALUE.

uint8_t ITC_GetSoftIntStatus ( void )

Gets the interrupt software priority bits (I1, I0) value from CPU CC register.

Parameters:
None
Return values:
The interrupt software priority bits value.

Definition at line 91 of file stm8s_itc.c.

References CPU_CC_I1I0, and ITC_GetCPUCC().

ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority ( ITC_Irq_TypeDef IrqNum )

Gets the software priority of the specified interrupt source.

Parameters:
IrqNum : Specifies the peripheral interrupt source.
Return values:
ITC_PriorityLevel_TypeDef : Specifies the software priority of the interrupt source.

Definition at line 101 of file stm8s_itc.c.

References IS_ITC_IRQ_OK, ITC, ITC_IRQ_AWU, ITC_IRQ_CLK, ITC_IRQ_EEPROM_EEC, ITC_IRQ_I2C, ITC_IRQ_PORTA, ITC_IRQ_PORTB, ITC_IRQ_PORTC, ITC_IRQ_PORTD, ITC_IRQ_PORTE, ITC_IRQ_SPI, ITC_IRQ_TIM1_CAPCOM, ITC_IRQ_TIM1_OVF, ITC_IRQ_TIM2_CAPCOM, ITC_IRQ_TIM2_OVF, ITC_IRQ_TIM3_CAPCOM, ITC_IRQ_TIM3_OVF, ITC_IRQ_TIM4_OVF, ITC_IRQ_TLI, ITC_IRQ_UART1_RX, and ITC_IRQ_UART1_TX.

void ITC_SetSoftwarePriority | ( | ITC_Irq_TypeDef | IrqNum,
 |  | ITC_PriorityLevel_TypeDef | PriorityValue
 | ) |  |

Sets the software priority of the specified interrupt source.

Note:
- The modification of the software priority is only possible when the interrupts are disabled.
  • The normal behavior is to disable the interrupt before calling this function, and re-enable it after.
  • The priority level 0 cannot be set (see product specification for more details).
Parameters:
IrqNum | : Specifies the peripheral interrupt source.
PriorityValue | : Specifies the software priority value to set, can be a value of ITC_PriorityLevel_TypeDef .
Return values:
None

Definition at line 208 of file stm8s_itc.c.

References IS_ITC_INTERRUPTS_DISABLED, IS_ITC_IRQ_OK, IS_ITC_PRIORITY_OK, ITC, ITC_IRQ_AWU, ITC_IRQ_CLK, ITC_IRQ_EEPROM_EEC, ITC_IRQ_I2C, ITC_IRQ_PORTA, ITC_IRQ_PORTB, ITC_IRQ_PORTC, ITC_IRQ_PORTD, ITC_IRQ_PORTE, ITC_IRQ_SPI, ITC_IRQ_TIM1_CAPCOM, ITC_IRQ_TIM1_OVF, ITC_IRQ_TIM2_CAPCOM, ITC_IRQ_TIM2_OVF, ITC_IRQ_TIM3_CAPCOM, ITC_IRQ_TIM3_OVF, ITC_IRQ_TIM4_OVF, ITC_IRQ_TLI, ITC_IRQ_UART1_RX, and ITC_IRQ_UART1_TX.


STM8S/A Standard Peripherals Drivers: RST_Public_Functions

Functions

RST_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | RST_ClearFlag (RST_Flag_TypeDef RST_Flag)
Clears the specified RST flag.
FlagStatus | RST_GetFlagStatus (RST_Flag_TypeDef RST_Flag)
Checks whether the specified RST flag is set or not.

Function Documentation

void RST_ClearFlag ( RST_Flag_TypeDef RST_Flag )

Clears the specified RST flag.

Parameters:
RST_Flag : specify the reset flag to clear. This parameter can be a value of RST_FLAG_TypeDef.
Return values:
None

Definition at line 64 of file stm8s_rst.c.

References IS_RST_FLAG_OK, and RST.

FlagStatus RST_GetFlagStatus ( RST_Flag_TypeDef RST_Flag )

Checks whether the specified RST flag is set or not.

Parameters:
RST_Flag : specify the reset flag to check. This parameter can be a value of RST_FLAG_TypeDef.
Return values:
FlagStatus,: status of the given RST flag.

Definition at line 48 of file stm8s_rst.c.

References IS_RST_FLAG_OK, and RST.


STM8S/A Standard Peripherals Drivers: SPI_Public_Functions

Functions

SPI_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | SPI_BiDirectionalLineConfig (SPI_Direction_TypeDef SPI_Direction)
Selects the data transfer direction in bi-directional mode.
void | SPI_CalculateCRCCmd (FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_ClearFlag (SPI_Flag_TypeDef SPI_FLAG)
Clears the SPI flags.
void | SPI_ClearITPendingBit (SPI_IT_TypeDef SPI_IT)
Clears the interrupt pending bits.
void | SPI_Cmd (FunctionalState NewState)
Enables or disables the SPI peripheral.
void | SPI_DeInit (void)
Deinitializes the SPI peripheral registers to their default reset values.
uint8_t | SPI_GetCRC (SPI_CRC_TypeDef SPI_CRC)
Returns the transmit or the receive CRC register value.
uint8_t | SPI_GetCRCPolynomial (void)
Returns the CRC Polynomial register value.
FlagStatus | SPI_GetFlagStatus (SPI_Flag_TypeDef SPI_FLAG)
Checks whether the specified SPI flag is set or not.
ITStatus | SPI_GetITStatus (SPI_IT_TypeDef SPI_IT)
Checks whether the specified interrupt has occurred or not.
void | SPI_Init (SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)
Initializes the SPI according to the specified parameters.
void | SPI_ITConfig (SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
Enables or disables the specified interrupts.
void | SPI_NSSInternalSoftwareCmd (FunctionalState NewState)
Configures internally by software the NSS pin.
uint8_t | SPI_ReceiveData (void)
Returns the most recent received data by the SPI peripheral.
void | SPI_ResetCRC (void)
Reset the Rx CRCR and Tx CRCR registers.
void | SPI_SendData (uint8_t Data)
Transmits a Data through the SPI peripheral.
void | SPI_TransmitCRC (void)
Enables the transmit of the CRC value.

Function Documentation

void SPI_BiDirectionalLineConfig ( SPI_Direction_TypeDef SPI_Direction )

Selects the data transfer direction in bi-directional mode.

Parameters:
SPI_Direction Specifies the data transfer direction in bi-directional mode.
Return values:
None

Definition at line 281 of file stm8s_spi.c.

References IS_SPI_DIRECTION_OK, SPI, SPI_CR2_BDOE, and SPI_DIRECTION_RX.

void SPI_CalculateCRCCmd ( FunctionalState NewState )

Enables or disables the CRC value calculation of the transferred bytes.

Parameters:
NewState Indicates the new state of the SPI CRC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 211 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR2_CRCEN.

Referenced by SPI_ResetCRC().

void SPI_ClearFlag ( SPI_Flag_TypeDef SPI_FLAG )

Clears the SPI flags.

Parameters:
SPI_FLAG : Specifies the flag to clear. This parameter can be one of the following values:

  • SPI_FLAG_CRCERR
  • SPI_FLAG_WKUP
Note:
- OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by a read operation to SPI_SR register (SPI_GetFlagStatus()).
  • MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_GetFlagStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 339 of file stm8s_spi.c.

References IS_SPI_CLEAR_FLAGS_OK, and SPI.

void SPI_ClearITPendingBit ( SPI_IT_TypeDef SPI_IT )

Clears the interrupt pending bits.

Parameters:
SPI_IT,: Specifies the interrupt pending bit to clear. This parameter can be one of the following values:

  • SPI_IT_CRCERR
  • SPI_IT_WKUP
Note:
- OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by a read operation to SPI_SR register (SPI_GetITStatus()).
  • MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_GetITStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 404 of file stm8s_spi.c.

References IS_SPI_CLEAR_IT_OK, and SPI.

void SPI_Cmd ( FunctionalState NewState )

Enables or disables the SPI peripheral.

Parameters:
NewState New state of the SPI peripheral. This parameter can be: ENABLE or DISABLE
Return values:
None

Definition at line 113 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR1_SPE.

Referenced by SPI_ResetCRC().

void SPI_DeInit ( void )

Deinitializes the SPI peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 44 of file stm8s_spi.c.

References SPI, SPI_CR1_RESET_VALUE, SPI_CR2_RESET_VALUE, SPI_CRCPR_RESET_VALUE, SPI_ICR_RESET_VALUE, and SPI_SR_RESET_VALUE.

uint8_t SPI_GetCRC ( SPI_CRC_TypeDef SPI_CRC )

Returns the transmit or the receive CRC register value.

Parameters:
SPI_CRC Specifies the CRC register to be read.
Return values:
The selected CRC register value.

Definition at line 231 of file stm8s_spi.c.

References IS_SPI_CRC_OK, SPI, and SPI_CRC_RX.

uint8_t SPI_GetCRCPolynomial ( void )

Returns the CRC Polynomial register value.

Parameters:
None
Return values:
The CRC Polynomial register value.

Definition at line 271 of file stm8s_spi.c.

References SPI.

FlagStatus SPI_GetFlagStatus ( SPI_Flag_TypeDef SPI_FLAG )

Checks whether the specified SPI flag is set or not.

Parameters:
SPI_FLAG : Specifies the flag to check. This parameter can be any of the SPI_FLAG_TypeDef enumeration.
Return values:
FlagStatus : Indicates the state of SPI_FLAG. This parameter can be any of the FlagStatus enumeration.

Definition at line 304 of file stm8s_spi.c.

References IS_SPI_FLAGS_OK, RESET, SET, and SPI.

ITStatus SPI_GetITStatus ( SPI_IT_TypeDef SPI_IT )

Checks whether the specified interrupt has occurred or not.

Parameters:
SPI_IT,: Specifies the SPI interrupt pending bit to check. This parameter can be one of the following values:

  • SPI_IT_CRCERR
  • SPI_IT_WKUP
  • SPI_IT_OVR
  • SPI_IT_MODF
  • SPI_IT_RXNE
  • SPI_IT_TXE
Return values:
ITStatus : Indicates the state of the SPI_IT. This parameter can be any of the ITStatus enumeration.

Definition at line 359 of file stm8s_spi.c.

References IS_SPI_GET_IT_OK, RESET, SET, and SPI.

void SPI_Init | ( | SPI_FirstBit_TypeDef | FirstBit,
 |  | SPI_BaudRatePrescaler_TypeDef | BaudRatePrescaler,
 |  | SPI_Mode_TypeDef | Mode,
 |  | SPI_ClockPolarity_TypeDef | ClockPolarity,
 |  | SPI_ClockPhase_TypeDef | ClockPhase,
 |  | SPI_DataDirection_TypeDef | Data_Direction,
 |  | SPI_NSS_TypeDef | Slave_Management,
 |  | uint8_t | CRCPolynomial
 | ) |  |

Initializes the SPI according to the specified parameters.

Parameters:
FirstBit | : This parameter can be any of the SPI_FirstBit_TypeDef enumeration.
BaudRatePrescaler | : This parameter can be any of the SPI_BaudRatePrescaler_TypeDef enumeration.
Mode | : This parameter can be any of the SPI_Mode_TypeDef enumeration.
ClockPolarity | : This parameter can be any of the SPI_ClockPolarity_TypeDef enumeration.
ClockPhase | : This parameter can be any of the SPI_ClockPhase_TypeDef enumeration.
Data_Direction | : This parameter can be any of the SPI_DataDirection_TypeDef enumeration.
Slave_Management | : This parameter can be any of the SPI_NSS_TypeDef enumeration.
CRCPolynomial | : Configures the CRC polynomial.
Return values:
None

Definition at line 72 of file stm8s_spi.c.

References IS_SPI_BAUDRATE_PRESCALER_OK, IS_SPI_CRC_POLYNOMIAL_OK, IS_SPI_DATA_DIRECTION_OK, IS_SPI_FIRSTBIT_OK, IS_SPI_MODE_OK, IS_SPI_PHASE_OK, IS_SPI_POLARITY_OK, IS_SPI_SLAVEMANAGEMENT_OK, SPI, SPI_CR2_SSI, and SPI_MODE_MASTER.

void SPI_ITConfig | ( | SPI_IT_TypeDef | SPI_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified interrupts.

Parameters:
SPI_IT Specifies the SPI interrupts sources to be enabled or disabled.
NewState,: The new state of the specified SPI interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 135 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_SPI_CONFIG_IT_OK, and SPI.

void SPI_NSSInternalSoftwareCmd ( FunctionalState NewState )

Configures internally by software the NSS pin.

Parameters:
NewState Indicates the new state of the SPI Software slave management. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 180 of file stm8s_spi.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, SPI, and SPI_CR2_SSI.

uint8_t SPI_ReceiveData ( void )

Returns the most recent received data by the SPI peripheral.

Parameters:
None
Return values:
The value of the received data.

Definition at line 169 of file stm8s_spi.c.

References SPI.

void SPI_ResetCRC ( void )

Reset the Rx CRCR and Tx CRCR registers.

Parameters:
None
Return values:
None

Definition at line 256 of file stm8s_spi.c.

References ENABLE, SPI_CalculateCRCCmd(), and SPI_Cmd().

void SPI_SendData ( uint8_t Data )

Transmits a Data through the SPI peripheral.

Parameters:
Data : Byte to be transmitted.
Return values:
None

Definition at line 159 of file stm8s_spi.c.

References SPI.

void SPI_TransmitCRC ( void )

Enables the transmit of the CRC value.

Parameters:
None
Return values:
None

Definition at line 200 of file stm8s_spi.c.

References SPI, and SPI_CR2_CRCNEXT.


STM8S/A Standard Peripherals Drivers: TIM1_Public_Functions

Functions

TIM1_Public_Functions

STM8S_StdPeriph_Driver

Functions

static void | TI1_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI3 as Input.
static void | TI4_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI4 as Input.
void | TIM1_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM1 peripheral Preload register on ARR.
void | TIM1_BDTRConfig (TIM1_OSSIState_TypeDef TIM1_OSSIState, TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime, TIM1_BreakState_TypeDef TIM1_Break, TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).
void | TIM1_CCPreloadControl (FunctionalState NewState)
Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
void | TIM1_CCxCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
void | TIM1_CCxNCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
void | TIM1_ClearFlag (TIM1_FLAG_TypeDef TIM1_FLAG)
Clears the TIM1’s pending flags.
void | TIM1_ClearITPendingBit (TIM1_IT_TypeDef TIM1_IT)
Clears the TIM1's interrupt pending bits.
void | TIM1_Cmd (FunctionalState NewState)
Enables or disables the TIM1 peripheral.
void | TIM1_CounterModeConfig (TIM1_CounterMode_TypeDef TIM1_CounterMode)
Specifies the TIM1 Counter Mode to be used.
void | TIM1_CtrlPWMOutputs (FunctionalState NewState)
Enables or disables the TIM1 peripheral Main Outputs.
void | TIM1_DeInit (void)
Deinitializes the TIM1 peripheral registers to their default reset values.
void | TIM1_EncoderInterfaceConfig (TIM1_EncoderMode_TypeDef TIM1_EncoderMode, TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
Configures the TIM1 Encoder Interface.
void | TIM1_ETRClockMode1Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode1.
void | TIM1_ETRClockMode2Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode2.
void | TIM1_ETRConfig (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External Trigger.
void | TIM1_ForcedOC1Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel1 output waveform to active or inactive level.
void | TIM1_ForcedOC2Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel2 output waveform to active or inactive level.
void | TIM1_ForcedOC3Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel3 output waveform to active or inactive level.
void | TIM1_ForcedOC4Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel4 output waveform to active or inactive level.
void | TIM1_GenerateEvent (TIM1_EventSource_TypeDef TIM1_EventSource)
Configures the TIM1 event to be generated by software.
uint16_t | TIM1_GetCapture1 (void)
Gets the TIM1 Input Capture 1 value.
uint16_t | TIM1_GetCapture2 (void)
Gets the TIM1 Input Capture 2 value.
uint16_t | TIM1_GetCapture3 (void)
Gets the TIM1 Input Capture 3 value.
uint16_t | TIM1_GetCapture4 (void)
Gets the TIM1 Input Capture 4 value.
uint16_t | TIM1_GetCounter (void)
Gets the TIM1 Counter value.
FlagStatus | TIM1_GetFlagStatus (TIM1_FLAG_TypeDef TIM1_FLAG)
Checks whether the specified TIM1 flag is set or not.
ITStatus | TIM1_GetITStatus (TIM1_IT_TypeDef TIM1_IT)
Checks whether the TIM1 interrupt has occurred or not.
uint16_t | TIM1_GetPrescaler (void)
Gets the TIM1 Prescaler value.
void | TIM1_ICInit (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Initializes the TIM1 peripheral according to the specified parameters.
void | TIM1_InternalClockConfig (void)
Configures the TIM1 internal Clock.
void | TIM1_ITConfig (TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState)
Enables or disables the specified TIM1 interrupts.
void | TIM1_OC1FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 1 Fast feature.
void | TIM1_OC1Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel1 according to the specified parameters.
void | TIM1_OC1NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 1N polarity.
void | TIM1_OC1PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 1 polarity.
void | TIM1_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR1.
void | TIM1_OC2FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 2 Fast feature.
void | TIM1_OC2Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel2 according to the specified parameters.
void | TIM1_OC2NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 2N polarity.
void | TIM1_OC2PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 2 polarity.
void | TIM1_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR2.
void | TIM1_OC3FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 3 Fast feature.
void | TIM1_OC3Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel3 according to the specified parameters.
void | TIM1_OC3NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 3N polarity.
void | TIM1_OC3PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 3 polarity.
void | TIM1_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR3.
void | TIM1_OC4FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 4 Fast feature.
void | TIM1_OC4Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
Initializes the TIM1 Channel4 according to the specified parameters.
void | TIM1_OC4PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 4 polarity.
void | TIM1_OC4PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR4.
void | TIM1_PrescalerConfig (uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
Configures the TIM1 Prescaler.
void | TIM1_PWMIConfig (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.
void | TIM1_SelectCOM (FunctionalState NewState)
Selects the TIM1 peripheral Commutation event.
void | TIM1_SelectHallSensor (FunctionalState NewState)
Enables or Disables the TIM1’s Hall sensor interface.
void | TIM1_SelectInputTrigger (TIM1_TS_TypeDef TIM1_InputTriggerSource)
Selects the TIM1 Input Trigger source.
void | TIM1_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM1 Master/Slave Mode.
void | TIM1_SelectOCxM (TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
Selects the TIM1 Output Compare Mode.
void | TIM1_SelectOnePulseMode (TIM1_OPMode_TypeDef TIM1_OPMode)
Selects the TIM1’s One Pulse Mode.
void | TIM1_SelectOutputTrigger (TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
Selects the TIM1 Trigger Output Mode.
void | TIM1_SelectSlaveMode (TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
Selects the TIM1 Slave Mode.
void | TIM1_SetAutoreload (uint16_t Autoreload)
Sets the TIM1 Autoreload Register value.
void | TIM1_SetCompare1 (uint16_t Compare1)
Sets the TIM1 Capture Compare1 Register value.
void | TIM1_SetCompare2 (uint16_t Compare2)
Sets the TIM1 Capture Compare2 Register value.
void | TIM1_SetCompare3 (uint16_t Compare3)
Sets the TIM1 Capture Compare3 Register value.
void | TIM1_SetCompare4 (uint16_t Compare4)
Sets the TIM1 Capture Compare4 Register value.
void | TIM1_SetCounter (uint16_t Counter)
Sets the TIM1 Counter Register value.
void | TIM1_SetIC1Prescaler (TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
Sets the TIM1 Input Capture 1 prescaler.
void | TIM1_SetIC2Prescaler (TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
Sets the TIM1 Input Capture 2 prescaler.
void | TIM1_SetIC3Prescaler (TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
Sets the TIM1 Input Capture 3 prescaler.
void | TIM1_SetIC4Prescaler (TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
Sets the TIM1 Input Capture 4 prescaler.
void | TIM1_TimeBaseInit (uint16_t TIM1_Prescaler, TIM1_CounterMode_TypeDef TIM1_CounterMode, uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter)
Initializes the TIM1 Time Base Unit according to the specified parameters.
void | TIM1_TIxExternalClockConfig (TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, uint8_t ICFilter)
Configures the TIM1 Trigger as External Clock.
void | TIM1_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM1 Update event.
void | TIM1_UpdateRequestConfig (TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
Selects the TIM1 Update Request Interrupt source.

Function Documentation

static void TI1_Config | ( | uint8_t | TIM1_ICPolarity,
 |  | uint8_t | TIM1_ICSelection,
 |  | uint8_t | TIM1_ICFilter
 | ) |  | [static]

Configure the TI1 as Input.

Parameters:
TIM1_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM1_ICSELECTION_DIRECTTI: TIM1 Input 1 is selected to be connected to IC1.
  • TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 1 is selected to be connected to IC2.
TIM1_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2224 of file stm8s_tim1.c.

References TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC1P, TIM1_CCMR_CCxS, TIM1_CCMR_ICxF, and TIM1_ICPOLARITY_RISING.

Referenced by TIM1_ICInit(), TIM1_PWMIConfig(), and TIM1_TIxExternalClockConfig().

static void TI2_Config | ( | uint8_t | TIM1_ICPolarity,
 |  | uint8_t | TIM1_ICSelection,
 |  | uint8_t | TIM1_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIM1_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM1_ICSELECTION_DIRECTTI: TIM1 Input 2 is selected to be connected to IC2.
  • TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 2 is selected to be connected to IC1.
TIM1_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2266 of file stm8s_tim1.c.

References TIM1, TIM1_CCER1_CC2E, TIM1_CCER1_CC2P, TIM1_CCMR_CCxS, TIM1_CCMR_ICxF, and TIM1_ICPOLARITY_RISING.

Referenced by TIM1_ICInit(), TIM1_PWMIConfig(), and TIM1_TIxExternalClockConfig().

static void TI3_Config | ( | uint8_t | TIM1_ICPolarity,
 |  | uint8_t | TIM1_ICSelection,
 |  | uint8_t | TIM1_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIM1_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM1_ICSELECTION_DIRECTTI: TIM1 Input 3 is selected to be connected to IC3.
  • TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 3 is selected to be connected to IC4.
TIM1_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2305 of file stm8s_tim1.c.

References TIM1, TIM1_CCER2_CC3E, TIM1_CCER2_CC3P, TIM1_CCMR_CCxS, TIM1_CCMR_ICxF, and TIM1_ICPOLARITY_RISING.

Referenced by TIM1_ICInit().

static void TI4_Config | ( | uint8_t | TIM1_ICPolarity,
 |  | uint8_t | TIM1_ICSelection,
 |  | uint8_t | TIM1_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIM1_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM1_ICSELECTION_DIRECTTI: TIM1 Input 4 is selected to be connected to IC4.
  • TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 4 is selected to be connected to IC3.
TIM1_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2346 of file stm8s_tim1.c.

References TIM1, TIM1_CCER2_CC4E, TIM1_CCER2_CC4P, TIM1_CCMR_CCxS, TIM1_CCMR_ICxF, and TIM1_ICPOLARITY_RISING.

Referenced by TIM1_ICInit().

void TIM1_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM1 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM1 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1157 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_ARPE.

void TIM1_BDTRConfig | ( | TIM1_OSSIState_TypeDef | TIM1_OSSIState,
 |  | TIM1_LockLevel_TypeDef | TIM1_LockLevel,
 |  | uint8_t | TIM1_DeadTime,
 |  | TIM1_BreakState_TypeDef | TIM1_Break,
 |  | TIM1_BreakPolarity_TypeDef | TIM1_BreakPolarity,
 |  | TIM1_AutomaticOutput_TypeDef | TIM1_AutomaticOutput
 | ) |  |

Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).

Parameters:
TIM1_OSSIState | specifies the OSSIS State from TIM1_OSSIState_TypeDef.
TIM1_LockLevel | specifies the lock level from TIM1_LockLevel_TypeDef.
TIM1_DeadTime | specifies the dead time value.
TIM1_Break | specifies the Break state TIM1_BreakState_TypeDef.
TIM1_BreakPolarity | specifies the Break polarity from TIM1_BreakPolarity_TypeDef.
TIM1_AutomaticOutput | specifies the Automatic Output configuration from TIM1_AutomaticOutput_TypeDef.
Return values:
None

Definition at line 387 of file stm8s_tim1.c.

References IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK, IS_TIM1_BREAK_POLARITY_OK, IS_TIM1_BREAK_STATE_OK, IS_TIM1_LOCK_LEVEL_OK, IS_TIM1_OSSI_STATE_OK, and TIM1.

void TIM1_CCPreloadControl ( FunctionalState NewState )

Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.

Parameters:
NewState new state of the Capture Compare Preload Control bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1202 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_CCPC.

void TIM1_CCxCmd | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:

  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
  • TIM1_CHANNEL_4: TIM1 Channel4
NewState specifies the TIM1 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1613 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_CHANNEL_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC2E, TIM1_CCER2_CC3E, TIM1_CCER2_CC4E, TIM1_CHANNEL_1, TIM1_CHANNEL_2, and TIM1_CHANNEL_3.

void TIM1_CCxNCmd | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:

  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
NewState specifies the TIM1 Channel CCxNE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1681 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_COMPLEMENTARY_CHANNEL_OK, TIM1, TIM1_CCER1_CC1NE, TIM1_CCER1_CC2NE, TIM1_CCER2_CC3NE, TIM1_CHANNEL_1, and TIM1_CHANNEL_2.

void TIM1_ClearFlag ( TIM1_FLAG_TypeDef TIM1_FLAG )

Clears the TIM1’s pending flags.

Parameters:
TIM1_FLAG specifies the flag to clear. This parameter can be one of the following values:

  • TIM1_FLAG_UPDATE: TIM1 update Flag
  • TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
  • TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
  • TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
  • TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
  • TIM1_FLAG_COM: TIM1 Commutation Flag
  • TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
  • TIM1_FLAG_BREAK: TIM1 Break Flag
  • TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
  • TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
  • TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
  • TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
Return values:
None.

Definition at line 2137 of file stm8s_tim1.c.

References IS_TIM1_CLEAR_FLAG_OK, and TIM1.

void TIM1_ClearITPendingBit ( TIM1_IT_TypeDef TIM1_IT )

Clears the TIM1's interrupt pending bits.

Parameters:
TIM1_IT specifies the pending bit to clear. This parameter can be one of the following values:

  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_COM: TIM1 Commutation Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
Return values:
None.

Definition at line 2199 of file stm8s_tim1.c.

References IS_TIM1_IT_OK, and TIM1.

void TIM1_Cmd ( FunctionalState NewState )

Enables or disables the TIM1 peripheral.

Parameters:
NewState new state of the TIM1 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 563 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_CEN.

void TIM1_CounterModeConfig ( TIM1_CounterMode_TypeDef TIM1_CounterMode )

Specifies the TIM1 Counter Mode to be used.

Parameters:
TIM1_CounterMode specifies the Counter Mode to be used This parameter can be one of the following values:

  • TIM1_COUNTERMODE_UP: TIM1 Up Counting Mode
  • TIM1_COUNTERMODE_DOWN: TIM1 Down Counting Mode
  • TIM1_COUNTERMODE_CENTERALIGNED1: TIM1 Center Aligned Mode1
  • TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
  • TIM1_COUNTERMODE_CENTERALIGNED3: TIM1 Center Aligned Mode3
Return values:
None

Definition at line 1061 of file stm8s_tim1.c.

References IS_TIM1_COUNTER_MODE_OK, TIM1, TIM1_CR1_CMS, and TIM1_CR1_DIR.

void TIM1_CtrlPWMOutputs ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Main Outputs.

Parameters:
NewState new state of the TIM1 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 585 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_BKR_MOE.

void TIM1_DeInit ( void )

Deinitializes the TIM1 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 52 of file stm8s_tim1.c.

References TIM1, TIM1_ARRH_RESET_VALUE, TIM1_ARRL_RESET_VALUE, TIM1_BKR_RESET_VALUE, TIM1_CCER1_RESET_VALUE, TIM1_CCER2_RESET_VALUE, TIM1_CCMR1_RESET_VALUE, TIM1_CCMR2_RESET_VALUE, TIM1_CCMR3_RESET_VALUE, TIM1_CCMR4_RESET_VALUE, TIM1_CCR1H_RESET_VALUE, TIM1_CCR1L_RESET_VALUE, TIM1_CCR2H_RESET_VALUE, TIM1_CCR2L_RESET_VALUE, TIM1_CCR3H_RESET_VALUE, TIM1_CCR3L_RESET_VALUE, TIM1_CCR4H_RESET_VALUE, TIM1_CCR4L_RESET_VALUE, TIM1_CNTRH_RESET_VALUE, TIM1_CNTRL_RESET_VALUE, TIM1_CR1_RESET_VALUE, TIM1_CR2_RESET_VALUE, TIM1_DTR_RESET_VALUE, TIM1_ETR_RESET_VALUE, TIM1_IER_RESET_VALUE, TIM1_OISR_RESET_VALUE, TIM1_PSCRH_RESET_VALUE, TIM1_PSCRL_RESET_VALUE, TIM1_RCR_RESET_VALUE, TIM1_SMCR_RESET_VALUE, TIM1_SR1_RESET_VALUE, and TIM1_SR2_RESET_VALUE.

void TIM1_EncoderInterfaceConfig | ( | TIM1_EncoderMode_TypeDef | TIM1_EncoderMode,
 |  | TIM1_ICPolarity_TypeDef | TIM1_IC1Polarity,
 |  | TIM1_ICPolarity_TypeDef | TIM1_IC2Polarity
 | ) |  |

Configures the TIM1 Encoder Interface.

Parameters:
TIM1_EncoderMode specifies the TIM1 Encoder Mode. This parameter can be one of the following values

  • TIM1_ENCODERMODE_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
  • TIM1_ENCODERMODE_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
  • TIM1_ENCODERMODE_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
TIM1_IC1Polarity specifies the IC1 Polarity. This parameter can be one of the following values

  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
TIM1_IC2Polarity specifies the IC2 Polarity. This parameter can be one of the following values

  • TIM1_ICPOLARITY_FALLING
  • TIM1_ICPOLARITY_RISING
Return values:
None

Definition at line 983 of file stm8s_tim1.c.

References CCMR_TIxDirect_Set, IS_TIM1_ENCODER_MODE_OK, IS_TIM1_IC_POLARITY_OK, TIM1, TIM1_CCER1_CC1P, TIM1_CCER1_CC2P, TIM1_CCMR_CCxS, TIM1_ICPOLARITY_RISING, TIM1_SMCR_MSM, and TIM1_SMCR_TS.

void TIM1_ETRClockMode1Config | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External clock Mode1.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:

  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:

  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 664 of file stm8s_tim1.c.

References IS_TIM1_EXT_POLARITY_OK, IS_TIM1_EXT_PRESCALER_OK, TIM1, TIM1_ETRConfig(), TIM1_SLAVEMODE_EXTERNAL1, TIM1_SMCR_SMS, TIM1_SMCR_TS, and TIM1_TS_ETRF.

void TIM1_ETRClockMode2Config | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External clock Mode2.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:

  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:

  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 696 of file stm8s_tim1.c.

References IS_TIM1_EXT_POLARITY_OK, IS_TIM1_EXT_PRESCALER_OK, TIM1, TIM1_ETR_ECE, and TIM1_ETRConfig().

void TIM1_ETRConfig | ( | TIM1_ExtTRGPSC_TypeDef | TIM1_ExtTRGPrescaler,
 |  | TIM1_ExtTRGPolarity_TypeDef | TIM1_ExtTRGPolarity,
 |  | uint8_t | ExtTRGFilter
 | ) |  |

Configures the TIM1 External Trigger.

Parameters:
TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. This parameter can be one of the following values:

  • TIM1_EXTTRGPSC_OFF
  • TIM1_EXTTRGPSC_DIV2
  • TIM1_EXTTRGPSC_DIV4
  • TIM1_EXTTRGPSC_DIV8.
TIM1_ExtTRGPolarity specifies the external Trigger Polarity. This parameter can be one of the following values:

  • TIM1_EXTTRGPOLARITY_INVERTED
  • TIM1_EXTTRGPOLARITY_NONINVERTED
ExtTRGFilter specifies the External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 727 of file stm8s_tim1.c.

References IS_TIM1_EXT_TRG_FILTER_OK, and TIM1.

Referenced by TIM1_ETRClockMode1Config(), and TIM1_ETRClockMode2Config().

void TIM1_ForcedOC1Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel1 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 1081 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC2Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel2 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 1100 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC3Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel3 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 1120 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_ForcedOC4Config ( TIM1_ForcedAction_TypeDef TIM1_ForcedAction )

Forces the TIM1 Channel4 output waveform to active or inactive level.

Parameters:
TIM1_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM1_FORCEDACTION_ACTIVE: Force active level on OC4REF
  • TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC4REF.
Return values:
None

Definition at line 1140 of file stm8s_tim1.c.

References IS_TIM1_FORCED_ACTION_OK, TIM1, and TIM1_CCMR_OCM.

void TIM1_GenerateEvent ( TIM1_EventSource_TypeDef TIM1_EventSource )

Configures the TIM1 event to be generated by software.

Parameters:
TIM1_EventSource specifies the event source. This parameter can be one of the following values:

  • TIM1_EVENTSOURCE_UPDATE: TIM1 update Event source
  • TIM1_EVENTSOURCE_CC1: TIM1 Capture Compare 1 Event source
  • TIM1_EVENTSOURCE_CC2: TIM1 Capture Compare 2 Event source
  • TIM1_EVENTSOURCE_CC3: TIM1 Capture Compare 3 Event source
  • TIM1_EVENTSOURCE_CC4: TIM1 Capture Compare 4 Event source
  • TIM1_EVENTSOURCE_COM: TIM1 COM Event source
  • TIM1_EVENTSOURCE_TRIGGER: TIM1 Trigger Event source
  • TIM1_EventSourceBreak: TIM1 Break Event source
Return values:
None

Definition at line 1418 of file stm8s_tim1.c.

References IS_TIM1_EVENT_SOURCE_OK, and TIM1.

uint16_t TIM1_GetCapture1 ( void )

Gets the TIM1 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 1972 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture2 ( void )

Gets the TIM1 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 1993 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture3 ( void )

Gets the TIM1 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 2014 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCapture4 ( void )

Gets the TIM1 Input Capture 4 value.

Parameters:
None
Return values:
Capture Compare 4 Register value.

Definition at line 2034 of file stm8s_tim1.c.

References TIM1.

uint16_t TIM1_GetCounter ( void )

Gets the TIM1 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 2054 of file stm8s_tim1.c.

References TIM1.

FlagStatus TIM1_GetFlagStatus ( TIM1_FLAG_TypeDef TIM1_FLAG )

Checks whether the specified TIM1 flag is set or not.

Parameters:
TIM1_FLAG specifies the flag to check. This parameter can be one of the following values:

  • TIM1_FLAG_UPDATE: TIM1 update Flag
  • TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
  • TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
  • TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
  • TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
  • TIM1_FLAG_COM: TIM1 Commutation Flag
  • TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
  • TIM1_FLAG_BREAK: TIM1 Break Flag
  • TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
  • TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
  • TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
  • TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
Return values:
FlagStatus The new state of TIM1_FLAG (SET or RESET).

Definition at line 2097 of file stm8s_tim1.c.

References IS_TIM1_GET_FLAG_OK, RESET, SET, and TIM1.

ITStatus TIM1_GetITStatus ( TIM1_IT_TypeDef TIM1_IT )

Checks whether the TIM1 interrupt has occurred or not.

Parameters:
TIM1_IT specifies the TIM1 interrupt source to check. This parameter can be one of the following values:

  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_COM: TIM1 Commutation Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
Return values:
ITStatus The new state of the TIM1_IT(SET or RESET).

Definition at line 2162 of file stm8s_tim1.c.

References IS_TIM1_GET_IT_OK, RESET, SET, and TIM1.

uint16_t TIM1_GetPrescaler ( void )

Gets the TIM1 Prescaler value.

Parameters:
None
Return values:
Prescaler Register value.

Definition at line 2069 of file stm8s_tim1.c.

References TIM1.

void TIM1_ICInit | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | TIM1_ICSelection_TypeDef | TIM1_ICSelection,
 |  | TIM1_ICPSC_TypeDef | TIM1_ICPrescaler,
 |  | uint8_t | TIM1_ICFilter
 | ) |  |

Initializes the TIM1 peripheral according to the specified parameters.

Parameters:
TIM1_Channel | specifies the input capture channel from TIM1_Channel_TypeDef.
TIM1_ICPolarity | specifies the Input capture polarity from TIM1_ICPolarity_TypeDef .
TIM1_ICSelection | specifies the Input capture source selection from TIM1_ICSelection_TypeDef.
TIM1_ICPrescaler | specifies the Input capture Prescaler from TIM1_ICPSC_TypeDef.
TIM1_ICFilter | specifies the Input capture filter value.
Return values:
None

Definition at line 423 of file stm8s_tim1.c.

References IS_TIM1_CHANNEL_OK, IS_TIM1_IC_FILTER_OK, IS_TIM1_IC_POLARITY_OK, IS_TIM1_IC_PRESCALER_OK, IS_TIM1_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM1_CHANNEL_1, TIM1_CHANNEL_2, TIM1_CHANNEL_3, TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), and TIM1_SetIC4Prescaler().

void TIM1_InternalClockConfig ( void )

Configures the TIM1 internal Clock.

Parameters:
None
Return values:
None

Definition at line 642 of file stm8s_tim1.c.

References TIM1, and TIM1_SMCR_SMS.

void TIM1_ITConfig | ( | TIM1_IT_TypeDef | TIM1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM1 interrupts.

Parameters:
NewState | new state of the TIM1 peripheral. This parameter can be: ENABLE or DISABLE.
TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM1_IT_UPDATE: TIM1 update Interrupt source
  • TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
  • TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
  • TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
  • TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
  • TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt source
  • TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
  • TIM1_IT_BREAK: TIM1 Break Interrupt source
NewState | new state of the TIM1 peripheral.
Return values:
None

Definition at line 619 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM1_IT_OK, and TIM1.

void TIM1_OC1FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 1 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1317 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC1Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel1 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 150 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC1NE, TIM1_CCER1_CC1NP, TIM1_CCER1_CC1P, TIM1_CCMR_OCM, TIM1_OISR_OIS1, and TIM1_OISR_OIS1N.

void TIM1_OC1NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 1N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC1N Polarity. This parameter can be one of the following values:

  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1461 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER1_CC1NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC1PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 1 polarity.

Parameters:
TIM1_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:

  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1436 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER1_CC1P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1225 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC2FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 2 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1341 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC2Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel2 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 213 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER1_CC2E, TIM1_CCER1_CC2NE, TIM1_CCER1_CC2NP, TIM1_CCER1_CC2P, TIM1_CCMR_OCM, TIM1_OISR_OIS2, and TIM1_OISR_OIS2N.

void TIM1_OC2NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 2N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC2N Polarity. This parameter can be one of the following values:

  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1510 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER1_CC2NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC2PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 2 polarity.

Parameters:
TIM1_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:

  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1486 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER1_CC2P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1248 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC3FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 3 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1364 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC3Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | TIM1_OutputNState_TypeDef | TIM1_OutputNState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCNPolarity_TypeDef | TIM1_OCNPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState,
 |  | TIM1_OCNIdleState_TypeDef | TIM1_OCNIdleState
 | ) |  |

Initializes the TIM1 Channel3 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_OutputNState | specifies the Complementary Output State from TIM1_OutputNState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCNPolarity | specifies the Complementary Output Compare Polarity from TIM1_OCNPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
TIM1_OCNIdleState | specifies the Complementary Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 278 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OCN_POLARITY_OK, IS_TIM1_OCNIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, IS_TIM1_OUTPUTN_STATE_OK, TIM1, TIM1_CCER2_CC3E, TIM1_CCER2_CC3NE, TIM1_CCER2_CC3NP, TIM1_CCER2_CC3P, TIM1_CCMR_OCM, TIM1_OISR_OIS3, and TIM1_OISR_OIS3N.

void TIM1_OC3NPolarityConfig ( TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity )

Configures the TIM1 Channel 3N polarity.

Parameters:
TIM1_OCNPolarity specifies the OC3N Polarity. This parameter can be one of the following values:

  • TIM1_OCNPOLARITY_LOW: Output Compare active low
  • TIM1_OCNPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1560 of file stm8s_tim1.c.

References IS_TIM1_OCN_POLARITY_OK, TIM1, TIM1_CCER2_CC3NP, and TIM1_OCNPOLARITY_HIGH.

void TIM1_OC3PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 3 polarity.

Parameters:
TIM1_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:

  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1535 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER2_CC3P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1271 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_OC4FastConfig ( FunctionalState NewState )

Configures the TIM1 Capture Compare 4 Fast feature.

Parameters:
NewState new state of the Output Compare Fast Enable bit. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1387 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxFE.

void TIM1_OC4Init | ( | TIM1_OCMode_TypeDef | TIM1_OCMode,
 |  | TIM1_OutputState_TypeDef | TIM1_OutputState,
 |  | uint16_t | TIM1_Pulse,
 |  | TIM1_OCPolarity_TypeDef | TIM1_OCPolarity,
 |  | TIM1_OCIdleState_TypeDef | TIM1_OCIdleState
 | ) |  |

Initializes the TIM1 Channel4 according to the specified parameters.

Parameters:
TIM1_OCMode | specifies the Output Compare mode from TIM1_OCMode_TypeDef.
TIM1_OutputState | specifies the Output State from TIM1_OutputState_TypeDef.
TIM1_Pulse | specifies the Pulse width value.
TIM1_OCPolarity | specifies the Output Compare Polarity from TIM1_OCPolarity_TypeDef.
TIM1_OCIdleState | specifies the Output Compare Idle State from TIM1_OCIdleState_TypeDef.
Return values:
None

Definition at line 336 of file stm8s_tim1.c.

References IS_TIM1_OC_MODE_OK, IS_TIM1_OC_POLARITY_OK, IS_TIM1_OCIDLE_STATE_OK, IS_TIM1_OUTPUT_STATE_OK, TIM1, TIM1_CCER2_CC4E, TIM1_CCER2_CC4P, TIM1_CCMR_OCM, TIM1_OCIDLESTATE_RESET, and TIM1_OISR_OIS4.

void TIM1_OC4PolarityConfig ( TIM1_OCPolarity_TypeDef TIM1_OCPolarity )

Configures the TIM1 Channel 4 polarity.

Parameters:
TIM1_OCPolarity specifies the OC4 Polarity. This parameter can be one of the following values:

  • TIM1_OCPOLARITY_LOW: Output Compare active low
  • TIM1_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 1584 of file stm8s_tim1.c.

References IS_TIM1_OC_POLARITY_OK, TIM1, TIM1_CCER2_CC4P, and TIM1_OCPOLARITY_HIGH.

void TIM1_OC4PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM1 peripheral Preload Register on CCR4.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1295 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CCMR_OCxPE.

void TIM1_PrescalerConfig | ( | uint16_t | Prescaler,
 |  | TIM1_PSCReloadMode_TypeDef | TIM1_PSCReloadMode
 | ) |  |

Configures the TIM1 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter must be a value between 0x0000 and 0xFFFF
TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode. This parameter can be one of the following values

  • TIM1_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM1_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 1035 of file stm8s_tim1.c.

References IS_TIM1_PRESCALER_RELOAD_OK, and TIM1.

void TIM1_PWMIConfig | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | TIM1_ICSelection_TypeDef | TIM1_ICSelection,
 |  | TIM1_ICPSC_TypeDef | TIM1_ICPrescaler,
 |  | uint8_t | TIM1_ICFilter
 | ) |  |

Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM1_Channel | specifies the input capture channel from TIM1_Channel_TypeDef.
TIM1_ICPolarity | specifies the Input capture polarity from TIM1_ICPolarity_TypeDef .
TIM1_ICSelection | specifies the Input capture source selection from TIM1_ICSelection_TypeDef.
TIM1_ICPrescaler | specifies the Input capture Prescaler from TIM1_ICPSC_TypeDef.
TIM1_ICFilter | specifies the Input capture filter value.
Return values:
None

Definition at line 490 of file stm8s_tim1.c.

References IS_TIM1_IC_POLARITY_OK, IS_TIM1_IC_PRESCALER_OK, IS_TIM1_IC_SELECTION_OK, IS_TIM1_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM1_CHANNEL_1, TIM1_ICPOLARITY_FALLING, TIM1_ICPOLARITY_RISING, TIM1_ICSELECTION_DIRECTTI, TIM1_ICSELECTION_INDIRECTTI, TIM1_SetIC1Prescaler(), and TIM1_SetIC2Prescaler().

void TIM1_SelectCOM ( FunctionalState NewState )

Selects the TIM1 peripheral Commutation event.

Parameters:
NewState new state of the Commutation event. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 1180 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_COMS.

void TIM1_SelectHallSensor ( FunctionalState NewState )

Enables or Disables the TIM1’s Hall sensor interface.

Parameters:
NewState new state of the TIM1 Hall sensor interface.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 853 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR2_TI1S.

void TIM1_SelectInputTrigger ( TIM1_TS_TypeDef TIM1_InputTriggerSource )

Selects the TIM1 Input Trigger source.

Parameters:
TIM1_InputTriggerSource specifies Input Trigger source. This parameter can be one of the following values:

  • TIM1_TS_TI1F_ED: TI1 Edge Detector
  • TIM1_TS_TI1FP1: Filtered Timer Input 1
  • TIM1_TS_TI2FP2: Filtered Timer Input 2
  • TIM1_TS_ETRF: External Trigger input
Return values:
None

Definition at line 789 of file stm8s_tim1.c.

References IS_TIM1_TRIGGER_SELECTION_OK, TIM1, and TIM1_SMCR_TS.

Referenced by TIM1_TIxExternalClockConfig().

void TIM1_SelectMasterSlaveMode ( FunctionalState NewState )

Sets or Resets the TIM1 Master/Slave Mode.

Parameters:
NewState new state of the synchronization between TIM1 and its slaves (through TRGO). This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 947 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_SMCR_MSM.

void TIM1_SelectOCxM | ( | TIM1_Channel_TypeDef | TIM1_Channel,
 |  | TIM1_OCMode_TypeDef | TIM1_OCMode
 | ) |  |

Selects the TIM1 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions.

Parameters:
TIM1_Channel specifies the TIM1 Channel. This parameter can be one of the following values:

  • TIM1_CHANNEL_1: TIM1 Channel1
  • TIM1_CHANNEL_2: TIM1 Channel2
  • TIM1_CHANNEL_3: TIM1 Channel3
  • TIM1_CHANNEL_4: TIM1 Channel4
TIM1_OCMode specifies the TIM1 Output Compare Mode. This paramter can be one of the following values:

  • TIM1_OCMODE_TIMING
  • TIM1_OCMODE_ACTIVE
  • TIM1_OCMODE_TOGGLE
  • TIM1_OCMODE_PWM1
  • TIM1_OCMODE_PWM2
  • TIM1_FORCEDACTION_ACTIVE
  • TIM1_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 1747 of file stm8s_tim1.c.

References IS_TIM1_CHANNEL_OK, IS_TIM1_OCM_OK, TIM1, TIM1_CCER1_CC1E, TIM1_CCER1_CC2E, TIM1_CCER2_CC3E, TIM1_CCER2_CC4E, TIM1_CCMR_OCM, TIM1_CHANNEL_1, TIM1_CHANNEL_2, and TIM1_CHANNEL_3.

void TIM1_SelectOnePulseMode ( TIM1_OPMode_TypeDef TIM1_OPMode )

Selects the TIM1’s One Pulse Mode.

Parameters:
TIM1_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values

  • TIM1_OPMODE_SINGLE
  • TIM1_OPMODE_REPETITIVE
Return values:
None

Definition at line 878 of file stm8s_tim1.c.

References IS_TIM1_OPM_MODE_OK, TIM1, TIM1_CR1_OPM, and TIM1_OPMODE_REPETITIVE.

void TIM1_SelectOutputTrigger ( TIM1_TRGOSource_TypeDef TIM1_TRGOSource )

Selects the TIM1 Trigger Output Mode.

Parameters:
TIM1_TRGOSource specifies the Trigger Output source. This parameter can be one of the following values

  • TIM1_TRGOSOURCE_RESET
  • TIM1_TRGOSOURCE_ENABLE
  • TIM1_TRGOSOURCE_UPDATE
  • TIM1_TRGOSource_OC1
  • TIM1_TRGOSOURCE_OC1REF
  • TIM1_TRGOSOURCE_OC2REF
  • TIM1_TRGOSOURCE_OC3REF
Return values:
None

Definition at line 909 of file stm8s_tim1.c.

References IS_TIM1_TRGO_SOURCE_OK, TIM1, and TIM1_CR2_MMS.

void TIM1_SelectSlaveMode ( TIM1_SlaveMode_TypeDef TIM1_SlaveMode )

Selects the TIM1 Slave Mode.

Parameters:
TIM1_SlaveMode specifies the TIM1 Slave Mode. This parameter can be one of the following values

  • TIM1_SLAVEMODE_RESET
  • TIM1_SLAVEMODE_GATED
  • TIM1_SLAVEMODE_TRIGGER
  • TIM1_SLAVEMODE_EXTERNAL1
Return values:
None

Definition at line 929 of file stm8s_tim1.c.

References IS_TIM1_SLAVE_MODE_OK, TIM1, and TIM1_SMCR_SMS.

void TIM1_SetAutoreload ( uint16_t Autoreload )

Sets the TIM1 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1813 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare1 ( uint16_t Compare1 )

Sets the TIM1 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1829 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare2 ( uint16_t Compare2 )

Sets the TIM1 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1844 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare3 ( uint16_t Compare3 )

Sets the TIM1 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1859 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCompare4 ( uint16_t Compare4 )

Sets the TIM1 Capture Compare4 Register value.

Parameters:
Compare4 specifies the Capture Compare4 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1874 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetCounter ( uint16_t Counter )

Sets the TIM1 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 1798 of file stm8s_tim1.c.

References TIM1.

void TIM1_SetIC1Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC1Prescaler )

Sets the TIM1 Input Capture 1 prescaler.

Parameters:
TIM1_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1892 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit(), and TIM1_PWMIConfig().

void TIM1_SetIC2Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC2Prescaler )

Sets the TIM1 Input Capture 2 prescaler.

Parameters:
TIM1_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1913 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit(), and TIM1_PWMIConfig().

void TIM1_SetIC3Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC3Prescaler )

Sets the TIM1 Input Capture 3 prescaler.

Parameters:
TIM1_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1935 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit().

void TIM1_SetIC4Prescaler ( TIM1_ICPSC_TypeDef TIM1_IC4Prescaler )

Sets the TIM1 Input Capture 4 prescaler.

Parameters:
TIM1_IC4Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM1_ICPSC_DIV1: no prescaler
  • TIM1_ICPSC_DIV2: capture is done once every 2 events
  • TIM1_ICPSC_DIV4: capture is done once every 4 events
  • TIM1_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1956 of file stm8s_tim1.c.

References IS_TIM1_IC_PRESCALER_OK, TIM1, and TIM1_CCMR_ICxPSC.

Referenced by TIM1_ICInit().

void TIM1_TimeBaseInit | ( | uint16_t | TIM1_Prescaler,
 |  | TIM1_CounterMode_TypeDef | TIM1_CounterMode,
 |  | uint16_t | TIM1_Period,
 |  | uint8_t | TIM1_RepetitionCounter
 | ) |  |

Initializes the TIM1 Time Base Unit according to the specified parameters.

Parameters:
TIM1_Prescaler | specifies the Prescaler value.
TIM1_CounterMode | specifies the counter mode from TIM1_CounterMode_TypeDef .
TIM1_Period | specifies the Period value.
TIM1_RepetitionCounter | specifies the Repetition counter value
Return values:
None

Definition at line 105 of file stm8s_tim1.c.

References IS_TIM1_COUNTER_MODE_OK, TIM1, TIM1_CR1_CMS, and TIM1_CR1_DIR.

void TIM1_TIxExternalClockConfig | ( | TIM1_TIxExternalCLK1Source_TypeDef | TIM1_TIxExternalCLKSource,
 |  | TIM1_ICPolarity_TypeDef | TIM1_ICPolarity,
 |  | uint8_t | ICFilter
 | ) |  |

Configures the TIM1 Trigger as External Clock.

Parameters:
TIM1_TIxExternalCLKSource specifies Trigger source. This parameter can be one of the following values:

  • TIM1_TIXEXTERNALCLK1SOURCE_TI1: TI1 Edge Detector
  • TIM1_TIXEXTERNALCLK1SOURCE_TI2: Filtered TIM1 Input 1
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1ED: Filtered TIM1 Input 2
TIM1_ICPolarity specifies the TIx Polarity. This parameter can be:

  • TIM1_ICPOLARITY_RISING
  • TIM1_ICPOLARITY_FALLING
ICFilter specifies the filter value. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 753 of file stm8s_tim1.c.

References IS_TIM1_IC_FILTER_OK, IS_TIM1_IC_POLARITY_OK, IS_TIM1_TIXCLK_SOURCE_OK, TI1_Config(), TI2_Config(), TIM1, TIM1_ICSELECTION_DIRECTTI, TIM1_SelectInputTrigger(), TIM1_SLAVEMODE_EXTERNAL1, and TIM1_TIXEXTERNALCLK1SOURCE_TI2.

void TIM1_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM1 Update event.

Parameters:
NewState new state of the TIM1 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 806 of file stm8s_tim1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, TIM1, and TIM1_CR1_UDIS.

void TIM1_UpdateRequestConfig ( TIM1_UpdateSource_TypeDef TIM1_UpdateSource )

Selects the TIM1 Update Request Interrupt source.

Parameters:
TIM1_UpdateSource specifies the Update source. This parameter can be one of the following values

  • TIM1_UPDATESOURCE_REGULAR
  • TIM1_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 830 of file stm8s_tim1.c.

References IS_TIM1_UPDATE_SOURCE_OK, TIM1, TIM1_CR1_URS, and TIM1_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM2_Public_Functions

Functions

TIM2_Public_Functions

STM8S_StdPeriph_Driver

Functions

static void | TI1_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI3 as Input.
void | TIM2_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM2 peripheral Preload register on ARR.
void | TIM2_CCxCmd (TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
Enables or disables the TIM2 Capture Compare Channel x.
void | TIM2_ClearFlag (TIM2_FLAG_TypeDef TIM2_FLAG)
Clears the TIM2’s pending flags.
void | TIM2_ClearITPendingBit (TIM2_IT_TypeDef TIM2_IT)
Clears the TIM2's interrupt pending bits.
void | TIM2_Cmd (FunctionalState NewState)
Enables or disables the TIM2 peripheral.
void | TIM2_DeInit (void)
Deinitializes the TIM2 peripheral registers to their default reset values.
void | TIM2_ForcedOC1Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel1 output waveform to active or inactive level.
void | TIM2_ForcedOC2Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel2 output waveform to active or inactive level.
void | TIM2_ForcedOC3Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel3 output waveform to active or inactive level.
void | TIM2_GenerateEvent (TIM2_EventSource_TypeDef TIM2_EventSource)
Configures the TIM2 event to be generated by software.
uint16_t | TIM2_GetCapture1 (void)
Gets the TIM2 Input Capture 1 value.
uint16_t | TIM2_GetCapture2 (void)
Gets the TIM2 Input Capture 2 value.
uint16_t | TIM2_GetCapture3 (void)
Gets the TIM2 Input Capture 3 value.
uint16_t | TIM2_GetCounter (void)
Gets the TIM2 Counter value.
FlagStatus | TIM2_GetFlagStatus (TIM2_FLAG_TypeDef TIM2_FLAG)
Checks whether the specified TIM2 flag is set or not.
ITStatus | TIM2_GetITStatus (TIM2_IT_TypeDef TIM2_IT)
Checks whether the TIM2 interrupt has occurred or not.
TIM2_Prescaler_TypeDef | TIM2_GetPrescaler (void)
Gets the TIM2 Prescaler value.
void | TIM2_ICInit (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Initializes the TIM2 peripheral according to the specified parameters.
void | TIM2_ITConfig (TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
Enables or disables the specified TIM2 interrupts.
void | TIM2_OC1Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel1 according to the specified parameters.
void | TIM2_OC1PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 1 polarity.
void | TIM2_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR1.
void | TIM2_OC2Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel2 according to the specified parameters.
void | TIM2_OC2PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 2 polarity.
void | TIM2_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR2.
void | TIM2_OC3Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel3 according to the specified parameters.
void | TIM2_OC3PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 3 polarity.
void | TIM2_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR3.
void | TIM2_PrescalerConfig (TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
Configures the TIM2 Prescaler.
void | TIM2_PWMIConfig (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.
void | TIM2_SelectOCxM (TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
Selects the TIM2 Output Compare Mode.
void | TIM2_SelectOnePulseMode (TIM2_OPMode_TypeDef TIM2_OPMode)
Selects the TIM2’s One Pulse Mode.
void | TIM2_SetAutoreload (uint16_t Autoreload)
Sets the TIM2 Autoreload Register value.
void | TIM2_SetCompare1 (uint16_t Compare1)
Sets the TIM2 Capture Compare1 Register value.
void | TIM2_SetCompare2 (uint16_t Compare2)
Sets the TIM2 Capture Compare2 Register value.
void | TIM2_SetCompare3 (uint16_t Compare3)
Sets the TIM2 Capture Compare3 Register value.
void | TIM2_SetCounter (uint16_t Counter)
Sets the TIM2 Counter Register value.
void | TIM2_SetIC1Prescaler (TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
Sets the TIM2 Input Capture 1 Prescaler.
void | TIM2_SetIC2Prescaler (TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
Sets the TIM2 Input Capture 2 prescaler.
void | TIM2_SetIC3Prescaler (TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
Sets the TIM2 Input Capture 3 prescaler.
void | TIM2_TimeBaseInit (TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period)
Initializes the TIM2 Time Base Unit according to the specified parameters.
void | TIM2_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM2 Update event.
void | TIM2_UpdateRequestConfig (TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
Selects the TIM2 Update Request Interrupt source.

Function Documentation

static void TI1_Config | ( | uint8_t | TIM2_ICPolarity,
 |  | uint8_t | TIM2_ICSelection,
 |  | uint8_t | TIM2_ICFilter
 | ) |  | [static]

Configure the TI1 as Input.

Parameters:
TIM2_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM2_ICPOLARITY_FALLING
  • TIM2_ICPOLARITY_RISING
TIM2_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM2_ICSELECTION_DIRECTTI: TIM2 Input 1 is selected to be connected to IC1.
  • TIM2_ICSELECTION_INDIRECTTI: TIM2 Input 1 is selected to be connected to IC2.
TIM2_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1214 of file stm8s_tim2.c.

References TIM2_CCER1_CC1E, TIM2_CCER1_CC1P, TIM2_CCMR_CCxS, TIM2_CCMR_ICxF, and TIM2_ICPOLARITY_RISING.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

static void TI2_Config | ( | uint8_t | TIM2_ICPolarity,
 |  | uint8_t | TIM2_ICSelection,
 |  | uint8_t | TIM2_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIM2_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM2_ICPOLARITY_FALLING
  • TIM2_ICPOLARITY_RISING
TIM2_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM2_ICSELECTION_DIRECTTI: TIM2 Input 2 is selected to be connected to IC2.
  • TIM2_ICSELECTION_INDIRECTTI: TIM2 Input 2 is selected to be connected to IC1.
TIM2_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1255 of file stm8s_tim2.c.

References TIM2_CCER1_CC2E, TIM2_CCER1_CC2P, TIM2_CCMR_CCxS, TIM2_CCMR_ICxF, and TIM2_ICPOLARITY_RISING.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

static void TI3_Config | ( | uint8_t | TIM2_ICPolarity,
 |  | uint8_t | TIM2_ICSelection,
 |  | uint8_t | TIM2_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIM2_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM2_ICPOLARITY_FALLING
  • TIM2_ICPOLARITY_RISING
TIM2_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM2_ICSELECTION_DIRECTTI: TIM2 Input 3 is selected to be connected to IC3.
TIM2_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1296 of file stm8s_tim2.c.

References TIM2_CCER2_CC3E, TIM2_CCER2_CC3P, TIM2_CCMR_CCxS, TIM2_CCMR_ICxF, and TIM2_ICPOLARITY_RISING.

Referenced by TIM2_ICInit().

void TIM2_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM2 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM2 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 567 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_ARPE.

void TIM2_CCxCmd | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM2 Capture Compare Channel x.

Parameters:
TIM2_Channel specifies the TIM2 Channel. This parameter can be one of the following values:

  • TIM2_CHANNEL_1: TIM2 Channel1
  • TIM2_CHANNEL_2: TIM2 Channel2
  • TIM2_CHANNEL_3: TIM2 Channel3
NewState specifies the TIM2 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 759 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM2_CHANNEL_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC2E, TIM2_CCER2_CC3E, TIM2_CHANNEL_1, and TIM2_CHANNEL_2.

void TIM2_ClearFlag ( TIM2_FLAG_TypeDef TIM2_FLAG )

Clears the TIM2’s pending flags.

Parameters:
TIM2_FLAG specifies the flag to clear. This parameter can be one of the following values:

  • TIM2_FLAG_UPDATE: TIM2 update Flag
  • TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
  • TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
  • TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
  • TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
  • TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
  • TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
Return values:
None.

Definition at line 1132 of file stm8s_tim2.c.

References IS_TIM2_CLEAR_FLAG_OK.

void TIM2_ClearITPendingBit ( TIM2_IT_TypeDef TIM2_IT )

Clears the TIM2's interrupt pending bits.

Parameters:
TIM2_IT specifies the pending bit to clear. This parameter can be one of the following values:

  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
Return values:
None.

Definition at line 1188 of file stm8s_tim2.c.

References IS_TIM2_IT_OK.

void TIM2_Cmd ( FunctionalState NewState )

Enables or disables the TIM2 peripheral.

Parameters:
NewState new state of the TIM2 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 339 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_CEN.

void TIM2_DeInit ( void )

Deinitializes the TIM2 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 46 of file stm8s_tim2.c.

References TIM2_ARRH_RESET_VALUE, TIM2_ARRL_RESET_VALUE, TIM2_CCER1_RESET_VALUE, TIM2_CCER2_RESET_VALUE, TIM2_CCMR1_RESET_VALUE, TIM2_CCMR2_RESET_VALUE, TIM2_CCMR3_RESET_VALUE, TIM2_CCR1H_RESET_VALUE, TIM2_CCR1L_RESET_VALUE, TIM2_CCR2H_RESET_VALUE, TIM2_CCR2L_RESET_VALUE, TIM2_CCR3H_RESET_VALUE, TIM2_CCR3L_RESET_VALUE, TIM2_CNTRH_RESET_VALUE, TIM2_CNTRL_RESET_VALUE, TIM2_CR1_RESET_VALUE, TIM2_IER_RESET_VALUE, TIM2_PSCR_RESET_VALUE, TIM2_SR1_RESET_VALUE, and TIM2_SR2_RESET_VALUE.

void TIM2_ForcedOC1Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel1 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 512 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_ForcedOC2Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel2 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 531 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_ForcedOC3Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel3 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 550 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_GenerateEvent ( TIM2_EventSource_TypeDef TIM2_EventSource )

Configures the TIM2 event to be generated by software.

Parameters:
TIM2_EventSource specifies the event source. This parameter can be one of the following values:

  • TIM2_EVENTSOURCE_UPDATE: TIM2 update Event source
  • TIM2_EVENTSOURCE_CC1: TIM2 Capture Compare 1 Event source
  • TIM2_EVENTSOURCE_CC2: TIM2 Capture Compare 2 Event source
  • TIM2_EVENTSOURCE_CC3: TIM2 Capture Compare 3 Event source
Return values:
None

Definition at line 663 of file stm8s_tim2.c.

References IS_TIM2_EVENT_SOURCE_OK.

uint16_t TIM2_GetCapture1 ( void )

Gets the TIM2 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 1001 of file stm8s_tim2.c.

uint16_t TIM2_GetCapture2 ( void )

Gets the TIM2 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 1021 of file stm8s_tim2.c.

uint16_t TIM2_GetCapture3 ( void )

Gets the TIM2 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 1041 of file stm8s_tim2.c.

uint16_t TIM2_GetCounter ( void )

Gets the TIM2 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 1061 of file stm8s_tim2.c.

FlagStatus TIM2_GetFlagStatus ( TIM2_FLAG_TypeDef TIM2_FLAG )

Checks whether the specified TIM2 flag is set or not.

Parameters:
TIM2_FLAG specifies the flag to check. This parameter can be one of the following values:

  • TIM2_FLAG_UPDATE: TIM2 update Flag
  • TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
  • TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
  • TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
  • TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
  • TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
  • TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
Return values:
FlagStatus The new state of TIM2_FLAG (SET or RESET).

Definition at line 1096 of file stm8s_tim2.c.

References IS_TIM2_GET_FLAG_OK, RESET, and SET.

ITStatus TIM2_GetITStatus ( TIM2_IT_TypeDef TIM2_IT )

Checks whether the TIM2 interrupt has occurred or not.

Parameters:
TIM2_IT specifies the TIM2 interrupt source to check. This parameter can be one of the following values:

  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
Return values:
ITStatus The new state of the TIM2_IT(SET or RESET).

Definition at line 1154 of file stm8s_tim2.c.

References IS_TIM2_GET_IT_OK, RESET, and SET.

TIM2_Prescaler_TypeDef TIM2_GetPrescaler ( void )

Gets the TIM2 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM2_Prescaler_TypeDef.

Definition at line 1076 of file stm8s_tim2.c.

void TIM2_ICInit | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_ICPolarity_TypeDef | TIM2_ICPolarity,
 |  | TIM2_ICSelection_TypeDef | TIM2_ICSelection,
 |  | TIM2_ICPSC_TypeDef | TIM2_ICPrescaler,
 |  | uint8_t | TIM2_ICFilter
 | ) |  |

Initializes the TIM2 peripheral according to the specified parameters.

Parameters:
TIM2_Channel | specifies the Input Capture Channel from TIM2_Channel_TypeDef.
TIM2_ICPolarity | specifies the Input Capture Polarity from TIM2_ICPolarity_TypeDef.
TIM2_ICSelection | specifies the Input Capture Selection from TIM2_ICSelection_TypeDef.
TIM2_ICPrescaler | specifies the Input Capture Prescaler from TIM2_ICPSC_TypeDef.
TIM2_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 210 of file stm8s_tim2.c.

References IS_TIM2_CHANNEL_OK, IS_TIM2_IC_FILTER_OK, IS_TIM2_IC_POLARITY_OK, IS_TIM2_IC_PRESCALER_OK, IS_TIM2_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TIM2_CHANNEL_1, TIM2_CHANNEL_2, TIM2_SetIC1Prescaler(), TIM2_SetIC2Prescaler(), and TIM2_SetIC3Prescaler().

void TIM2_ITConfig | ( | TIM2_IT_TypeDef | TIM2_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM2 interrupts.

Parameters:
NewState | new state of the TIM2 peripheral. This parameter can be: ENABLE or DISABLE.
TIM2_IT specifies the TIM2 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
NewState | new state of the TIM2 peripheral.
Return values:
None

Definition at line 369 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM2_IT_OK.

void TIM2_OC1Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel1 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 104 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC1P, and TIM2_CCMR_OCM.

void TIM2_OC1PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 1 polarity.

Parameters:
TIM2_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:

  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 681 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER1_CC1P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 590 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_OC2Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel2 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 138 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER1_CC2E, TIM2_CCER1_CC2P, and TIM2_CCMR_OCM.

void TIM2_OC2PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 2 polarity.

Parameters:
TIM2_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:

  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 706 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER1_CC2P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 613 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_OC3Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel3 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 175 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER2_CC3E, TIM2_CCER2_CC3P, and TIM2_CCMR_OCM.

void TIM2_OC3PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 3 polarity.

Parameters:
TIM2_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:

  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 731 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER2_CC3P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 636 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_PrescalerConfig | ( | TIM2_Prescaler_TypeDef | Prescaler,
 |  | TIM2_PSCReloadMode_TypeDef | TIM2_PSCReloadMode
 | ) |  |

Configures the TIM2 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values

  • TIM2_PRESCALER_1
  • TIM2_PRESCALER_2
  • TIM2_PRESCALER_4
  • TIM2_PRESCALER_8
  • TIM2_PRESCALER_16
  • TIM2_PRESCALER_32
  • TIM2_PRESCALER_64
  • TIM2_PRESCALER_128
  • TIM2_PRESCALER_256
  • TIM2_PRESCALER_512
  • TIM2_PRESCALER_1024
  • TIM2_PRESCALER_2048
  • TIM2_PRESCALER_4096
  • TIM2_PRESCALER_8192
  • TIM2_PRESCALER_16384
  • TIM2_PRESCALER_32768
TIM2_PSCReloadMode specifies the TIM2 Prescaler Reload mode. This parameter can be one of the following values

  • TIM2_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM2_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 489 of file stm8s_tim2.c.

References IS_TIM2_PRESCALER_OK, and IS_TIM2_PRESCALER_RELOAD_OK.

void TIM2_PWMIConfig | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_ICPolarity_TypeDef | TIM2_ICPolarity,
 |  | TIM2_ICSelection_TypeDef | TIM2_ICSelection,
 |  | TIM2_ICPSC_TypeDef | TIM2_ICPrescaler,
 |  | uint8_t | TIM2_ICFilter
 | ) |  |

Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM2_Channel | specifies the Input Capture Channel from TIM2_Channel_TypeDef.
TIM2_ICPolarity | specifies the Input Capture Polarity from TIM2_ICPolarity_TypeDef.
TIM2_ICSelection | specifies the Input Capture Selection from TIM2_ICSelection_TypeDef.
TIM2_ICPrescaler | specifies the Input Capture Prescaler from TIM2_ICPSC_TypeDef.
TIM2_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 265 of file stm8s_tim2.c.

References IS_TIM2_IC_POLARITY_OK, IS_TIM2_IC_PRESCALER_OK, IS_TIM2_IC_SELECTION_OK, IS_TIM2_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM2_CHANNEL_1, TIM2_ICPOLARITY_FALLING, TIM2_ICPOLARITY_RISING, TIM2_ICSELECTION_DIRECTTI, TIM2_ICSELECTION_INDIRECTTI, TIM2_SetIC1Prescaler(), and TIM2_SetIC2Prescaler().

void TIM2_SelectOCxM | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_OCMode_TypeDef | TIM2_OCMode
 | ) |  |

Selects the TIM2 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM2_CCxCmd and TIM2_CCxNCmd functions.

Parameters:
TIM2_Channel specifies the TIM2 Channel. This parameter can be one of the following values:

  • TIM2_CHANNEL_1: TIM2 Channel1
  • TIM2_CHANNEL_2: TIM2 Channel2
  • TIM2_CHANNEL_3: TIM2 Channel3
TIM2_OCMode specifies the TIM2 Output Compare Mode. This paramter can be one of the following values:

  • TIM2_OCMODE_TIMING
  • TIM2_OCMODE_ACTIVE
  • TIM2_OCMODE_TOGGLE
  • TIM2_OCMODE_PWM1
  • TIM2_OCMODE_PWM2
  • TIM2_FORCEDACTION_ACTIVE
  • TIM2_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 824 of file stm8s_tim2.c.

References IS_TIM2_CHANNEL_OK, IS_TIM2_OCM_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC2E, TIM2_CCER2_CC3E, TIM2_CCMR_OCM, TIM2_CHANNEL_1, and TIM2_CHANNEL_2.

void TIM2_SelectOnePulseMode ( TIM2_OPMode_TypeDef TIM2_OPMode )

Selects the TIM2’s One Pulse Mode.

Parameters:
TIM2_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values

  • TIM2_OPMODE_SINGLE
  • TIM2_OPMODE_REPETITIVE
Return values:
None

Definition at line 443 of file stm8s_tim2.c.

References IS_TIM2_OPM_MODE_OK, TIM2_CR1_OPM, and TIM2_OPMODE_REPETITIVE.

void TIM2_SetAutoreload ( uint16_t Autoreload )

Sets the TIM2 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 881 of file stm8s_tim2.c.

void TIM2_SetCompare1 ( uint16_t Compare1 )

Sets the TIM2 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 897 of file stm8s_tim2.c.

void TIM2_SetCompare2 ( uint16_t Compare2 )

Sets the TIM2 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 912 of file stm8s_tim2.c.

void TIM2_SetCompare3 ( uint16_t Compare3 )

Sets the TIM2 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 927 of file stm8s_tim2.c.

void TIM2_SetCounter ( uint16_t Counter )

Sets the TIM2 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 866 of file stm8s_tim2.c.

void TIM2_SetIC1Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC1Prescaler )

Sets the TIM2 Input Capture 1 Prescaler.

Parameters:
TIM2_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 946 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

void TIM2_SetIC2Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC2Prescaler )

Sets the TIM2 Input Capture 2 prescaler.

Parameters:
TIM2_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 966 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

void TIM2_SetIC3Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC3Prescaler )

Sets the TIM2 Input Capture 3 prescaler.

Parameters:
TIM2_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 986 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit().

void TIM2_TimeBaseInit | ( | TIM2_Prescaler_TypeDef | TIM2_Prescaler,
 |  | uint16_t | TIM2_Period
 | ) |  |

Initializes the TIM2 Time Base Unit according to the specified parameters.

Parameters:
TIM2_Prescaler | specifies the Prescaler from TIM2_Prescaler_TypeDef.
TIM2_Period | specifies the Period value.
Return values:
None

Definition at line 85 of file stm8s_tim2.c.

void TIM2_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM2 Update event.

Parameters:
NewState new state of the TIM2 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 394 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_UDIS.

void TIM2_UpdateRequestConfig ( TIM2_UpdateSource_TypeDef TIM2_UpdateSource )

Selects the TIM2 Update Request Interrupt source.

Parameters:
TIM2_UpdateSource specifies the Update source. This parameter can be one of the following values

  • TIM2_UPDATESOURCE_REGULAR
  • TIM2_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 418 of file stm8s_tim2.c.

References IS_TIM2_UPDATE_SOURCE_OK, TIM2_CR1_URS, and TIM2_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM3_Public_Functions

Functions

TIM3_Public_Functions

STM8S_StdPeriph_Driver

Functions

static void | TI1_Config (uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter)
Configure the TI2 as Input.
void | TIM3_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM3 peripheral Preload register on ARR.
void | TIM3_CCxCmd (TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
Enables or disables the TIM3 Capture Compare Channel x.
void | TIM3_ClearFlag (TIM3_FLAG_TypeDef TIM3_FLAG)
Clears the TIM3’s pending flags.
void | TIM3_ClearITPendingBit (TIM3_IT_TypeDef TIM3_IT)
Clears the TIM3's interrupt pending bits.
void | TIM3_Cmd (FunctionalState NewState)
Enables or disables the TIM3 peripheral.
void | TIM3_DeInit (void)
Deinitializes the TIM3 peripheral registers to their default reset values.
void | TIM3_ForcedOC1Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel1 output waveform to active or inactive level.
void | TIM3_ForcedOC2Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel2 output waveform to active or inactive level.
void | TIM3_GenerateEvent (TIM3_EventSource_TypeDef TIM3_EventSource)
Configures the TIM3 event to be generated by software.
uint16_t | TIM3_GetCapture1 (void)
Gets the TIM3 Input Capture 1 value.
uint16_t | TIM3_GetCapture2 (void)
Gets the TIM3 Input Capture 2 value.
uint16_t | TIM3_GetCounter (void)
Gets the TIM3 Counter value.
FlagStatus | TIM3_GetFlagStatus (TIM3_FLAG_TypeDef TIM3_FLAG)
Checks whether the specified TIM3 flag is set or not.
ITStatus | TIM3_GetITStatus (TIM3_IT_TypeDef TIM3_IT)
Checks whether the TIM3 interrupt has occurred or not.
TIM3_Prescaler_TypeDef | TIM3_GetPrescaler (void)
Gets the TIM3 Prescaler value.
void | TIM3_ICInit (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Initializes the TIM3 peripheral according to the specified parameters.
void | TIM3_ITConfig (TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
Enables or disables the specified TIM3 interrupts.
void | TIM3_OC1Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel1 according to the specified parameters.
void | TIM3_OC1PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 1 polarity.
void | TIM3_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR1.
void | TIM3_OC2Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel2 according to the specified parameters.
void | TIM3_OC2PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 2 polarity.
void | TIM3_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR2.
void | TIM3_PrescalerConfig (TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
Configures the TIM3 Prescaler.
void | TIM3_PWMIConfig (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.
void | TIM3_SelectOCxM (TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
Selects the TIM3 Output Compare Mode.
void | TIM3_SelectOnePulseMode (TIM3_OPMode_TypeDef TIM3_OPMode)
Selects the TIM3’s One Pulse Mode.
void | TIM3_SetAutoreload (uint16_t Autoreload)
Sets the TIM3 Autoreload Register value.
void | TIM3_SetCompare1 (uint16_t Compare1)
Sets the TIM3 Capture Compare1 Register value.
void | TIM3_SetCompare2 (uint16_t Compare2)
Sets the TIM3 Capture Compare2 Register value.
void | TIM3_SetCounter (uint16_t Counter)
Sets the TIM3 Counter Register value.
void | TIM3_SetIC1Prescaler (TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
Sets the TIM3 Input Capture 1 prescaler.
void | TIM3_SetIC2Prescaler (TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
Sets the TIM3 Input Capture 2 prescaler.
void | TIM3_TimeBaseInit (TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period)
Initializes the TIM3 Time Base Unit according to the specified parameters.
void | TIM3_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM3 Update event.
void | TIM3_UpdateRequestConfig (TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
Selects the TIM3 Update Request Interrupt source.

Function Documentation

static void TI1_Config | ( | uint8_t | TIM3_ICPolarity,
 |  | uint8_t | TIM3_ICSelection,
 |  | uint8_t | TIM3_ICFilter
 | ) |  | [static]

Configure the TI1 as Input.

Parameters:
TIM3_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM3_ICPOLARITY_FALLING
  • TIM3_ICPOLARITY_RISING
TIM3_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM3_ICSELECTION_DIRECTTI: TIM3 Input 1 is selected to be connected to IC1.
  • TIM3_ICSELECTION_INDIRECTTI: TIM3 Input 1 is selected to be connected to IC2.
TIM3_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 991 of file stm8s_tim3.c.

References TIM3_CCER1_CC1E, TIM3_CCER1_CC1P, TIM3_CCMR_CCxS, TIM3_CCMR_ICxF, and TIM3_ICPOLARITY_RISING.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

static void TI2_Config | ( | uint8_t | TIM3_ICPolarity,
 |  | uint8_t | TIM3_ICSelection,
 |  | uint8_t | TIM3_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIM3_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM3_ICPOLARITY_FALLING
  • TIM3_ICPOLARITY_RISING
TIM3_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM3_ICSELECTION_DIRECTTI: TIM3 Input 2 is selected to be connected to IC2.
  • TIM3_ICSELECTION_INDIRECTTI: TIM3 Input 2 is selected to be connected to IC1.
TIM3_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1031 of file stm8s_tim3.c.

References TIM3_CCER1_CC2E, TIM3_CCER1_CC2P, TIM3_CCMR_CCxS, TIM3_CCMR_ICxF, and TIM3_ICPOLARITY_RISING.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

void TIM3_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM3 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM3 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 486 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_ARPE.

void TIM3_CCxCmd | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM3 Capture Compare Channel x.

Parameters:
TIM3_Channel specifies the TIM3 Channel. This parameter can be one of the following values:

  • TIM3_CHANNEL_1: TIM3 Channel1
  • TIM3_CHANNEL_2: TIM3 Channel2
NewState specifies the TIM3 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 627 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM3_CHANNEL_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC2E, and TIM3_CHANNEL_1.

void TIM3_ClearFlag ( TIM3_FLAG_TypeDef TIM3_FLAG )

Clears the TIM3’s pending flags.

Parameters:
TIM3_FLAG specifies the flag to clear. This parameter can be one of the following values:

  • TIM3_FLAG_UPDATE: TIM3 update Flag
  • TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
  • TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
  • TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
  • TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
Return values:
None.

Definition at line 911 of file stm8s_tim3.c.

References IS_TIM3_CLEAR_FLAG_OK.

void TIM3_ClearITPendingBit ( TIM3_IT_TypeDef TIM3_IT )

Clears the TIM3's interrupt pending bits.

Parameters:
TIM3_IT specifies the pending bit to clear. This parameter can be one of the following values:

  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
Return values:
None.

Definition at line 965 of file stm8s_tim3.c.

References IS_TIM3_IT_OK.

void TIM3_Cmd ( FunctionalState NewState )

Enables or disables the TIM3 peripheral.

Parameters:
NewState new state of the TIM3 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 280 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_CEN.

void TIM3_DeInit ( void )

Deinitializes the TIM3 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 45 of file stm8s_tim3.c.

References TIM3_ARRH_RESET_VALUE, TIM3_ARRL_RESET_VALUE, TIM3_CCER1_RESET_VALUE, TIM3_CCMR1_RESET_VALUE, TIM3_CCMR2_RESET_VALUE, TIM3_CCR1H_RESET_VALUE, TIM3_CCR1L_RESET_VALUE, TIM3_CCR2H_RESET_VALUE, TIM3_CCR2L_RESET_VALUE, TIM3_CNTRH_RESET_VALUE, TIM3_CNTRL_RESET_VALUE, TIM3_CR1_RESET_VALUE, TIM3_IER_RESET_VALUE, TIM3_PSCR_RESET_VALUE, TIM3_SR1_RESET_VALUE, and TIM3_SR2_RESET_VALUE.

void TIM3_ForcedOC1Config ( TIM3_ForcedAction_TypeDef TIM3_ForcedAction )

Forces the TIM3 Channel1 output waveform to active or inactive level.

Parameters:
TIM3_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM3_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM3_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 452 of file stm8s_tim3.c.

References IS_TIM3_FORCED_ACTION_OK, and TIM3_CCMR_OCM.

void TIM3_ForcedOC2Config ( TIM3_ForcedAction_TypeDef TIM3_ForcedAction )

Forces the TIM3 Channel2 output waveform to active or inactive level.

Parameters:
TIM3_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM3_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM3_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 470 of file stm8s_tim3.c.

References IS_TIM3_FORCED_ACTION_OK, and TIM3_CCMR_OCM.

void TIM3_GenerateEvent ( TIM3_EventSource_TypeDef TIM3_EventSource )

Configures the TIM3 event to be generated by software.

Parameters:
TIM3_EventSource specifies the event source. This parameter can be one of the following values:

  • TIM3_EVENTSOURCE_UPDATE: TIM3 update Event source
  • TIM3_EVENTSOURCE_CC1: TIM3 Capture Compare 1 Event source
  • TIM3_EVENTSOURCE_CC2: TIM3 Capture Compare 2 Event source
Return values:
None

Definition at line 557 of file stm8s_tim3.c.

References IS_TIM3_EVENT_SOURCE_OK.

uint16_t TIM3_GetCapture1 ( void )

Gets the TIM3 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 804 of file stm8s_tim3.c.

uint16_t TIM3_GetCapture2 ( void )

Gets the TIM3 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 824 of file stm8s_tim3.c.

uint16_t TIM3_GetCounter ( void )

Gets the TIM3 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 844 of file stm8s_tim3.c.

FlagStatus TIM3_GetFlagStatus ( TIM3_FLAG_TypeDef TIM3_FLAG )

Checks whether the specified TIM3 flag is set or not.

Parameters:
TIM3_FLAG specifies the flag to check. This parameter can be one of the following values:

  • TIM3_FLAG_UPDATE: TIM3 update Flag
  • TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
  • TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
  • TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
  • TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
Return values:
FlagStatus The new state of TIM3_FLAG (SET or RESET).

Definition at line 877 of file stm8s_tim3.c.

References IS_TIM3_GET_FLAG_OK, RESET, and SET.

ITStatus TIM3_GetITStatus ( TIM3_IT_TypeDef TIM3_IT )

Checks whether the TIM3 interrupt has occurred or not.

Parameters:
TIM3_IT specifies the TIM3 interrupt source to check. This parameter can be one of the following values:

  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
Return values:
ITStatus The new state of the TIM3_IT(SET or RESET).

Definition at line 932 of file stm8s_tim3.c.

References IS_TIM3_GET_IT_OK, RESET, and SET.

TIM3_Prescaler_TypeDef TIM3_GetPrescaler ( void )

Gets the TIM3 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM3_Prescaler_TypeDef.

Definition at line 859 of file stm8s_tim3.c.

void TIM3_ICInit | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_ICPolarity_TypeDef | TIM3_ICPolarity,
 |  | TIM3_ICSelection_TypeDef | TIM3_ICSelection,
 |  | TIM3_ICPSC_TypeDef | TIM3_ICPrescaler,
 |  | uint8_t | TIM3_ICFilter
 | ) |  |

Initializes the TIM3 peripheral according to the specified parameters.

Parameters:
TIM3_Channel | specifies the Input Capture Channel from TIM3_Channel_TypeDef.
TIM3_ICPolarity | specifies the Input Capture Polarity from TIM3_ICPolarity_TypeDef.
TIM3_ICSelection | specifies the Input Capture Selection from TIM3_ICSelection_TypeDef.
TIM3_ICPrescaler | specifies the Input Capture Prescaler from TIM3_ICPSC_TypeDef.
TIM3_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 163 of file stm8s_tim3.c.

References IS_TIM3_CHANNEL_OK, IS_TIM3_IC_FILTER_OK, IS_TIM3_IC_POLARITY_OK, IS_TIM3_IC_PRESCALER_OK, IS_TIM3_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TIM3_CHANNEL_2, TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

void TIM3_ITConfig | ( | TIM3_IT_TypeDef | TIM3_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM3 interrupts.

Parameters:
NewState | new state of the TIM3 peripheral. This parameter can be: ENABLE or DISABLE.
TIM3_IT specifies the TIM3 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM3_IT_UPDATE: TIM3 update Interrupt source
  • TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
  • TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
  • TIM3_IT_CC3: TIM3 Capture Compare 3 Interrupt source
NewState | new state of the TIM3 peripheral. *
Return values:
None

Definition at line 309 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM3_IT_OK.

void TIM3_OC1Init | ( | TIM3_OCMode_TypeDef | TIM3_OCMode,
 |  | TIM3_OutputState_TypeDef | TIM3_OutputState,
 |  | uint16_t | TIM3_Pulse,
 |  | TIM3_OCPolarity_TypeDef | TIM3_OCPolarity
 | ) |  |

Initializes the TIM3 Channel1 according to the specified parameters.

Parameters:
TIM3_OCMode | specifies the Output Compare mode from TIM3_OCMode_TypeDef.
TIM3_OutputState | specifies the Output State from TIM3_OutputState_TypeDef.
TIM3_Pulse | specifies the Pulse width value.
TIM3_OCPolarity | specifies the Output Compare Polarity from TIM3_OCPolarity_TypeDef.
Return values:
None

Definition at line 96 of file stm8s_tim3.c.

References IS_TIM3_OC_MODE_OK, IS_TIM3_OC_POLARITY_OK, IS_TIM3_OUTPUT_STATE_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC1P, and TIM3_CCMR_OCM.

void TIM3_OC1PolarityConfig ( TIM3_OCPolarity_TypeDef TIM3_OCPolarity )

Configures the TIM3 Channel 1 polarity.

Parameters:
TIM3_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:

  • TIM3_OCPOLARITY_LOW: Output Compare active low
  • TIM3_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 575 of file stm8s_tim3.c.

References IS_TIM3_OC_POLARITY_OK, TIM3_CCER1_CC1P, and TIM3_OCPOLARITY_HIGH.

void TIM3_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM3 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 509 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CCMR_OCxPE.

void TIM3_OC2Init | ( | TIM3_OCMode_TypeDef | TIM3_OCMode,
 |  | TIM3_OutputState_TypeDef | TIM3_OutputState,
 |  | uint16_t | TIM3_Pulse,
 |  | TIM3_OCPolarity_TypeDef | TIM3_OCPolarity
 | ) |  |

Initializes the TIM3 Channel2 according to the specified parameters.

Parameters:
TIM3_OCMode | specifies the Output Compare mode from TIM3_OCMode_TypeDef.
TIM3_OutputState | specifies the Output State from TIM3_OutputState_TypeDef.
TIM3_Pulse | specifies the Pulse width value.
TIM3_OCPolarity | specifies the Output Compare Polarity from TIM3_OCPolarity_TypeDef.
Return values:
None

Definition at line 128 of file stm8s_tim3.c.

References IS_TIM3_OC_MODE_OK, IS_TIM3_OC_POLARITY_OK, IS_TIM3_OUTPUT_STATE_OK, TIM3_CCER1_CC2E, TIM3_CCER1_CC2P, and TIM3_CCMR_OCM.

void TIM3_OC2PolarityConfig ( TIM3_OCPolarity_TypeDef TIM3_OCPolarity )

Configures the TIM3 Channel 2 polarity.

Parameters:
TIM3_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:

  • TIM3_OCPOLARITY_LOW: Output Compare active low
  • TIM3_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 600 of file stm8s_tim3.c.

References IS_TIM3_OC_POLARITY_OK, TIM3_CCER1_CC2P, and TIM3_OCPOLARITY_HIGH.

void TIM3_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM3 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 532 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CCMR_OCxPE.

void TIM3_PrescalerConfig | ( | TIM3_Prescaler_TypeDef | Prescaler,
 |  | TIM3_PSCReloadMode_TypeDef | TIM3_PSCReloadMode
 | ) |  |

Configures the TIM3 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values

  • TIM3_PRESCALER_1
  • TIM3_PRESCALER_2
  • TIM3_PRESCALER_4
  • TIM3_PRESCALER_8
  • TIM3_PRESCALER_16
  • TIM3_PRESCALER_32
  • TIM3_PRESCALER_64
  • TIM3_PRESCALER_128
  • TIM3_PRESCALER_256
  • TIM3_PRESCALER_512
  • TIM3_PRESCALER_1024
  • TIM3_PRESCALER_2048
  • TIM3_PRESCALER_4096
  • TIM3_PRESCALER_8192
  • TIM3_PRESCALER_16384
  • TIM3_PRESCALER_32768
TIM3_PSCReloadMode specifies the TIM3 Prescaler Reload mode. This parameter can be one of the following values

  • TIM3_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediatly.
  • TIM3_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 429 of file stm8s_tim3.c.

References IS_TIM3_PRESCALER_OK, and IS_TIM3_PRESCALER_RELOAD_OK.

void TIM3_PWMIConfig | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_ICPolarity_TypeDef | TIM3_ICPolarity,
 |  | TIM3_ICSelection_TypeDef | TIM3_ICSelection,
 |  | TIM3_ICPSC_TypeDef | TIM3_ICPrescaler,
 |  | uint8_t | TIM3_ICFilter
 | ) |  |

Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM3_Channel | specifies the Input Capture Channel from TIM3_Channel_TypeDef.
TIM3_ICPolarity | specifies the Input Capture Polarity from TIM3_ICPolarity_TypeDef.
TIM3_ICSelection | specifies the Input Capture Selection from TIM3_ICSelection_TypeDef.
TIM3_ICPrescaler | specifies the Input Capture Prescaler from TIM3_ICPSC_TypeDef.
TIM3_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 206 of file stm8s_tim3.c.

References IS_TIM3_IC_POLARITY_OK, IS_TIM3_IC_PRESCALER_OK, IS_TIM3_IC_SELECTION_OK, IS_TIM3_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM3_CHANNEL_2, TIM3_ICPOLARITY_FALLING, TIM3_ICPOLARITY_RISING, TIM3_ICSELECTION_DIRECTTI, TIM3_ICSELECTION_INDIRECTTI, TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

void TIM3_SelectOCxM | ( | TIM3_Channel_TypeDef | TIM3_Channel,
 |  | TIM3_OCMode_TypeDef | TIM3_OCMode
 | ) |  |

Selects the TIM3 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM3_CCxCmd and TIM3_CCxNCmd functions.

Parameters:
TIM3_Channel specifies the TIM3 Channel. This parameter can be one of the following values:

  • TIM3_CHANNEL_1: TIM3 Channel1
  • TIM3_CHANNEL_2: TIM3 Channel2
TIM3_OCMode specifies the TIM3 Output Compare Mode. This paramter can be one of the following values:

  • TIM3_OCMODE_TIMING
  • TIM3_OCMODE_ACTIVE
  • TIM3_OCMODE_TOGGLE
  • TIM3_OCMODE_PWM1
  • TIM3_OCMODE_PWM2
  • TIM3_FORCEDACTION_ACTIVE
  • TIM3_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 680 of file stm8s_tim3.c.

References IS_TIM3_CHANNEL_OK, IS_TIM3_OCM_OK, TIM3_CCER1_CC1E, TIM3_CCER1_CC2E, TIM3_CCMR_OCM, and TIM3_CHANNEL_1.

void TIM3_SelectOnePulseMode ( TIM3_OPMode_TypeDef TIM3_OPMode )

Selects the TIM3’s One Pulse Mode.

Parameters:
TIM3_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values

  • TIM3_OPMODE_SINGLE
  • TIM3_OPMODE_REPETITIVE
Return values:
None

Definition at line 383 of file stm8s_tim3.c.

References IS_TIM3_OPM_MODE_OK, TIM3_CR1_OPM, and TIM3_OPMODE_REPETITIVE.

void TIM3_SetAutoreload ( uint16_t Autoreload )

Sets the TIM3 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 726 of file stm8s_tim3.c.

void TIM3_SetCompare1 ( uint16_t Compare1 )

Sets the TIM3 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 740 of file stm8s_tim3.c.

void TIM3_SetCompare2 ( uint16_t Compare2 )

Sets the TIM3 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 754 of file stm8s_tim3.c.

void TIM3_SetCounter ( uint16_t Counter )

Sets the TIM3 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 711 of file stm8s_tim3.c.

void TIM3_SetIC1Prescaler ( TIM3_ICPSC_TypeDef TIM3_IC1Prescaler )

Sets the TIM3 Input Capture 1 prescaler.

Parameters:
TIM3_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM3_ICPSC_DIV1: no prescaler
  • TIM3_ICPSC_DIV2: capture is done once every 2 events
  • TIM3_ICPSC_DIV4: capture is done once every 4 events
  • TIM3_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 772 of file stm8s_tim3.c.

References IS_TIM3_IC_PRESCALER_OK, and TIM3_CCMR_ICxPSC.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

void TIM3_SetIC2Prescaler ( TIM3_ICPSC_TypeDef TIM3_IC2Prescaler )

Sets the TIM3 Input Capture 2 prescaler.

Parameters:
TIM3_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM3_ICPSC_DIV1: no prescaler
  • TIM3_ICPSC_DIV2: capture is done once every 2 events
  • TIM3_ICPSC_DIV4: capture is done once every 4 events
  • TIM3_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 791 of file stm8s_tim3.c.

References IS_TIM3_IC_PRESCALER_OK, and TIM3_CCMR_ICxPSC.

Referenced by TIM3_ICInit(), and TIM3_PWMIConfig().

void TIM3_TimeBaseInit | ( | TIM3_Prescaler_TypeDef | TIM3_Prescaler,
 |  | uint16_t | TIM3_Period
 | ) |  |

Initializes the TIM3 Time Base Unit according to the specified parameters.

Parameters:
TIM3_Prescaler | specifies the Prescaler from TIM3_Prescaler_TypeDef.
TIM3_Period | specifies the Period value.
Return values:
None

Definition at line 78 of file stm8s_tim3.c.

void TIM3_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM3 Update event.

Parameters:
NewState new state of the TIM3 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 334 of file stm8s_tim3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM3_CR1_UDIS.

void TIM3_UpdateRequestConfig ( TIM3_UpdateSource_TypeDef TIM3_UpdateSource )

Selects the TIM3 Update Request Interrupt source.

Parameters:
TIM3_UpdateSource specifies the Update source. This parameter can be one of the following values

  • TIM3_UPDATESOURCE_REGULAR
  • TIM3_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 358 of file stm8s_tim3.c.

References IS_TIM3_UPDATE_SOURCE_OK, TIM3_CR1_URS, and TIM3_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM4_Public_Functions

Functions

TIM4_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | TIM4_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM4 peripheral Preload register on ARR.
void | TIM4_ClearFlag (TIM4_FLAG_TypeDef TIM4_FLAG)
Clears the TIM4’s pending flags.
void | TIM4_ClearITPendingBit (TIM4_IT_TypeDef TIM4_IT)
Clears the TIM4's interrupt pending bits.
void | TIM4_Cmd (FunctionalState NewState)
Enables or disables the TIM4 peripheral.
void | TIM4_DeInit (void)
Deinitializes the TIM4 peripheral registers to their default reset values.
void | TIM4_GenerateEvent (TIM4_EventSource_TypeDef TIM4_EventSource)
Configures the TIM4 event to be generated by software.
uint8_t | TIM4_GetCounter (void)
Gets the TIM4 Counter value.
FlagStatus | TIM4_GetFlagStatus (TIM4_FLAG_TypeDef TIM4_FLAG)
Checks whether the specified TIM4 flag is set or not.
ITStatus | TIM4_GetITStatus (TIM4_IT_TypeDef TIM4_IT)
Checks whether the TIM4 interrupt has occurred or not.
TIM4_Prescaler_TypeDef | TIM4_GetPrescaler (void)
Gets the TIM4 Prescaler value.
void | TIM4_ITConfig (TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
Enables or disables the specified TIM4 interrupts.
void | TIM4_PrescalerConfig (TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
Configures the TIM4 Prescaler.
void | TIM4_SelectOnePulseMode (TIM4_OPMode_TypeDef TIM4_OPMode)
Selects the TIM4’s One Pulse Mode.
void | TIM4_SetAutoreload (uint8_t Autoreload)
Sets the TIM4 Autoreload Register value.
void | TIM4_SetCounter (uint8_t Counter)
Sets the TIM4 Counter Register value.
void | TIM4_TimeBaseInit (TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)
Initializes the TIM4 Time Base Unit according to the specified parameters.
void | TIM4_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM4 Update event.
void | TIM4_UpdateRequestConfig (TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
Selects the TIM4 Update Request Interrupt source.

Function Documentation

void TIM4_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM4 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM4 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 231 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_ARPE.

void TIM4_ClearFlag ( TIM4_FLAG_TypeDef TIM4_FLAG )

Clears the TIM4’s pending flags.

Parameters:
TIM4_FLAG specifies the flag to clear. This parameter can be one of the following values:

  • TIM4_FLAG_UPDATE: TIM4 update Flag
Return values:
None.

Definition at line 343 of file stm8s_tim4.c.

References IS_TIM4_GET_FLAG_OK.

void TIM4_ClearITPendingBit ( TIM4_IT_TypeDef TIM4_IT )

Clears the TIM4's interrupt pending bits.

Parameters:
TIM4_IT specifies the pending bit to clear. This parameter can be one of the following values:

  • TIM4_IT_UPDATE: TIM4 update Interrupt source
Return values:
None.

Definition at line 391 of file stm8s_tim4.c.

References IS_TIM4_IT_OK.

void TIM4_Cmd ( FunctionalState NewState )

Enables or disables the TIM4 peripheral.

Parameters:
NewState new state of the TIM4 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 77 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_CEN.

void TIM4_DeInit ( void )

Deinitializes the TIM4 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 43 of file stm8s_tim4.c.

References TIM4_ARR_RESET_VALUE, TIM4_CNTR_RESET_VALUE, TIM4_CR1_RESET_VALUE, TIM4_IER_RESET_VALUE, TIM4_PSCR_RESET_VALUE, and TIM4_SR1_RESET_VALUE.

void TIM4_GenerateEvent ( TIM4_EventSource_TypeDef TIM4_EventSource )

Configures the TIM4 event to be generated by software.

Parameters:
TIM4_EventSource specifies the event source. This parameter can be one of the following values:

  • TIM4_EVENTSOURCE_UPDATE: TIM4 update Event source
Return values:
None

Definition at line 254 of file stm8s_tim4.c.

References IS_TIM4_EVENT_SOURCE_OK.

uint8_t TIM4_GetCounter ( void )

Gets the TIM4 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 294 of file stm8s_tim4.c.

FlagStatus TIM4_GetFlagStatus ( TIM4_FLAG_TypeDef TIM4_FLAG )

Checks whether the specified TIM4 flag is set or not.

Parameters:
TIM4_FLAG specifies the flag to check. This parameter can be one of the following values:

  • TIM4_FLAG_UPDATE: TIM4 update Flag
Return values:
FlagStatus The new state of TIM4_FLAG (SET or RESET).

Definition at line 318 of file stm8s_tim4.c.

References IS_TIM4_GET_FLAG_OK, RESET, and SET.

ITStatus TIM4_GetITStatus ( TIM4_IT_TypeDef TIM4_IT )

Checks whether the TIM4 interrupt has occurred or not.

Parameters:
TIM4_IT specifies the TIM4 interrupt source to check. This parameter can be one of the following values:

  • TIM4_IT_UPDATE: TIM4 update Interrupt source
Return values:
ITStatus The new state of the TIM4_IT (SET or RESET).

Definition at line 360 of file stm8s_tim4.c.

References IS_TIM4_IT_OK, RESET, and SET.

TIM4_Prescaler_TypeDef TIM4_GetPrescaler ( void )

Gets the TIM4 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value.

Definition at line 305 of file stm8s_tim4.c.

void TIM4_ITConfig | ( | TIM4_IT_TypeDef | TIM4_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM4 interrupts.

Parameters:
NewState | new state of the TIM4 peripheral. This parameter can be: ENABLE or DISABLE.
TIM4_IT specifies the TIM4 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM4_IT_UPDATE: TIM4 update Interrupt source
NewState | new state of the TIM4 peripheral.
Return values:
None

Definition at line 103 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM4_IT_OK.

void TIM4_PrescalerConfig | ( | TIM4_Prescaler_TypeDef | Prescaler,
 |  | TIM4_PSCReloadMode_TypeDef | TIM4_PSCReloadMode
 | ) |  |

Configures the TIM4 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values

  • TIM4_PRESCALER_1
  • TIM4_PRESCALER_2
  • TIM4_PRESCALER_4
  • TIM4_PRESCALER_8
  • TIM4_PRESCALER_16
  • TIM4_PRESCALER_32
  • TIM4_PRESCALER_64
  • TIM4_PRESCALER_128
TIM4_PSCReloadMode specifies the TIM4 Prescaler Reload mode. This parameter can be one of the following values

  • TIM4_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediatly.
  • TIM4_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 212 of file stm8s_tim4.c.

References IS_TIM4_PRESCALER_OK, and IS_TIM4_PRESCALER_RELOAD_OK.

void TIM4_SelectOnePulseMode ( TIM4_OPMode_TypeDef TIM4_OPMode )

Selects the TIM4’s One Pulse Mode.

Parameters:
TIM4_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values

  • TIM4_OPMODE_SINGLE
  • TIM4_OPMODE_REPETITIVE
Return values:
None

Definition at line 175 of file stm8s_tim4.c.

References IS_TIM4_OPM_MODE_OK, TIM4_CR1_OPM, and TIM4_OPMODE_REPETITIVE.

void TIM4_SetAutoreload ( uint8_t Autoreload )

Sets the TIM4 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 283 of file stm8s_tim4.c.

void TIM4_SetCounter ( uint8_t Counter )

Sets the TIM4 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 270 of file stm8s_tim4.c.

void TIM4_TimeBaseInit | ( | TIM4_Prescaler_TypeDef | TIM4_Prescaler,
 |  | uint8_t | TIM4_Period
 | ) |  |

Initializes the TIM4 Time Base Unit according to the specified parameters.

Parameters:
TIM4_Prescaler | specifies the Prescaler from TIM4_Prescaler_TypeDef.
TIM4_Period | specifies the Period value.
Return values:
None

Definition at line 59 of file stm8s_tim4.c.

References IS_TIM4_PRESCALER_OK.

void TIM4_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM4 Update event.

Parameters:
NewState new state of the TIM4 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 127 of file stm8s_tim4.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM4_CR1_UDIS.

void TIM4_UpdateRequestConfig ( TIM4_UpdateSource_TypeDef TIM4_UpdateSource )

Selects the TIM4 Update Request Interrupt source.

Parameters:
TIM4_UpdateSource specifies the Update source. This parameter can be one of the following values

  • TIM4_UPDATESOURCE_REGULAR
  • TIM4_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 151 of file stm8s_tim4.c.

References IS_TIM4_UPDATE_SOURCE_OK, TIM4_CR1_URS, and TIM4_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM5_Public_Functions

Functions

TIM5_Public_Functions

STM8S_StdPeriph_Driver

Functions

static void | TI1_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI3 as Input.
void | TIM5_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM5 peripheral Preload register on ARR.
void | TIM5_CCxCmd (TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)
Enables or disables the TIM5 Capture Compare Channel x.
void | TIM5_ClearFlag (TIM5_FLAG_TypeDef TIM5_FLAG)
Clears the TIM5’s pending flags.
void | TIM5_ClearITPendingBit (TIM5_IT_TypeDef TIM5_IT)
Clears the TIM5's interrupt pending bits.
void | TIM5_Cmd (FunctionalState NewState)
Enables or disables the TIM5 peripheral.
void | TIM5_DeInit (void)
Deinitializes the TIM5 peripheral registers to their default reset values.
void | TIM5_EncoderInterfaceConfig (TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
Configures the TIM5 Encoder Interface.
void | TIM5_ForcedOC1Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel1 output waveform to active or inactive level.
void | TIM5_ForcedOC2Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel2 output waveform to active or inactive level.
void | TIM5_ForcedOC3Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel3 output waveform to active or inactive level.
void | TIM5_GenerateEvent (TIM5_EventSource_TypeDef TIM5_EventSource)
Configures the TIM5 event to be generated by software.
uint16_t | TIM5_GetCapture1 (void)
Gets the TIM5 Input Capture 1 value.
uint16_t | TIM5_GetCapture2 (void)
Gets the TIM5 Input Capture 2 value.
uint16_t | TIM5_GetCapture3 (void)
Gets the TIM5 Input Capture 3 value.
uint16_t | TIM5_GetCounter (void)
Gets the TIM5 Counter value.
FlagStatus | TIM5_GetFlagStatus (TIM5_FLAG_TypeDef TIM5_FLAG)
Checks whether the specified TIM5 flag is set or not.
ITStatus | TIM5_GetITStatus (TIM5_IT_TypeDef TIM5_IT)
Checks whether the TIM5 interrupt has occurred or not.
TIM5_Prescaler_TypeDef | TIM5_GetPrescaler (void)
Gets the TIM5 Prescaler value.
void | TIM5_ICInit (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Initializes the TIM5 peripheral according to the specified parameters.
void | TIM5_InternalClockConfig (void)
Enables the TIM5 internal Clock.
void | TIM5_ITConfig (TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
Enables or disables the specified TIM5 interrupts.
void | TIM5_OC1Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel1 according to the specified parameters.
void | TIM5_OC1PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 1 polarity.
void | TIM5_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR1.
void | TIM5_OC2Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel2 according to the specified parameters.
void | TIM5_OC2PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 2 polarity.
void | TIM5_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR2.
void | TIM5_OC3Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel3 according to the specified parameters.
void | TIM5_OC3PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 3 polarity.
void | TIM5_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR3.
void | TIM5_PrescalerConfig (TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
Configures the TIM5 Prescaler.
void | TIM5_PWMIConfig (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.
void | TIM5_SelectInputTrigger (TIM5_TS_TypeDef TIM5_InputTriggerSource)
Selects the TIM5 Input Trigger source.
void | TIM5_SelectOCxM (TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)
Selects the TIM5 Output Compare Mode.
void | TIM5_SelectOnePulseMode (TIM5_OPMode_TypeDef TIM5_OPMode)
Selects the TIM5’s One Pulse Mode.
void | TIM5_SelectOutputTrigger (TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
Selects the TIM5 Trigger Output Mode.
void | TIM5_SelectSlaveMode (TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
Selects the TIM5 Slave Mode.
void | TIM5_SetAutoreload (uint16_t Autoreload)
Sets the TIM5 Autoreload Register value.
void | TIM5_SetCompare1 (uint16_t Compare1)
Sets the TIM5 Capture Compare1 Register value.
void | TIM5_SetCompare2 (uint16_t Compare2)
Sets the TIM5 Capture Compare2 Register value.
void | TIM5_SetCompare3 (uint16_t Compare3)
Sets the TIM5 Capture Compare3 Register value.
void | TIM5_SetCounter (uint16_t Counter)
Sets the TIM5 Counter Register value.
void | TIM5_SetIC1Prescaler (TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
Sets the TIM5 Input Capture 1 prescaler.
void | TIM5_SetIC2Prescaler (TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
Sets the TIM5 Input Capture 2 prescaler.
void | TIM5_SetIC3Prescaler (TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)
Sets the TIM5 Input Capture 3 prescaler.
void | TIM5_TimeBaseInit (TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period)
Initializes the TIM5 Time Base Unit according to the specified parameters.
void | TIM5_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM5 Update event.
void | TIM5_UpdateRequestConfig (TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
Selects the TIM5 Update Request Interrupt source.

Function Documentation

static void TI1_Config | ( | uint8_t | TIM5_ICPolarity,
 |  | uint8_t | TIM5_ICSelection,
 |  | uint8_t | TIM5_ICFilter
 | ) |  | [static]

Configure the TI1 as Input.

Parameters:
TIM5_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM5_ICPOLARITY_FALLING
  • TIM5_ICPOLARITY_RISING
TIM5_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM5_ICSELECTION_DIRECTTI: TIM5 Input 1 is selected to be connected to IC1.
  • TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 1 is selected to be connected to IC2.
TIM5_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1200 of file stm8s_tim5.c.

References TIM5_CCER1_CC1E, TIM5_CCER1_CC1P, TIM5_CCMR_CCxS, TIM5_CCMR_ICxF, and TIM5_ICPOLARITY_RISING.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

static void TI2_Config | ( | uint8_t | TIM5_ICPolarity,
 |  | uint8_t | TIM5_ICSelection,
 |  | uint8_t | TIM5_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIM5_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM5_ICPOLARITY_FALLING
  • TIM5_ICPOLARITY_RISING
TIM5_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM5_ICSELECTION_DIRECTTI: TIM5 Input 2 is selected to be connected to IC2.
  • TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 2 is selected to be connected to IC1.
TIM5_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1241 of file stm8s_tim5.c.

References TIM5_CCER1_CC2E, TIM5_CCER1_CC2P, TIM5_CCMR_CCxS, TIM5_CCMR_ICxF, and TIM5_ICPOLARITY_RISING.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

static void TI3_Config | ( | uint8_t | TIM5_ICPolarity,
 |  | uint8_t | TIM5_ICSelection,
 |  | uint8_t | TIM5_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIM5_ICPolarity The Input Polarity. This parameter can be one of the following values:

  • TIM5_ICPOLARITY_FALLING
  • TIM5_ICPOLARITY_RISING
TIM5_ICSelection specifies the input to be used. This parameter can be one of the following values:

  • TIM5_ICSELECTION_DIRECTTI: TIM5 Input 3 is selected to be connected to IC3.
TIM5_ICFilter Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 1282 of file stm8s_tim5.c.

References TIM5_CCER2_CC3E, TIM5_CCER2_CC3P, TIM5_CCMR_CCxS, TIM5_CCMR_ICxF, and TIM5_ICPOLARITY_RISING.

Referenced by TIM5_ICInit().

void TIM5_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM5 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM5 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 568 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_ARPE.

void TIM5_CCxCmd | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM5 Capture Compare Channel x.

Parameters:
TIM5_Channel specifies the TIM5 Channel. This parameter can be one of the following values:

  • TIM5_Channel1: TIM5 Channel1
  • TIM5_Channel2: TIM5 Channel2
  • TIM5_Channel3: TIM5 Channel3
NewState specifies the TIM5 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 760 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM5_CHANNEL_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC2E, TIM5_CCER2_CC3E, TIM5_CHANNEL_1, and TIM5_CHANNEL_2.

void TIM5_ClearFlag ( TIM5_FLAG_TypeDef TIM5_FLAG )

Clears the TIM5’s pending flags.

Parameters:
TIM5_FLAG specifies the flag to clear. This parameter can be one of the following values:

  • TIM5_FLAG_UPDATE: TIM5 update Flag
  • TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
  • TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
  • TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
  • TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
  • TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
  • TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
Return values:
None.

Definition at line 1118 of file stm8s_tim5.c.

References IS_TIM5_CLEAR_FLAG_OK.

void TIM5_ClearITPendingBit ( TIM5_IT_TypeDef TIM5_IT )

Clears the TIM5's interrupt pending bits.

Parameters:
TIM5_IT specifies the pending bit to clear. This parameter can be one of the following values:

  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
Return values:
None.

Definition at line 1174 of file stm8s_tim5.c.

References IS_TIM5_IT_OK.

void TIM5_Cmd ( FunctionalState NewState )

Enables or disables the TIM5 peripheral.

Parameters:
NewState new state of the TIM5 peripheral.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 340 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_CEN.

void TIM5_DeInit ( void )

Deinitializes the TIM5 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 46 of file stm8s_tim5.c.

References TIM5_ARRH_RESET_VALUE, TIM5_ARRL_RESET_VALUE, TIM5_CCER1_RESET_VALUE, TIM5_CCER2_RESET_VALUE, TIM5_CCMR1_RESET_VALUE, TIM5_CCMR2_RESET_VALUE, TIM5_CCMR3_RESET_VALUE, TIM5_CCR1H_RESET_VALUE, TIM5_CCR1L_RESET_VALUE, TIM5_CCR2H_RESET_VALUE, TIM5_CCR2L_RESET_VALUE, TIM5_CCR3H_RESET_VALUE, TIM5_CCR3L_RESET_VALUE, TIM5_CNTRH_RESET_VALUE, TIM5_CNTRL_RESET_VALUE, TIM5_CR1_RESET_VALUE, TIM5_CR2_RESET_VALUE, TIM5_IER_RESET_VALUE, TIM5_PSCR_RESET_VALUE, TIM5_SMCR_RESET_VALUE, TIM5_SR1_RESET_VALUE, and TIM5_SR2_RESET_VALUE.

void TIM5_EncoderInterfaceConfig | ( | TIM5_EncoderMode_TypeDef | TIM5_EncoderMode,
 |  | TIM5_ICPolarity_TypeDef | TIM5_IC1Polarity,
 |  | TIM5_ICPolarity_TypeDef | TIM5_IC2Polarity
 | ) |  |

Configures the TIM5 Encoder Interface.

Parameters:
TIM5_EncoderMode | : Specifies the TIM5 Encoder Mode. This parameter can be one of the TIM5_EncoderMode_TypeDef enumeration.
TIM5_IC1Polarity | : Specifies the IC1 Polarity. This parameter can be one of the TIM5_ICPolarity_TypeDef enumeration.
TIM5_IC2Polarity | : Specifies the IC2 Polarity. This parameter can be one of the TIM5_ICPolarity_TypeDef enumeration.
Return values:
None

Definition at line 1394 of file stm8s_tim5.c.

References IS_TIM5_ENCODER_MODE_OK, IS_TIM5_IC_POLARITY_OK, TIM5_CCER1_CC1P, TIM5_CCER1_CC2P, TIM5_CCMR_CCxS, TIM5_CCMR_TIxDirect_Set, TIM5_ICPOLARITY_FALLING, TIM5_SMCR_MSM, and TIM5_SMCR_TS.

void TIM5_ForcedOC1Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel1 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 513 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_ForcedOC2Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel2 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 532 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_ForcedOC3Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel3 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 551 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_GenerateEvent ( TIM5_EventSource_TypeDef TIM5_EventSource )

Configures the TIM5 event to be generated by software.

Parameters:
TIM5_EventSource specifies the event source. This parameter can be one of the following values:

  • TIM5_EVENTSOURCE_UPDATE: TIM5 update Event source
  • TIM5_EVENTSOURCE_CC1: TIM5 Capture Compare 1 Event source
  • TIM5_EVENTSOURCE_CC2: TIM5 Capture Compare 2 Event source
  • TIM5_EVENTSOURCE_CC3: TIM5 Capture Compare 3 Event source
Return values:
None

Definition at line 664 of file stm8s_tim5.c.

References IS_TIM5_EVENT_SOURCE_OK.

uint16_t TIM5_GetCapture1 ( void )

Gets the TIM5 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 1002 of file stm8s_tim5.c.

uint16_t TIM5_GetCapture2 ( void )

Gets the TIM5 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 1017 of file stm8s_tim5.c.

uint16_t TIM5_GetCapture3 ( void )

Gets the TIM5 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 1032 of file stm8s_tim5.c.

uint16_t TIM5_GetCounter ( void )

Gets the TIM5 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 1046 of file stm8s_tim5.c.

FlagStatus TIM5_GetFlagStatus ( TIM5_FLAG_TypeDef TIM5_FLAG )

Checks whether the specified TIM5 flag is set or not.

Parameters:
TIM5_FLAG specifies the flag to check. This parameter can be one of the following values:

  • TIM5_FLAG_UPDATE: TIM5 update Flag
  • TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
  • TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
  • TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
  • TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
  • TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
  • TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
Return values:
FlagStatus The new state of TIM5_FLAG (SET or RESET).

Definition at line 1082 of file stm8s_tim5.c.

References IS_TIM5_GET_FLAG_OK, RESET, and SET.

ITStatus TIM5_GetITStatus ( TIM5_IT_TypeDef TIM5_IT )

Checks whether the TIM5 interrupt has occurred or not.

Parameters:
TIM5_IT specifies the TIM5 interrupt source to check. This parameter can be one of the following values:

  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
Return values:
ITStatus The new state of the TIM5_IT(SET or RESET).

Definition at line 1140 of file stm8s_tim5.c.

References IS_TIM5_GET_IT_OK, RESET, and SET.

TIM5_Prescaler_TypeDef TIM5_GetPrescaler ( void )

Gets the TIM5 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM5_Prescaler_TypeDef .

Definition at line 1061 of file stm8s_tim5.c.

void TIM5_ICInit | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_ICPolarity_TypeDef | TIM5_ICPolarity,
 |  | TIM5_ICSelection_TypeDef | TIM5_ICSelection,
 |  | TIM5_ICPSC_TypeDef | TIM5_ICPrescaler,
 |  | uint8_t | TIM5_ICFilter
 | ) |  |

Initializes the TIM5 peripheral according to the specified parameters.

Parameters:
TIM5_Channel | specifies the Input Capture Channel from TIM5_Channel_TypeDef.
TIM5_ICPolarity | specifies the Input Capture Polarity from TIM5_ICPolarity_TypeDef.
TIM5_ICSelection | specifies theInput Capture Selection from TIM5_ICSelection_TypeDef.
TIM5_ICPrescaler | specifies the Input Capture Prescaler from TIM5_ICPSC_TypeDef.
TIM5_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 211 of file stm8s_tim5.c.

References IS_TIM5_CHANNEL_OK, IS_TIM5_IC_FILTER_OK, IS_TIM5_IC_POLARITY_OK, IS_TIM5_IC_PRESCALER_OK, IS_TIM5_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TIM5_CHANNEL_1, TIM5_CHANNEL_2, TIM5_SetIC1Prescaler(), TIM5_SetIC2Prescaler(), and TIM5_SetIC3Prescaler().

void TIM5_InternalClockConfig ( void )

Enables the TIM5 internal Clock.

Parameters:
None
Return values:
None

Definition at line 1311 of file stm8s_tim5.c.

References TIM5_SMCR_SMS.

void TIM5_ITConfig | ( | TIM5_IT_TypeDef | TIM5_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM5 interrupts.

Parameters:
NewState | new state of the TIM5 peripheral. This parameter can be: ENABLE or DISABLE.
TIM5_IT specifies the TIM5 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
NewState | new state of the TIM5 peripheral.
Return values:
None

Definition at line 370 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM5_IT_OK.

void TIM5_OC1Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel1 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 106 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC1P, and TIM5_CCMR_OCM.

void TIM5_OC1PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 1 polarity.

Parameters:
TIM5_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:

  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 682 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER1_CC1P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 591 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_OC2Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel2 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 140 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER1_CC2E, TIM5_CCER1_CC2P, and TIM5_CCMR_OCM.

void TIM5_OC2PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 2 polarity.

Parameters:
TIM5_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:

  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 707 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER1_CC2P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 614 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_OC3Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel3 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 177 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER2_CC3E, TIM5_CCER2_CC3P, and TIM5_CCMR_OCM.

void TIM5_OC3PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 3 polarity.

Parameters:
TIM5_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:

  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 732 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER2_CC3P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 637 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_PrescalerConfig | ( | TIM5_Prescaler_TypeDef | Prescaler,
 |  | TIM5_PSCReloadMode_TypeDef | TIM5_PSCReloadMode
 | ) |  |

Configures the TIM5 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values

  • TIM5_PRESCALER_1
  • TIM5_PRESCALER_2
  • TIM5_PRESCALER_4
  • TIM5_PRESCALER_8
  • TIM5_PRESCALER_16
  • TIM5_PRESCALER_32
  • TIM5_PRESCALER_64
  • TIM5_PRESCALER_128
  • TIM5_PRESCALER_256
  • TIM5_PRESCALER_512
  • TIM5_PRESCALER_1024
  • TIM5_PRESCALER_2048
  • TIM5_PRESCALER_4096
  • TIM5_PRESCALER_8192
  • TIM5_PRESCALER_16384
  • TIM5_PRESCALER_32768
TIM5_PSCReloadMode specifies the TIM5 Prescaler Reload mode. This parameter can be one of the following values

  • TIM5_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediatly.
  • TIM5_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 490 of file stm8s_tim5.c.

References IS_TIM5_PRESCALER_OK, and IS_TIM5_PRESCALER_RELOAD_OK.

void TIM5_PWMIConfig | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_ICPolarity_TypeDef | TIM5_ICPolarity,
 |  | TIM5_ICSelection_TypeDef | TIM5_ICSelection,
 |  | TIM5_ICPSC_TypeDef | TIM5_ICPrescaler,
 |  | uint8_t | TIM5_ICFilter
 | ) |  |

Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM5_Channel | specifies the Input Capture Channel from TIM5_Channel_TypeDef.
TIM5_ICPolarity | specifies the Input Capture Polarity from TIM5_ICPolarity_TypeDef.
TIM5_ICSelection | specifies theInput Capture Selection from TIM5_ICSelection_TypeDef.
TIM5_ICPrescaler | specifies the Input Capture Prescaler from TIM5_ICPSC_TypeDef.
TIM5_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 266 of file stm8s_tim5.c.

References IS_TIM5_IC_POLARITY_OK, IS_TIM5_IC_PRESCALER_OK, IS_TIM5_IC_SELECTION_OK, IS_TIM5_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM5_CHANNEL_1, TIM5_ICPOLARITY_FALLING, TIM5_ICPOLARITY_RISING, TIM5_ICSELECTION_DIRECTTI, TIM5_ICSELECTION_INDIRECTTI, TIM5_SetIC1Prescaler(), and TIM5_SetIC2Prescaler().

void TIM5_SelectInputTrigger ( TIM5_TS_TypeDef TIM5_InputTriggerSource )

Selects the TIM5 Input Trigger source.

Parameters:
TIM5_InputTriggerSource : Specifies Input Trigger source. This parameter can be one of the TIM5_TS_TypeDef enumeration.
Return values:
None

Definition at line 1369 of file stm8s_tim5.c.

References IS_TIM5_TRIGGER_SELECTION_OK, and TIM5_SMCR_TS.

void TIM5_SelectOCxM | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_OCMode_TypeDef | TIM5_OCMode
 | ) |  |

Selects the TIM5 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM5_CCxCmd and TIM5_CCxNCmd functions.

Parameters:
TIM5_Channel specifies the TIM5 Channel. This parameter can be one of the following values:

  • TIM5_Channel1: TIM5 Channel1
  • TIM5_Channel2: TIM5 Channel2
  • TIM5_Channel3: TIM5 Channel3
TIM5_OCMode specifies the TIM5 Output Compare Mode. This paramter can be one of the following values:

  • TIM5_OCMODE_TIMING
  • TIM5_OCMODE_ACTIVE
  • TIM5_OCMODE_TOGGLE
  • TIM5_OCMODE_PWM1
  • TIM5_OCMODE_PWM2
  • TIM5_FORCEDACTION_ACTIVE
  • TIM5_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 825 of file stm8s_tim5.c.

References IS_TIM5_CHANNEL_OK, IS_TIM5_OCM_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC2E, TIM5_CCER2_CC3E, TIM5_CCMR_OCM, TIM5_CHANNEL_1, and TIM5_CHANNEL_2.

void TIM5_SelectOnePulseMode ( TIM5_OPMode_TypeDef TIM5_OPMode )

Selects the TIM5’s One Pulse Mode.

Parameters:
TIM5_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values

  • TIM5_OPMODE_SINGLE
  • TIM5_OPMODE_REPETITIVE
Return values:
None

Definition at line 444 of file stm8s_tim5.c.

References IS_TIM5_OPM_MODE_OK, TIM5_CR1_OPM, and TIM5_OPMODE_REPETITIVE.

void TIM5_SelectOutputTrigger ( TIM5_TRGOSource_TypeDef TIM5_TRGOSource )

Selects the TIM5 Trigger Output Mode.

Parameters:
TIM5_TRGOSource : Specifies the Trigger Output source. This parameter can be one of the TIM5_TRGOSource_TypeDef enumeration.
Return values:
None

Definition at line 1323 of file stm8s_tim5.c.

References IS_TIM5_TRGO_SOURCE_OK, and TIM5_CR2_MMS.

void TIM5_SelectSlaveMode ( TIM5_SlaveMode_TypeDef TIM5_SlaveMode )

Selects the TIM5 Slave Mode.

Parameters:
TIM5_SlaveMode : Specifies the TIM5 Slave Mode. This parameter can be one of the TIM5_SlaveMode_TypeDef enumeration.
Return values:
None

Definition at line 1346 of file stm8s_tim5.c.

References IS_TIM5_SLAVE_MODE_OK, and TIM5_SMCR_SMS.

void TIM5_SetAutoreload ( uint16_t Autoreload )

Sets the TIM5 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 882 of file stm8s_tim5.c.

void TIM5_SetCompare1 ( uint16_t Compare1 )

Sets the TIM5 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 898 of file stm8s_tim5.c.

void TIM5_SetCompare2 ( uint16_t Compare2 )

Sets the TIM5 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 913 of file stm8s_tim5.c.

void TIM5_SetCompare3 ( uint16_t Compare3 )

Sets the TIM5 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 928 of file stm8s_tim5.c.

void TIM5_SetCounter ( uint16_t Counter )

Sets the TIM5 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 867 of file stm8s_tim5.c.

void TIM5_SetIC1Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC1Prescaler )

Sets the TIM5 Input Capture 1 prescaler.

Parameters:
TIM5_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 947 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

void TIM5_SetIC2Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC2Prescaler )

Sets the TIM5 Input Capture 2 prescaler.

Parameters:
TIM5_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 967 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

void TIM5_SetIC3Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC3Prescaler )

Sets the TIM5 Input Capture 3 prescaler.

Parameters:
TIM5_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 987 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit().

void TIM5_TimeBaseInit | ( | TIM5_Prescaler_TypeDef | TIM5_Prescaler,
 |  | uint16_t | TIM5_Period
 | ) |  |

Initializes the TIM5 Time Base Unit according to the specified parameters.

Parameters:
TIM5_Prescaler | specifies the Prescaler from TIM5_Prescaler_TypeDef.
TIM5_Period | specifies the Period value.
Return values:
None

Definition at line 87 of file stm8s_tim5.c.

void TIM5_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM5 Update event.

Parameters:
NewState new state of the TIM5 peripheral Preload register.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 395 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_UDIS.

void TIM5_UpdateRequestConfig ( TIM5_UpdateSource_TypeDef TIM5_UpdateSource )

Selects the TIM5 Update Request Interrupt source.

Parameters:
TIM5_UpdateSource specifies the Update source. This parameter can be one of the following values

  • TIM5_UPDATESOURCE_REGULAR
  • TIM5_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 419 of file stm8s_tim5.c.

References IS_TIM5_UPDATE_SOURCE_OK, TIM5_CR1_URS, and TIM5_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM6_Public_Functions

Functions

TIM6_Public_Functions

STM8S_StdPeriph_Driver

Functions

void | TIM6_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM6 peripheral Preload register on ARR.
void | TIM6_ClearFlag (TIM6_FLAG_TypeDef TIM6_FLAG)
Clears the TIM’s pending flags.
void | TIM6_ClearITPendingBit (TIM6_IT_TypeDef TIM6_IT)
Clears the TIM6's interrupt pending bits.
void | TIM6_Cmd (FunctionalState NewState)
Enables or disables the TIM6 peripheral.
void | TIM6_DeInit (void)
Deinitializes the TIM6 peripheral registers to their default reset values.
void | TIM6_GenerateEvent (TIM6_EventSource_TypeDef TIM6_EventSource)
Configures the TIM6 event to be generated by software.
uint8_t | TIM6_GetCounter (void)
Gets the TIM6 Counter value.
FlagStatus | TIM6_GetFlagStatus (TIM6_FLAG_TypeDef TIM6_FLAG)
Checks whether the specified TIM6 flag is set or not.
ITStatus | TIM6_GetITStatus (TIM6_IT_TypeDef TIM6_IT)
Checks whether the TIM6 interrupt has occurred or not.
TIM6_Prescaler_TypeDef | TIM6_GetPrescaler (void)
Gets the TIM6 Prescaler value.
void | TIM6_InternalClockConfig (void)
Enables the TIM6 internal Clock.
void | TIM6_ITConfig (TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)
Enables or disables the specified TIM6 interrupts.
void | TIM6_PrescalerConfig (TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)
Configures the TIM6 Prescaler.
void | TIM6_SelectInputTrigger (TIM6_TS_TypeDef TIM6_InputTriggerSource)
Selects the TIM6 Input Trigger source.
void | TIM6_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM6 Master/Slave Mode.
void | TIM6_SelectOnePulseMode (TIM6_OPMode_TypeDef TIM6_OPMode)
Selects the TIM6’s One Pulse Mode.
void | TIM6_SelectOutputTrigger (TIM6_TRGOSource_TypeDef TIM6_TRGOSource)
Selects the TIM6 Trigger Output Mode.
void | TIM6_SelectSlaveMode (TIM6_SlaveMode_TypeDef TIM6_SlaveMode)
Selects the TIM6 Slave Mode.
void | TIM6_SetAutoreload (uint8_t Autoreload)
Sets the TIM6 Autoreload Register value.
void | TIM6_SetCounter (uint8_t Counter)
Sets the TIM6 Counter Register value.
void | TIM6_TimeBaseInit (TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period)
Initializes the TIM6 Time Base Unit according to the specified parameters.
void | TIM6_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM6 Update event.
void | TIM6_UpdateRequestConfig (TIM6_UpdateSource_TypeDef TIM6_UpdateSource)
Selects the TIM6 Update Request Interrupt source.

Function Documentation

void TIM6_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM6 peripheral Preload register on ARR.

Parameters:
NewState : The new state of the TIM6 peripheral Preload register. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 205 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_ARPE.

void TIM6_ClearFlag ( TIM6_FLAG_TypeDef TIM6_FLAG )

Clears the TIM’s pending flags.

Parameters:
TIM6_FLAG : Specifies the flag to clear. This parameter can be one of the TIM6_FLAG_TypeDef enumeration.
Return values:
None

Definition at line 305 of file stm8s_tim6.c.

References IS_TIM6_CLEAR_FLAG_OK.

void TIM6_ClearITPendingBit ( TIM6_IT_TypeDef TIM6_IT )

Clears the TIM6's interrupt pending bits.

Parameters:
TIM6_IT : Specifies the pending bit to clear. This parameter can be one of the TIM6_IT_TypeDef enumeration.
Return values:
None

Definition at line 390 of file stm8s_tim6.c.

References IS_TIM6_IT_OK.

void TIM6_Cmd ( FunctionalState NewState )

Enables or disables the TIM6 peripheral.

Parameters:
NewState : The new state of the TIM6 peripheral. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 87 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_CEN.

void TIM6_DeInit ( void )

Deinitializes the TIM6 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 51 of file stm8s_tim6.c.

References TIM6_ARR_RESET_VALUE, TIM6_CNTR_RESET_VALUE, TIM6_CR1_RESET_VALUE, TIM6_CR2_RESET_VALUE, TIM6_IER_RESET_VALUE, TIM6_PSCR_RESET_VALUE, TIM6_SMCR_RESET_VALUE, and TIM6_SR1_RESET_VALUE.

void TIM6_GenerateEvent ( TIM6_EventSource_TypeDef TIM6_EventSource )

Configures the TIM6 event to be generated by software.

Parameters:
TIM6_EventSource : Specifies the event source. This parameter can be one of the TIM6_EventSource_TypeDef enumeration.
Return values:
None

Definition at line 350 of file stm8s_tim6.c.

References IS_TIM6_EVENT_SOURCE_OK.

uint8_t TIM6_GetCounter ( void )

Gets the TIM6 Counter value.

Parameters:
None
Return values:
uint8_t,: Counter Register value.

Definition at line 251 of file stm8s_tim6.c.

FlagStatus TIM6_GetFlagStatus ( TIM6_FLAG_TypeDef TIM6_FLAG )

Checks whether the specified TIM6 flag is set or not.

Parameters:
TIM6_FLAG : Specifies the flag to check. This parameter can be one of the TIM6_FLAG_TypeDef enumeration.
Return values:
FlagStatus : The new state of TIM6_FLAG. This parameter can be any of the FlagStatus enumeration.

Definition at line 366 of file stm8s_tim6.c.

References IS_TIM6_GET_FLAG_OK, RESET, and SET.

ITStatus TIM6_GetITStatus ( TIM6_IT_TypeDef TIM6_IT )

Checks whether the TIM6 interrupt has occurred or not.

Parameters:
TIM6_IT : Specifies the TIM6 interrupt source to check. This parameter can be one of the TIM6_IT_TypeDef enumeration.
Return values:
ITStatus : The new state of the TIM6_IT. This parameter can be any of the ITStatus enumeration.

Definition at line 321 of file stm8s_tim6.c.

References IS_TIM6_GET_IT_OK, RESET, and SET.

TIM6_Prescaler_TypeDef TIM6_GetPrescaler ( void )

Gets the TIM6 Prescaler value.

Parameters:
None
Return values:
TIM6_Prescaler_TypeDef : Prescaler Register configuration value.

Definition at line 264 of file stm8s_tim6.c.

void TIM6_InternalClockConfig ( void )

Enables the TIM6 internal Clock.

Parameters:
None
Return values:
None

Definition at line 473 of file stm8s_tim6.c.

References TIM6_SMCR_SMS.

void TIM6_ITConfig | ( | TIM6_IT_TypeDef | TIM6_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM6 interrupts.

Parameters:
TIM6_IT | : Specifies the TIM6 interrupts sources to be enabled or disabled. This parameter can be any combination of the TIM6_IT_TypeDef enumeration.
NewState | : The new state of the TIM6 peripheral. This parameter can be any of the FunctionalState enumeration.
Return values:
None
Required preconditions:
If QST option bit is enabled, the TIM6 Interrupt vector will be mapped on IRQ number 2 (irq0). Otherwise, it will be mapped on IRQ number 27 (irq25).

Definition at line 281 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM6_IT_OK.

void TIM6_PrescalerConfig | ( | TIM6_Prescaler_TypeDef | Prescaler,
 |  | TIM6_PSCReloadMode_TypeDef | TIM6_PSCReloadMode
 | ) |  |

Configures the TIM6 Prescaler.

Parameters:
Prescaler | : Specifies the Prescaler Register value This parameter can be one of the TIM6_Prescaler_TypeDef enumeration.
TIM6_PSCReloadMode | : Specifies the TIM6 Prescaler Reload mode. This parameter can be one of the TIM6_PSCReloadMode_TypeDef enumeration.
Return values:
None

Definition at line 178 of file stm8s_tim6.c.

References IS_TIM6_PRESCALER_OK, IS_TIM6_PRESCALER_RELOAD_OK, TIM6_EGR_UG, and TIM6_PSCRELOADMODE_IMMEDIATE.

void TIM6_SelectInputTrigger ( TIM6_TS_TypeDef TIM6_InputTriggerSource )

Selects the TIM6 Input Trigger source.

Parameters:
TIM6_InputTriggerSource : Specifies Input Trigger source. This parameter can be one of the TIM6_TS_TypeDef enumeration.
Return values:
None

Definition at line 452 of file stm8s_tim6.c.

References IS_TIM6_TRIGGER_SELECTION_OK, and TIM6_SMCR_TS.

void TIM6_SelectMasterSlaveMode ( FunctionalState NewState )

Sets or Resets the TIM6 Master/Slave Mode.

Parameters:
NewState : The new state of the synchronization between TIM6 and its slaves (through TRGO). This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 430 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_SMCR_MSM.

void TIM6_SelectOnePulseMode ( TIM6_OPMode_TypeDef TIM6_OPMode )

Selects the TIM6’s One Pulse Mode.

Parameters:
TIM6_OPMode : Specifies the OPM Mode to be used. This parameter can be one of the TIM6_OPMode_TypeDef enumeration.
Return values:
None

Definition at line 153 of file stm8s_tim6.c.

References IS_TIM6_OPM_MODE_OK, TIM6_CR1_OPM, and TIM6_OPMODE_SINGLE.

void TIM6_SelectOutputTrigger ( TIM6_TRGOSource_TypeDef TIM6_TRGOSource )

Selects the TIM6 Trigger Output Mode.

Parameters:
TIM6_TRGOSource : Specifies the Trigger Output source. This parameter can be one of the TIM6_TRGOSource_TypeDef enumeration.
Return values:
None

Definition at line 405 of file stm8s_tim6.c.

References IS_TIM6_TRGO_SOURCE_OK, and TIM6_CR2_MMS.

void TIM6_SelectSlaveMode ( TIM6_SlaveMode_TypeDef TIM6_SlaveMode )

Selects the TIM6 Slave Mode.

Parameters:
TIM6_SlaveMode : Specifies the TIM6 Slave Mode. This parameter can be one of the TIM6_SlaveMode_TypeDef enumeration.
Return values:
None

Definition at line 485 of file stm8s_tim6.c.

References IS_TIM6_SLAVE_MODE_OK, and TIM6_SMCR_SMS.

void TIM6_SetAutoreload ( uint8_t Autoreload )

Sets the TIM6 Autoreload Register value.

Parameters:
Autoreload : Specifies the Autoreload register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 239 of file stm8s_tim6.c.

void TIM6_SetCounter ( uint8_t Counter )

Sets the TIM6 Counter Register value.

Parameters:
Counter : Specifies the Counter register new value. This parameter is between 0x00 and 0xFF.
Return values:
None

Definition at line 227 of file stm8s_tim6.c.

void TIM6_TimeBaseInit | ( | TIM6_Prescaler_TypeDef | TIM6_Prescaler,
 |  | uint8_t | TIM6_Period
 | ) |  |

Initializes the TIM6 Time Base Unit according to the specified parameters.

Parameters:
TIM6_Prescaler | : This parameter can be any of the TIM5_Prescaler_TypeDef enumeration.
TIM6_Period | : This parameter must be a value between 0x00 and 0xFF.
Return values:
None

Definition at line 70 of file stm8s_tim6.c.

References IS_TIM6_PRESCALER_OK.

void TIM6_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM6 Update event.

Parameters:
NewState : The new state of the TIM6 peripheral Preload register. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 109 of file stm8s_tim6.c.

References ENABLE, IS_FUNCTIONALSTATE_OK, and TIM6_CR1_UDIS.

void TIM6_UpdateRequestConfig ( TIM6_UpdateSource_TypeDef TIM6_UpdateSource )

Selects the TIM6 Update Request Interrupt source.

Parameters:
TIM6_UpdateSource : Specifies the Update source. This parameter can be one of the TIM6_UpdateSource_TypeDef enumeration.
Return values:
None

Definition at line 131 of file stm8s_tim6.c.

References IS_TIM6_UPDATE_SOURCE_OK, TIM6_CR1_URS, and TIM6_UPDATESOURCE_REGULAR.


STM8S/A Standard Peripherals Drivers: WWDG_Public_Functions

Functions

WWDG_Public_Functions

STM8S_StdPeriph_Driver

Functions

uint8_t | WWDG_GetCounter (void)
Gets the WWDG Counter Value.
void | WWDG_Init (uint8_t Counter, uint8_t WindowValue)
Initializes the WWDG peripheral.
void | WWDG_SetCounter (uint8_t Counter)
Refreshes the WWDG peripheral.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.
void | WWDG_SWReset (void)
Generates immediate WWDG RESET.

Function Documentation

uint8_t WWDG_GetCounter ( void )

Gets the WWDG Counter Value.

This value could be used to check if WWDG is in the window, where refresh is allowed.

Parameters:
None
Return values:
WWDG Counter Value

Definition at line 82 of file stm8s_wwdg.c.

References WWDG.

void WWDG_Init | ( | uint8_t | Counter,
 |  | uint8_t | WindowValue
 | ) |  |

Initializes the WWDG peripheral.

This function set Window Register = WindowValue, Counter Register according to Counter and ENABLE WWDG

Parameters:
Counter | : WWDG counter value
WindowValue | : specifies the WWDG Window Register, range is 0x00 to 0x7F.
Return values:
None

Definition at line 47 of file stm8s_wwdg.c.

References IS_WWDG_WINDOWLIMITVALUE_OK, WWDG, WWDG_CR_T6, WWDG_CR_WDGA, and WWDG_WR_RESET_VALUE.

void WWDG_SetCounter ( uint8_t Counter )

Refreshes the WWDG peripheral.

Parameters:
Counter : WWDG Counter Value This parameter must be a number between 0x40 and 0x7F.
Return values:
None

Definition at line 63 of file stm8s_wwdg.c.

References BIT_MASK, IS_WWDG_COUNTERVALUE_OK, and WWDG.

void WWDG_SetWindowValue ( uint8_t WindowValue )

Sets the WWDG window value.

Parameters:
WindowValue,: specifies the window value to be compared to the downcounter. This parameter value must be lower than 0x80.
Return values:
None

Definition at line 104 of file stm8s_wwdg.c.

References IS_WWDG_WINDOWLIMITVALUE_OK, WWDG, WWDG_CR_T6, and WWDG_CR_WDGA.

void WWDG_SWReset ( void )

Generates immediate WWDG RESET.

Parameters:
None
Return values:
None

Definition at line 92 of file stm8s_wwdg.c.

References WWDG, and WWDG_CR_WDGA.


STM8S/A Standard Peripherals Drivers: STM8S_StdPeriph_Driver

Modules | Defines | Enumerations | Variables

STM8S_StdPeriph_Driver

Modules

I2C_Private_Defines
Exported_types
MAP_FILE_Exported_Types_and_Constants
IWDG_Private_Define
IWDG_Private_Macros
IWDG_Exported_Types
IWDG_Exported_Functions
RST_Exported_Types
RST_Private_Macros
RST_Exported_functions
SPI_Exported_Types
SPI_Private_Macros

Macros used by the assert_param function to check the different functions parameters.

SPI_Exported_Functions
TIM1_Exported_Types
TIM1_Exported_Functions
TIM3_Exported_Types
TIM3_Exported_Functions
TIM4_Exported_Types
TIM4_Exported_Functions
TIM6_Exported_Types
TIM6_Private_Macros
TIM6_Exported_Functions
UART1_Exported_Types
UART1_Private_Macros
UART1_Exported_Functions
UART2_Exported_Types
UART2_Private_Macros
UART2_Exported_Functions
UART3_Exported_Types
UART3_Private_Macros
UART3_Exported_Functions
WWDG_Private_Macros
WWDG_Exported_Functions
ADC1_Public_Functions
ADC2_Public_Functions
AWU_Public_Functions
BEEP_Public_Functions
CAN_Public_Functions
CLK_Private_Constants
CLK_Public_Functions
EXTI_Public_Functions
FLASH_Public_functions
GPIO_Public_Functions
I2C_Public_Functions
ITC_Private_Functions
ITC_Public_Functions
RST_Public_Functions
SPI_Public_Functions
TIM1_Public_Functions
TIM2_Public_Functions
TIM3_Public_Functions
TIM4_Public_Functions
TIM5_Public_Functions
TIM6_Public_Functions
WWDG_Public_Functions

Defines

#define | __STM8S_STDPERIPH_VERSION
#define | __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02)
#define | __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00)
#define | __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x01)
#define | __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00)
#define | BIT_MASK ((uint8_t)0x7F)
#define | CAN_ACKNOWLEDGE_TIMEOUT ((uint16_t)0xFFFF)
#define | CAN_IDLIST_IDMASK_MASK ((uint8_t) 0x55)
#define | CAN_IDMASK_IDLIST_MASK ((uint8_t) 0xAA)
#define | CAN_MODE_MASK ((uint8_t) 0x03)
#define | CONST const
#define | EEPROM __eeprom
#define | FAR __far
#define | FLASH_CLEAR_BYTE ((uint8_t)0x00)
#define | FLASH_SET_BYTE ((uint8_t)0xFF)
#define | HSE_VALUE ((u32)16000000)
In the following line adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSI_VALUE ((uint32_t)16000000)
Definition of Device on-chip RC oscillator frequencies.
#define | IN_RAM(a) a
#define | IS_TIM2_CHANNEL_OK(CHANNEL)
#define | IS_TIM2_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
#define | IS_TIM2_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM2_FORCED_ACTION_OK(ACTION)
#define | IS_TIM2_GET_FLAG_OK(FLAG)
#define | IS_TIM2_GET_IT_OK(IT)
#define | IS_TIM2_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM2 Input Capture Filer Value.
#define | IS_TIM2_IC_POLARITY_OK(POLARITY)
#define | IS_TIM2_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM2_IC_SELECTION1_OK(SELECTION)
#define | IS_TIM2_IC_SELECTION_OK(SELECTION)
#define | IS_TIM2_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x0F))
#define | IS_TIM2_OC_MODE_OK(MODE)
#define | IS_TIM2_OC_POLARITY_OK(POLARITY)
#define | IS_TIM2_OCM_OK(MODE)
#define | IS_TIM2_OPM_MODE_OK(MODE)
#define | IS_TIM2_OUTPUT_STATE_OK(STATE)
#define | IS_TIM2_PRESCALER_OK(PRESCALER)
#define | IS_TIM2_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM2_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM2_UPDATE_SOURCE_OK(SOURCE)
#define | IS_TIM5_CHANNEL_OK(CHANNEL)
#define | IS_TIM5_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
#define | IS_TIM5_ENCODER_MODE_OK(MODE)
Macro TIM5 encoder mode.
#define | IS_TIM5_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM5_EXT_FILTER_OK(EXTFILTER) ((EXTFILTER) <= 0x0F)
Macro TIM5 External Trigger Filter.
#define | IS_TIM5_EXT_POLARITY_OK(POLARITY)
Macro TIM5 Trigger Polarity.
#define | IS_TIM5_EXT_PRESCALER_OK(PRESCALER)
Macro TIM5 external trigger prescaler.
#define | IS_TIM5_FORCED_ACTION_OK(ACTION)
#define | IS_TIM5_GET_FLAG_OK(FLAG)
#define | IS_TIM5_GET_IT_OK(IT)
#define | IS_TIM5_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM5 Input Capture Filer Value.
#define | IS_TIM5_IC_POLARITY_OK(POLARITY)
#define | IS_TIM5_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM5_IC_SELECTION1_OK(SELECTION)
#define | IS_TIM5_IC_SELECTION_OK(SELECTION)
#define | IS_TIM5_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x4F))
#define | IS_TIM5_OC_MODE_OK(MODE)
#define | IS_TIM5_OC_POLARITY_OK(POLARITY)
#define | IS_TIM5_OCM_OK(MODE)
#define | IS_TIM5_OPM_MODE_OK(MODE)
#define | IS_TIM5_OUTPUT_STATE_OK(STATE)
#define | IS_TIM5_PRESCALER_OK(PRESCALER)
#define | IS_TIM5_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM5_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM5_SLAVE_MODE_OK(MODE)
Macro TIM5 Slave mode.
#define | IS_TIM5_TIX_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM5_TRGO_SOURCE_OK(SOURCE)
Macro TIM5 TRGO source.
#define | IS_TIM5_TRIGGER_SELECTION_OK(SELECTION)
Macro TIM5 Trigger Selection.
#define | IS_TIM5_UPDATE_SOURCE_OK(SOURCE)
#define | LSI_VALUE ((uint32_t)128000)
#define | NEAR __near
#define | OPERATION_TIMEOUT ((uint32_t)0xFFFFF)
#define | PointerAttr FAR
#define | TINY __tiny
#define | USE_STDPERIPH_DRIVER

Enumerations

enum | TIM2_Channel_TypeDef { TIM2_CHANNEL_1 = ((uint8_t)0x00), TIM2_CHANNEL_2 = ((uint8_t)0x01), TIM2_CHANNEL_3 = ((uint8_t)0x02) }

TIM2 Channel.

More...
enum | TIM2_EventSource_TypeDef { TIM2_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM2_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM2_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM2_EVENTSOURCE_CC3 = ((uint8_t)0x08) }

TIM2 Event Source.

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enum TIM2_FLAG_TypeDef {
TIM2_FLAG_UPDATE = ((uint16_t)0x0001), TIM2_FLAG_CC1 = ((uint16_t)0x0002), TIM2_FLAG_CC2 = ((uint16_t)0x0004), TIM2_FLAG_CC3 = ((uint16_t)0x0008),
TIM2_FLAG_CC1OF = ((uint16_t)0x0200), TIM2_FLAG_CC2OF = ((uint16_t)0x0400), TIM2_FLAG_CC3OF = ((uint16_t)0x0800)
}

TIM2 Flags.

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enum | TIM2_ForcedAction_TypeDef { TIM2_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM2_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }

TIM2 Forced Action.

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enum | TIM2_ICPolarity_TypeDef { TIM2_ICPOLARITY_RISING = ((uint8_t)0x00), TIM2_ICPOLARITY_FALLING = ((uint8_t)0x44) }

TIM2 Input Capture Polarity.

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enum | TIM2_ICPSC_TypeDef { TIM2_ICPSC_DIV1 = ((uint8_t)0x00), TIM2_ICPSC_DIV2 = ((uint8_t)0x04), TIM2_ICPSC_DIV4 = ((uint8_t)0x08), TIM2_ICPSC_DIV8 = ((uint8_t)0x0C) }

TIM2 Input Capture Prescaler.

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enum | TIM2_ICSelection_TypeDef { TIM2_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM2_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM2_ICSELECTION_TRGI = ((uint8_t)0x03) }

TIM2 Input Capture Selection.

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enum | TIM2_IT_TypeDef { TIM2_IT_UPDATE = ((uint8_t)0x01), TIM2_IT_CC1 = ((uint8_t)0x02), TIM2_IT_CC2 = ((uint8_t)0x04), TIM2_IT_CC3 = ((uint8_t)0x08) }

TIM2 interrupt sources.

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enum TIM2_OCMode_TypeDef {
TIM2_OCMODE_TIMING = ((uint8_t)0x00), TIM2_OCMODE_ACTIVE = ((uint8_t)0x10), TIM2_OCMODE_INACTIVE = ((uint8_t)0x20), TIM2_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM2_OCMODE_PWM1 = ((uint8_t)0x60), TIM2_OCMODE_PWM2 = ((uint8_t)0x70)
}

TIM2 Output Compare and PWM modes.

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enum | TIM2_OCPolarity_TypeDef { TIM2_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM2_OCPOLARITY_LOW = ((uint8_t)0x22) }

TIM2 Output Compare Polarity.

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enum | TIM2_OPMode_TypeDef { TIM2_OPMODE_SINGLE = ((uint8_t)0x01), TIM2_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM2 One Pulse Mode.

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enum | TIM2_OutputState_TypeDef { TIM2_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM2_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }

TIM2 Output Compare states.

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enum TIM2_Prescaler_TypeDef {
TIM2_PRESCALER_1 = ((uint8_t)0x00), TIM2_PRESCALER_2 = ((uint8_t)0x01), TIM2_PRESCALER_4 = ((uint8_t)0x02), TIM2_PRESCALER_8 = ((uint8_t)0x03),
TIM2_PRESCALER_16 = ((uint8_t)0x04), TIM2_PRESCALER_32 = ((uint8_t)0x05), TIM2_PRESCALER_64 = ((uint8_t)0x06), TIM2_PRESCALER_128 = ((uint8_t)0x07),
TIM2_PRESCALER_256 = ((uint8_t)0x08), TIM2_PRESCALER_512 = ((uint8_t)0x09), TIM2_PRESCALER_1024 = ((uint8_t)0x0A), TIM2_PRESCALER_2048 = ((uint8_t)0x0B),
TIM2_PRESCALER_4096 = ((uint8_t)0x0C), TIM2_PRESCALER_8192 = ((uint8_t)0x0D), TIM2_PRESCALER_16384 = ((uint8_t)0x0E), TIM2_PRESCALER_32768 = ((uint8_t)0x0F)
}

TIM2 Prescaler.

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enum | TIM2_PSCReloadMode_TypeDef { TIM2_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM2_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM2 Prescaler Reload Mode.

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enum | TIM2_UpdateSource_TypeDef { TIM2_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM2_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM2 Update Source.

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enum | TIM5_Channel_TypeDef { TIM5_CHANNEL_1 = ((uint8_t)0x00), TIM5_CHANNEL_2 = ((uint8_t)0x01), TIM5_CHANNEL_3 = ((uint8_t)0x02) }

TIM5 Channel.

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enum | TIM5_EncoderMode_TypeDef { TIM5_ENCODERMODE_TI1 = ((uint8_t)0x01), TIM5_ENCODERMODE_TI2 = ((uint8_t)0x02), TIM5_ENCODERMODE_TI12 = ((uint8_t)0x03) }

TIM5 Encoder Mode.

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enum TIM5_EventSource_TypeDef {
TIM5_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM5_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM5_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM5_EVENTSOURCE_CC3 = ((uint8_t)0x08),
TIM5_EVENTSOURCE_TRIGGER = ((uint8_t)0x40)
}

TIM5 Event Source.

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enum | TIM5_ExtTRGPolarity_TypeDef { TIM5_EXTTRGPOLARITY_INVERTED = ((uint8_t)0x80), TIM5_EXTTRGPOLARITY_NONINVERTED = ((uint8_t)0x00) }

TIM5 External Trigger Polarity.

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enum | TIM5_ExtTRGPSC_TypeDef { TIM5_EXTTRGPSC_OFF = ((uint8_t)0x00), TIM5_EXTTRGPSC_DIV2 = ((uint8_t)0x10), TIM5_EXTTRGPSC_DIV4 = ((uint8_t)0x20), TIM5_EXTTRGPSC_DIV8 = ((uint8_t)0x30) }

TIM5 External Trigger Prescaler.

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enum TIM5_FLAG_TypeDef {
TIM5_FLAG_UPDATE = ((uint16_t)0x0001), TIM5_FLAG_CC1 = ((uint16_t)0x0002), TIM5_FLAG_CC2 = ((uint16_t)0x0004), TIM5_FLAG_CC3 = ((uint16_t)0x0008),
TIM5_FLAG_TRIGGER = ((uint16_t)0x0040), TIM5_FLAG_CC1OF = ((uint16_t)0x0200), TIM5_FLAG_CC2OF = ((uint16_t)0x0400), TIM5_FLAG_CC3OF = ((uint16_t)0x0800)
}

TIM5 Flags.

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enum | TIM5_ForcedAction_TypeDef { TIM5_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM5_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }

TIM5 Forced Action.

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enum | TIM5_ICPolarity_TypeDef { TIM5_ICPOLARITY_RISING = ((uint8_t)0x00), TIM5_ICPOLARITY_FALLING = ((uint8_t)0x44) }

TIM5 Input Capture Polarity.

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enum | TIM5_ICPSC_TypeDef { TIM5_ICPSC_DIV1 = ((uint8_t)0x00), TIM5_ICPSC_DIV2 = ((uint8_t)0x04), TIM5_ICPSC_DIV4 = ((uint8_t)0x08), TIM5_ICPSC_DIV8 = ((uint8_t)0x0C) }

TIM5 Input Capture Prescaler.

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enum | TIM5_ICSelection_TypeDef { TIM5_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM5_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM5_ICSELECTION_TRGI = ((uint8_t)0x03) }

TIM5 Input Capture Selection.

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enum TIM5_IT_TypeDef {
TIM5_IT_UPDATE = ((uint8_t)0x01), TIM5_IT_CC1 = ((uint8_t)0x02), TIM5_IT_CC2 = ((uint8_t)0x04), TIM5_IT_CC3 = ((uint8_t)0x08),
TIM5_IT_TRIGGER = ((uint8_t)0x40)
}

TIM5 interrupt sources.

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enum TIM5_OCMode_TypeDef {
TIM5_OCMODE_TIMING = ((uint8_t)0x00), TIM5_OCMODE_ACTIVE = ((uint8_t)0x10), TIM5_OCMODE_INACTIVE = ((uint8_t)0x20), TIM5_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM5_OCMODE_PWM1 = ((uint8_t)0x60), TIM5_OCMODE_PWM2 = ((uint8_t)0x70)
}

TIM5 Output Compare and PWM modes.

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enum | TIM5_OCPolarity_TypeDef { TIM5_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM5_OCPOLARITY_LOW = ((uint8_t)0x22) }

TIM5 Output Compare Polarity.

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enum | TIM5_OPMode_TypeDef { TIM5_OPMODE_SINGLE = ((uint8_t)0x01), TIM5_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM5 One Pulse Mode.

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enum | TIM5_OutputState_TypeDef { TIM5_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM5_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }

TIM5 Output Compare states.

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enum TIM5_Prescaler_TypeDef {
TIM5_PRESCALER_1 = ((uint8_t)0x00), TIM5_PRESCALER_2 = ((uint8_t)0x01), TIM5_PRESCALER_4 = ((uint8_t)0x02), TIM5_PRESCALER_8 = ((uint8_t)0x03),
TIM5_PRESCALER_16 = ((uint8_t)0x04), TIM5_PRESCALER_32 = ((uint8_t)0x05), TIM5_PRESCALER_64 = ((uint8_t)0x06), TIM5_PRESCALER_128 = ((uint8_t)0x07),
TIM5_PRESCALER_256 = ((uint8_t)0x08), TIM5_PRESCALER_512 = ((uint8_t)0x09), TIM5_PRESCALER_1024 = ((uint8_t)0x0A), TIM5_PRESCALER_2048 = ((uint8_t)0x0B),
TIM5_PRESCALER_4096 = ((uint8_t)0x0C), TIM5_PRESCALER_8192 = ((uint8_t)0x0D), TIM5_PRESCALER_16384 = ((uint8_t)0x0E), TIM5_PRESCALER_32768 = ((uint8_t)0x0F)
}

TIM5 Prescaler.

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enum | TIM5_PSCReloadMode_TypeDef { TIM5_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM5_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM5 Prescaler Reload Mode.

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enum | TIM5_SlaveMode_TypeDef { TIM5_SLAVEMODE_RESET = ((uint8_t)0x04), TIM5_SLAVEMODE_GATED = ((uint8_t)0x05), TIM5_SLAVEMODE_TRIGGER = ((uint8_t)0x06), TIM5_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07) }

TIM5 Slave Mode.

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enum TIM5_TRGOSource_TypeDef {
TIM5_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM5_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM5_TRGOSOURCE_UPDATE = ((uint8_t)0x20), TIM5_TRGOSOURCE_OC1 = ((uint8_t)0x30),
TIM5_TRGOSOURCE_OC1REF = ((uint8_t)0x40), TIM5_TRGOSOURCE_OC2REF = ((uint8_t)0x50)
}

TIM5 Trigger Output Source.

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enum | TIM5_TS_TypeDef { TIM5_TS_TIM6 = ((uint8_t)0x00), TIM5_TS_TIM1 = ((uint8_t)0x03) }

TIM5 Internal Trigger Selection.

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enum | TIM5_UpdateSource_TypeDef { TIM5_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM5_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM5 Update Source.

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Variables

__IO uint8_t | _Data [8] = {0}
__IO uint8_t | _DLC = 0
__IO uint8_t | _FMI = 0
__IO uint32_t | _Id = 0
__IO uint8_t | _IDE = 0
__IO uint8_t | _RTR = 0
CONST uint8_t | APR_Array [17]
Contains the different values to write in the APR register (used by AWU_Init function)
CONST uint8_t | TBR_Array [17]
Contains the different values to write in the TBR register (used by AWU_Init function)

Define Documentation

#define __STM8S_STDPERIPH_VERSION
Value:
( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\
                                          |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\
                                          |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\
                                          |(__STM8S_STDPERIPH_VERSION_RC))

Definition at line 174 of file stm8s.h.

#define __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02)

< [31:16] STM8S Standard Peripheral Library main version V2.1.0 [31:24] main version

Definition at line 170 of file stm8s.h.

#define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00)

[7:0] release candidate

Definition at line 173 of file stm8s.h.

#define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x01)

[23:16] sub1 version

Definition at line 171 of file stm8s.h.

#define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00)

[15:8] sub2 version

Definition at line 172 of file stm8s.h.

#define BIT_MASK ((uint8_t)0x7F)

Definition at line 29 of file stm8s_wwdg.c.

Referenced by WWDG_SetCounter().

#define CAN_ACKNOWLEDGE_TIMEOUT ((uint16_t)0xFFFF)

Definition at line 33 of file stm8s_can.c.

Referenced by CAN_Init(), and CAN_OperatingModeRequest().

#define CAN_IDLIST_IDMASK_MASK ((uint8_t) 0x55)

Definition at line 30 of file stm8s_can.c.

Referenced by CAN_FilterInit().

#define CAN_IDMASK_IDLIST_MASK ((uint8_t) 0xAA)

Definition at line 31 of file stm8s_can.c.

Referenced by CAN_FilterInit().

#define CAN_MODE_MASK ((uint8_t) 0x03)

Definition at line 32 of file stm8s_can.c.

Referenced by CAN_OperatingModeRequest().

#define CONST const

Definition at line 136 of file stm8s.h.

#define EEPROM __eeprom

Definition at line 135 of file stm8s.h.

#define FAR __far

Definition at line 132 of file stm8s.h.

#define FLASH_CLEAR_BYTE ((uint8_t)0x00)
 This driver provides functions to configure and program the Flash memory of all
 STM8S devices.

 It includes as well functions that can be either executed from RAM or not, and
 other functions that must be executed from RAM otherwise useless.

 The table below lists the functions that can be executed from RAM.

 +--------------------------------------------------------------------------------|
 |   Functions prototypes      |    RAM execution            |     Comments       |
 ---------------------------------------------------------------------------------|
 |                             | Mandatory in case of block  | Can be executed    |
 | FLASH_WaitForLastOperation  | Operation:                  | from Flash in case |
 |                             | - Block programming         | of byte and word   |
 |                             | - Block erase               | Operations         |
 |--------------------------------------------------------------------------------|
 | FLASH_ProgramBlock          |       Exclusively           | useless from Flash |
 |--------------------------------------------------------------------------------|
 | FLASH_EraseBlock            |       Exclusively           | useless from Flash |
 |--------------------------------------------------------------------------------|

 To be able to execute functions from RAM several steps have to be followed.
 These steps may differ from one toolchain to another.
 A detailed description is available below within this driver.
 You can also refer to the FLASH examples provided within the
 STM8S_StdPeriph_Lib package.

Definition at line 63 of file stm8s_flash.c.

Referenced by FLASH_EraseByte(), and FLASH_EraseOptionByte().

#define FLASH_SET_BYTE ((uint8_t)0xFF)

Definition at line 64 of file stm8s_flash.c.

Referenced by FLASH_EraseOptionByte().

#define HSE_VALUE ((u32)16000000)

In the following line adjust the value of External High Speed oscillator (HSE) used in your application.

Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor.

Definition at line 101 of file stm8s.h.

Referenced by CLK_GetClockFreq().

#define HSI_VALUE ((uint32_t)16000000)

Definition of Device on-chip RC oscillator frequencies.

Typical Value of the HSI in Hz

Definition at line 108 of file stm8s.h.

Referenced by CLK_GetClockFreq().

#define IN_RAM ( a ) a

Definition at line 166 of file stm8s.h.

#define IS_TIM2_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM2_CHANNEL_1) || \
                                     ((CHANNEL) == TIM2_CHANNEL_2) || \
                                     ((CHANNEL) == TIM2_CHANNEL_3))

Definition at line 129 of file stm8s_tim2.h.

Referenced by TIM2_CCxCmd(), TIM2_ICInit(), and TIM2_SelectOCxM().

#define IS_TIM2_CLEAR_FLAG_OK ( FLAG ) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))

Definition at line 265 of file stm8s_tim2.h.

Referenced by TIM2_ClearFlag().

#define IS_TIM2_EVENT_SOURCE_OK ( SOURCE ) (((SOURCE) != 0x00))

Definition at line 233 of file stm8s_tim2.h.

Referenced by TIM2_GenerateEvent().

#define IS_TIM2_FORCED_ACTION_OK ( ACTION )
Value:
(((ACTION) == TIM2_FORCEDACTION_ACTIVE) || \
    ((ACTION) == TIM2_FORCEDACTION_INACTIVE))

Definition at line 43 of file stm8s_tim2.h.

Referenced by TIM2_ForcedOC1Config(), TIM2_ForcedOC2Config(), and TIM2_ForcedOC3Config().

#define IS_TIM2_GET_FLAG_OK ( FLAG )
Value:
(((FLAG) == TIM2_FLAG_UPDATE) || \
                                   ((FLAG) == TIM2_FLAG_CC1) || \
                                   ((FLAG) == TIM2_FLAG_CC2) || \
                                   ((FLAG) == TIM2_FLAG_CC3) || \
                                   ((FLAG) == TIM2_FLAG_CC1OF) || \
                                   ((FLAG) == TIM2_FLAG_CC2OF) || \
                                   ((FLAG) == TIM2_FLAG_CC3OF))

Definition at line 257 of file stm8s_tim2.h.

Referenced by TIM2_GetFlagStatus().

#define IS_TIM2_GET_IT_OK ( IT )
Value:
(((IT) == TIM2_IT_UPDATE) || \
                               ((IT) == TIM2_IT_CC1) || \
                               ((IT) == TIM2_IT_CC2) || \
                               ((IT) == TIM2_IT_CC3))

Definition at line 209 of file stm8s_tim2.h.

Referenced by TIM2_GetITStatus().

#define IS_TIM2_IC_FILTER_OK ( ICFILTER ) ((ICFILTER) <= 0x0F)

TIM2 Input Capture Filer Value.

Definition at line 196 of file stm8s_tim2.h.

Referenced by TIM2_ICInit().

#define IS_TIM2_IC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM2_ICPOLARITY_RISING) || \
    ((POLARITY) == TIM2_ICPOLARITY_FALLING))

Definition at line 163 of file stm8s_tim2.h.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

#define IS_TIM2_IC_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM2_ICPSC_DIV1) || \
    ((PRESCALER) == TIM2_ICPSC_DIV2) || \
    ((PRESCALER) == TIM2_ICPSC_DIV4) || \
    ((PRESCALER) == TIM2_ICPSC_DIV8))

Definition at line 190 of file stm8s_tim2.h.

Referenced by TIM2_ICInit(), TIM2_PWMIConfig(), TIM2_SetIC1Prescaler(), TIM2_SetIC2Prescaler(), and TIM2_SetIC3Prescaler().

#define IS_TIM2_IC_SELECTION1_OK ( SELECTION )
Value:
(((SELECTION) == TIM2_ICSELECTION_DIRECTTI) || \
    ((SELECTION) == TIM2_ICSELECTION_TRGI))

Definition at line 178 of file stm8s_tim2.h.

#define IS_TIM2_IC_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM2_ICSELECTION_DIRECTTI) || \
    ((SELECTION) == TIM2_ICSELECTION_INDIRECTTI) || \
    ((SELECTION) == TIM2_ICSELECTION_TRGI))

Definition at line 174 of file stm8s_tim2.h.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

#define IS_TIM2_IT_OK ( IT ) (((IT) != 0x00) && ((IT) <= 0x0F))

Definition at line 207 of file stm8s_tim2.h.

Referenced by TIM2_ClearITPendingBit(), and TIM2_ITConfig().

#define IS_TIM2_OC_MODE_OK ( MODE )
Value:
(((MODE) ==  TIM2_OCMODE_TIMING) || \
                                  ((MODE) == TIM2_OCMODE_ACTIVE) || \
                                  ((MODE) == TIM2_OCMODE_INACTIVE) || \
                                  ((MODE) == TIM2_OCMODE_TOGGLE)|| \
                                  ((MODE) == TIM2_OCMODE_PWM1) || \
                                  ((MODE) == TIM2_OCMODE_PWM2))

Definition at line 95 of file stm8s_tim2.h.

Referenced by TIM2_OC1Init(), TIM2_OC2Init(), and TIM2_OC3Init().

#define IS_TIM2_OC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM2_OCPOLARITY_HIGH) || \
    ((POLARITY) == TIM2_OCPOLARITY_LOW))

Definition at line 143 of file stm8s_tim2.h.

Referenced by TIM2_OC1Init(), TIM2_OC1PolarityConfig(), TIM2_OC2Init(), TIM2_OC2PolarityConfig(), TIM2_OC3Init(), and TIM2_OC3PolarityConfig().

#define IS_TIM2_OCM_OK ( MODE )
Value:
(((MODE) ==  TIM2_OCMODE_TIMING) || \
                             ((MODE) == TIM2_OCMODE_ACTIVE) || \
                             ((MODE) == TIM2_OCMODE_INACTIVE) || \
                             ((MODE) == TIM2_OCMODE_TOGGLE)|| \
                             ((MODE) == TIM2_OCMODE_PWM1) || \
                             ((MODE) == TIM2_OCMODE_PWM2) || \
                             ((MODE) == (uint8_t)TIM2_FORCEDACTION_ACTIVE) || \
                             ((MODE) == (uint8_t)TIM2_FORCEDACTION_INACTIVE))

Definition at line 102 of file stm8s_tim2.h.

Referenced by TIM2_SelectOCxM().

#define IS_TIM2_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM2_OPMODE_SINGLE) || \
                                   ((MODE) == TIM2_OPMODE_REPETITIVE))

Definition at line 118 of file stm8s_tim2.h.

Referenced by TIM2_SelectOnePulseMode().

#define IS_TIM2_OUTPUT_STATE_OK ( STATE )
Value:
(((STATE) == TIM2_OUTPUTSTATE_DISABLE) || \
                                        ((STATE) == TIM2_OUTPUTSTATE_ENABLE))

Definition at line 153 of file stm8s_tim2.h.

Referenced by TIM2_OC1Init(), TIM2_OC2Init(), and TIM2_OC3Init().

#define IS_TIM2_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM2_PRESCALER_1  ) || \
    ((PRESCALER) == TIM2_PRESCALER_2    ) || \
    ((PRESCALER) == TIM2_PRESCALER_4    ) || \
    ((PRESCALER) == TIM2_PRESCALER_8  ) || \
    ((PRESCALER) == TIM2_PRESCALER_16   ) || \
    ((PRESCALER) == TIM2_PRESCALER_32     ) || \
    ((PRESCALER) == TIM2_PRESCALER_64    ) || \
    ((PRESCALER) == TIM2_PRESCALER_128   ) || \
    ((PRESCALER) == TIM2_PRESCALER_256   ) || \
    ((PRESCALER) == TIM2_PRESCALER_512   ) || \
    ((PRESCALER) == TIM2_PRESCALER_1024  ) || \
    ((PRESCALER) == TIM2_PRESCALER_2048 ) || \
    ((PRESCALER) == TIM2_PRESCALER_4096 ) || \
    ((PRESCALER) == TIM2_PRESCALER_8192 ) || \
    ((PRESCALER) == TIM2_PRESCALER_16384 ) || \
    ((PRESCALER) == TIM2_PRESCALER_32768 ))

Definition at line 67 of file stm8s_tim2.h.

Referenced by TIM2_PrescalerConfig().

#define IS_TIM2_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM2_PSCRELOADMODE_UPDATE) || \
    ((RELOAD) == TIM2_PSCRELOADMODE_IMMEDIATE))

Definition at line 221 of file stm8s_tim2.h.

Referenced by TIM2_PrescalerConfig().

#define IS_TIM2_PWMI_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM2_CHANNEL_1) || \
    ((CHANNEL) == TIM2_CHANNEL_2))

Definition at line 133 of file stm8s_tim2.h.

Referenced by TIM2_PWMIConfig().

#define IS_TIM2_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM2_UPDATESOURCE_GLOBAL) || \
    ((SOURCE) == TIM2_UPDATESOURCE_REGULAR))

Definition at line 242 of file stm8s_tim2.h.

Referenced by TIM2_UpdateRequestConfig().

#define IS_TIM5_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM5_CHANNEL_1) || \
                                     ((CHANNEL) == TIM5_CHANNEL_2) || \
                                     ((CHANNEL) == TIM5_CHANNEL_3))

Definition at line 129 of file stm8s_tim5.h.

Referenced by TIM5_CCxCmd(), TIM5_ICInit(), and TIM5_SelectOCxM().

#define IS_TIM5_CLEAR_FLAG_OK ( FLAG ) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))

Definition at line 295 of file stm8s_tim5.h.

Referenced by TIM5_ClearFlag().

#define IS_TIM5_ENCODER_MODE_OK ( MODE )
Value:
(((MODE) == TIM5_ENCODERMODE_TI1) || \
    ((MODE) == TIM5_ENCODERMODE_TI2) || \
    ((MODE) == TIM5_ENCODERMODE_TI12))

Macro TIM5 encoder mode.

Definition at line 353 of file stm8s_tim5.h.

Referenced by TIM5_EncoderInterfaceConfig().

#define IS_TIM5_EVENT_SOURCE_OK ( SOURCE ) (((SOURCE) != 0x00))

Definition at line 236 of file stm8s_tim5.h.

Referenced by TIM5_GenerateEvent().

#define IS_TIM5_EXT_FILTER_OK ( EXTFILTER ) ((EXTFILTER) <= 0x0F)

Macro TIM5 External Trigger Filter.

Definition at line 397 of file stm8s_tim5.h.

#define IS_TIM5_EXT_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM5_EXTTRGPOLARITY_INVERTED) || \
    ((POLARITY) == TIM5_EXTTRGPOLARITY_NONINVERTED))

Macro TIM5 Trigger Polarity.

Definition at line 390 of file stm8s_tim5.h.

#define IS_TIM5_EXT_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM5_EXTTRGPSC_OFF)  || \
    ((PRESCALER) == TIM5_EXTTRGPSC_DIV2) || \
    ((PRESCALER) == TIM5_EXTTRGPSC_DIV4) || \
    ((PRESCALER) == TIM5_EXTTRGPSC_DIV8))

Macro TIM5 external trigger prescaler.

Definition at line 372 of file stm8s_tim5.h.

#define IS_TIM5_FORCED_ACTION_OK ( ACTION )
Value:
(((ACTION) == TIM5_FORCEDACTION_ACTIVE) || \
                                       ((ACTION) == TIM5_FORCEDACTION_INACTIVE))

Definition at line 43 of file stm8s_tim5.h.

Referenced by TIM5_ForcedOC1Config(), TIM5_ForcedOC2Config(), and TIM5_ForcedOC3Config().

#define IS_TIM5_GET_FLAG_OK ( FLAG )
Value:
(((FLAG) == TIM5_FLAG_UPDATE) || \
                                ((FLAG) == TIM5_FLAG_CC1) || \
                                ((FLAG) == TIM5_FLAG_CC2) || \
                                ((FLAG) == TIM5_FLAG_CC3) || \
                                ((FLAG) == TIM5_FLAG_TRIGGER) || \
                                ((FLAG) == TIM5_FLAG_CC1OF) || \
                                ((FLAG) == TIM5_FLAG_CC2OF) || \
                                ((FLAG) == TIM5_FLAG_CC3OF))

Definition at line 286 of file stm8s_tim5.h.

Referenced by TIM5_GetFlagStatus().

#define IS_TIM5_GET_IT_OK ( IT )
Value:
(((IT) == TIM5_IT_UPDATE) || \
                            ((IT) == TIM5_IT_CC1) || \
                            ((IT) == TIM5_IT_CC2) || \
                            ((IT) == TIM5_IT_CC3) || \
                            ((IT) == TIM5_IT_TRIGGER))

Definition at line 210 of file stm8s_tim5.h.

Referenced by TIM5_GetITStatus().

#define IS_TIM5_IC_FILTER_OK ( ICFILTER ) ((ICFILTER) <= 0x0F)

TIM5 Input Capture Filer Value.

Definition at line 196 of file stm8s_tim5.h.

Referenced by TIM5_ICInit().

#define IS_TIM5_IC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM5_ICPOLARITY_RISING) || \
                                       ((POLARITY) == TIM5_ICPOLARITY_FALLING))

Definition at line 163 of file stm8s_tim5.h.

Referenced by TIM5_EncoderInterfaceConfig(), TIM5_ICInit(), and TIM5_PWMIConfig().

#define IS_TIM5_IC_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM5_ICPSC_DIV1) || \
                                         ((PRESCALER) == TIM5_ICPSC_DIV2) || \
                                         ((PRESCALER) == TIM5_ICPSC_DIV4) || \
                                         ((PRESCALER) == TIM5_ICPSC_DIV8))

Definition at line 190 of file stm8s_tim5.h.

Referenced by TIM5_ICInit(), TIM5_PWMIConfig(), TIM5_SetIC1Prescaler(), TIM5_SetIC2Prescaler(), and TIM5_SetIC3Prescaler().

#define IS_TIM5_IC_SELECTION1_OK ( SELECTION )
Value:
(((SELECTION) == TIM5_ICSELECTION_DIRECTTI) || \
                                             ((SELECTION) == TIM5_ICSELECTION_TRGI))

Definition at line 178 of file stm8s_tim5.h.

#define IS_TIM5_IC_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM5_ICSELECTION_DIRECTTI) || \
                                           ((SELECTION) == TIM5_ICSELECTION_INDIRECTTI) || \
                                           ((SELECTION) == TIM5_ICSELECTION_TRGI))

Definition at line 174 of file stm8s_tim5.h.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

#define IS_TIM5_IT_OK ( IT ) (((IT) != 0x00) && ((IT) <= 0x4F))

Definition at line 208 of file stm8s_tim5.h.

Referenced by TIM5_ClearITPendingBit(), and TIM5_ITConfig().

#define IS_TIM5_OC_MODE_OK ( MODE )
Value:
(((MODE) ==  TIM5_OCMODE_TIMING) || \
                                  ((MODE) == TIM5_OCMODE_ACTIVE) || \
                                  ((MODE) == TIM5_OCMODE_INACTIVE) || \
                                  ((MODE) == TIM5_OCMODE_TOGGLE)|| \
                                  ((MODE) == TIM5_OCMODE_PWM1) || \
                                  ((MODE) == TIM5_OCMODE_PWM2))

Definition at line 95 of file stm8s_tim5.h.

Referenced by TIM5_OC1Init(), TIM5_OC2Init(), and TIM5_OC3Init().

#define IS_TIM5_OC_POLARITY_OK ( POLARITY )
Value:
(((POLARITY) == TIM5_OCPOLARITY_HIGH) || \
                                       ((POLARITY) == TIM5_OCPOLARITY_LOW))

Definition at line 143 of file stm8s_tim5.h.

Referenced by TIM5_OC1Init(), TIM5_OC1PolarityConfig(), TIM5_OC2Init(), TIM5_OC2PolarityConfig(), TIM5_OC3Init(), and TIM5_OC3PolarityConfig().

#define IS_TIM5_OCM_OK ( MODE )
Value:
(((MODE) ==  TIM5_OCMODE_TIMING) || \
                             ((MODE) == TIM5_OCMODE_ACTIVE) || \
                             ((MODE) == TIM5_OCMODE_INACTIVE) || \
                             ((MODE) == TIM5_OCMODE_TOGGLE)|| \
                             ((MODE) == TIM5_OCMODE_PWM1) || \
                             ((MODE) == TIM5_OCMODE_PWM2) ||  \
                             ((MODE) == (uint8_t)TIM5_FORCEDACTION_ACTIVE) || \
                             ((MODE) == (uint8_t)TIM5_FORCEDACTION_INACTIVE))

Definition at line 102 of file stm8s_tim5.h.

Referenced by TIM5_SelectOCxM().

#define IS_TIM5_OPM_MODE_OK ( MODE )
Value:
(((MODE) == TIM5_OPMODE_SINGLE) || \
                                   ((MODE) == TIM5_OPMODE_REPETITIVE))

Definition at line 118 of file stm8s_tim5.h.

Referenced by TIM5_SelectOnePulseMode().

#define IS_TIM5_OUTPUT_STATE_OK ( STATE )
Value:
(((STATE) == TIM5_OUTPUTSTATE_DISABLE) || \
                                     ((STATE) == TIM5_OUTPUTSTATE_ENABLE))

Definition at line 153 of file stm8s_tim5.h.

Referenced by TIM5_OC1Init(), TIM5_OC2Init(), and TIM5_OC3Init().

#define IS_TIM5_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == TIM5_PRESCALER_1) || \
                 ((PRESCALER) == TIM5_PRESCALER_2     ) || \
                 ((PRESCALER) == TIM5_PRESCALER_4     ) || \
                 ((PRESCALER) == TIM5_PRESCALER_8    ) || \
                 ((PRESCALER) == TIM5_PRESCALER_16    ) || \
                 ((PRESCALER) == TIM5_PRESCALER_32      ) || \
                 ((PRESCALER) == TIM5_PRESCALER_64     ) || \
                 ((PRESCALER) == TIM5_PRESCALER_128    ) || \
                 ((PRESCALER) == TIM5_PRESCALER_256    ) || \
                 ((PRESCALER) == TIM5_PRESCALER_512    ) || \
                 ((PRESCALER) == TIM5_PRESCALER_1024   ) || \
                 ((PRESCALER) == TIM5_PRESCALER_2048  ) || \
                 ((PRESCALER) == TIM5_PRESCALER_4096  ) || \
                 ((PRESCALER) == TIM5_PRESCALER_8192  ) || \
                 ((PRESCALER) == TIM5_PRESCALER_16384  ) || \
                 ((PRESCALER) == TIM5_PRESCALER_32768  ))

Definition at line 67 of file stm8s_tim5.h.

Referenced by TIM5_PrescalerConfig().

#define IS_TIM5_PRESCALER_RELOAD_OK ( RELOAD )
Value:
(((RELOAD) == TIM5_PSCRELOADMODE_UPDATE) || \
                                          ((RELOAD) == TIM5_PSCRELOADMODE_IMMEDIATE))

Definition at line 223 of file stm8s_tim5.h.

Referenced by TIM5_PrescalerConfig().

#define IS_TIM5_PWMI_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == TIM5_CHANNEL_1) || \
                                          ((CHANNEL) == TIM5_CHANNEL_2))

Definition at line 133 of file stm8s_tim5.h.

Referenced by TIM5_PWMIConfig().

#define IS_TIM5_SLAVE_MODE_OK ( MODE )
Value:
(((MODE) == TIM5_SLAVEMODE_RESET)   || \
    ((MODE) == TIM5_SLAVEMODE_GATED)   || \
    ((MODE) == TIM5_SLAVEMODE_TRIGGER) || \
    ((MODE) == TIM5_SLAVEMODE_EXTERNAL1))

Macro TIM5 Slave mode.

Definition at line 312 of file stm8s_tim5.h.

Referenced by TIM5_SelectSlaveMode().

#define IS_TIM5_TIX_TRIGGER_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM5_TS_TI1F_ED) || \
    ((SELECTION) == TIM5_TS_TI1FP1)  || \
    ((SELECTION) == TIM5_TS_TI2FP2))

Definition at line 335 of file stm8s_tim5.h.

#define IS_TIM5_TRGO_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM5_TRGOSOURCE_RESET)  || \
    ((SOURCE) == TIM5_TRGOSOURCE_ENABLE) || \
    ((SOURCE) == TIM5_TRGOSOURCE_UPDATE) || \
    ((SOURCE) == TIM5_TRGOSOURCE_OC1)    || \
    ((SOURCE) == TIM5_TRGOSOURCE_OC1REF) || \
    ((SOURCE) == TIM5_TRGOSOURCE_OC2REF))

Macro TIM5 TRGO source.

Definition at line 265 of file stm8s_tim5.h.

Referenced by TIM5_SelectOutputTrigger().

#define IS_TIM5_TRIGGER_SELECTION_OK ( SELECTION )
Value:
(((SELECTION) == TIM5_TS_TIM6)  || \
    ((SELECTION) == TIM5_TS_TIM1)  )

Macro TIM5 Trigger Selection.

Definition at line 330 of file stm8s_tim5.h.

Referenced by TIM5_SelectInputTrigger().

#define IS_TIM5_UPDATE_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == TIM5_UPDATESOURCE_GLOBAL) || \
                                       ((SOURCE) == TIM5_UPDATESOURCE_REGULAR))

Definition at line 246 of file stm8s_tim5.h.

Referenced by TIM5_UpdateRequestConfig().

#define LSI_VALUE ((uint32_t)128000)

Typical Value of the LSI in Hz

Definition at line 109 of file stm8s.h.

Referenced by CLK_GetClockFreq().

#define NEAR __near

Definition at line 133 of file stm8s.h.

Referenced by FLASH_EraseOptionByte(), FLASH_ProgramOptionByte(), and FLASH_ReadOptionByte().

#define OPERATION_TIMEOUT ((uint32_t)0xFFFFF)

Definition at line 65 of file stm8s_flash.c.

#define PointerAttr FAR

< Used with memory Models for code higher than 64K

Definition at line 149 of file stm8s.h.

Referenced by FLASH_EraseByte(), FLASH_ProgramByte(), FLASH_ProgramWord(), and FLASH_ReadByte().

#define TINY __tiny

Definition at line 134 of file stm8s.h.

#define USE_STDPERIPH_DRIVER

< STM8S High density devices with CAN

< STM8S High density devices without CAN

< STM8S Value Line High density devices

< STM8A High density devices with CAN

< STM8A High density devices without CAN

< STM8S Medium density devices

< STM8S Value Line Medium density devices

< STM8A Medium density devices

< STM8S Low density devices

< STM8S Value Line Low density devices

< STM8S Low density devices

Definition at line 86 of file stm8s.h.

Enumeration Type Documentation

enum TIM2_Channel_TypeDef

TIM2 Channel.

Enumerator:
TIM2_CHANNEL_1
TIM2_CHANNEL_2
TIM2_CHANNEL_3

Definition at line 122 of file stm8s_tim2.h.

enum TIM2_EventSource_TypeDef

TIM2 Event Source.

Enumerator:
TIM2_EVENTSOURCE_UPDATE
TIM2_EVENTSOURCE_CC1
TIM2_EVENTSOURCE_CC2
TIM2_EVENTSOURCE_CC3

Definition at line 225 of file stm8s_tim2.h.

enum TIM2_FLAG_TypeDef

TIM2 Flags.

Enumerator:
TIM2_FLAG_UPDATE
TIM2_FLAG_CC1
TIM2_FLAG_CC2
TIM2_FLAG_CC3
TIM2_FLAG_CC1OF
TIM2_FLAG_CC2OF
TIM2_FLAG_CC3OF

Definition at line 246 of file stm8s_tim2.h.

enum TIM2_ForcedAction_TypeDef

TIM2 Forced Action.

Enumerator:
TIM2_FORCEDACTION_ACTIVE
TIM2_FORCEDACTION_INACTIVE

Definition at line 37 of file stm8s_tim2.h.

enum TIM2_ICPolarity_TypeDef

TIM2 Input Capture Polarity.

Enumerator:
TIM2_ICPOLARITY_RISING
TIM2_ICPOLARITY_FALLING

Definition at line 157 of file stm8s_tim2.h.

enum TIM2_ICPSC_TypeDef

TIM2 Input Capture Prescaler.

Enumerator:
TIM2_ICPSC_DIV1
TIM2_ICPSC_DIV2
TIM2_ICPSC_DIV4
TIM2_ICPSC_DIV8

Definition at line 182 of file stm8s_tim2.h.

enum TIM2_ICSelection_TypeDef

TIM2 Input Capture Selection.

Enumerator:
TIM2_ICSELECTION_DIRECTTI
TIM2_ICSELECTION_INDIRECTTI
TIM2_ICSELECTION_TRGI

Definition at line 167 of file stm8s_tim2.h.

enum TIM2_IT_TypeDef

TIM2 interrupt sources.

Enumerator:
TIM2_IT_UPDATE
TIM2_IT_CC1
TIM2_IT_CC2
TIM2_IT_CC3

Definition at line 199 of file stm8s_tim2.h.

enum TIM2_OCMode_TypeDef

TIM2 Output Compare and PWM modes.

Enumerator:
TIM2_OCMODE_TIMING
TIM2_OCMODE_ACTIVE
TIM2_OCMODE_INACTIVE
TIM2_OCMODE_TOGGLE
TIM2_OCMODE_PWM1
TIM2_OCMODE_PWM2

Definition at line 85 of file stm8s_tim2.h.

enum TIM2_OCPolarity_TypeDef

TIM2 Output Compare Polarity.

Enumerator:
TIM2_OCPOLARITY_HIGH
TIM2_OCPOLARITY_LOW

Definition at line 137 of file stm8s_tim2.h.

enum TIM2_OPMode_TypeDef

TIM2 One Pulse Mode.

Enumerator:
TIM2_OPMODE_SINGLE
TIM2_OPMODE_REPETITIVE

Definition at line 112 of file stm8s_tim2.h.

enum TIM2_OutputState_TypeDef

TIM2 Output Compare states.

Enumerator:
TIM2_OUTPUTSTATE_DISABLE
TIM2_OUTPUTSTATE_ENABLE

Definition at line 147 of file stm8s_tim2.h.

enum TIM2_Prescaler_TypeDef

TIM2 Prescaler.

Enumerator:
TIM2_PRESCALER_1
TIM2_PRESCALER_2
TIM2_PRESCALER_4
TIM2_PRESCALER_8
TIM2_PRESCALER_16
TIM2_PRESCALER_32
TIM2_PRESCALER_64
TIM2_PRESCALER_128
TIM2_PRESCALER_256
TIM2_PRESCALER_512
TIM2_PRESCALER_1024
TIM2_PRESCALER_2048
TIM2_PRESCALER_4096
TIM2_PRESCALER_8192
TIM2_PRESCALER_16384
TIM2_PRESCALER_32768

Definition at line 47 of file stm8s_tim2.h.

enum TIM2_PSCReloadMode_TypeDef

TIM2 Prescaler Reload Mode.

Enumerator:
TIM2_PSCRELOADMODE_UPDATE
TIM2_PSCRELOADMODE_IMMEDIATE

Definition at line 215 of file stm8s_tim2.h.

enum TIM2_UpdateSource_TypeDef

TIM2 Update Source.

Enumerator:
TIM2_UPDATESOURCE_GLOBAL
TIM2_UPDATESOURCE_REGULAR

Definition at line 236 of file stm8s_tim2.h.

enum TIM5_Channel_TypeDef

TIM5 Channel.

Enumerator:
TIM5_CHANNEL_1
TIM5_CHANNEL_2
TIM5_CHANNEL_3

Definition at line 122 of file stm8s_tim5.h.

enum TIM5_EncoderMode_TypeDef

TIM5 Encoder Mode.

Enumerator:
TIM5_ENCODERMODE_TI1

Encoder mode 1

TIM5_ENCODERMODE_TI2

Encoder mode 2

TIM5_ENCODERMODE_TI12

Encoder mode 3

Definition at line 344 of file stm8s_tim5.h.

enum TIM5_EventSource_TypeDef

TIM5 Event Source.

Enumerator:
TIM5_EVENTSOURCE_UPDATE
TIM5_EVENTSOURCE_CC1
TIM5_EVENTSOURCE_CC2
TIM5_EVENTSOURCE_CC3
TIM5_EVENTSOURCE_TRIGGER

Definition at line 227 of file stm8s_tim5.h.

enum TIM5_ExtTRGPolarity_TypeDef

TIM5 External Trigger Polarity.

Enumerator:
TIM5_EXTTRGPOLARITY_INVERTED

External Trigger Polarity = inverted

TIM5_EXTTRGPOLARITY_NONINVERTED

External Trigger Polarity = non inverted

Definition at line 381 of file stm8s_tim5.h.

enum TIM5_ExtTRGPSC_TypeDef

TIM5 External Trigger Prescaler.

Enumerator:
TIM5_EXTTRGPSC_OFF

No External Trigger prescaler

TIM5_EXTTRGPSC_DIV2

External Trigger prescaler = 2 (ETRP frequency divided by 2)

TIM5_EXTTRGPSC_DIV4

External Trigger prescaler = 4 (ETRP frequency divided by 4)

TIM5_EXTTRGPSC_DIV8

External Trigger prescaler = 8 (ETRP frequency divided by 8)

Definition at line 361 of file stm8s_tim5.h.

enum TIM5_FLAG_TypeDef

TIM5 Flags.

Enumerator:
TIM5_FLAG_UPDATE
TIM5_FLAG_CC1
TIM5_FLAG_CC2
TIM5_FLAG_CC3
TIM5_FLAG_TRIGGER
TIM5_FLAG_CC1OF
TIM5_FLAG_CC2OF
TIM5_FLAG_CC3OF

Definition at line 274 of file stm8s_tim5.h.

enum TIM5_ForcedAction_TypeDef

TIM5 Forced Action.

Enumerator:
TIM5_FORCEDACTION_ACTIVE
TIM5_FORCEDACTION_INACTIVE

Definition at line 37 of file stm8s_tim5.h.

enum TIM5_ICPolarity_TypeDef

TIM5 Input Capture Polarity.

Enumerator:
TIM5_ICPOLARITY_RISING
TIM5_ICPOLARITY_FALLING

Definition at line 157 of file stm8s_tim5.h.

enum TIM5_ICPSC_TypeDef

TIM5 Input Capture Prescaler.

Enumerator:
TIM5_ICPSC_DIV1
TIM5_ICPSC_DIV2
TIM5_ICPSC_DIV4
TIM5_ICPSC_DIV8

Definition at line 182 of file stm8s_tim5.h.

enum TIM5_ICSelection_TypeDef

TIM5 Input Capture Selection.

Enumerator:
TIM5_ICSELECTION_DIRECTTI
TIM5_ICSELECTION_INDIRECTTI
TIM5_ICSELECTION_TRGI

Definition at line 167 of file stm8s_tim5.h.

enum TIM5_IT_TypeDef

TIM5 interrupt sources.

Enumerator:
TIM5_IT_UPDATE
TIM5_IT_CC1
TIM5_IT_CC2
TIM5_IT_CC3
TIM5_IT_TRIGGER

Definition at line 199 of file stm8s_tim5.h.

enum TIM5_OCMode_TypeDef

TIM5 Output Compare and PWM modes.

Enumerator:
TIM5_OCMODE_TIMING
TIM5_OCMODE_ACTIVE
TIM5_OCMODE_INACTIVE
TIM5_OCMODE_TOGGLE
TIM5_OCMODE_PWM1
TIM5_OCMODE_PWM2

Definition at line 85 of file stm8s_tim5.h.

enum TIM5_OCPolarity_TypeDef

TIM5 Output Compare Polarity.

Enumerator:
TIM5_OCPOLARITY_HIGH
TIM5_OCPOLARITY_LOW

Definition at line 137 of file stm8s_tim5.h.

enum TIM5_OPMode_TypeDef

TIM5 One Pulse Mode.

Enumerator:
TIM5_OPMODE_SINGLE
TIM5_OPMODE_REPETITIVE

Definition at line 112 of file stm8s_tim5.h.

enum TIM5_OutputState_TypeDef

TIM5 Output Compare states.

Enumerator:
TIM5_OUTPUTSTATE_DISABLE
TIM5_OUTPUTSTATE_ENABLE

Definition at line 147 of file stm8s_tim5.h.

enum TIM5_Prescaler_TypeDef

TIM5 Prescaler.

Enumerator:
TIM5_PRESCALER_1
TIM5_PRESCALER_2
TIM5_PRESCALER_4
TIM5_PRESCALER_8
TIM5_PRESCALER_16
TIM5_PRESCALER_32
TIM5_PRESCALER_64
TIM5_PRESCALER_128
TIM5_PRESCALER_256
TIM5_PRESCALER_512
TIM5_PRESCALER_1024
TIM5_PRESCALER_2048
TIM5_PRESCALER_4096
TIM5_PRESCALER_8192
TIM5_PRESCALER_16384
TIM5_PRESCALER_32768

Definition at line 47 of file stm8s_tim5.h.

enum TIM5_PSCReloadMode_TypeDef

TIM5 Prescaler Reload Mode.

Enumerator:
TIM5_PSCRELOADMODE_UPDATE
TIM5_PSCRELOADMODE_IMMEDIATE

Definition at line 217 of file stm8s_tim5.h.

enum TIM5_SlaveMode_TypeDef

TIM5 Slave Mode.

Enumerator:
TIM5_SLAVEMODE_RESET

Slave Mode Selection = Reset

TIM5_SLAVEMODE_GATED

Slave Mode Selection = Gated

TIM5_SLAVEMODE_TRIGGER

Slave Mode Selection = Trigger

TIM5_SLAVEMODE_EXTERNAL1

Slave Mode Selection = External 1

Definition at line 301 of file stm8s_tim5.h.

enum TIM5_TRGOSource_TypeDef

TIM5 Trigger Output Source.

Enumerator:
TIM5_TRGOSOURCE_RESET

Trigger Output source = Reset

TIM5_TRGOSOURCE_ENABLE

Trigger Output source = TIM5 is enabled

TIM5_TRGOSOURCE_UPDATE

Trigger Output source = Update event

TIM5_TRGOSOURCE_OC1

Trigger Output source = output compare channel1

TIM5_TRGOSOURCE_OC1REF

Trigger Output source = output compare channel 1 reference

TIM5_TRGOSOURCE_OC2REF

Trigger Output source = output compare channel 2 reference

Definition at line 252 of file stm8s_tim5.h.

enum TIM5_TS_TypeDef

TIM5 Internal Trigger Selection.

Enumerator:
TIM5_TS_TIM6

TRIG Input source = TIM6 TRIG Output

TIM5_TS_TIM1

TRIG Input source = TIM1 TRIG Output

Definition at line 321 of file stm8s_tim5.h.

enum TIM5_UpdateSource_TypeDef

TIM5 Update Source.

Enumerator:
TIM5_UPDATESOURCE_GLOBAL
TIM5_UPDATESOURCE_REGULAR

Definition at line 239 of file stm8s_tim5.h.

Variable Documentation

__IO uint8_t _Data[8] = {0}

Definition at line 40 of file stm8s_can.c.

Referenced by CAN_GetReceivedData(), and CAN_Receive().

__IO uint8_t _DLC = 0

Definition at line 39 of file stm8s_can.c.

Referenced by CAN_GetReceivedDLC(), and CAN_Receive().

__IO uint8_t _FMI = 0

Definition at line 41 of file stm8s_can.c.

Referenced by CAN_GetReceivedFMI(), and CAN_Receive().

__IO uint32_t _Id = 0

Definition at line 36 of file stm8s_can.c.

Referenced by CAN_GetReceivedId(), and CAN_Receive().

__IO uint8_t _IDE = 0

Definition at line 37 of file stm8s_can.c.

Referenced by CAN_GetReceivedIDE(), and CAN_Receive().

__IO uint8_t _RTR = 0

Definition at line 38 of file stm8s_can.c.

Referenced by CAN_GetReceivedRTR(), and CAN_Receive().

CONST uint8_t APR_Array[17]
Initial value:
    {
        0, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 61, 23, 23, 62
    }

Contains the different values to write in the APR register (used by AWU_Init function)

Definition at line 43 of file stm8s_awu.c.

Referenced by AWU_Init().

CONST uint8_t TBR_Array[17]
Initial value:
    {
        0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 12, 14, 15, 15
    }

Contains the different values to write in the TBR register (used by AWU_Init function)

Definition at line 49 of file stm8s_awu.c.

Referenced by AWU_Init().


STM8S/A Standard Peripherals Drivers: AWU_Registers_Reset_Value

Defines

AWU_Registers_Reset_Value

Defines

#define | AWU_APR_RESET_VALUE ((uint8_t)0x3F)
#define | AWU_CSR_RESET_VALUE ((uint8_t)0x00)
#define | AWU_TBR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define AWU_APR_RESET_VALUE ((uint8_t)0x3F)

Definition at line 436 of file stm8s.h.

Referenced by AWU_DeInit().

#define AWU_CSR_RESET_VALUE ((uint8_t)0x00)

Definition at line 435 of file stm8s.h.

Referenced by AWU_DeInit().

#define AWU_TBR_RESET_VALUE ((uint8_t)0x00)

Definition at line 437 of file stm8s.h.

Referenced by AWU_DeInit().


STM8S/A Standard Peripherals Drivers: AWU_Registers_Bits_Definition

Defines

AWU_Registers_Bits_Definition

Defines

#define | AWU_APR_APR ((uint8_t)0x3F)
#define | AWU_CSR_AWUEN ((uint8_t)0x10)
#define | AWU_CSR_AWUF ((uint8_t)0x20)
#define | AWU_CSR_MSR ((uint8_t)0x01)
#define | AWU_TBR_AWUTB ((uint8_t)0x0F)

Define Documentation

#define AWU_APR_APR ((uint8_t)0x3F)

Asynchronous Prescaler divider mask

Definition at line 451 of file stm8s.h.

Referenced by AWU_Init().

#define AWU_CSR_AWUEN ((uint8_t)0x10)

Auto Wake-up enable mask

Definition at line 448 of file stm8s.h.

Referenced by AWU_Cmd(), AWU_IdleModeEnable(), and AWU_Init().

#define AWU_CSR_AWUF ((uint8_t)0x20)

Interrupt flag mask

Definition at line 447 of file stm8s.h.

Referenced by AWU_GetFlagStatus().

#define AWU_CSR_MSR ((uint8_t)0x01)

LSI Measurement enable mask

Definition at line 449 of file stm8s.h.

#define AWU_TBR_AWUTB ((uint8_t)0x0F)

Timebase selection mask

Definition at line 453 of file stm8s.h.

Referenced by AWU_IdleModeEnable(), and AWU_Init().


STM8S/A Standard Peripherals Drivers: BEEP_Registers_Reset_Value

Defines

BEEP_Registers_Reset_Value

Defines

#define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)

Define Documentation

#define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)

Definition at line 473 of file stm8s.h.

Referenced by BEEP_DeInit().


STM8S/A Standard Peripherals Drivers: BEEP_Registers_Bits_Definition

Defines

BEEP_Registers_Bits_Definition

Defines

#define | BEEP_CSR_BEEPDIV ((uint8_t)0x1F)
#define | BEEP_CSR_BEEPEN ((uint8_t)0x20)
#define | BEEP_CSR_BEEPSEL ((uint8_t)0xC0)

Define Documentation

#define BEEP_CSR_BEEPDIV ((uint8_t)0x1F)

Beeper Divider prescalar mask

Definition at line 483 of file stm8s.h.

Referenced by BEEP_Init(), and BEEP_LSICalibrationConfig().

#define BEEP_CSR_BEEPEN ((uint8_t)0x20)

Beeper enable mask

Definition at line 482 of file stm8s.h.

Referenced by BEEP_Cmd().

#define BEEP_CSR_BEEPSEL ((uint8_t)0xC0)

Beeper frequency selection mask

Definition at line 481 of file stm8s.h.

Referenced by BEEP_Init().


STM8S/A Standard Peripherals Drivers: CLK_Registers_Reset_Value

Defines

CLK_Registers_Reset_Value

Defines

#define | CLK_CCOR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)
#define | CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)
#define | CLK_CSSR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_ECKR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_ICKR_RESET_VALUE ((uint8_t)0x01)
#define | CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)
#define | CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)
#define | CLK_SWCR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_SWR_RESET_VALUE ((uint8_t)0xE1)

Define Documentation

#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00)

Definition at line 524 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)

Definition at line 520 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)

Definition at line 517 of file stm8s.h.

#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00)

Definition at line 523 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_ECKR_RESET_VALUE ((uint8_t)0x00)

Definition at line 516 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)

Definition at line 525 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_ICKR_RESET_VALUE ((uint8_t)0x01)

Definition at line 515 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)

Definition at line 521 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)

Definition at line 522 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 519 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 526 of file stm8s.h.

Referenced by CLK_DeInit().

#define CLK_SWR_RESET_VALUE ((uint8_t)0xE1)

Definition at line 518 of file stm8s.h.

Referenced by CLK_DeInit().


STM8S/A Standard Peripherals Drivers: CLK_Registers_Bits_Definition

Defines

CLK_Registers_Bits_Definition

Defines

#define | CLK_CCOR_CCOBSY ((uint8_t)0x40)
#define | CLK_CCOR_CCOEN ((uint8_t)0x01)
#define | CLK_CCOR_CCORDY ((uint8_t)0x20)
#define | CLK_CCOR_CCOSEL ((uint8_t)0x1E)
#define | CLK_CKDIVR_CPUDIV ((uint8_t)0x07)
#define | CLK_CKDIVR_HSIDIV ((uint8_t)0x18)
#define | CLK_CMSR_CKM ((uint8_t)0xFF)
#define | CLK_CSSR_AUX ((uint8_t)0x02)
#define | CLK_CSSR_CSSD ((uint8_t)0x08)
#define | CLK_CSSR_CSSDIE ((uint8_t)0x04)
#define | CLK_CSSR_CSSEN ((uint8_t)0x01)
#define | CLK_ECKR_HSEEN ((uint8_t)0x01)
#define | CLK_ECKR_HSERDY ((uint8_t)0x02)
#define | CLK_HSITRIMR_HSITRIM ((uint8_t)0x07)
#define | CLK_ICKR_FHWU ((uint8_t)0x04)
#define | CLK_ICKR_HSIEN ((uint8_t)0x01)
#define | CLK_ICKR_HSIRDY ((uint8_t)0x02)
#define | CLK_ICKR_LSIEN ((uint8_t)0x08)
#define | CLK_ICKR_LSIRDY ((uint8_t)0x10)
#define | CLK_ICKR_SWUAH ((uint8_t)0x20)
#define | CLK_PCKENR1_I2C ((uint8_t)0x01)
#define | CLK_PCKENR1_SPI ((uint8_t)0x02)
#define | CLK_PCKENR1_TIM1 ((uint8_t)0x80)
#define | CLK_PCKENR1_TIM2 ((uint8_t)0x20)
#define | CLK_PCKENR1_TIM3 ((uint8_t)0x40)
#define | CLK_PCKENR1_TIM4 ((uint8_t)0x10)
#define | CLK_PCKENR1_TIM5 ((uint8_t)0x20)
#define | CLK_PCKENR1_TIM6 ((uint8_t)0x10)
#define | CLK_PCKENR1_UART1 ((uint8_t)0x04)
#define | CLK_PCKENR1_UART2 ((uint8_t)0x08)
#define | CLK_PCKENR1_UART3 ((uint8_t)0x08)
#define | CLK_PCKENR2_ADC ((uint8_t)0x08)
#define | CLK_PCKENR2_AWU ((uint8_t)0x04)
#define | CLK_PCKENR2_CAN ((uint8_t)0x80)
#define | CLK_SWCR_SWBSY ((uint8_t)0x01)
#define | CLK_SWCR_SWEN ((uint8_t)0x02)
#define | CLK_SWCR_SWIEN ((uint8_t)0x04)
#define | CLK_SWCR_SWIF ((uint8_t)0x08)
#define | CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01)
#define | CLK_SWR_SWI ((uint8_t)0xFF)

Define Documentation

#define CLK_CCOR_CCOBSY ((uint8_t)0x40)

Configurable clock output busy

Definition at line 578 of file stm8s.h.

#define CLK_CCOR_CCOEN ((uint8_t)0x01)

Configurable clock output enable

Definition at line 581 of file stm8s.h.

Referenced by CLK_CCOCmd(), CLK_CCOConfig(), and CLK_DeInit().

#define CLK_CCOR_CCORDY ((uint8_t)0x20)

Configurable clock output ready

Definition at line 579 of file stm8s.h.

#define CLK_CCOR_CCOSEL ((uint8_t)0x1E)

Configurable clock output selection

Definition at line 580 of file stm8s.h.

Referenced by CLK_CCOConfig().

#define CLK_CKDIVR_CPUDIV ((uint8_t)0x07)

CPU clock prescaler

Definition at line 555 of file stm8s.h.

Referenced by CLK_SYSCLKConfig().

#define CLK_CKDIVR_HSIDIV ((uint8_t)0x18)

High speed internal clock prescaler

Definition at line 554 of file stm8s.h.

Referenced by CLK_GetClockFreq(), CLK_HSIPrescalerConfig(), and CLK_SYSCLKConfig().

#define CLK_CMSR_CKM ((uint8_t)0xFF)

Clock master status bits

Definition at line 545 of file stm8s.h.

#define CLK_CSSR_AUX ((uint8_t)0x02)

Auxiliary oscillator connected to master clock

Definition at line 575 of file stm8s.h.

#define CLK_CSSR_CSSD ((uint8_t)0x08)

Clock security system detection

Definition at line 573 of file stm8s.h.

Referenced by CLK_ClearITPendingBit().

#define CLK_CSSR_CSSDIE ((uint8_t)0x04)

Clock security system detection interrupt enable

Definition at line 574 of file stm8s.h.

Referenced by CLK_ITConfig().

#define CLK_CSSR_CSSEN ((uint8_t)0x01)

Clock security system enable

Definition at line 576 of file stm8s.h.

Referenced by CLK_ClockSecuritySystemEnable().

#define CLK_ECKR_HSEEN ((uint8_t)0x01)

High speed external crystal oscillator enable

Definition at line 543 of file stm8s.h.

Referenced by CLK_ClockSwitchConfig(), and CLK_HSECmd().

#define CLK_ECKR_HSERDY ((uint8_t)0x02)

High speed external crystal oscillator ready

Definition at line 542 of file stm8s.h.

#define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07)

High speed internal oscillator trimmer

Definition at line 583 of file stm8s.h.

Referenced by CLK_AdjustHSICalibrationValue().

#define CLK_ICKR_FHWU ((uint8_t)0x04)

Fast Wake-up from Active Halt/Halt mode

Definition at line 538 of file stm8s.h.

Referenced by CLK_FastHaltWakeUpCmd().

#define CLK_ICKR_HSIEN ((uint8_t)0x01)

High speed internal RC oscillator enable

Definition at line 540 of file stm8s.h.

Referenced by CLK_ClockSwitchConfig(), and CLK_HSICmd().

#define CLK_ICKR_HSIRDY ((uint8_t)0x02)

High speed internal RC oscillator ready

Definition at line 539 of file stm8s.h.

#define CLK_ICKR_LSIEN ((uint8_t)0x08)

Low speed internal RC oscillator enable

Definition at line 537 of file stm8s.h.

Referenced by CLK_ClockSwitchConfig(), and CLK_LSICmd().

#define CLK_ICKR_LSIRDY ((uint8_t)0x10)

Low speed internal oscillator ready

Definition at line 536 of file stm8s.h.

#define CLK_ICKR_SWUAH ((uint8_t)0x20)

Slow Wake-up from Active Halt/Halt modes

Definition at line 535 of file stm8s.h.

Referenced by CLK_SlowActiveHaltWakeUpCmd().

#define CLK_PCKENR1_I2C ((uint8_t)0x01)

I2C clock enable

Definition at line 567 of file stm8s.h.

#define CLK_PCKENR1_SPI ((uint8_t)0x02)

SPI clock enable

Definition at line 566 of file stm8s.h.

#define CLK_PCKENR1_TIM1 ((uint8_t)0x80)

Timer 1 clock enable

Definition at line 557 of file stm8s.h.

#define CLK_PCKENR1_TIM2 ((uint8_t)0x20)

Timer 2 clock enable

Definition at line 559 of file stm8s.h.

#define CLK_PCKENR1_TIM3 ((uint8_t)0x40)

Timer 3 clock enable

Definition at line 558 of file stm8s.h.

#define CLK_PCKENR1_TIM4 ((uint8_t)0x10)

Timer 4 clock enable

Definition at line 561 of file stm8s.h.

#define CLK_PCKENR1_TIM5 ((uint8_t)0x20)

Timer 5 clock enable

Definition at line 560 of file stm8s.h.

#define CLK_PCKENR1_TIM6 ((uint8_t)0x10)

Timer 6 clock enable

Definition at line 562 of file stm8s.h.

#define CLK_PCKENR1_UART1 ((uint8_t)0x04)

UART1 clock enable

Definition at line 565 of file stm8s.h.

#define CLK_PCKENR1_UART2 ((uint8_t)0x08)

UART2 clock enable

Definition at line 564 of file stm8s.h.

#define CLK_PCKENR1_UART3 ((uint8_t)0x08)

UART3 clock enable

Definition at line 563 of file stm8s.h.

#define CLK_PCKENR2_ADC ((uint8_t)0x08)

ADC clock enable

Definition at line 570 of file stm8s.h.

#define CLK_PCKENR2_AWU ((uint8_t)0x04)

AWU clock enable

Definition at line 571 of file stm8s.h.

#define CLK_PCKENR2_CAN ((uint8_t)0x80)

CAN clock enable

Definition at line 569 of file stm8s.h.

#define CLK_SWCR_SWBSY ((uint8_t)0x01)

Switch busy flag

Definition at line 552 of file stm8s.h.

Referenced by CLK_ClockSwitchConfig(), and CLK_SYSCLKEmergencyClear().

#define CLK_SWCR_SWEN ((uint8_t)0x02)

Switch start/stop

Definition at line 551 of file stm8s.h.

Referenced by CLK_ClockSwitchCmd(), and CLK_ClockSwitchConfig().

#define CLK_SWCR_SWIEN ((uint8_t)0x04)

Clock switch interrupt enable

Definition at line 550 of file stm8s.h.

Referenced by CLK_ClockSwitchConfig(), and CLK_ITConfig().

#define CLK_SWCR_SWIF ((uint8_t)0x08)

Clock switch interrupt flag

Definition at line 549 of file stm8s.h.

Referenced by CLK_ClearITPendingBit().

#define CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01)

SWIM Clock Dividing Factor

Definition at line 585 of file stm8s.h.

Referenced by CLK_SWIMConfig().

#define CLK_SWR_SWI ((uint8_t)0xFF)

Clock master selection bits

Definition at line 547 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM1_Registers_Reset_Value

Defines

TIM1_Registers_Reset_Value

Defines

#define | TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM1_BKR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_DTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_ETR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_OISR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_RCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SR2_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)

Definition at line 655 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)

Definition at line 656 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_BKR_RESET_VALUE ((uint8_t)0x00)

Definition at line 666 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)

Definition at line 649 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)

Definition at line 650 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 645 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 646 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 647 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)

Definition at line 648 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)

Definition at line 658 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)

Definition at line 659 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)

Definition at line 660 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)

Definition at line 661 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)

Definition at line 662 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)

Definition at line 663 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)

Definition at line 664 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)

Definition at line 665 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 651 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 652 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 637 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 638 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_DTR_RESET_VALUE ((uint8_t)0x00)

Definition at line 667 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 644 of file stm8s.h.

#define TIM1_ETR_RESET_VALUE ((uint8_t)0x00)

Definition at line 640 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 641 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_OISR_RESET_VALUE ((uint8_t)0x00)

Definition at line 668 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 653 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 654 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_RCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 657 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 639 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 642 of file stm8s.h.

Referenced by TIM1_DeInit().

#define TIM1_SR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 643 of file stm8s.h.

Referenced by TIM1_DeInit().


STM8S/A Standard Peripherals Drivers: TIM1_Registers_Bits_Definition

Defines

TIM1_Registers_Bits_Definition

Defines

#define | CCMR_TIxDirect_Set ((uint8_t)0x01)
#define | TIM1_ARRH_ARR ((uint8_t)0xFF)
#define | TIM1_ARRL_ARR ((uint8_t)0xFF)
#define | TIM1_BKR_AOE ((uint8_t)0x40)
#define | TIM1_BKR_BKE ((uint8_t)0x10)
#define | TIM1_BKR_BKP ((uint8_t)0x20)
#define | TIM1_BKR_LOCK ((uint8_t)0x03)
#define | TIM1_BKR_MOE ((uint8_t)0x80)
#define | TIM1_BKR_OSSI ((uint8_t)0x04)
#define | TIM1_BKR_OSSR ((uint8_t)0x08)
#define | TIM1_CCER1_CC1E ((uint8_t)0x01)
#define | TIM1_CCER1_CC1NE ((uint8_t)0x04)
#define | TIM1_CCER1_CC1NP ((uint8_t)0x08)
#define | TIM1_CCER1_CC1P ((uint8_t)0x02)
#define | TIM1_CCER1_CC2E ((uint8_t)0x10)
#define | TIM1_CCER1_CC2NE ((uint8_t)0x40)
#define | TIM1_CCER1_CC2NP ((uint8_t)0x80)
#define | TIM1_CCER1_CC2P ((uint8_t)0x20)
#define | TIM1_CCER2_CC3E ((uint8_t)0x01)
#define | TIM1_CCER2_CC3NE ((uint8_t)0x04)
#define | TIM1_CCER2_CC3NP ((uint8_t)0x08)
#define | TIM1_CCER2_CC3P ((uint8_t)0x02)
#define | TIM1_CCER2_CC4E ((uint8_t)0x10)
#define | TIM1_CCER2_CC4P ((uint8_t)0x20)
#define | TIM1_CCMR_CCxS ((uint8_t)0x03)
#define | TIM1_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM1_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM1_CCMR_OCM ((uint8_t)0x70)
#define | TIM1_CCMR_OCxFE ((uint8_t)0x04)
#define | TIM1_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM1_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM1_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM1_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM1_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM1_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM1_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM1_CCR4H_CCR4 ((uint8_t)0xFF)
#define | TIM1_CCR4L_CCR4 ((uint8_t)0xFF)
#define | TIM1_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM1_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM1_CR1_ARPE ((uint8_t)0x80)
#define | TIM1_CR1_CEN ((uint8_t)0x01)
#define | TIM1_CR1_CMS ((uint8_t)0x60)
#define | TIM1_CR1_DIR ((uint8_t)0x10)
#define | TIM1_CR1_OPM ((uint8_t)0x08)
#define | TIM1_CR1_UDIS ((uint8_t)0x02)
#define | TIM1_CR1_URS ((uint8_t)0x04)
#define | TIM1_CR2_CCPC ((uint8_t)0x01)
#define | TIM1_CR2_COMS ((uint8_t)0x04)
#define | TIM1_CR2_MMS ((uint8_t)0x70)
#define | TIM1_CR2_TI1S ((uint8_t)0x80)
#define | TIM1_DTR_DTG ((uint8_t)0xFF)
#define | TIM1_EGR_BG ((uint8_t)0x80)
#define | TIM1_EGR_CC1G ((uint8_t)0x02)
#define | TIM1_EGR_CC2G ((uint8_t)0x04)
#define | TIM1_EGR_CC3G ((uint8_t)0x08)
#define | TIM1_EGR_CC4G ((uint8_t)0x10)
#define | TIM1_EGR_COMG ((uint8_t)0x20)
#define | TIM1_EGR_TG ((uint8_t)0x40)
#define | TIM1_EGR_UG ((uint8_t)0x01)
#define | TIM1_ETR_ECE ((uint8_t)0x40)
#define | TIM1_ETR_ETF ((uint8_t)0x0F)
#define | TIM1_ETR_ETP ((uint8_t)0x80)
#define | TIM1_ETR_ETPS ((uint8_t)0x30)
#define | TIM1_IER_BIE ((uint8_t)0x80)
#define | TIM1_IER_CC1IE ((uint8_t)0x02)
#define | TIM1_IER_CC2IE ((uint8_t)0x04)
#define | TIM1_IER_CC3IE ((uint8_t)0x08)
#define | TIM1_IER_CC4IE ((uint8_t)0x10)
#define | TIM1_IER_COMIE ((uint8_t)0x20)
#define | TIM1_IER_TIE ((uint8_t)0x40)
#define | TIM1_IER_UIE ((uint8_t)0x01)
#define | TIM1_OISR_OIS1 ((uint8_t)0x01)
#define | TIM1_OISR_OIS1N ((uint8_t)0x02)
#define | TIM1_OISR_OIS2 ((uint8_t)0x04)
#define | TIM1_OISR_OIS2N ((uint8_t)0x08)
#define | TIM1_OISR_OIS3 ((uint8_t)0x10)
#define | TIM1_OISR_OIS3N ((uint8_t)0x20)
#define | TIM1_OISR_OIS4 ((uint8_t)0x40)
#define | TIM1_PSCH_PSC ((uint8_t)0xFF)
#define | TIM1_PSCL_PSC ((uint8_t)0xFF)
#define | TIM1_RCR_REP ((uint8_t)0xFF)
#define | TIM1_SMCR_MSM ((uint8_t)0x80)
#define | TIM1_SMCR_SMS ((uint8_t)0x07)
#define | TIM1_SMCR_TS ((uint8_t)0x70)
#define | TIM1_SR1_BIF ((uint8_t)0x80)
#define | TIM1_SR1_CC1IF ((uint8_t)0x02)
#define | TIM1_SR1_CC2IF ((uint8_t)0x04)
#define | TIM1_SR1_CC3IF ((uint8_t)0x08)
#define | TIM1_SR1_CC4IF ((uint8_t)0x10)
#define | TIM1_SR1_COMIF ((uint8_t)0x20)
#define | TIM1_SR1_TIF ((uint8_t)0x40)
#define | TIM1_SR1_UIF ((uint8_t)0x01)
#define | TIM1_SR2_CC1OF ((uint8_t)0x02)
#define | TIM1_SR2_CC2OF ((uint8_t)0x04)
#define | TIM1_SR2_CC3OF ((uint8_t)0x08)
#define | TIM1_SR2_CC4OF ((uint8_t)0x10)

Define Documentation

#define CCMR_TIxDirect_Set ((uint8_t)0x01)

Definition at line 739 of file stm8s.h.

Referenced by TIM1_EncoderInterfaceConfig().

#define TIM1_ARRH_ARR ((uint8_t)0xFF)

Autoreload Value (MSB) mask.

Definition at line 765 of file stm8s.h.

#define TIM1_ARRL_ARR ((uint8_t)0xFF)

Autoreload Value (LSB) mask.

Definition at line 766 of file stm8s.h.

#define TIM1_BKR_AOE ((uint8_t)0x40)

Automatic Output Enable mask.

Definition at line 783 of file stm8s.h.

#define TIM1_BKR_BKE ((uint8_t)0x10)

Break Enable mask.

Definition at line 785 of file stm8s.h.

#define TIM1_BKR_BKP ((uint8_t)0x20)

Break Polarity mask.

Definition at line 784 of file stm8s.h.

#define TIM1_BKR_LOCK ((uint8_t)0x03)

Lock Configuration mask.

Definition at line 788 of file stm8s.h.

#define TIM1_BKR_MOE ((uint8_t)0x80)

Main Output Enable mask.

Definition at line 782 of file stm8s.h.

Referenced by TIM1_CtrlPWMOutputs().

#define TIM1_BKR_OSSI ((uint8_t)0x04)

Off-State Selection for Idle mode mask.

Definition at line 787 of file stm8s.h.

#define TIM1_BKR_OSSR ((uint8_t)0x08)

Off-State Selection for Run mode mask.

Definition at line 786 of file stm8s.h.

#define TIM1_CCER1_CC1E ((uint8_t)0x01)

Capture/Compare 1 output enable mask.

Definition at line 748 of file stm8s.h.

Referenced by TI1_Config(), TIM1_CCxCmd(), TIM1_OC1Init(), and TIM1_SelectOCxM().

#define TIM1_CCER1_CC1NE ((uint8_t)0x04)

Capture/Compare 1 Complementary output enable mask.

Definition at line 746 of file stm8s.h.

Referenced by TIM1_CCxNCmd(), and TIM1_OC1Init().

#define TIM1_CCER1_CC1NP ((uint8_t)0x08)

Capture/Compare 1 Complementary output Polarity mask.

Definition at line 745 of file stm8s.h.

Referenced by TIM1_OC1Init(), and TIM1_OC1NPolarityConfig().

#define TIM1_CCER1_CC1P ((uint8_t)0x02)

Capture/Compare 1 output Polarity mask.

Definition at line 747 of file stm8s.h.

Referenced by TI1_Config(), TIM1_EncoderInterfaceConfig(), TIM1_OC1Init(), and TIM1_OC1PolarityConfig().

#define TIM1_CCER1_CC2E ((uint8_t)0x10)

Capture/Compare 2 output enable mask.

Definition at line 744 of file stm8s.h.

Referenced by TI2_Config(), TIM1_CCxCmd(), TIM1_OC2Init(), and TIM1_SelectOCxM().

#define TIM1_CCER1_CC2NE ((uint8_t)0x40)

Capture/Compare 2 Complementary output enable mask.

Definition at line 742 of file stm8s.h.

Referenced by TIM1_CCxNCmd(), and TIM1_OC2Init().

#define TIM1_CCER1_CC2NP ((uint8_t)0x80)

Capture/Compare 2 Complementary output Polarity mask.

Definition at line 741 of file stm8s.h.

Referenced by TIM1_OC2Init(), and TIM1_OC2NPolarityConfig().

#define TIM1_CCER1_CC2P ((uint8_t)0x20)

Capture/Compare 2 output Polarity mask.

Definition at line 743 of file stm8s.h.

Referenced by TI2_Config(), TIM1_EncoderInterfaceConfig(), TIM1_OC2Init(), and TIM1_OC2PolarityConfig().

#define TIM1_CCER2_CC3E ((uint8_t)0x01)

Capture/Compare 3 output enable mask.

Definition at line 755 of file stm8s.h.

Referenced by TI3_Config(), TIM1_CCxCmd(), TIM1_OC3Init(), and TIM1_SelectOCxM().

#define TIM1_CCER2_CC3NE ((uint8_t)0x04)

Capture/Compare 3 Complementary output enable mask.

Definition at line 753 of file stm8s.h.

Referenced by TIM1_CCxNCmd(), and TIM1_OC3Init().

#define TIM1_CCER2_CC3NP ((uint8_t)0x08)

Capture/Compare 3 Complementary output Polarity mask.

Definition at line 752 of file stm8s.h.

Referenced by TIM1_OC3Init(), and TIM1_OC3NPolarityConfig().

#define TIM1_CCER2_CC3P ((uint8_t)0x02)

Capture/Compare 3 output Polarity mask.

Definition at line 754 of file stm8s.h.

Referenced by TI3_Config(), TIM1_OC3Init(), and TIM1_OC3PolarityConfig().

#define TIM1_CCER2_CC4E ((uint8_t)0x10)

Capture/Compare 4 output enable mask.

Definition at line 751 of file stm8s.h.

Referenced by TI4_Config(), TIM1_CCxCmd(), TIM1_OC4Init(), and TIM1_SelectOCxM().

#define TIM1_CCER2_CC4P ((uint8_t)0x20)

Capture/Compare 4 output Polarity mask.

Definition at line 750 of file stm8s.h.

Referenced by TI4_Config(), TIM1_OC4Init(), and TIM1_OC4PolarityConfig().

#define TIM1_CCMR_CCxS ((uint8_t)0x03)

Capture/Compare x Selection mask.

Definition at line 737 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), and TIM1_EncoderInterfaceConfig().

#define TIM1_CCMR_ICxF ((uint8_t)0xF0)

Input Capture x Filter mask.

Definition at line 733 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), and TI4_Config().

#define TIM1_CCMR_ICxPSC ((uint8_t)0x0C)

Input Capture x Prescaler mask.

Definition at line 732 of file stm8s.h.

Referenced by TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), and TIM1_SetIC4Prescaler().

#define TIM1_CCMR_OCM ((uint8_t)0x70)

Output Compare x Mode mask.

Definition at line 734 of file stm8s.h.

Referenced by TIM1_ForcedOC1Config(), TIM1_ForcedOC2Config(), TIM1_ForcedOC3Config(), TIM1_ForcedOC4Config(), TIM1_OC1Init(), TIM1_OC2Init(), TIM1_OC3Init(), TIM1_OC4Init(), and TIM1_SelectOCxM().

#define TIM1_CCMR_OCxFE ((uint8_t)0x04)

Output Compare x Fast Enable mask.

Definition at line 736 of file stm8s.h.

Referenced by TIM1_OC1FastConfig(), TIM1_OC2FastConfig(), TIM1_OC3FastConfig(), and TIM1_OC4FastConfig().

#define TIM1_CCMR_OCxPE ((uint8_t)0x08)

Output Compare x Preload Enable mask.

Definition at line 735 of file stm8s.h.

Referenced by TIM1_OC1PreloadConfig(), TIM1_OC2PreloadConfig(), TIM1_OC3PreloadConfig(), and TIM1_OC4PreloadConfig().

#define TIM1_CCR1H_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (MSB) mask.

Definition at line 770 of file stm8s.h.

#define TIM1_CCR1L_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (LSB) mask.

Definition at line 771 of file stm8s.h.

#define TIM1_CCR2H_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (MSB) mask.

Definition at line 773 of file stm8s.h.

#define TIM1_CCR2L_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (LSB) mask.

Definition at line 774 of file stm8s.h.

#define TIM1_CCR3H_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (MSB) mask.

Definition at line 776 of file stm8s.h.

#define TIM1_CCR3L_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (LSB) mask.

Definition at line 777 of file stm8s.h.

#define TIM1_CCR4H_CCR4 ((uint8_t)0xFF)

Capture/Compare 4 Value (MSB) mask.

Definition at line 779 of file stm8s.h.

#define TIM1_CCR4L_CCR4 ((uint8_t)0xFF)

Capture/Compare 4 Value (LSB) mask.

Definition at line 780 of file stm8s.h.

#define TIM1_CNTRH_CNT ((uint8_t)0xFF)

Counter Value (MSB) mask.

Definition at line 757 of file stm8s.h.

#define TIM1_CNTRL_CNT ((uint8_t)0xFF)

Counter Value (LSB) mask.

Definition at line 759 of file stm8s.h.

#define TIM1_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable mask.

Definition at line 678 of file stm8s.h.

Referenced by TIM1_ARRPreloadConfig().

#define TIM1_CR1_CEN ((uint8_t)0x01)

Counter Enable mask.

Definition at line 684 of file stm8s.h.

Referenced by TIM1_Cmd().

#define TIM1_CR1_CMS ((uint8_t)0x60)

Center-aligned Mode Selection mask.

Definition at line 679 of file stm8s.h.

Referenced by TIM1_CounterModeConfig(), and TIM1_TimeBaseInit().

#define TIM1_CR1_DIR ((uint8_t)0x10)

Direction mask.

Definition at line 680 of file stm8s.h.

Referenced by TIM1_CounterModeConfig(), and TIM1_TimeBaseInit().

#define TIM1_CR1_OPM ((uint8_t)0x08)

One Pulse Mode mask.

Definition at line 681 of file stm8s.h.

Referenced by TIM1_SelectOnePulseMode().

#define TIM1_CR1_UDIS ((uint8_t)0x02)

Update DIsable mask.

Definition at line 683 of file stm8s.h.

Referenced by TIM1_UpdateDisableConfig().

#define TIM1_CR1_URS ((uint8_t)0x04)

Update Request Source mask.

Definition at line 682 of file stm8s.h.

Referenced by TIM1_UpdateRequestConfig().

#define TIM1_CR2_CCPC ((uint8_t)0x01)

Capture/Compare Preloaded Control mask.

Definition at line 689 of file stm8s.h.

Referenced by TIM1_CCPreloadControl().

#define TIM1_CR2_COMS ((uint8_t)0x04)

Capture/Compare Control Update Selection mask.

Definition at line 688 of file stm8s.h.

Referenced by TIM1_SelectCOM().

#define TIM1_CR2_MMS ((uint8_t)0x70)

MMS Selection mask.

Definition at line 687 of file stm8s.h.

Referenced by TIM1_SelectOutputTrigger().

#define TIM1_CR2_TI1S ((uint8_t)0x80)

TI1S Selection mask.

Definition at line 686 of file stm8s.h.

Referenced by TIM1_SelectHallSensor().

#define TIM1_DTR_DTG ((uint8_t)0xFF)

Dead-Time Generator set-up mask.

Definition at line 790 of file stm8s.h.

#define TIM1_EGR_BG ((uint8_t)0x80)

Break Generation mask.

Definition at line 723 of file stm8s.h.

#define TIM1_EGR_CC1G ((uint8_t)0x02)

Capture/Compare 1 Generation mask.

Definition at line 729 of file stm8s.h.

#define TIM1_EGR_CC2G ((uint8_t)0x04)

Capture/Compare 2 Generation mask.

Definition at line 728 of file stm8s.h.

#define TIM1_EGR_CC3G ((uint8_t)0x08)

Capture/Compare 3 Generation mask.

Definition at line 727 of file stm8s.h.

#define TIM1_EGR_CC4G ((uint8_t)0x10)

Capture/Compare 4 Generation mask.

Definition at line 726 of file stm8s.h.

#define TIM1_EGR_COMG ((uint8_t)0x20)

Capture/Compare Control Update Generation mask.

Definition at line 725 of file stm8s.h.

#define TIM1_EGR_TG ((uint8_t)0x40)

Trigger Generation mask.

Definition at line 724 of file stm8s.h.

#define TIM1_EGR_UG ((uint8_t)0x01)

Update Generation mask.

Definition at line 730 of file stm8s.h.

#define TIM1_ETR_ECE ((uint8_t)0x40)

External Clock mask.

Definition at line 696 of file stm8s.h.

Referenced by TIM1_ETRClockMode2Config().

#define TIM1_ETR_ETF ((uint8_t)0x0F)

External Trigger Filter mask.

Definition at line 698 of file stm8s.h.

#define TIM1_ETR_ETP ((uint8_t)0x80)

External Trigger Polarity mask.

Definition at line 695 of file stm8s.h.

#define TIM1_ETR_ETPS ((uint8_t)0x30)

External Trigger Prescaler mask.

Definition at line 697 of file stm8s.h.

#define TIM1_IER_BIE ((uint8_t)0x80)

Break Interrupt Enable mask.

Definition at line 700 of file stm8s.h.

#define TIM1_IER_CC1IE ((uint8_t)0x02)

Capture/Compare 1 Interrupt Enable mask.

Definition at line 706 of file stm8s.h.

#define TIM1_IER_CC2IE ((uint8_t)0x04)

Capture/Compare 2 Interrupt Enable mask.

Definition at line 705 of file stm8s.h.

#define TIM1_IER_CC3IE ((uint8_t)0x08)

Capture/Compare 3 Interrupt Enable mask.

Definition at line 704 of file stm8s.h.

#define TIM1_IER_CC4IE ((uint8_t)0x10)

Capture/Compare 4 Interrupt Enable mask.

Definition at line 703 of file stm8s.h.

#define TIM1_IER_COMIE ((uint8_t)0x20)

Commutation Interrupt Enable mask.

Definition at line 702 of file stm8s.h.

#define TIM1_IER_TIE ((uint8_t)0x40)

Trigger Interrupt Enable mask.

Definition at line 701 of file stm8s.h.

#define TIM1_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable mask.

Definition at line 707 of file stm8s.h.

#define TIM1_OISR_OIS1 ((uint8_t)0x01)

Output Idle state 1 (OC1 output) mask.

Definition at line 798 of file stm8s.h.

Referenced by TIM1_OC1Init().

#define TIM1_OISR_OIS1N ((uint8_t)0x02)

Output Idle state 1 (OC1N output) mask.

Definition at line 797 of file stm8s.h.

Referenced by TIM1_OC1Init().

#define TIM1_OISR_OIS2 ((uint8_t)0x04)

Output Idle state 2 (OC2 output) mask.

Definition at line 796 of file stm8s.h.

Referenced by TIM1_OC2Init().

#define TIM1_OISR_OIS2N ((uint8_t)0x08)

Output Idle state 2 (OC2N output) mask.

Definition at line 795 of file stm8s.h.

Referenced by TIM1_OC2Init().

#define TIM1_OISR_OIS3 ((uint8_t)0x10)

Output Idle state 3 (OC3 output) mask.

Definition at line 794 of file stm8s.h.

Referenced by TIM1_OC3Init().

#define TIM1_OISR_OIS3N ((uint8_t)0x20)

Output Idle state 3 (OC3N output) mask.

Definition at line 793 of file stm8s.h.

Referenced by TIM1_OC3Init().

#define TIM1_OISR_OIS4 ((uint8_t)0x40)

Output Idle state 4 (OC4 output) mask.

Definition at line 792 of file stm8s.h.

Referenced by TIM1_OC4Init().

#define TIM1_PSCH_PSC ((uint8_t)0xFF)

Prescaler Value (MSB) mask.

Definition at line 761 of file stm8s.h.

#define TIM1_PSCL_PSC ((uint8_t)0xFF)

Prescaler Value (LSB) mask.

Definition at line 763 of file stm8s.h.

#define TIM1_RCR_REP ((uint8_t)0xFF)

Repetition Counter Value mask.

Definition at line 768 of file stm8s.h.

#define TIM1_SMCR_MSM ((uint8_t)0x80)

Master/Slave Mode mask.

Definition at line 691 of file stm8s.h.

Referenced by TIM1_EncoderInterfaceConfig(), and TIM1_SelectMasterSlaveMode().

#define TIM1_SMCR_SMS ((uint8_t)0x07)

Slave Mode Selection mask.

Definition at line 693 of file stm8s.h.

Referenced by TIM1_ETRClockMode1Config(), TIM1_InternalClockConfig(), and TIM1_SelectSlaveMode().

#define TIM1_SMCR_TS ((uint8_t)0x70)

Trigger Selection mask.

Definition at line 692 of file stm8s.h.

Referenced by TIM1_EncoderInterfaceConfig(), TIM1_ETRClockMode1Config(), and TIM1_SelectInputTrigger().

#define TIM1_SR1_BIF ((uint8_t)0x80)

Break Interrupt Flag mask.

Definition at line 709 of file stm8s.h.

#define TIM1_SR1_CC1IF ((uint8_t)0x02)

Capture/Compare 1 Interrupt Flag mask.

Definition at line 715 of file stm8s.h.

#define TIM1_SR1_CC2IF ((uint8_t)0x04)

Capture/Compare 2 Interrupt Flag mask.

Definition at line 714 of file stm8s.h.

#define TIM1_SR1_CC3IF ((uint8_t)0x08)

Capture/Compare 3 Interrupt Flag mask.

Definition at line 713 of file stm8s.h.

#define TIM1_SR1_CC4IF ((uint8_t)0x10)

Capture/Compare 4 Interrupt Flag mask.

Definition at line 712 of file stm8s.h.

#define TIM1_SR1_COMIF ((uint8_t)0x20)

Commutation Interrupt Flag mask.

Definition at line 711 of file stm8s.h.

#define TIM1_SR1_TIF ((uint8_t)0x40)

Trigger Interrupt Flag mask.

Definition at line 710 of file stm8s.h.

#define TIM1_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag mask.

Definition at line 716 of file stm8s.h.

#define TIM1_SR2_CC1OF ((uint8_t)0x02)

Capture/Compare 1 Overcapture Flag mask.

Definition at line 721 of file stm8s.h.

#define TIM1_SR2_CC2OF ((uint8_t)0x04)

Capture/Compare 2 Overcapture Flag mask.

Definition at line 720 of file stm8s.h.

#define TIM1_SR2_CC3OF ((uint8_t)0x08)

Capture/Compare 3 Overcapture Flag mask.

Definition at line 719 of file stm8s.h.

#define TIM1_SR2_CC4OF ((uint8_t)0x10)

Capture/Compare 4 Overcapture Flag mask.

Definition at line 718 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM2_Registers_Reset_Value

Defines

TIM2_Registers_Reset_Value

Defines

#define | TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_SR2_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)

Definition at line 855 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)

Definition at line 856 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)

Definition at line 850 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)

Definition at line 851 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 847 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 848 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 849 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)

Definition at line 857 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)

Definition at line 858 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)

Definition at line 859 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)

Definition at line 860 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)

Definition at line 861 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)

Definition at line 862 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 852 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 853 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 842 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 846 of file stm8s.h.

#define TIM2_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 843 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 854 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 844 of file stm8s.h.

Referenced by TIM2_DeInit().

#define TIM2_SR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 845 of file stm8s.h.

Referenced by TIM2_DeInit().


STM8S/A Standard Peripherals Drivers: TIM2_Registers_Bits_Definition

Defines

TIM2_Registers_Bits_Definition

Defines

#define | TIM2_ARRH_ARR ((uint8_t)0xFF)
#define | TIM2_ARRL_ARR ((uint8_t)0xFF)
#define | TIM2_CCER1_CC1E ((uint8_t)0x01)
#define | TIM2_CCER1_CC1P ((uint8_t)0x02)
#define | TIM2_CCER1_CC2E ((uint8_t)0x10)
#define | TIM2_CCER1_CC2P ((uint8_t)0x20)
#define | TIM2_CCER2_CC3E ((uint8_t)0x01)
#define | TIM2_CCER2_CC3P ((uint8_t)0x02)
#define | TIM2_CCMR_CCxS ((uint8_t)0x03)
#define | TIM2_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM2_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM2_CCMR_OCM ((uint8_t)0x70)
#define | TIM2_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM2_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM2_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM2_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM2_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM2_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM2_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM2_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM2_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM2_CR1_ARPE ((uint8_t)0x80)
#define | TIM2_CR1_CEN ((uint8_t)0x01)
#define | TIM2_CR1_OPM ((uint8_t)0x08)
#define | TIM2_CR1_UDIS ((uint8_t)0x02)
#define | TIM2_CR1_URS ((uint8_t)0x04)
#define | TIM2_EGR_CC1G ((uint8_t)0x02)
#define | TIM2_EGR_CC2G ((uint8_t)0x04)
#define | TIM2_EGR_CC3G ((uint8_t)0x08)
#define | TIM2_EGR_UG ((uint8_t)0x01)
#define | TIM2_IER_CC1IE ((uint8_t)0x02)
#define | TIM2_IER_CC2IE ((uint8_t)0x04)
#define | TIM2_IER_CC3IE ((uint8_t)0x08)
#define | TIM2_IER_UIE ((uint8_t)0x01)
#define | TIM2_PSCR_PSC ((uint8_t)0xFF)
#define | TIM2_SR1_CC1IF ((uint8_t)0x02)
#define | TIM2_SR1_CC2IF ((uint8_t)0x04)
#define | TIM2_SR1_CC3IF ((uint8_t)0x08)
#define | TIM2_SR1_UIF ((uint8_t)0x01)
#define | TIM2_SR2_CC1OF ((uint8_t)0x02)
#define | TIM2_SR2_CC2OF ((uint8_t)0x04)
#define | TIM2_SR2_CC3OF ((uint8_t)0x08)

Define Documentation

#define TIM2_ARRH_ARR ((uint8_t)0xFF)

Autoreload Value (MSB) mask.

Definition at line 916 of file stm8s.h.

#define TIM2_ARRL_ARR ((uint8_t)0xFF)

Autoreload Value (LSB) mask.

Definition at line 917 of file stm8s.h.

#define TIM2_CCER1_CC1E ((uint8_t)0x01)

Capture/Compare 1 output enable mask.

Definition at line 906 of file stm8s.h.

Referenced by TI1_Config(), TIM2_CCxCmd(), TIM2_OC1Init(), and TIM2_SelectOCxM().

#define TIM2_CCER1_CC1P ((uint8_t)0x02)

Capture/Compare 1 output Polarity mask.

Definition at line 905 of file stm8s.h.

Referenced by TI1_Config(), TIM2_OC1Init(), and TIM2_OC1PolarityConfig().

#define TIM2_CCER1_CC2E ((uint8_t)0x10)

Capture/Compare 2 output enable mask.

Definition at line 904 of file stm8s.h.

Referenced by TI2_Config(), TIM2_CCxCmd(), TIM2_OC2Init(), and TIM2_SelectOCxM().

#define TIM2_CCER1_CC2P ((uint8_t)0x20)

Capture/Compare 2 output Polarity mask.

Definition at line 903 of file stm8s.h.

Referenced by TI2_Config(), TIM2_OC2Init(), and TIM2_OC2PolarityConfig().

#define TIM2_CCER2_CC3E ((uint8_t)0x01)

Capture/Compare 3 output enable mask.

Definition at line 909 of file stm8s.h.

Referenced by TI3_Config(), TIM2_CCxCmd(), TIM2_OC3Init(), and TIM2_SelectOCxM().

#define TIM2_CCER2_CC3P ((uint8_t)0x02)

Capture/Compare 3 output Polarity mask.

Definition at line 908 of file stm8s.h.

Referenced by TI3_Config(), TIM2_OC3Init(), and TIM2_OC3PolarityConfig().

#define TIM2_CCMR_CCxS ((uint8_t)0x03)

Capture/Compare x Selection mask.

Definition at line 901 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), and TI3_Config().

#define TIM2_CCMR_ICxF ((uint8_t)0xF0)

Input Capture x Filter mask.

Definition at line 898 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), and TI3_Config().

#define TIM2_CCMR_ICxPSC ((uint8_t)0x0C)

Input Capture x Prescaler mask.

Definition at line 897 of file stm8s.h.

Referenced by TIM2_SetIC1Prescaler(), TIM2_SetIC2Prescaler(), and TIM2_SetIC3Prescaler().

#define TIM2_CCMR_OCM ((uint8_t)0x70)

Output Compare x Mode mask.

Definition at line 899 of file stm8s.h.

Referenced by TIM2_ForcedOC1Config(), TIM2_ForcedOC2Config(), TIM2_ForcedOC3Config(), TIM2_OC1Init(), TIM2_OC2Init(), TIM2_OC3Init(), and TIM2_SelectOCxM().

#define TIM2_CCMR_OCxPE ((uint8_t)0x08)

Output Compare x Preload Enable mask.

Definition at line 900 of file stm8s.h.

Referenced by TIM2_OC1PreloadConfig(), TIM2_OC2PreloadConfig(), and TIM2_OC3PreloadConfig().

#define TIM2_CCR1H_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (MSB) mask.

Definition at line 919 of file stm8s.h.

#define TIM2_CCR1L_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (LSB) mask.

Definition at line 920 of file stm8s.h.

#define TIM2_CCR2H_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (MSB) mask.

Definition at line 922 of file stm8s.h.

#define TIM2_CCR2L_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (LSB) mask.

Definition at line 923 of file stm8s.h.

#define TIM2_CCR3H_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (MSB) mask.

Definition at line 925 of file stm8s.h.

#define TIM2_CCR3L_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (LSB) mask.

Definition at line 926 of file stm8s.h.

#define TIM2_CNTRH_CNT ((uint8_t)0xFF)

Counter Value (MSB) mask.

Definition at line 911 of file stm8s.h.

#define TIM2_CNTRL_CNT ((uint8_t)0xFF)

Counter Value (LSB) mask.

Definition at line 912 of file stm8s.h.

#define TIM2_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable mask.

Definition at line 872 of file stm8s.h.

Referenced by TIM2_ARRPreloadConfig().

#define TIM2_CR1_CEN ((uint8_t)0x01)

Counter Enable mask.

Definition at line 876 of file stm8s.h.

Referenced by TIM2_Cmd().

#define TIM2_CR1_OPM ((uint8_t)0x08)

One Pulse Mode mask.

Definition at line 873 of file stm8s.h.

Referenced by TIM2_SelectOnePulseMode().

#define TIM2_CR1_UDIS ((uint8_t)0x02)

Update DIsable mask.

Definition at line 875 of file stm8s.h.

Referenced by TIM2_UpdateDisableConfig().

#define TIM2_CR1_URS ((uint8_t)0x04)

Update Request Source mask.

Definition at line 874 of file stm8s.h.

Referenced by TIM2_UpdateRequestConfig().

#define TIM2_EGR_CC1G ((uint8_t)0x02)

Capture/Compare 1 Generation mask.

Definition at line 894 of file stm8s.h.

#define TIM2_EGR_CC2G ((uint8_t)0x04)

Capture/Compare 2 Generation mask.

Definition at line 893 of file stm8s.h.

#define TIM2_EGR_CC3G ((uint8_t)0x08)

Capture/Compare 3 Generation mask.

Definition at line 892 of file stm8s.h.

#define TIM2_EGR_UG ((uint8_t)0x01)

Update Generation mask.

Definition at line 895 of file stm8s.h.

#define TIM2_IER_CC1IE ((uint8_t)0x02)

Capture/Compare 1 Interrupt Enable mask.

Definition at line 880 of file stm8s.h.

#define TIM2_IER_CC2IE ((uint8_t)0x04)

Capture/Compare 2 Interrupt Enable mask.

Definition at line 879 of file stm8s.h.

#define TIM2_IER_CC3IE ((uint8_t)0x08)

Capture/Compare 3 Interrupt Enable mask.

Definition at line 878 of file stm8s.h.

#define TIM2_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable mask.

Definition at line 881 of file stm8s.h.

#define TIM2_PSCR_PSC ((uint8_t)0xFF)

Prescaler Value (MSB) mask.

Definition at line 914 of file stm8s.h.

#define TIM2_SR1_CC1IF ((uint8_t)0x02)

Capture/Compare 1 Interrupt Flag mask.

Definition at line 885 of file stm8s.h.

#define TIM2_SR1_CC2IF ((uint8_t)0x04)

Capture/Compare 2 Interrupt Flag mask.

Definition at line 884 of file stm8s.h.

#define TIM2_SR1_CC3IF ((uint8_t)0x08)

Capture/Compare 3 Interrupt Flag mask.

Definition at line 883 of file stm8s.h.

#define TIM2_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag mask.

Definition at line 886 of file stm8s.h.

#define TIM2_SR2_CC1OF ((uint8_t)0x02)

Capture/Compare 1 Overcapture Flag mask.

Definition at line 890 of file stm8s.h.

#define TIM2_SR2_CC2OF ((uint8_t)0x04)

Capture/Compare 2 Overcapture Flag mask.

Definition at line 889 of file stm8s.h.

#define TIM2_SR2_CC3OF ((uint8_t)0x08)

Capture/Compare 3 Overcapture Flag mask.

Definition at line 888 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM3_Registers_Reset_Value

Defines

TIM3_Registers_Reset_Value

Defines

#define | TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_SR2_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)

Definition at line 973 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)

Definition at line 974 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)

Definition at line 969 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 967 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 968 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)

Definition at line 975 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)

Definition at line 976 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)

Definition at line 977 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)

Definition at line 978 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 970 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 971 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 962 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 966 of file stm8s.h.

#define TIM3_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 963 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 972 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 964 of file stm8s.h.

Referenced by TIM3_DeInit().

#define TIM3_SR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 965 of file stm8s.h.

Referenced by TIM3_DeInit().


STM8S/A Standard Peripherals Drivers: TIM3_Registers_Bits_Definition

Defines

TIM3_Registers_Bits_Definition

Defines

#define | TIM3_ARRH_ARR ((uint8_t)0xFF)
#define | TIM3_ARRL_ARR ((uint8_t)0xFF)
#define | TIM3_CCER1_CC1E ((uint8_t)0x01)
#define | TIM3_CCER1_CC1P ((uint8_t)0x02)
#define | TIM3_CCER1_CC2E ((uint8_t)0x10)
#define | TIM3_CCER1_CC2P ((uint8_t)0x20)
#define | TIM3_CCMR_CCxS ((uint8_t)0x03)
#define | TIM3_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM3_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM3_CCMR_OCM ((uint8_t)0x70)
#define | TIM3_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM3_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM3_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM3_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM3_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM3_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM3_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM3_CR1_ARPE ((uint8_t)0x80)
#define | TIM3_CR1_CEN ((uint8_t)0x01)
#define | TIM3_CR1_OPM ((uint8_t)0x08)
#define | TIM3_CR1_UDIS ((uint8_t)0x02)
#define | TIM3_CR1_URS ((uint8_t)0x04)
#define | TIM3_EGR_CC1G ((uint8_t)0x02)
#define | TIM3_EGR_CC2G ((uint8_t)0x04)
#define | TIM3_EGR_UG ((uint8_t)0x01)
#define | TIM3_IER_CC1IE ((uint8_t)0x02)
#define | TIM3_IER_CC2IE ((uint8_t)0x04)
#define | TIM3_IER_UIE ((uint8_t)0x01)
#define | TIM3_PSCR_PSC ((uint8_t)0xFF)
#define | TIM3_SR1_CC1IF ((uint8_t)0x02)
#define | TIM3_SR1_CC2IF ((uint8_t)0x04)
#define | TIM3_SR1_UIF ((uint8_t)0x01)
#define | TIM3_SR2_CC1OF ((uint8_t)0x02)
#define | TIM3_SR2_CC2OF ((uint8_t)0x04)

Define Documentation

#define TIM3_ARRH_ARR ((uint8_t)0xFF)

Autoreload Value (MSB) mask.

Definition at line 1025 of file stm8s.h.

#define TIM3_ARRL_ARR ((uint8_t)0xFF)

Autoreload Value (LSB) mask.

Definition at line 1026 of file stm8s.h.

#define TIM3_CCER1_CC1E ((uint8_t)0x01)

Capture/Compare 1 output enable mask.

Definition at line 1018 of file stm8s.h.

Referenced by TI1_Config(), TIM3_CCxCmd(), TIM3_OC1Init(), and TIM3_SelectOCxM().

#define TIM3_CCER1_CC1P ((uint8_t)0x02)

Capture/Compare 1 output Polarity mask.

Definition at line 1017 of file stm8s.h.

Referenced by TI1_Config(), TIM3_OC1Init(), and TIM3_OC1PolarityConfig().

#define TIM3_CCER1_CC2E ((uint8_t)0x10)

Capture/Compare 2 output enable mask.

Definition at line 1016 of file stm8s.h.

Referenced by TI2_Config(), TIM3_CCxCmd(), TIM3_OC2Init(), and TIM3_SelectOCxM().

#define TIM3_CCER1_CC2P ((uint8_t)0x20)

Capture/Compare 2 output Polarity mask.

Definition at line 1015 of file stm8s.h.

Referenced by TI2_Config(), TIM3_OC2Init(), and TIM3_OC2PolarityConfig().

#define TIM3_CCMR_CCxS ((uint8_t)0x03)

Capture/Compare x Selection mask.

Definition at line 1013 of file stm8s.h.

Referenced by TI1_Config(), and TI2_Config().

#define TIM3_CCMR_ICxF ((uint8_t)0xF0)

Input Capture x Filter mask.

Definition at line 1010 of file stm8s.h.

Referenced by TI1_Config(), and TI2_Config().

#define TIM3_CCMR_ICxPSC ((uint8_t)0x0C)

Input Capture x Prescaler mask.

Definition at line 1009 of file stm8s.h.

Referenced by TIM3_SetIC1Prescaler(), and TIM3_SetIC2Prescaler().

#define TIM3_CCMR_OCM ((uint8_t)0x70)

Output Compare x Mode mask.

Definition at line 1011 of file stm8s.h.

Referenced by TIM3_ForcedOC1Config(), TIM3_ForcedOC2Config(), TIM3_OC1Init(), TIM3_OC2Init(), and TIM3_SelectOCxM().

#define TIM3_CCMR_OCxPE ((uint8_t)0x08)

Output Compare x Preload Enable mask.

Definition at line 1012 of file stm8s.h.

Referenced by TIM3_OC1PreloadConfig(), and TIM3_OC2PreloadConfig().

#define TIM3_CCR1H_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (MSB) mask.

Definition at line 1028 of file stm8s.h.

#define TIM3_CCR1L_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (LSB) mask.

Definition at line 1029 of file stm8s.h.

#define TIM3_CCR2H_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (MSB) mask.

Definition at line 1031 of file stm8s.h.

#define TIM3_CCR2L_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (LSB) mask.

Definition at line 1032 of file stm8s.h.

#define TIM3_CNTRH_CNT ((uint8_t)0xFF)

Counter Value (MSB) mask.

Definition at line 1020 of file stm8s.h.

#define TIM3_CNTRL_CNT ((uint8_t)0xFF)

Counter Value (LSB) mask.

Definition at line 1021 of file stm8s.h.

#define TIM3_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable mask.

Definition at line 988 of file stm8s.h.

Referenced by TIM3_ARRPreloadConfig().

#define TIM3_CR1_CEN ((uint8_t)0x01)

Counter Enable mask.

Definition at line 992 of file stm8s.h.

Referenced by TIM3_Cmd().

#define TIM3_CR1_OPM ((uint8_t)0x08)

One Pulse Mode mask.

Definition at line 989 of file stm8s.h.

Referenced by TIM3_SelectOnePulseMode().

#define TIM3_CR1_UDIS ((uint8_t)0x02)

Update DIsable mask.

Definition at line 991 of file stm8s.h.

Referenced by TIM3_UpdateDisableConfig().

#define TIM3_CR1_URS ((uint8_t)0x04)

Update Request Source mask.

Definition at line 990 of file stm8s.h.

Referenced by TIM3_UpdateRequestConfig().

#define TIM3_EGR_CC1G ((uint8_t)0x02)

Capture/Compare 1 Generation mask.

Definition at line 1006 of file stm8s.h.

#define TIM3_EGR_CC2G ((uint8_t)0x04)

Capture/Compare 2 Generation mask.

Definition at line 1005 of file stm8s.h.

#define TIM3_EGR_UG ((uint8_t)0x01)

Update Generation mask.

Definition at line 1007 of file stm8s.h.

#define TIM3_IER_CC1IE ((uint8_t)0x02)

Capture/Compare 1 Interrupt Enable mask.

Definition at line 995 of file stm8s.h.

#define TIM3_IER_CC2IE ((uint8_t)0x04)

Capture/Compare 2 Interrupt Enable mask.

Definition at line 994 of file stm8s.h.

#define TIM3_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable mask.

Definition at line 996 of file stm8s.h.

#define TIM3_PSCR_PSC ((uint8_t)0xFF)

Prescaler Value (MSB) mask.

Definition at line 1023 of file stm8s.h.

#define TIM3_SR1_CC1IF ((uint8_t)0x02)

Capture/Compare 1 Interrupt Flag mask.

Definition at line 999 of file stm8s.h.

#define TIM3_SR1_CC2IF ((uint8_t)0x04)

Capture/Compare 2 Interrupt Flag mask.

Definition at line 998 of file stm8s.h.

#define TIM3_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag mask.

Definition at line 1000 of file stm8s.h.

#define TIM3_SR2_CC1OF ((uint8_t)0x02)

Capture/Compare 1 Overcapture Flag mask.

Definition at line 1003 of file stm8s.h.

#define TIM3_SR2_CC2OF ((uint8_t)0x04)

Capture/Compare 2 Overcapture Flag mask.

Definition at line 1002 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM4_Registers_Reset_Value

Defines

TIM4_Registers_Reset_Value

Defines

#define | TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)
#define | TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_SR1_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1068 of file stm8s.h.

Referenced by TIM4_DeInit().

#define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1066 of file stm8s.h.

Referenced by TIM4_DeInit().

#define TIM4_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1062 of file stm8s.h.

Referenced by TIM4_DeInit().

#define TIM4_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1065 of file stm8s.h.

#define TIM4_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 1063 of file stm8s.h.

Referenced by TIM4_DeInit().

#define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1067 of file stm8s.h.

Referenced by TIM4_DeInit().

#define TIM4_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1064 of file stm8s.h.

Referenced by TIM4_DeInit().


STM8S/A Standard Peripherals Drivers: TIM4_Registers_Bits_Definition

Defines

TIM4_Registers_Bits_Definition

Defines

#define | TIM4_ARR_ARR ((uint8_t)0xFF)
#define | TIM4_CNTR_CNT ((uint8_t)0xFF)
#define | TIM4_CR1_ARPE ((uint8_t)0x80)
#define | TIM4_CR1_CEN ((uint8_t)0x01)
#define | TIM4_CR1_OPM ((uint8_t)0x08)
#define | TIM4_CR1_UDIS ((uint8_t)0x02)
#define | TIM4_CR1_URS ((uint8_t)0x04)
#define | TIM4_EGR_UG ((uint8_t)0x01)
#define | TIM4_IER_UIE ((uint8_t)0x01)
#define | TIM4_PSCR_PSC ((uint8_t)0x07)
#define | TIM4_SR1_UIF ((uint8_t)0x01)

Define Documentation

#define TIM4_ARR_ARR ((uint8_t)0xFF)

Autoreload Value mask.

Definition at line 1094 of file stm8s.h.

#define TIM4_CNTR_CNT ((uint8_t)0xFF)

Counter Value (LSB) mask.

Definition at line 1090 of file stm8s.h.

#define TIM4_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable mask.

Definition at line 1078 of file stm8s.h.

Referenced by TIM4_ARRPreloadConfig().

#define TIM4_CR1_CEN ((uint8_t)0x01)

Counter Enable mask.

Definition at line 1082 of file stm8s.h.

Referenced by TIM4_Cmd().

#define TIM4_CR1_OPM ((uint8_t)0x08)

One Pulse Mode mask.

Definition at line 1079 of file stm8s.h.

Referenced by TIM4_SelectOnePulseMode().

#define TIM4_CR1_UDIS ((uint8_t)0x02)

Update DIsable mask.

Definition at line 1081 of file stm8s.h.

Referenced by TIM4_UpdateDisableConfig().

#define TIM4_CR1_URS ((uint8_t)0x04)

Update Request Source mask.

Definition at line 1080 of file stm8s.h.

Referenced by TIM4_UpdateRequestConfig().

#define TIM4_EGR_UG ((uint8_t)0x01)

Update Generation mask.

Definition at line 1088 of file stm8s.h.

#define TIM4_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable mask.

Definition at line 1084 of file stm8s.h.

#define TIM4_PSCR_PSC ((uint8_t)0x07)

Prescaler Value mask.

Definition at line 1092 of file stm8s.h.

#define TIM4_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag mask.

Definition at line 1086 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM5_Registers_Reset_Value

Defines

TIM5_Registers_Reset_Value

Defines

#define | TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SR2_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1151 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1152 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1146 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1147 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1143 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1144 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 1145 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)

Definition at line 1153 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)

Definition at line 1154 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)

Definition at line 1155 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)

Definition at line 1156 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)

Definition at line 1157 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)

Definition at line 1158 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 1148 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 1149 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1136 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1137 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1142 of file stm8s.h.

#define TIM5_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 1139 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1150 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_SMCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1138 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1140 of file stm8s.h.

Referenced by TIM5_DeInit().

#define TIM5_SR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1141 of file stm8s.h.

Referenced by TIM5_DeInit().


STM8S/A Standard Peripherals Drivers: TIM5_Registers_Bits_Definition

Defines

TIM5_Registers_Bits_Definition

Defines

#define | TIM5_ARRH_ARR ((uint8_t)0xFF)
#define | TIM5_ARRL_ARR ((uint8_t)0xFF)
#define | TIM5_CCER1_CC1E ((uint8_t)0x01)
#define | TIM5_CCER1_CC1P ((uint8_t)0x02)
#define | TIM5_CCER1_CC2E ((uint8_t)0x10)
#define | TIM5_CCER1_CC2P ((uint8_t)0x20)
#define | TIM5_CCER2_CC3E ((uint8_t)0x01)
#define | TIM5_CCER2_CC3P ((uint8_t)0x02)
#define | TIM5_CCMR_CCxS ((uint8_t)0x03)
#define | TIM5_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM5_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM5_CCMR_OCM ((uint8_t)0x70)
#define | TIM5_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)
#define | TIM5_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM5_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM5_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM5_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM5_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM5_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM5_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM5_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM5_CR1_ARPE ((uint8_t)0x80)
#define | TIM5_CR1_CEN ((uint8_t)0x01)
#define | TIM5_CR1_OPM ((uint8_t)0x08)
#define | TIM5_CR1_UDIS ((uint8_t)0x02)
#define | TIM5_CR1_URS ((uint8_t)0x04)
#define | TIM5_CR2_MMS ((uint8_t)0x70)
#define | TIM5_CR2_TI1S ((uint8_t)0x80)
#define | TIM5_EGR_CC1G ((uint8_t)0x02)
#define | TIM5_EGR_CC2G ((uint8_t)0x04)
#define | TIM5_EGR_CC3G ((uint8_t)0x08)
#define | TIM5_EGR_TG ((uint8_t)0x40)
#define | TIM5_EGR_UG ((uint8_t)0x01)
#define | TIM5_IER_CC1IE ((uint8_t)0x02)
#define | TIM5_IER_CC2IE ((uint8_t)0x04)
#define | TIM5_IER_CC3IE ((uint8_t)0x08)
#define | TIM5_IER_TIE ((uint8_t)0x40)
#define | TIM5_IER_UIE ((uint8_t)0x01)
#define | TIM5_PSCR_PSC ((uint8_t)0xFF)
#define | TIM5_SMCR_MSM ((uint8_t)0x80)
#define | TIM5_SMCR_SMS ((uint8_t)0x07)
#define | TIM5_SMCR_TS ((uint8_t)0x70)
#define | TIM5_SR1_CC1IF ((uint8_t)0x02)
#define | TIM5_SR1_CC2IF ((uint8_t)0x04)
#define | TIM5_SR1_CC3IF ((uint8_t)0x08)
#define | TIM5_SR1_TIF ((uint8_t)0x40)
#define | TIM5_SR1_UIF ((uint8_t)0x01)
#define | TIM5_SR2_CC1OF ((uint8_t)0x02)
#define | TIM5_SR2_CC2OF ((uint8_t)0x04)
#define | TIM5_SR2_CC3OF ((uint8_t)0x08)

Define Documentation

#define TIM5_ARRH_ARR ((uint8_t)0xFF)

Autoreload Value (MSB) mask.

Definition at line 1222 of file stm8s.h.

#define TIM5_ARRL_ARR ((uint8_t)0xFF)

Autoreload Value (LSB) mask.

Definition at line 1223 of file stm8s.h.

#define TIM5_CCER1_CC1E ((uint8_t)0x01)

Capture/Compare 1 output enable mask.

Definition at line 1212 of file stm8s.h.

Referenced by TI1_Config(), TIM5_CCxCmd(), TIM5_OC1Init(), and TIM5_SelectOCxM().

#define TIM5_CCER1_CC1P ((uint8_t)0x02)

Capture/Compare 1 output Polarity mask.

Definition at line 1211 of file stm8s.h.

Referenced by TI1_Config(), TIM5_EncoderInterfaceConfig(), TIM5_OC1Init(), and TIM5_OC1PolarityConfig().

#define TIM5_CCER1_CC2E ((uint8_t)0x10)

Capture/Compare 2 output enable mask.

Definition at line 1210 of file stm8s.h.

Referenced by TI2_Config(), TIM5_CCxCmd(), TIM5_OC2Init(), and TIM5_SelectOCxM().

#define TIM5_CCER1_CC2P ((uint8_t)0x20)

Capture/Compare 2 output Polarity mask.

Definition at line 1209 of file stm8s.h.

Referenced by TI2_Config(), TIM5_EncoderInterfaceConfig(), TIM5_OC2Init(), and TIM5_OC2PolarityConfig().

#define TIM5_CCER2_CC3E ((uint8_t)0x01)

Capture/Compare 3 output enable mask.

Definition at line 1215 of file stm8s.h.

Referenced by TI3_Config(), TIM5_CCxCmd(), TIM5_OC3Init(), and TIM5_SelectOCxM().

#define TIM5_CCER2_CC3P ((uint8_t)0x02)

Capture/Compare 3 output Polarity mask.

Definition at line 1214 of file stm8s.h.

Referenced by TI3_Config(), TIM5_OC3Init(), and TIM5_OC3PolarityConfig().

#define TIM5_CCMR_CCxS ((uint8_t)0x03)

Capture/Compare x Selection mask.

Definition at line 1207 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), and TIM5_EncoderInterfaceConfig().

#define TIM5_CCMR_ICxF ((uint8_t)0xF0)

Input Capture x Filter mask.

Definition at line 1204 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), and TI3_Config().

#define TIM5_CCMR_ICxPSC ((uint8_t)0x0C)

Input Capture x Prescaler mask.

Definition at line 1203 of file stm8s.h.

Referenced by TIM5_SetIC1Prescaler(), TIM5_SetIC2Prescaler(), and TIM5_SetIC3Prescaler().

#define TIM5_CCMR_OCM ((uint8_t)0x70)

Output Compare x Mode mask.

Definition at line 1205 of file stm8s.h.

Referenced by TIM5_ForcedOC1Config(), TIM5_ForcedOC2Config(), TIM5_ForcedOC3Config(), TIM5_OC1Init(), TIM5_OC2Init(), TIM5_OC3Init(), and TIM5_SelectOCxM().

#define TIM5_CCMR_OCxPE ((uint8_t)0x08)

Output Compare x Preload Enable mask.

Definition at line 1206 of file stm8s.h.

Referenced by TIM5_OC1PreloadConfig(), TIM5_OC2PreloadConfig(), and TIM5_OC3PreloadConfig().

#define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)

Definition at line 1234 of file stm8s.h.

Referenced by TIM5_EncoderInterfaceConfig().

#define TIM5_CCR1H_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (MSB) mask.

Definition at line 1225 of file stm8s.h.

#define TIM5_CCR1L_CCR1 ((uint8_t)0xFF)

Capture/Compare 1 Value (LSB) mask.

Definition at line 1226 of file stm8s.h.

#define TIM5_CCR2H_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (MSB) mask.

Definition at line 1228 of file stm8s.h.

#define TIM5_CCR2L_CCR2 ((uint8_t)0xFF)

Capture/Compare 2 Value (LSB) mask.

Definition at line 1229 of file stm8s.h.

#define TIM5_CCR3H_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (MSB) mask.

Definition at line 1231 of file stm8s.h.

#define TIM5_CCR3L_CCR3 ((uint8_t)0xFF)

Capture/Compare 3 Value (LSB) mask.

Definition at line 1232 of file stm8s.h.

#define TIM5_CNTRH_CNT ((uint8_t)0xFF)

Counter Value (MSB) mask.

Definition at line 1217 of file stm8s.h.

#define TIM5_CNTRL_CNT ((uint8_t)0xFF)

Counter Value (LSB) mask.

Definition at line 1218 of file stm8s.h.

#define TIM5_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable mask.

Definition at line 1168 of file stm8s.h.

Referenced by TIM5_ARRPreloadConfig().

#define TIM5_CR1_CEN ((uint8_t)0x01)

Counter Enable mask.

Definition at line 1172 of file stm8s.h.

Referenced by TIM5_Cmd().

#define TIM5_CR1_OPM ((uint8_t)0x08)

One Pulse Mode mask.

Definition at line 1169 of file stm8s.h.

Referenced by TIM5_SelectOnePulseMode().

#define TIM5_CR1_UDIS ((uint8_t)0x02)

Update DIsable mask.

Definition at line 1171 of file stm8s.h.

Referenced by TIM5_UpdateDisableConfig().

#define TIM5_CR1_URS ((uint8_t)0x04)

Update Request Source mask.

Definition at line 1170 of file stm8s.h.

Referenced by TIM5_UpdateRequestConfig().

#define TIM5_CR2_MMS ((uint8_t)0x70)

MMS Selection Mask.

Definition at line 1175 of file stm8s.h.

Referenced by TIM5_SelectOutputTrigger().

#define TIM5_CR2_TI1S ((uint8_t)0x80)

TI1S Selection Mask.

Definition at line 1174 of file stm8s.h.

#define TIM5_EGR_CC1G ((uint8_t)0x02)

Capture/Compare 1 Generation mask.

Definition at line 1200 of file stm8s.h.

#define TIM5_EGR_CC2G ((uint8_t)0x04)

Capture/Compare 2 Generation mask.

Definition at line 1199 of file stm8s.h.

#define TIM5_EGR_CC3G ((uint8_t)0x08)

Capture/Compare 3 Generation mask.

Definition at line 1198 of file stm8s.h.

#define TIM5_EGR_TG ((uint8_t)0x40)

Trigger Generation mask.

Definition at line 1197 of file stm8s.h.

#define TIM5_EGR_UG ((uint8_t)0x01)

Update Generation mask.

Definition at line 1201 of file stm8s.h.

#define TIM5_IER_CC1IE ((uint8_t)0x02)

Capture/Compare 1 Interrupt Enable mask.

Definition at line 1184 of file stm8s.h.

#define TIM5_IER_CC2IE ((uint8_t)0x04)

Capture/Compare 2 Interrupt Enable mask.

Definition at line 1183 of file stm8s.h.

#define TIM5_IER_CC3IE ((uint8_t)0x08)

Capture/Compare 3 Interrupt Enable mask.

Definition at line 1182 of file stm8s.h.

#define TIM5_IER_TIE ((uint8_t)0x40)

Trigger Interrupt Enable mask.

Definition at line 1181 of file stm8s.h.

#define TIM5_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable mask.

Definition at line 1185 of file stm8s.h.

#define TIM5_PSCR_PSC ((uint8_t)0xFF)

Prescaler Value (MSB) mask.

Definition at line 1220 of file stm8s.h.

#define TIM5_SMCR_MSM ((uint8_t)0x80)

Master/Slave Mode Mask.

Definition at line 1177 of file stm8s.h.

Referenced by TIM5_EncoderInterfaceConfig().

#define TIM5_SMCR_SMS ((uint8_t)0x07)

Slave Mode Selection Mask.

Definition at line 1179 of file stm8s.h.

Referenced by TIM5_InternalClockConfig(), and TIM5_SelectSlaveMode().

#define TIM5_SMCR_TS ((uint8_t)0x70)

Trigger Selection Mask.

Definition at line 1178 of file stm8s.h.

Referenced by TIM5_EncoderInterfaceConfig(), and TIM5_SelectInputTrigger().

#define TIM5_SR1_CC1IF ((uint8_t)0x02)

Capture/Compare 1 Interrupt Flag mask.

Definition at line 1190 of file stm8s.h.

#define TIM5_SR1_CC2IF ((uint8_t)0x04)

Capture/Compare 2 Interrupt Flag mask.

Definition at line 1189 of file stm8s.h.

#define TIM5_SR1_CC3IF ((uint8_t)0x08)

Capture/Compare 3 Interrupt Flag mask.

Definition at line 1188 of file stm8s.h.

#define TIM5_SR1_TIF ((uint8_t)0x40)

Trigger Interrupt Flag mask.

Definition at line 1187 of file stm8s.h.

#define TIM5_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag mask.

Definition at line 1191 of file stm8s.h.

#define TIM5_SR2_CC1OF ((uint8_t)0x02)

Capture/Compare 1 Overcapture Flag mask.

Definition at line 1195 of file stm8s.h.

#define TIM5_SR2_CC2OF ((uint8_t)0x04)

Capture/Compare 2 Overcapture Flag mask.

Definition at line 1194 of file stm8s.h.

#define TIM5_SR2_CC3OF ((uint8_t)0x08)

Capture/Compare 3 Overcapture Flag mask.

Definition at line 1193 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: TIM6_Registers_Reset_Value

Defines

TIM6_Registers_Reset_Value

Defines

#define | TIM6_ARR_RESET_VALUE ((uint8_t)0xFF)
#define | TIM6_CNTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_SR1_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define TIM6_ARR_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1268 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_CNTR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1266 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1260 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1261 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_EGR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1265 of file stm8s.h.

#define TIM6_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 1263 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1267 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_SMCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1262 of file stm8s.h.

Referenced by TIM6_DeInit().

#define TIM6_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1264 of file stm8s.h.

Referenced by TIM6_DeInit().


STM8S/A Standard Peripherals Drivers: TIM6_Registers_Bits_Definition

Defines

TIM6_Registers_Bits_Definition

Defines

#define | TIM6_ARR_ARR ((uint8_t)0xFF)
#define | TIM6_CNTR_CNT ((uint8_t)0xFF)
#define | TIM6_CR1_ARPE ((uint8_t)0x80)
#define | TIM6_CR1_CEN ((uint8_t)0x01)
#define | TIM6_CR1_OPM ((uint8_t)0x08)
#define | TIM6_CR1_UDIS ((uint8_t)0x02)
#define | TIM6_CR1_URS ((uint8_t)0x04)
#define | TIM6_CR2_MMS ((uint8_t)0x70)
#define | TIM6_EGR_TG ((uint8_t)0x40)
#define | TIM6_EGR_UG ((uint8_t)0x01)
#define | TIM6_IER_TIE ((uint8_t)0x40)
#define | TIM6_IER_UIE ((uint8_t)0x01)
#define | TIM6_PSCR_PSC ((uint8_t)0x07)
#define | TIM6_SMCR_MSM ((uint8_t)0x80)
#define | TIM6_SMCR_SMS ((uint8_t)0x07)
#define | TIM6_SMCR_TS ((uint8_t)0x70)
#define | TIM6_SR1_TIF ((uint8_t)0x40)
#define | TIM6_SR1_UIF ((uint8_t)0x01)

Define Documentation

#define TIM6_ARR_ARR ((uint8_t)0xFF)

Autoreload Value Mask.

Definition at line 1303 of file stm8s.h.

#define TIM6_CNTR_CNT ((uint8_t)0xFF)

Counter Value (LSB) Mask.

Definition at line 1299 of file stm8s.h.

#define TIM6_CR1_ARPE ((uint8_t)0x80)

Auto-Reload Preload Enable Mask.

Definition at line 1278 of file stm8s.h.

Referenced by TIM6_ARRPreloadConfig().

#define TIM6_CR1_CEN ((uint8_t)0x01)

Counter Enable Mask.

Definition at line 1282 of file stm8s.h.

Referenced by TIM6_Cmd().

#define TIM6_CR1_OPM ((uint8_t)0x08)

One Pulse Mode Mask.

Definition at line 1279 of file stm8s.h.

Referenced by TIM6_SelectOnePulseMode().

#define TIM6_CR1_UDIS ((uint8_t)0x02)

Update DIsable Mask.

Definition at line 1281 of file stm8s.h.

Referenced by TIM6_UpdateDisableConfig().

#define TIM6_CR1_URS ((uint8_t)0x04)

Update Request Source Mask.

Definition at line 1280 of file stm8s.h.

Referenced by TIM6_UpdateRequestConfig().

#define TIM6_CR2_MMS ((uint8_t)0x70)

MMS Selection Mask.

Definition at line 1284 of file stm8s.h.

Referenced by TIM6_SelectOutputTrigger().

#define TIM6_EGR_TG ((uint8_t)0x40)

Trigger Generation mask.

Definition at line 1296 of file stm8s.h.

#define TIM6_EGR_UG ((uint8_t)0x01)

Update Generation Mask.

Definition at line 1297 of file stm8s.h.

Referenced by TIM6_PrescalerConfig().

#define TIM6_IER_TIE ((uint8_t)0x40)

Trigger Interrupt Enable Mask.

Definition at line 1290 of file stm8s.h.

#define TIM6_IER_UIE ((uint8_t)0x01)

Update Interrupt Enable Mask.

Definition at line 1291 of file stm8s.h.

#define TIM6_PSCR_PSC ((uint8_t)0x07)

Prescaler Value Mask.

Definition at line 1301 of file stm8s.h.

#define TIM6_SMCR_MSM ((uint8_t)0x80)

Master/Slave Mode Mask.

Definition at line 1286 of file stm8s.h.

Referenced by TIM6_SelectMasterSlaveMode().

#define TIM6_SMCR_SMS ((uint8_t)0x07)

Slave Mode Selection Mask.

Definition at line 1288 of file stm8s.h.

Referenced by TIM6_InternalClockConfig(), and TIM6_SelectSlaveMode().

#define TIM6_SMCR_TS ((uint8_t)0x70)

Trigger Selection Mask.

Definition at line 1287 of file stm8s.h.

Referenced by TIM6_SelectInputTrigger().

#define TIM6_SR1_TIF ((uint8_t)0x40)

Trigger Interrupt Flag mask.

Definition at line 1293 of file stm8s.h.

#define TIM6_SR1_UIF ((uint8_t)0x01)

Update Interrupt Flag Mask.

Definition at line 1294 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: I2C_Registers_Reset_Value

Defines

I2C_Registers_Reset_Value

Defines

#define | I2C_CCRH_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CCRL_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CR1_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CR2_RESET_VALUE ((uint8_t)0x00)
#define | I2C_DR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_FREQR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_ITR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_OARH_RESET_VALUE ((uint8_t)0x00)
#define | I2C_OARL_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR1_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR2_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR3_RESET_VALUE ((uint8_t)0x00)
#define | I2C_TRISER_RESET_VALUE ((uint8_t)0x02)

Define Documentation

#define I2C_CCRH_RESET_VALUE ((uint8_t)0x00)

Definition at line 1347 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_CCRL_RESET_VALUE ((uint8_t)0x00)

Definition at line 1346 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1336 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1337 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_DR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1341 of file stm8s.h.

#define I2C_FREQR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1338 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_ITR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1345 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_OARH_RESET_VALUE ((uint8_t)0x00)

Definition at line 1340 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_OARL_RESET_VALUE ((uint8_t)0x00)

Definition at line 1339 of file stm8s.h.

Referenced by I2C_DeInit().

#define I2C_SR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1342 of file stm8s.h.

#define I2C_SR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1343 of file stm8s.h.

#define I2C_SR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 1344 of file stm8s.h.

#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)

Definition at line 1348 of file stm8s.h.

Referenced by I2C_DeInit().


STM8S/A Standard Peripherals Drivers: I2C_Registers_Bits_Definition

Defines

I2C_Registers_Bits_Definition

Defines

#define | I2C_CCRH_CCR ((uint8_t)0x0F)
#define | I2C_CCRH_DUTY ((uint8_t)0x40)
#define | I2C_CCRH_FS ((uint8_t)0x80)
#define | I2C_CCRL_CCR ((uint8_t)0xFF)
#define | I2C_CR1_ENGC ((uint8_t)0x40)
#define | I2C_CR1_NOSTRETCH ((uint8_t)0x80)
#define | I2C_CR1_PE ((uint8_t)0x01)
#define | I2C_CR2_ACK ((uint8_t)0x04)
#define | I2C_CR2_POS ((uint8_t)0x08)
#define | I2C_CR2_START ((uint8_t)0x01)
#define | I2C_CR2_STOP ((uint8_t)0x02)
#define | I2C_CR2_SWRST ((uint8_t)0x80)
#define | I2C_DR_DR ((uint8_t)0xFF)
#define | I2C_FREQR_FREQ ((uint8_t)0x3F)
#define | I2C_ITR_ITBUFEN ((uint8_t)0x04)
#define | I2C_ITR_ITERREN ((uint8_t)0x01)
#define | I2C_ITR_ITEVTEN ((uint8_t)0x02)
#define | I2C_OARH_ADD ((uint8_t)0x06)
#define | I2C_OARH_ADDCONF ((uint8_t)0x40)
#define | I2C_OARH_ADDMODE ((uint8_t)0x80)
#define | I2C_OARL_ADD ((uint8_t)0xFE)
#define | I2C_OARL_ADD0 ((uint8_t)0x01)
#define | I2C_SR1_ADD10 ((uint8_t)0x08)
#define | I2C_SR1_ADDR ((uint8_t)0x02)
#define | I2C_SR1_BTF ((uint8_t)0x04)
#define | I2C_SR1_RXNE ((uint8_t)0x40)
#define | I2C_SR1_SB ((uint8_t)0x01)
#define | I2C_SR1_STOPF ((uint8_t)0x10)
#define | I2C_SR1_TXE ((uint8_t)0x80)
#define | I2C_SR2_AF ((uint8_t)0x04)
#define | I2C_SR2_ARLO ((uint8_t)0x02)
#define | I2C_SR2_BERR ((uint8_t)0x01)
#define | I2C_SR2_OVR ((uint8_t)0x08)
#define | I2C_SR2_WUFH ((uint8_t)0x20)
#define | I2C_SR3_BUSY ((uint8_t)0x02)
#define | I2C_SR3_GENCALL ((uint8_t)0x10)
#define | I2C_SR3_MSL ((uint8_t)0x01)
#define | I2C_SR3_TRA ((uint8_t)0x04)
#define | I2C_TRISER_TRISE ((uint8_t)0x3F)

Define Documentation

#define I2C_CCRH_CCR ((uint8_t)0x0F)

Clock Control Register in Fast/Standard mode (Master mode) bits [11..8]

Definition at line 1406 of file stm8s.h.

Referenced by I2C_Init().

#define I2C_CCRH_DUTY ((uint8_t)0x40)

Fast Mode Duty Cycle

Definition at line 1405 of file stm8s.h.

Referenced by I2C_FastModeDutyCycleConfig(), and I2C_Init().

#define I2C_CCRH_FS ((uint8_t)0x80)

Master Mode Selection

Definition at line 1404 of file stm8s.h.

Referenced by I2C_Init().

#define I2C_CCRL_CCR ((uint8_t)0xFF)

Clock Control Register (Master mode)

Definition at line 1402 of file stm8s.h.

Referenced by I2C_Init().

#define I2C_CR1_ENGC ((uint8_t)0x40)

General Call Enable

Definition at line 1359 of file stm8s.h.

Referenced by I2C_GeneralCallCmd().

#define I2C_CR1_NOSTRETCH ((uint8_t)0x80)

Clock Stretching Disable (Slave mode)

Definition at line 1358 of file stm8s.h.

Referenced by I2C_StretchClockCmd().

#define I2C_CR1_PE ((uint8_t)0x01)

Peripheral Enable

Definition at line 1360 of file stm8s.h.

Referenced by I2C_Cmd(), and I2C_Init().

#define I2C_CR2_ACK ((uint8_t)0x04)

Acknowledge Enable

Definition at line 1364 of file stm8s.h.

Referenced by I2C_AcknowledgeConfig().

#define I2C_CR2_POS ((uint8_t)0x08)

Acknowledge

Definition at line 1363 of file stm8s.h.

Referenced by I2C_AcknowledgeConfig().

#define I2C_CR2_START ((uint8_t)0x01)

Start Generation

Definition at line 1366 of file stm8s.h.

Referenced by I2C_GenerateSTART().

#define I2C_CR2_STOP ((uint8_t)0x02)

Stop Generation

Definition at line 1365 of file stm8s.h.

Referenced by I2C_GenerateSTOP().

#define I2C_CR2_SWRST ((uint8_t)0x80)

Software Reset

Definition at line 1362 of file stm8s.h.

Referenced by I2C_SoftwareResetCmd().

#define I2C_DR_DR ((uint8_t)0xFF)

Data Register

Definition at line 1377 of file stm8s.h.

#define I2C_FREQR_FREQ ((uint8_t)0x3F)

Peripheral Clock Frequency

Definition at line 1368 of file stm8s.h.

Referenced by I2C_Init().

#define I2C_ITR_ITBUFEN ((uint8_t)0x04)

Buffer Interrupt Enable

Definition at line 1398 of file stm8s.h.

#define I2C_ITR_ITERREN ((uint8_t)0x01)

Error Interrupt Enable

Definition at line 1400 of file stm8s.h.

#define I2C_ITR_ITEVTEN ((uint8_t)0x02)

Event Interrupt Enable

Definition at line 1399 of file stm8s.h.

#define I2C_OARH_ADD ((uint8_t)0x06)

Interface Address bits [9..8]

Definition at line 1375 of file stm8s.h.

#define I2C_OARH_ADDCONF ((uint8_t)0x40)

Address Mode Configuration

Definition at line 1374 of file stm8s.h.

Referenced by I2C_Init().

#define I2C_OARH_ADDMODE ((uint8_t)0x80)

Addressing Mode (Slave mode)

Definition at line 1373 of file stm8s.h.

#define I2C_OARL_ADD ((uint8_t)0xFE)

Interface Address bits [7..1]

Definition at line 1370 of file stm8s.h.

#define I2C_OARL_ADD0 ((uint8_t)0x01)

Interface Address bit0

Definition at line 1371 of file stm8s.h.

#define I2C_SR1_ADD10 ((uint8_t)0x08)

10-bit header sent (Master mode)

Definition at line 1382 of file stm8s.h.

#define I2C_SR1_ADDR ((uint8_t)0x02)

Address sent (master mode)/matched (slave mode)

Definition at line 1384 of file stm8s.h.

#define I2C_SR1_BTF ((uint8_t)0x04)

Byte Transfer Finished

Definition at line 1383 of file stm8s.h.

#define I2C_SR1_RXNE ((uint8_t)0x40)

Data Register not Empty (receivers)

Definition at line 1380 of file stm8s.h.

#define I2C_SR1_SB ((uint8_t)0x01)

Start Bit (Master mode)

Definition at line 1385 of file stm8s.h.

#define I2C_SR1_STOPF ((uint8_t)0x10)

Stop detection (Slave mode)

Definition at line 1381 of file stm8s.h.

#define I2C_SR1_TXE ((uint8_t)0x80)

Data Register Empty (transmitters)

Definition at line 1379 of file stm8s.h.

#define I2C_SR2_AF ((uint8_t)0x04)

Acknowledge Failure

Definition at line 1389 of file stm8s.h.

Referenced by I2C_CheckEvent(), and I2C_GetLastEvent().

#define I2C_SR2_ARLO ((uint8_t)0x02)

Arbitration Lost (master mode)

Definition at line 1390 of file stm8s.h.

#define I2C_SR2_BERR ((uint8_t)0x01)

Bus Error

Definition at line 1391 of file stm8s.h.

#define I2C_SR2_OVR ((uint8_t)0x08)

Overrun/Underrun

Definition at line 1388 of file stm8s.h.

#define I2C_SR2_WUFH ((uint8_t)0x20)

Wake-up from Halt

Definition at line 1387 of file stm8s.h.

#define I2C_SR3_BUSY ((uint8_t)0x02)

Bus Busy

Definition at line 1395 of file stm8s.h.

#define I2C_SR3_GENCALL ((uint8_t)0x10)

General Call Header (Slave mode)

Definition at line 1393 of file stm8s.h.

#define I2C_SR3_MSL ((uint8_t)0x01)

Master/Slave

Definition at line 1396 of file stm8s.h.

#define I2C_SR3_TRA ((uint8_t)0x04)

Transmitter/Receiver

Definition at line 1394 of file stm8s.h.

#define I2C_TRISER_TRISE ((uint8_t)0x3F)

Maximum Rise Time in Fast/Standard mode (Master mode)

Definition at line 1408 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: ITC_Registers_Reset_Value

Defines

ITC_Registers_Reset_Value

Defines

#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF)

Define Documentation

#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF)

Reset value of Software Priority registers

Definition at line 1436 of file stm8s.h.

Referenced by ITC_DeInit().


STM8S/A Standard Peripherals Drivers: CPU_Registers_Bits_Definition

Defines

CPU_Registers_Bits_Definition

Defines

#define CPU_CC_I1I0 ((uint8_t)0x28)

Define Documentation

#define CPU_CC_I1I0 ((uint8_t)0x28)

Condition Code register, I1 and I0 bits mask

Definition at line 1446 of file stm8s.h.

Referenced by ITC_GetSoftIntStatus().


STM8S/A Standard Peripherals Drivers: EXTI_Registers_Reset_Value

Defines

EXTI_Registers_Reset_Value

Defines

#define | EXTI_CR1_RESET_VALUE ((uint8_t)0x00)
#define | EXTI_CR2_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define EXTI_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1468 of file stm8s.h.

Referenced by EXTI_DeInit().

#define EXTI_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1469 of file stm8s.h.

Referenced by EXTI_DeInit().


STM8S/A Standard Peripherals Drivers: EXTI_Registers_Bits_Definition

Defines

EXTI_Registers_Bits_Definition

Defines

#define | EXTI_CR1_PAIS ((uint8_t)0x03)
#define | EXTI_CR1_PBIS ((uint8_t)0x0C)
#define | EXTI_CR1_PCIS ((uint8_t)0x30)
#define | EXTI_CR1_PDIS ((uint8_t)0xC0)
#define | EXTI_CR2_PEIS ((uint8_t)0x03)
#define | EXTI_CR2_TLIS ((uint8_t)0x04)

Define Documentation

#define EXTI_CR1_PAIS ((uint8_t)0x03)

PORTA external interrupt sensitivity bits mask

Definition at line 1482 of file stm8s.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define EXTI_CR1_PBIS ((uint8_t)0x0C)

PORTB external interrupt sensitivity bits mask

Definition at line 1481 of file stm8s.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define EXTI_CR1_PCIS ((uint8_t)0x30)

PORTC external interrupt sensitivity bits mask

Definition at line 1480 of file stm8s.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define EXTI_CR1_PDIS ((uint8_t)0xC0)

PORTD external interrupt sensitivity bits mask

Definition at line 1479 of file stm8s.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define EXTI_CR2_PEIS ((uint8_t)0x03)

PORTE external interrupt sensitivity bits mask

Definition at line 1485 of file stm8s.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define EXTI_CR2_TLIS ((uint8_t)0x04)

Top level interrupt sensitivity bit mask

Definition at line 1484 of file stm8s.h.

Referenced by EXTI_GetTLISensitivity(), and EXTI_SetTLISensitivity().


STM8S/A Standard Peripherals Drivers: FLASH_Registers_Reset_Value

Defines

FLASH_Registers_Reset_Value

Defines

#define | FLASH_CR1_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_CR2_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_DUKR_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)
#define | FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF)
#define | FLASH_PUKR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define FLASH_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1518 of file stm8s.h.

Referenced by FLASH_DeInit().

#define FLASH_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1519 of file stm8s.h.

Referenced by FLASH_DeInit().

#define FLASH_DUKR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1523 of file stm8s.h.

#define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)

Definition at line 1521 of file stm8s.h.

#define FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1520 of file stm8s.h.

Referenced by FLASH_DeInit().

#define FLASH_PUKR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1522 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: FLASH_Registers_Bits_Definition

Defines

FLASH_Registers_Bits_Definition

Defines

#define | FLASH_CR1_AHALT ((uint8_t)0x04)
#define | FLASH_CR1_FIX ((uint8_t)0x01)
#define | FLASH_CR1_HALT ((uint8_t)0x08)
#define | FLASH_CR1_IE ((uint8_t)0x02)
#define | FLASH_CR2_ERASE ((uint8_t)0x20)
#define | FLASH_CR2_FPRG ((uint8_t)0x10)
#define | FLASH_CR2_OPT ((uint8_t)0x80)
#define | FLASH_CR2_PRG ((uint8_t)0x01)
#define | FLASH_CR2_WPRG ((uint8_t)0x40)
#define | FLASH_DUKR_DUK ((uint8_t)0xFF)
#define | FLASH_IAPSR_DUL ((uint8_t)0x08)
#define | FLASH_IAPSR_EOP ((uint8_t)0x04)
#define | FLASH_IAPSR_HVOFF ((uint8_t)0x40)
#define | FLASH_IAPSR_PUL ((uint8_t)0x02)
#define | FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01)
#define | FLASH_NCR2_NERASE ((uint8_t)0x20)
#define | FLASH_NCR2_NFPRG ((uint8_t)0x10)
#define | FLASH_NCR2_NOPT ((uint8_t)0x80)
#define | FLASH_NCR2_NPRG ((uint8_t)0x01)
#define | FLASH_NCR2_NWPRG ((uint8_t)0x40)
#define | FLASH_PUKR_PUK ((uint8_t)0xFF)

Define Documentation

#define FLASH_CR1_AHALT ((uint8_t)0x04)

Standby in Active Halt mode mask

Definition at line 1534 of file stm8s.h.

Referenced by FLASH_GetLowPowerMode(), and FLASH_SetLowPowerMode().

#define FLASH_CR1_FIX ((uint8_t)0x01)

Fix programming time mask

Definition at line 1536 of file stm8s.h.

Referenced by FLASH_GetProgrammingTime(), and FLASH_SetProgrammingTime().

#define FLASH_CR1_HALT ((uint8_t)0x08)

Standby in Halt mode mask

Definition at line 1533 of file stm8s.h.

Referenced by FLASH_GetLowPowerMode(), and FLASH_SetLowPowerMode().

#define FLASH_CR1_IE ((uint8_t)0x02)

Flash Interrupt enable mask

Definition at line 1535 of file stm8s.h.

Referenced by FLASH_ITConfig().

#define FLASH_CR2_ERASE ((uint8_t)0x20)

Erase block mask

Definition at line 1540 of file stm8s.h.

#define FLASH_CR2_FPRG ((uint8_t)0x10)

Fast programming mode mask

Definition at line 1541 of file stm8s.h.

#define FLASH_CR2_OPT ((uint8_t)0x80)

Select option byte mask

Definition at line 1538 of file stm8s.h.

Referenced by FLASH_EraseOptionByte(), and FLASH_ProgramOptionByte().

#define FLASH_CR2_PRG ((uint8_t)0x01)

Program block mask

Definition at line 1542 of file stm8s.h.

#define FLASH_CR2_WPRG ((uint8_t)0x40)

Word Programming mask

Definition at line 1539 of file stm8s.h.

Referenced by FLASH_ProgramWord().

#define FLASH_DUKR_DUK ((uint8_t)0xFF)

Data EEPROM unprotection mask

Definition at line 1558 of file stm8s.h.

#define FLASH_IAPSR_DUL ((uint8_t)0x08)

Data EEPROM unlocked flag mask

Definition at line 1551 of file stm8s.h.

Referenced by FLASH_DeInit().

#define FLASH_IAPSR_EOP ((uint8_t)0x04)

End of operation flag mask

Definition at line 1552 of file stm8s.h.

#define FLASH_IAPSR_HVOFF ((uint8_t)0x40)

End of high voltage flag mask

Definition at line 1550 of file stm8s.h.

#define FLASH_IAPSR_PUL ((uint8_t)0x02)

Flash Program memory unlocked flag mask

Definition at line 1553 of file stm8s.h.

Referenced by FLASH_DeInit().

#define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01)

Write attempted to protected page mask

Definition at line 1554 of file stm8s.h.

#define FLASH_NCR2_NERASE ((uint8_t)0x20)

Erase block mask

Definition at line 1546 of file stm8s.h.

#define FLASH_NCR2_NFPRG ((uint8_t)0x10)

Fast programming mode mask

Definition at line 1547 of file stm8s.h.

#define FLASH_NCR2_NOPT ((uint8_t)0x80)

Select option byte mask

Definition at line 1544 of file stm8s.h.

Referenced by FLASH_EraseOptionByte(), and FLASH_ProgramOptionByte().

#define FLASH_NCR2_NPRG ((uint8_t)0x01)

Program block mask

Definition at line 1548 of file stm8s.h.

#define FLASH_NCR2_NWPRG ((uint8_t)0x40)

Word Programming mask

Definition at line 1545 of file stm8s.h.

Referenced by FLASH_ProgramWord().

#define FLASH_PUKR_PUK ((uint8_t)0xFF)

Flash Program memory unprotection mask

Definition at line 1556 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: IWDG_Registers_Reset_Value

Defines

IWDG_Registers_Reset_Value

Defines

#define | IWDG_PR_RESET_VALUE ((uint8_t)0x00)
#define | IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)

Define Documentation

#define IWDG_PR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1605 of file stm8s.h.

#define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)

Definition at line 1606 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: WWDG_Registers_Reset_Value

Defines

WWDG_Registers_Reset_Value

Defines

#define | WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
#define | WWDG_WR_RESET_VALUE ((uint8_t)0x7F)

Define Documentation

#define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)

Definition at line 1628 of file stm8s.h.

#define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)

Definition at line 1629 of file stm8s.h.

Referenced by WWDG_Init().


STM8S/A Standard Peripherals Drivers: WWDG_Registers_Bits_Definition

Defines

WWDG_Registers_Bits_Definition

Defines

#define | WWDG_CR_T ((uint8_t)0x7F)
#define | WWDG_CR_T6 ((uint8_t)0x40)
#define | WWDG_CR_WDGA ((uint8_t)0x80)
#define | WWDG_WR_MSB ((uint8_t)0x80)
#define | WWDG_WR_W ((uint8_t)0x7F)

Define Documentation

#define WWDG_CR_T ((uint8_t)0x7F)

T bits mask

Definition at line 1641 of file stm8s.h.

#define WWDG_CR_T6 ((uint8_t)0x40)

T6 bit mask

Definition at line 1640 of file stm8s.h.

Referenced by WWDG_Init(), and WWDG_SetWindowValue().

#define WWDG_CR_WDGA ((uint8_t)0x80)

WDGA bit mask

Definition at line 1639 of file stm8s.h.

Referenced by WWDG_Init(), WWDG_SetWindowValue(), and WWDG_SWReset().

#define WWDG_WR_MSB ((uint8_t)0x80)

MSB bit mask

Definition at line 1643 of file stm8s.h.

#define WWDG_WR_W ((uint8_t)0x7F)

W bits mask

Definition at line 1644 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: RST_Registers_Bits_Definition

Defines

RST_Registers_Bits_Definition

Defines

#define | RST_SR_EMCF ((uint8_t)0x10)
#define | RST_SR_ILLOPF ((uint8_t)0x04)
#define | RST_SR_IWDGF ((uint8_t)0x02)
#define | RST_SR_SWIMF ((uint8_t)0x08)
#define | RST_SR_WWDGF ((uint8_t)0x01)

Define Documentation

#define RST_SR_EMCF ((uint8_t)0x10)

EMC reset flag bit mask

Definition at line 1665 of file stm8s.h.

#define RST_SR_ILLOPF ((uint8_t)0x04)

Illegal opcode reset flag bit mask

Definition at line 1667 of file stm8s.h.

#define RST_SR_IWDGF ((uint8_t)0x02)

IWDG reset flag bit mask

Definition at line 1668 of file stm8s.h.

#define RST_SR_SWIMF ((uint8_t)0x08)

SWIM reset flag bit mask

Definition at line 1666 of file stm8s.h.

#define RST_SR_WWDGF ((uint8_t)0x01)

WWDG reset flag bit mask

Definition at line 1669 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: SPI_Registers_Reset_Value

Defines

SPI_Registers_Reset_Value

Defines

#define | SPI_CR1_RESET_VALUE ((uint8_t)0x00)
#define | SPI_CR2_RESET_VALUE ((uint8_t)0x00)
#define | SPI_CRCPR_RESET_VALUE ((uint8_t)0x07)
#define | SPI_DR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_ICR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_SR_RESET_VALUE ((uint8_t)0x02)
#define | SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define SPI_CR1_RESET_VALUE ((uint8_t)0x00)

Control Register 1 reset value

Definition at line 1697 of file stm8s.h.

Referenced by SPI_DeInit().

#define SPI_CR2_RESET_VALUE ((uint8_t)0x00)

Control Register 2 reset value

Definition at line 1698 of file stm8s.h.

Referenced by SPI_DeInit().

#define SPI_CRCPR_RESET_VALUE ((uint8_t)0x07)

Polynomial Register reset value

Definition at line 1702 of file stm8s.h.

Referenced by SPI_DeInit().

#define SPI_DR_RESET_VALUE ((uint8_t)0x00)

Data Register reset value

Definition at line 1701 of file stm8s.h.

#define SPI_ICR_RESET_VALUE ((uint8_t)0x00)

Interrupt Control Register reset value

Definition at line 1699 of file stm8s.h.

Referenced by SPI_DeInit().

#define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00)

RX CRC Register reset value

Definition at line 1703 of file stm8s.h.

#define SPI_SR_RESET_VALUE ((uint8_t)0x02)

Status Register reset value

Definition at line 1700 of file stm8s.h.

Referenced by SPI_DeInit().

#define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00)

TX CRC Register reset value

Definition at line 1704 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: SPI_Registers_Bits_Definition

Defines

SPI_Registers_Bits_Definition

Defines

#define | SPI_CR1_BR ((uint8_t)0x38)
#define | SPI_CR1_CPHA ((uint8_t)0x01)
#define | SPI_CR1_CPOL ((uint8_t)0x02)
#define | SPI_CR1_LSBFIRST ((uint8_t)0x80)
#define | SPI_CR1_MSTR ((uint8_t)0x04)
#define | SPI_CR1_SPE ((uint8_t)0x40)
#define | SPI_CR2_BDM ((uint8_t)0x80)
#define | SPI_CR2_BDOE ((uint8_t)0x40)
#define | SPI_CR2_CRCEN ((uint8_t)0x20)
#define | SPI_CR2_CRCNEXT ((uint8_t)0x10)
#define | SPI_CR2_RXONLY ((uint8_t)0x04)
#define | SPI_CR2_SSI ((uint8_t)0x01)
#define | SPI_CR2_SSM ((uint8_t)0x02)
#define | SPI_ICR_ERRIE ((uint8_t)0x20)
#define | SPI_ICR_RXEI ((uint8_t)0x40)
#define | SPI_ICR_TXEI ((uint8_t)0x80)
#define | SPI_ICR_WKIE ((uint8_t)0x10)
#define | SPI_SR_BSY ((uint8_t)0x80)
#define | SPI_SR_CRCERR ((uint8_t)0x10)
#define | SPI_SR_MODF ((uint8_t)0x20)
#define | SPI_SR_OVR ((uint8_t)0x40)
#define | SPI_SR_RXNE ((uint8_t)0x01)
#define | SPI_SR_TXE ((uint8_t)0x02)
#define | SPI_SR_WKUP ((uint8_t)0x08)

Define Documentation

#define SPI_CR1_BR ((uint8_t)0x38)

Baud rate control mask

Definition at line 1716 of file stm8s.h.

#define SPI_CR1_CPHA ((uint8_t)0x01)

Clock Phase mask

Definition at line 1719 of file stm8s.h.

#define SPI_CR1_CPOL ((uint8_t)0x02)

Clock Polarity mask

Definition at line 1718 of file stm8s.h.

#define SPI_CR1_LSBFIRST ((uint8_t)0x80)

Frame format mask

Definition at line 1714 of file stm8s.h.

#define SPI_CR1_MSTR ((uint8_t)0x04)

Master Selection mask

Definition at line 1717 of file stm8s.h.

#define SPI_CR1_SPE ((uint8_t)0x40)

Enable bits mask

Definition at line 1715 of file stm8s.h.

Referenced by SPI_Cmd().

#define SPI_CR2_BDM ((uint8_t)0x80)

Bi-directional data mode enable mask

Definition at line 1721 of file stm8s.h.

#define SPI_CR2_BDOE ((uint8_t)0x40)

Output enable in bi-directional mode mask

Definition at line 1722 of file stm8s.h.

Referenced by SPI_BiDirectionalLineConfig().

#define SPI_CR2_CRCEN ((uint8_t)0x20)

Hardware CRC calculation enable mask

Definition at line 1723 of file stm8s.h.

Referenced by SPI_CalculateCRCCmd().

#define SPI_CR2_CRCNEXT ((uint8_t)0x10)

Transmit CRC next mask

Definition at line 1724 of file stm8s.h.

Referenced by SPI_TransmitCRC().

#define SPI_CR2_RXONLY ((uint8_t)0x04)

Receive only mask

Definition at line 1725 of file stm8s.h.

#define SPI_CR2_SSI ((uint8_t)0x01)

Internal slave select mask

Definition at line 1727 of file stm8s.h.

Referenced by SPI_Init(), and SPI_NSSInternalSoftwareCmd().

#define SPI_CR2_SSM ((uint8_t)0x02)

Software slave management mask

Definition at line 1726 of file stm8s.h.

#define SPI_ICR_ERRIE ((uint8_t)0x20)

Error interrupt enable mask

Definition at line 1731 of file stm8s.h.

#define SPI_ICR_RXEI ((uint8_t)0x40)

Rx buffer empty interrupt enable mask

Definition at line 1730 of file stm8s.h.

#define SPI_ICR_TXEI ((uint8_t)0x80)

Tx buffer empty interrupt enable mask

Definition at line 1729 of file stm8s.h.

#define SPI_ICR_WKIE ((uint8_t)0x10)

Wake-up interrupt enable mask

Definition at line 1732 of file stm8s.h.

#define SPI_SR_BSY ((uint8_t)0x80)

Busy flag

Definition at line 1734 of file stm8s.h.

#define SPI_SR_CRCERR ((uint8_t)0x10)

CRC error flag

Definition at line 1737 of file stm8s.h.

#define SPI_SR_MODF ((uint8_t)0x20)

Mode fault

Definition at line 1736 of file stm8s.h.

#define SPI_SR_OVR ((uint8_t)0x40)

Overrun flag

Definition at line 1735 of file stm8s.h.

#define SPI_SR_RXNE ((uint8_t)0x01)

Receive buffer not empty

Definition at line 1740 of file stm8s.h.

#define SPI_SR_TXE ((uint8_t)0x02)

Transmit buffer empty

Definition at line 1739 of file stm8s.h.

#define SPI_SR_WKUP ((uint8_t)0x08)

Wake-Up flag

Definition at line 1738 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART1_Registers_Reset_Value

Defines

UART1_Registers_Reset_Value

Defines

#define | UART1_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART1_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR5_RESET_VALUE ((uint8_t)0x00)
#define | UART1_GTR_RESET_VALUE ((uint8_t)0x00)
#define | UART1_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | UART1_SR_RESET_VALUE ((uint8_t)0xC0)

Define Documentation

#define UART1_BRR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1772 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_BRR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1773 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1774 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1775 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_CR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 1776 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_CR4_RESET_VALUE ((uint8_t)0x00)

Definition at line 1777 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_CR5_RESET_VALUE ((uint8_t)0x00)

Definition at line 1778 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_GTR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1779 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1780 of file stm8s.h.

Referenced by UART1_DeInit().

#define UART1_SR_RESET_VALUE ((uint8_t)0xC0)

Definition at line 1771 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART1_Registers_Bits_Definition

Defines

UART1_Registers_Bits_Definition

Defines

#define | UART1_BRR1_DIVM ((uint8_t)0xFF)
#define | UART1_BRR2_DIVF ((uint8_t)0x0F)
#define | UART1_BRR2_DIVM ((uint8_t)0xF0)
#define | UART1_CR1_M ((uint8_t)0x10)
#define | UART1_CR1_PCEN ((uint8_t)0x04)
#define | UART1_CR1_PIEN ((uint8_t)0x01)
#define | UART1_CR1_PS ((uint8_t)0x02)
#define | UART1_CR1_R8 ((uint8_t)0x80)
#define | UART1_CR1_T8 ((uint8_t)0x40)
#define | UART1_CR1_UARTD ((uint8_t)0x20)
#define | UART1_CR1_WAKE ((uint8_t)0x08)
#define | UART1_CR2_ILIEN ((uint8_t)0x10)
#define | UART1_CR2_REN ((uint8_t)0x04)
#define | UART1_CR2_RIEN ((uint8_t)0x20)
#define | UART1_CR2_RWU ((uint8_t)0x02)
#define | UART1_CR2_SBK ((uint8_t)0x01)
#define | UART1_CR2_TCIEN ((uint8_t)0x40)
#define | UART1_CR2_TEN ((uint8_t)0x08)
#define | UART1_CR2_TIEN ((uint8_t)0x80)
#define | UART1_CR3_CKEN ((uint8_t)0x08)
#define | UART1_CR3_CPHA ((uint8_t)0x02)
#define | UART1_CR3_CPOL ((uint8_t)0x04)
#define | UART1_CR3_LBCL ((uint8_t)0x01)
#define | UART1_CR3_LINEN ((uint8_t)0x40)
#define | UART1_CR3_STOP ((uint8_t)0x30)
#define | UART1_CR4_ADD ((uint8_t)0x0F)
#define | UART1_CR4_LBDF ((uint8_t)0x10)
#define | UART1_CR4_LBDIEN ((uint8_t)0x40)
#define | UART1_CR4_LBDL ((uint8_t)0x20)
#define | UART1_CR5_HDSEL ((uint8_t)0x08)
#define | UART1_CR5_IREN ((uint8_t)0x02)
#define | UART1_CR5_IRLP ((uint8_t)0x04)
#define | UART1_CR5_NACK ((uint8_t)0x10)
#define | UART1_CR5_SCEN ((uint8_t)0x20)
#define | UART1_SR_FE ((uint8_t)0x02)
#define | UART1_SR_IDLE ((uint8_t)0x10)
#define | UART1_SR_NF ((uint8_t)0x04)
#define | UART1_SR_OR ((uint8_t)0x08)
#define | UART1_SR_PE ((uint8_t)0x01)
#define | UART1_SR_RXNE ((uint8_t)0x20)
#define | UART1_SR_TC ((uint8_t)0x40)
#define | UART1_SR_TXE ((uint8_t)0x80)

Define Documentation

#define UART1_BRR1_DIVM ((uint8_t)0xFF)

LSB mantissa of UART1DIV [7:0] mask

Definition at line 1799 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_BRR2_DIVF ((uint8_t)0x0F)

Fraction bits of UART1DIV [3:0] mask

Definition at line 1802 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_BRR2_DIVM ((uint8_t)0xF0)

MSB mantissa of UART1DIV [11:8] mask

Definition at line 1801 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR1_M ((uint8_t)0x10)

Word length mask

Definition at line 1807 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR1_PCEN ((uint8_t)0x04)

Parity Control Enable mask

Definition at line 1809 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR1_PIEN ((uint8_t)0x01)

UART1 Parity Interrupt Enable mask

Definition at line 1811 of file stm8s.h.

#define UART1_CR1_PS ((uint8_t)0x02)

UART1 Parity Selection

Definition at line 1810 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR1_R8 ((uint8_t)0x80)

Receive Data bit 8

Definition at line 1804 of file stm8s.h.

Referenced by UART1_ReceiveData9().

#define UART1_CR1_T8 ((uint8_t)0x40)

Transmit data bit 8

Definition at line 1805 of file stm8s.h.

Referenced by UART1_SendData9().

#define UART1_CR1_UARTD ((uint8_t)0x20)

UART1 Disable (for low power consumption)

Definition at line 1806 of file stm8s.h.

Referenced by UART1_Cmd().

#define UART1_CR1_WAKE ((uint8_t)0x08)

Wake-up method mask

Definition at line 1808 of file stm8s.h.

Referenced by UART1_WakeUpConfig().

#define UART1_CR2_ILIEN ((uint8_t)0x10)

IDLE Line Interrupt Enable mask

Definition at line 1816 of file stm8s.h.

#define UART1_CR2_REN ((uint8_t)0x04)

Receiver Enable mask

Definition at line 1818 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR2_RIEN ((uint8_t)0x20)

Receiver Interrupt Enable mask

Definition at line 1815 of file stm8s.h.

#define UART1_CR2_RWU ((uint8_t)0x02)

Receiver Wake-Up mask

Definition at line 1819 of file stm8s.h.

Referenced by UART1_ReceiverWakeUpCmd().

#define UART1_CR2_SBK ((uint8_t)0x01)

Send Break mask

Definition at line 1820 of file stm8s.h.

Referenced by UART1_SendBreak().

#define UART1_CR2_TCIEN ((uint8_t)0x40)

Transmission Complete Interrupt Enable mask

Definition at line 1814 of file stm8s.h.

#define UART1_CR2_TEN ((uint8_t)0x08)

Transmitter Enable mask

Definition at line 1817 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR2_TIEN ((uint8_t)0x80)

Transmitter Interrupt Enable mask

Definition at line 1813 of file stm8s.h.

#define UART1_CR3_CKEN ((uint8_t)0x08)

Clock Enable mask

Definition at line 1824 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR3_CPHA ((uint8_t)0x02)

Clock Phase mask

Definition at line 1826 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR3_CPOL ((uint8_t)0x04)

Clock Polarity mask

Definition at line 1825 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR3_LBCL ((uint8_t)0x01)

Last Bit Clock pulse mask

Definition at line 1827 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR3_LINEN ((uint8_t)0x40)

Alternate Function output mask

Definition at line 1822 of file stm8s.h.

Referenced by UART1_LINCmd().

#define UART1_CR3_STOP ((uint8_t)0x30)

STOP bits [1:0] mask

Definition at line 1823 of file stm8s.h.

Referenced by UART1_Init().

#define UART1_CR4_ADD ((uint8_t)0x0F)

Address of the UART1 node mask

Definition at line 1832 of file stm8s.h.

Referenced by UART1_SetAddress().

#define UART1_CR4_LBDF ((uint8_t)0x10)

LIN Break Detection Flag mask

Definition at line 1831 of file stm8s.h.

Referenced by UART1_ClearFlag(), and UART1_ClearITPendingBit().

#define UART1_CR4_LBDIEN ((uint8_t)0x40)

LIN Break Detection Interrupt Enable mask

Definition at line 1829 of file stm8s.h.

#define UART1_CR4_LBDL ((uint8_t)0x20)

LIN Break Detection Length mask

Definition at line 1830 of file stm8s.h.

Referenced by UART1_LINBreakDetectionConfig().

#define UART1_CR5_HDSEL ((uint8_t)0x08)

Half-Duplex Selection mask

Definition at line 1836 of file stm8s.h.

Referenced by UART1_HalfDuplexCmd().

#define UART1_CR5_IREN ((uint8_t)0x02)

Irda Enable mask

Definition at line 1838 of file stm8s.h.

Referenced by UART1_IrDACmd().

#define UART1_CR5_IRLP ((uint8_t)0x04)

Irda Low Power Selection mask

Definition at line 1837 of file stm8s.h.

Referenced by UART1_IrDAConfig().

#define UART1_CR5_NACK ((uint8_t)0x10)

Smart Card Nack Enable mask

Definition at line 1835 of file stm8s.h.

Referenced by UART1_SmartCardNACKCmd().

#define UART1_CR5_SCEN ((uint8_t)0x20)

Smart Card Enable mask

Definition at line 1834 of file stm8s.h.

Referenced by UART1_SmartCardCmd().

#define UART1_SR_FE ((uint8_t)0x02)

Framing Error mask

Definition at line 1796 of file stm8s.h.

#define UART1_SR_IDLE ((uint8_t)0x10)

IDLE line detected mask

Definition at line 1793 of file stm8s.h.

#define UART1_SR_NF ((uint8_t)0x04)

Noise Flag mask

Definition at line 1795 of file stm8s.h.

#define UART1_SR_OR ((uint8_t)0x08)

OverRun error mask

Definition at line 1794 of file stm8s.h.

#define UART1_SR_PE ((uint8_t)0x01)

Parity Error mask

Definition at line 1797 of file stm8s.h.

#define UART1_SR_RXNE ((uint8_t)0x20)

Read Data Register Not Empty mask

Definition at line 1792 of file stm8s.h.

Referenced by UART1_ClearFlag(), and UART1_ClearITPendingBit().

#define UART1_SR_TC ((uint8_t)0x40)

Transmission Complete mask

Definition at line 1791 of file stm8s.h.

#define UART1_SR_TXE ((uint8_t)0x80)

Transmit Data Register Empty mask

Definition at line 1790 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART2_Registers_Reset_Value

Defines

UART2_Registers_Reset_Value

Defines

#define | UART2_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART2_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR5_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR6_RESET_VALUE ((uint8_t)0x00)
#define | UART2_GTR_RESET_VALUE ((uint8_t)0x00)
#define | UART2_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | UART2_SR_RESET_VALUE ((uint8_t)0xC0)

Define Documentation

#define UART2_BRR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1871 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_BRR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1872 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1873 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1874 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 1875 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR4_RESET_VALUE ((uint8_t)0x00)

Definition at line 1876 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR5_RESET_VALUE ((uint8_t)0x00)

Definition at line 1877 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_CR6_RESET_VALUE ((uint8_t)0x00)

Definition at line 1878 of file stm8s.h.

Referenced by UART2_DeInit().

#define UART2_GTR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1879 of file stm8s.h.

#define UART2_PSCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 1880 of file stm8s.h.

#define UART2_SR_RESET_VALUE ((uint8_t)0xC0)

Definition at line 1870 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART2_Registers_Bits_Definition

Defines

UART2_Registers_Bits_Definition

Defines

#define | UART2_BRR1_DIVM ((uint8_t)0xFF)
#define | UART2_BRR2_DIVF ((uint8_t)0x0F)
#define | UART2_BRR2_DIVM ((uint8_t)0xF0)
#define | UART2_CR1_M ((uint8_t)0x10)
#define | UART2_CR1_PCEN ((uint8_t)0x04)
#define | UART2_CR1_PIEN ((uint8_t)0x01)
#define | UART2_CR1_PS ((uint8_t)0x02)
#define | UART2_CR1_R8 ((uint8_t)0x80)
#define | UART2_CR1_T8 ((uint8_t)0x40)
#define | UART2_CR1_UARTD ((uint8_t)0x20)
#define | UART2_CR1_WAKE ((uint8_t)0x08)
#define | UART2_CR2_ILIEN ((uint8_t)0x10)
#define | UART2_CR2_REN ((uint8_t)0x04)
#define | UART2_CR2_RIEN ((uint8_t)0x20)
#define | UART2_CR2_RWU ((uint8_t)0x02)
#define | UART2_CR2_SBK ((uint8_t)0x01)
#define | UART2_CR2_TCIEN ((uint8_t)0x40)
#define | UART2_CR2_TEN ((uint8_t)0x08)
#define | UART2_CR2_TIEN ((uint8_t)0x80)
#define | UART2_CR3_CKEN ((uint8_t)0x08)
#define | UART2_CR3_CPHA ((uint8_t)0x02)
#define | UART2_CR3_CPOL ((uint8_t)0x04)
#define | UART2_CR3_LBCL ((uint8_t)0x01)
#define | UART2_CR3_LINEN ((uint8_t)0x40)
#define | UART2_CR3_STOP ((uint8_t)0x30)
#define | UART2_CR4_ADD ((uint8_t)0x0F)
#define | UART2_CR4_LBDF ((uint8_t)0x10)
#define | UART2_CR4_LBDIEN ((uint8_t)0x40)
#define | UART2_CR4_LBDL ((uint8_t)0x20)
#define | UART2_CR5_HDSEL ((uint8_t)0x08)
#define | UART2_CR5_IREN ((uint8_t)0x02)
#define | UART2_CR5_IRLP ((uint8_t)0x04)
#define | UART2_CR5_NACK ((uint8_t)0x10)
#define | UART2_CR5_SCEN ((uint8_t)0x20)
#define | UART2_CR6_LASE ((uint8_t)0x10)
#define | UART2_CR6_LDUM ((uint8_t)0x80)
#define | UART2_CR6_LHDF ((uint8_t)0x02)
#define | UART2_CR6_LHDIEN ((uint8_t)0x04)
#define | UART2_CR6_LSF ((uint8_t)0x01)
#define | UART2_CR6_LSLV ((uint8_t)0x20)
#define | UART2_SR_FE ((uint8_t)0x02)
#define | UART2_SR_IDLE ((uint8_t)0x10)
#define | UART2_SR_NF ((uint8_t)0x04)
#define | UART2_SR_OR ((uint8_t)0x08)
#define | UART2_SR_PE ((uint8_t)0x01)
#define | UART2_SR_RXNE ((uint8_t)0x20)
#define | UART2_SR_TC ((uint8_t)0x40)
#define | UART2_SR_TXE ((uint8_t)0x80)

Define Documentation

#define UART2_BRR1_DIVM ((uint8_t)0xFF)

LSB mantissa of UART2DIV [7:0] mask

Definition at line 1899 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_BRR2_DIVF ((uint8_t)0x0F)

Fraction bits of UART2DIV [3:0] mask

Definition at line 1902 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_BRR2_DIVM ((uint8_t)0xF0)

MSB mantissa of UART2DIV [11:8] mask

Definition at line 1901 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR1_M ((uint8_t)0x10)

Word length mask

Definition at line 1907 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR1_PCEN ((uint8_t)0x04)

Parity Control Enable mask

Definition at line 1909 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR1_PIEN ((uint8_t)0x01)

UART2 Parity Interrupt Enable mask

Definition at line 1911 of file stm8s.h.

#define UART2_CR1_PS ((uint8_t)0x02)

UART2 Parity Selection

Definition at line 1910 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR1_R8 ((uint8_t)0x80)

Receive Data bit 8

Definition at line 1904 of file stm8s.h.

Referenced by UART2_ReceiveData9().

#define UART2_CR1_T8 ((uint8_t)0x40)

Transmit data bit 8

Definition at line 1905 of file stm8s.h.

Referenced by UART2_SendData9().

#define UART2_CR1_UARTD ((uint8_t)0x20)

UART2 Disable (for low power consumption)

Definition at line 1906 of file stm8s.h.

Referenced by UART2_Cmd().

#define UART2_CR1_WAKE ((uint8_t)0x08)

Wake-up method mask

Definition at line 1908 of file stm8s.h.

Referenced by UART2_WakeUpConfig().

#define UART2_CR2_ILIEN ((uint8_t)0x10)

IDLE Line Interrupt Enable mask

Definition at line 1916 of file stm8s.h.

#define UART2_CR2_REN ((uint8_t)0x04)

Receiver Enable mask

Definition at line 1918 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR2_RIEN ((uint8_t)0x20)

Receiver Interrupt Enable mask

Definition at line 1915 of file stm8s.h.

#define UART2_CR2_RWU ((uint8_t)0x02)

Receiver Wake-Up mask

Definition at line 1919 of file stm8s.h.

Referenced by UART2_ReceiverWakeUpCmd().

#define UART2_CR2_SBK ((uint8_t)0x01)

Send Break mask

Definition at line 1920 of file stm8s.h.

Referenced by UART2_SendBreak().

#define UART2_CR2_TCIEN ((uint8_t)0x40)

Transmission Complete Interrupt Enable mask

Definition at line 1914 of file stm8s.h.

#define UART2_CR2_TEN ((uint8_t)0x08)

Transmitter Enable mask

Definition at line 1917 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR2_TIEN ((uint8_t)0x80)

Transmitter Interrupt Enable mask

Definition at line 1913 of file stm8s.h.

#define UART2_CR3_CKEN ((uint8_t)0x08)

Clock Enable mask

Definition at line 1924 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR3_CPHA ((uint8_t)0x02)

Clock Phase mask

Definition at line 1926 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR3_CPOL ((uint8_t)0x04)

Clock Polarity mask

Definition at line 1925 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR3_LBCL ((uint8_t)0x01)

Last Bit Clock pulse mask

Definition at line 1927 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR3_LINEN ((uint8_t)0x40)

Alternate Function output mask

Definition at line 1922 of file stm8s.h.

Referenced by UART2_LINCmd().

#define UART2_CR3_STOP ((uint8_t)0x30)

STOP bits [1:0] mask

Definition at line 1923 of file stm8s.h.

Referenced by UART2_Init().

#define UART2_CR4_ADD ((uint8_t)0x0F)

Address of the UART2 node mask

Definition at line 1932 of file stm8s.h.

Referenced by UART2_SetAddress().

#define UART2_CR4_LBDF ((uint8_t)0x10)

LIN Break Detection Flag mask

Definition at line 1931 of file stm8s.h.

Referenced by UART2_ClearFlag(), and UART2_ClearITPendingBit().

#define UART2_CR4_LBDIEN ((uint8_t)0x40)

LIN Break Detection Interrupt Enable mask

Definition at line 1929 of file stm8s.h.

#define UART2_CR4_LBDL ((uint8_t)0x20)

LIN Break Detection Length mask

Definition at line 1930 of file stm8s.h.

Referenced by UART2_LINBreakDetectionConfig().

#define UART2_CR5_HDSEL ((uint8_t)0x08)

Half-Duplex Selection mask

Definition at line 1936 of file stm8s.h.

#define UART2_CR5_IREN ((uint8_t)0x02)

Irda Enable mask

Definition at line 1938 of file stm8s.h.

Referenced by UART2_IrDACmd().

#define UART2_CR5_IRLP ((uint8_t)0x04)

Irda Low Power Selection mask

Definition at line 1937 of file stm8s.h.

Referenced by UART2_IrDAConfig().

#define UART2_CR5_NACK ((uint8_t)0x10)

Smart Card Nack Enable mask

Definition at line 1935 of file stm8s.h.

Referenced by UART2_SmartCardNACKCmd().

#define UART2_CR5_SCEN ((uint8_t)0x20)

Smart Card Enable mask

Definition at line 1934 of file stm8s.h.

Referenced by UART2_SmartCardCmd().

#define UART2_CR6_LASE ((uint8_t)0x10)

LIN Auto synchronization Enable

Definition at line 1942 of file stm8s.h.

Referenced by UART2_LINConfig().

#define UART2_CR6_LDUM ((uint8_t)0x80)

LIN Divider Update Method

Definition at line 1940 of file stm8s.h.

Referenced by UART2_LINConfig().

#define UART2_CR6_LHDF ((uint8_t)0x02)

LIN Header Detection Flag

Definition at line 1944 of file stm8s.h.

Referenced by UART2_ClearFlag(), and UART2_ClearITPendingBit().

#define UART2_CR6_LHDIEN ((uint8_t)0x04)

LIN Header Detection Interrupt Enable

Definition at line 1943 of file stm8s.h.

#define UART2_CR6_LSF ((uint8_t)0x01)

LIN Synch Field

Definition at line 1945 of file stm8s.h.

Referenced by UART2_ClearFlag().

#define UART2_CR6_LSLV ((uint8_t)0x20)

LIN Slave Enable

Definition at line 1941 of file stm8s.h.

Referenced by UART2_LINConfig().

#define UART2_SR_FE ((uint8_t)0x02)

Framing Error mask

Definition at line 1896 of file stm8s.h.

#define UART2_SR_IDLE ((uint8_t)0x10)

IDLE line detected mask

Definition at line 1893 of file stm8s.h.

#define UART2_SR_NF ((uint8_t)0x04)

Noise Flag mask

Definition at line 1895 of file stm8s.h.

#define UART2_SR_OR ((uint8_t)0x08)

OverRun error mask

Definition at line 1894 of file stm8s.h.

#define UART2_SR_PE ((uint8_t)0x01)

Parity Error mask

Definition at line 1897 of file stm8s.h.

#define UART2_SR_RXNE ((uint8_t)0x20)

Read Data Register Not Empty mask

Definition at line 1892 of file stm8s.h.

Referenced by UART2_ClearFlag(), and UART2_ClearITPendingBit().

#define UART2_SR_TC ((uint8_t)0x40)

Transmission Complete mask

Definition at line 1891 of file stm8s.h.

#define UART2_SR_TXE ((uint8_t)0x80)

Transmit Data Register Empty mask

Definition at line 1890 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART3_Registers_Reset_Value

Defines

UART3_Registers_Reset_Value

Defines

#define | UART3_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART3_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR6_RESET_VALUE ((uint8_t)0x00)
#define | UART3_SR_RESET_VALUE ((uint8_t)0xC0)

Define Documentation

#define UART3_BRR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1977 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_BRR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1978 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_CR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 1979 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_CR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 1980 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_CR3_RESET_VALUE ((uint8_t)0x00)

Definition at line 1981 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_CR4_RESET_VALUE ((uint8_t)0x00)

Definition at line 1982 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_CR6_RESET_VALUE ((uint8_t)0x00)

Definition at line 1983 of file stm8s.h.

Referenced by UART3_DeInit().

#define UART3_SR_RESET_VALUE ((uint8_t)0xC0)

Definition at line 1976 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: UART3_Registers_Bits_Definition

Defines

UART3_Registers_Bits_Definition

Defines

#define | UART3_BRR1_DIVM ((uint8_t)0xFF)
#define | UART3_BRR2_DIVF ((uint8_t)0x0F)
#define | UART3_BRR2_DIVM ((uint8_t)0xF0)
#define | UART3_CR1_M ((uint8_t)0x10)
#define | UART3_CR1_PCEN ((uint8_t)0x04)
#define | UART3_CR1_PIEN ((uint8_t)0x01)
#define | UART3_CR1_PS ((uint8_t)0x02)
#define | UART3_CR1_R8 ((uint8_t)0x80)
#define | UART3_CR1_T8 ((uint8_t)0x40)
#define | UART3_CR1_UARTD ((uint8_t)0x20)
#define | UART3_CR1_WAKE ((uint8_t)0x08)
#define | UART3_CR2_ILIEN ((uint8_t)0x10)
#define | UART3_CR2_REN ((uint8_t)0x04)
#define | UART3_CR2_RIEN ((uint8_t)0x20)
#define | UART3_CR2_RWU ((uint8_t)0x02)
#define | UART3_CR2_SBK ((uint8_t)0x01)
#define | UART3_CR2_TCIEN ((uint8_t)0x40)
#define | UART3_CR2_TEN ((uint8_t)0x08)
#define | UART3_CR2_TIEN ((uint8_t)0x80)
#define | UART3_CR3_LINEN ((uint8_t)0x40)
#define | UART3_CR3_STOP ((uint8_t)0x30)
#define | UART3_CR4_ADD ((uint8_t)0x0F)
#define | UART3_CR4_LBDF ((uint8_t)0x10)
#define | UART3_CR4_LBDIEN ((uint8_t)0x40)
#define | UART3_CR4_LBDL ((uint8_t)0x20)
#define | UART3_CR6_LASE ((uint8_t)0x10)
#define | UART3_CR6_LDUM ((uint8_t)0x80)
#define | UART3_CR6_LHDF ((uint8_t)0x02)
#define | UART3_CR6_LHDIEN ((uint8_t)0x04)
#define | UART3_CR6_LSF ((uint8_t)0x01)
#define | UART3_CR6_LSLV ((uint8_t)0x20)
#define | UART3_SR_FE ((uint8_t)0x02)
#define | UART3_SR_IDLE ((uint8_t)0x10)
#define | UART3_SR_NF ((uint8_t)0x04)
#define | UART3_SR_OR ((uint8_t)0x08)
#define | UART3_SR_PE ((uint8_t)0x01)
#define | UART3_SR_RXNE ((uint8_t)0x20)
#define | UART3_SR_TC ((uint8_t)0x40)
#define | UART3_SR_TXE ((uint8_t)0x80)

Define Documentation

#define UART3_BRR1_DIVM ((uint8_t)0xFF)

LSB mantissa of UARTDIV [7:0] mask

Definition at line 2002 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_BRR2_DIVF ((uint8_t)0x0F)

Fraction bits of UARTDIV [3:0] mask

Definition at line 2005 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_BRR2_DIVM ((uint8_t)0xF0)

MSB mantissa of UARTDIV [11:8] mask

Definition at line 2004 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR1_M ((uint8_t)0x10)

Word length mask

Definition at line 2010 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR1_PCEN ((uint8_t)0x04)

Parity control enable mask

Definition at line 2012 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR1_PIEN ((uint8_t)0x01)

Parity interrupt enable bit mask

Definition at line 2014 of file stm8s.h.

#define UART3_CR1_PS ((uint8_t)0x02)

Parity selection bit mask

Definition at line 2013 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR1_R8 ((uint8_t)0x80)

Receive Data bit 8

Definition at line 2007 of file stm8s.h.

Referenced by UART3_ReceiveData9().

#define UART3_CR1_T8 ((uint8_t)0x40)

Transmit data bit 8

Definition at line 2008 of file stm8s.h.

Referenced by UART3_SendData9().

#define UART3_CR1_UARTD ((uint8_t)0x20)

UART Disable (for low power consumption)

Definition at line 2009 of file stm8s.h.

Referenced by UART3_Cmd().

#define UART3_CR1_WAKE ((uint8_t)0x08)

Wake-up method mask

Definition at line 2011 of file stm8s.h.

Referenced by UART3_WakeUpConfig().

#define UART3_CR2_ILIEN ((uint8_t)0x10)

IDLE Line Interrupt Enable mask

Definition at line 2019 of file stm8s.h.

#define UART3_CR2_REN ((uint8_t)0x04)

Receiver Enable mask

Definition at line 2021 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR2_RIEN ((uint8_t)0x20)

Receiver Interrupt Enable mask

Definition at line 2018 of file stm8s.h.

#define UART3_CR2_RWU ((uint8_t)0x02)

Receiver Wake-Up mask

Definition at line 2022 of file stm8s.h.

Referenced by UART3_ReceiverWakeUpCmd().

#define UART3_CR2_SBK ((uint8_t)0x01)

Send Break mask

Definition at line 2023 of file stm8s.h.

Referenced by UART3_SendBreak().

#define UART3_CR2_TCIEN ((uint8_t)0x40)

Transmission Complete Interrupt Enable mask

Definition at line 2017 of file stm8s.h.

#define UART3_CR2_TEN ((uint8_t)0x08)

Transmitter Enable mask

Definition at line 2020 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR2_TIEN ((uint8_t)0x80)

Transmitter Interrupt Enable mask

Definition at line 2016 of file stm8s.h.

#define UART3_CR3_LINEN ((uint8_t)0x40)

Alternate Function output mask

Definition at line 2025 of file stm8s.h.

Referenced by UART3_LINCmd().

#define UART3_CR3_STOP ((uint8_t)0x30)

STOP bits [1:0] mask

Definition at line 2026 of file stm8s.h.

Referenced by UART3_Init().

#define UART3_CR4_ADD ((uint8_t)0x0F)

Address of the UART3 node mask

Definition at line 2031 of file stm8s.h.

Referenced by UART3_SetAddress().

#define UART3_CR4_LBDF ((uint8_t)0x10)

LIN Break Detection Flag mask

Definition at line 2030 of file stm8s.h.

Referenced by UART3_ClearFlag(), and UART3_ClearITPendingBit().

#define UART3_CR4_LBDIEN ((uint8_t)0x40)

LIN Break Detection Interrupt Enable mask

Definition at line 2028 of file stm8s.h.

#define UART3_CR4_LBDL ((uint8_t)0x20)

LIN Break Detection Length mask

Definition at line 2029 of file stm8s.h.

Referenced by UART3_LINBreakDetectionConfig().

#define UART3_CR6_LASE ((uint8_t)0x10)

LIN Auto synchronization Enable

Definition at line 2035 of file stm8s.h.

Referenced by UART3_LINConfig().

#define UART3_CR6_LDUM ((uint8_t)0x80)

LIN Divider Update Method

Definition at line 2033 of file stm8s.h.

Referenced by UART3_LINConfig().

#define UART3_CR6_LHDF ((uint8_t)0x02)

LIN Header Detection Flag

Definition at line 2037 of file stm8s.h.

Referenced by UART3_ClearFlag(), and UART3_ClearITPendingBit().

#define UART3_CR6_LHDIEN ((uint8_t)0x04)

LIN Header Detection Interrupt Enable

Definition at line 2036 of file stm8s.h.

#define UART3_CR6_LSF ((uint8_t)0x01)

LIN Synch Field

Definition at line 2038 of file stm8s.h.

Referenced by UART3_ClearFlag().

#define UART3_CR6_LSLV ((uint8_t)0x20)

LIN Slave Enable

Definition at line 2034 of file stm8s.h.

Referenced by UART3_LINConfig().

#define UART3_SR_FE ((uint8_t)0x02)

Framing Error mask

Definition at line 1999 of file stm8s.h.

#define UART3_SR_IDLE ((uint8_t)0x10)

IDLE line detected mask

Definition at line 1996 of file stm8s.h.

#define UART3_SR_NF ((uint8_t)0x04)

Noise Flag mask

Definition at line 1998 of file stm8s.h.

#define UART3_SR_OR ((uint8_t)0x08)

OverRun error mask

Definition at line 1997 of file stm8s.h.

#define UART3_SR_PE ((uint8_t)0x01)

Parity Error mask

Definition at line 2000 of file stm8s.h.

#define UART3_SR_RXNE ((uint8_t)0x20)

Read Data Register Not Empty mask

Definition at line 1995 of file stm8s.h.

Referenced by UART3_ClearFlag(), and UART3_ClearITPendingBit().

#define UART3_SR_TC ((uint8_t)0x40)

Transmission Complete mask

Definition at line 1994 of file stm8s.h.

#define UART3_SR_TXE ((uint8_t)0x80)

Transmit Data Register Empty mask

Definition at line 1993 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: CAN_Registers_Bits_Definition

Defines

CAN_Registers_Bits_Definition

Defines

#define | CAN_DGR_LBKM ((uint8_t)0x01)
#define | CAN_DGR_RX ((uint8_t)0x08)
#define | CAN_DGR_SAMP ((uint8_t)0x04)
#define | CAN_DGR_SLIM ((uint8_t)0x02)
#define | CAN_DGR_TXM2E ((uint8_t)0x10)
#define | CAN_EIER_BOFIE ((uint8_t)0x04)
#define | CAN_EIER_EPVIE ((uint8_t)0x02)
#define | CAN_EIER_ERRIE ((uint8_t)0x80)
#define | CAN_EIER_EWGIE ((uint8_t)0x01)
#define | CAN_EIER_LECIE ((uint8_t)0x10)
#define | CAN_ESR_BOFF ((uint8_t)0x04)
#define | CAN_ESR_EPVF ((uint8_t)0x02)
#define | CAN_ESR_EWGF ((uint8_t)0x01)
#define | CAN_ESR_LEC ((uint8_t)0x70)
#define | CAN_ESR_LEC0 ((uint8_t)0x10)
#define | CAN_ESR_LEC1 ((uint8_t)0x20)
#define | CAN_ESR_LEC2 ((uint8_t)0x40)
#define | CAN_FCR1_FACT0 ((uint8_t)0x01)
#define | CAN_FCR1_FACT1 ((uint8_t)0x10)
#define | CAN_FCR1_FSC00 ((uint8_t)0x02)
#define | CAN_FCR1_FSC01 ((uint8_t)0x04)
#define | CAN_FCR1_FSC10 ((uint8_t)0x20)
#define | CAN_FCR1_FSC11 ((uint8_t)0x40)
#define | CAN_FCR2_FACT2 ((uint8_t)0x01)
#define | CAN_FCR2_FACT3 ((uint8_t)0x10)
#define | CAN_FCR2_FSC20 ((uint8_t)0x02)
#define | CAN_FCR2_FSC21 ((uint8_t)0x04)
#define | CAN_FCR2_FSC30 ((uint8_t)0x20)
#define | CAN_FCR2_FSC31 ((uint8_t)0x40)
#define | CAN_FCR3_FACT4 ((uint8_t)0x01)
#define | CAN_FCR3_FACT5 ((uint8_t)0x10)
#define | CAN_FCR3_FSC40 ((uint8_t)0x02)
#define | CAN_FCR3_FSC41 ((uint8_t)0x04)
#define | CAN_FCR3_FSC50 ((uint8_t)0x20)
#define | CAN_FCR3_FSC51 ((uint8_t)0x40)
#define | CAN_FMR1_FMH0 ((uint8_t)0x02)
#define | CAN_FMR1_FMH1 ((uint8_t)0x08)
#define | CAN_FMR1_FMH2 ((uint8_t)0x20)
#define | CAN_FMR1_FMH3 ((uint8_t)0x80)
#define | CAN_FMR1_FML0 ((uint8_t)0x01)
#define | CAN_FMR1_FML1 ((uint8_t)0x04)
#define | CAN_FMR1_FML2 ((uint8_t)0x10)
#define | CAN_FMR1_FML3 ((uint8_t)0x40)
#define | CAN_FMR2_FMH4 ((uint8_t)0x02)
#define | CAN_FMR2_FMH5 ((uint8_t)0x08)
#define | CAN_FMR2_FML4 ((uint8_t)0x01)
#define | CAN_FMR2_FML5 ((uint8_t)0x04)
#define | CAN_IER_FFIE ((uint8_t)0x04)
#define | CAN_IER_FMPIE ((uint8_t)0x02)
#define | CAN_IER_FOVIE ((uint8_t)0x08)
#define | CAN_IER_TMEIE ((uint8_t)0x01)
#define | CAN_IER_WKUIE ((uint8_t)0x80)
#define | CAN_MCR_ABOM ((uint8_t)0x40)
#define | CAN_MCR_AWUM ((uint8_t)0x20)
#define | CAN_MCR_INRQ ((uint8_t)0x01)
#define | CAN_MCR_NART ((uint8_t)0x10)
#define | CAN_MCR_RFLM ((uint8_t)0x08)
#define | CAN_MCR_SLEEP ((uint8_t)0x02)
#define | CAN_MCR_TTCM ((uint8_t)0x80)
#define | CAN_MCR_TXFP ((uint8_t)0x04)
#define | CAN_MCSR_ABRQ ((uint8_t)0x02)
#define | CAN_MCSR_ALST ((uint8_t)0x10)
#define | CAN_MCSR_RQCP ((uint8_t)0x04)
#define | CAN_MCSR_TERR ((uint8_t)0x20)
#define | CAN_MCSR_TXOK ((uint8_t)0x08)
#define | CAN_MCSR_TXRQ ((uint8_t)0x01)
#define | CAN_MDLCR_DLC ((uint8_t)0x0F)
#define | CAN_MDLCR_TGT ((uint8_t)0x80)
#define | CAN_MIDR1_IDE ((uint8_t)0x40)
#define | CAN_MIDR1_RTR ((uint8_t)0x20)
#define | CAN_MSR_ERRI ((uint8_t)0x04)
#define | CAN_MSR_INAK ((uint8_t)0x01)
#define | CAN_MSR_RX ((uint8_t)0x20)
#define | CAN_MSR_SLAK ((uint8_t)0x02)
#define | CAN_MSR_TX ((uint8_t)0x10)
#define | CAN_MSR_WKUI ((uint8_t)0x08)
#define | CAN_PSR_PS0 ((uint8_t)0x01)
#define | CAN_PSR_PS1 ((uint8_t)0x02)
#define | CAN_PSR_PS2 ((uint8_t)0x04)
#define | CAN_RECR_REC0 ((uint8_t)0x01)
#define | CAN_RECR_REC1 ((uint8_t)0x02)
#define | CAN_RECR_REC2 ((uint8_t)0x04)
#define | CAN_RECR_REC3 ((uint8_t)0x08)
#define | CAN_RECR_REC4 ((uint8_t)0x10)
#define | CAN_RECR_REC5 ((uint8_t)0x20)
#define | CAN_RECR_REC6 ((uint8_t)0x40)
#define | CAN_RECR_REC7 ((uint8_t)0x80)
#define | CAN_RFR_FMP01 ((uint8_t)0x03)
#define | CAN_RFR_FOVR ((uint8_t)0x10)
#define | CAN_RFR_FULL ((uint8_t)0x08)
#define | CAN_RFR_RFOM ((uint8_t)0x20)
#define | CAN_TECR_TEC0 ((uint8_t)0x01)
#define | CAN_TECR_TEC1 ((uint8_t)0x02)
#define | CAN_TECR_TEC2 ((uint8_t)0x04)
#define | CAN_TECR_TEC3 ((uint8_t)0x08)
#define | CAN_TECR_TEC4 ((uint8_t)0x10)
#define | CAN_TECR_TEC5 ((uint8_t)0x20)
#define | CAN_TECR_TEC6 ((uint8_t)0x40)
#define | CAN_TECR_TEC7 ((uint8_t)0x80)
#define | CAN_TPR_CODE0 ((uint8_t)0x01)
#define | CAN_TPR_LOW0 ((uint8_t)0x20)
#define | CAN_TPR_LOW1 ((uint8_t)0x40)
#define | CAN_TPR_LOW2 ((uint8_t)0x80)
#define | CAN_TPR_TME0 ((uint8_t)0x04)
#define | CAN_TPR_TME1 ((uint8_t)0x08)
#define | CAN_TPR_TME2 ((uint8_t)0x10)
#define | CAN_TSR_RQCP0 ((uint8_t)0x01)
#define | CAN_TSR_RQCP012 ((uint8_t)0x07)
#define | CAN_TSR_RQCP1 ((uint8_t)0x02)
#define | CAN_TSR_RQCP2 ((uint8_t)0x04)
#define | CAN_TSR_TXOK0 ((uint8_t)0x10)
#define | CAN_TSR_TXOK1 ((uint8_t)0x20)
#define | CAN_TSR_TXOK2 ((uint8_t)0x40)

Define Documentation

#define CAN_DGR_LBKM ((uint8_t)0x01)

Definition at line 2266 of file stm8s.h.

#define CAN_DGR_RX ((uint8_t)0x08)

Definition at line 2269 of file stm8s.h.

#define CAN_DGR_SAMP ((uint8_t)0x04)

Definition at line 2268 of file stm8s.h.

#define CAN_DGR_SLIM ((uint8_t)0x02)

Definition at line 2267 of file stm8s.h.

#define CAN_DGR_TXM2E ((uint8_t)0x10)

Definition at line 2270 of file stm8s.h.

Referenced by CAN_ST7CompatibilityCmd().

#define CAN_EIER_BOFIE ((uint8_t)0x04)

Definition at line 2307 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_EIER_EPVIE ((uint8_t)0x02)

Definition at line 2306 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_EIER_ERRIE ((uint8_t)0x80)

Definition at line 2309 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_EIER_EWGIE ((uint8_t)0x01)

Definition at line 2305 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_EIER_LECIE ((uint8_t)0x10)

Definition at line 2308 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_BOFF ((uint8_t)0x04)

Definition at line 2298 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_EPVF ((uint8_t)0x02)

Definition at line 2297 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_EWGF ((uint8_t)0x01)

Definition at line 2296 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_LEC ((uint8_t)0x70)

Definition at line 2302 of file stm8s.h.

Referenced by CAN_GetITStatus(), and CAN_GetLastErrorCode().

#define CAN_ESR_LEC0 ((uint8_t)0x10)

Definition at line 2299 of file stm8s.h.

#define CAN_ESR_LEC1 ((uint8_t)0x20)

Definition at line 2300 of file stm8s.h.

#define CAN_ESR_LEC2 ((uint8_t)0x40)

Definition at line 2301 of file stm8s.h.

#define CAN_FCR1_FACT0 ((uint8_t)0x01)

Definition at line 2347 of file stm8s.h.

#define CAN_FCR1_FACT1 ((uint8_t)0x10)

Definition at line 2348 of file stm8s.h.

#define CAN_FCR1_FSC00 ((uint8_t)0x02)

Definition at line 2354 of file stm8s.h.

Referenced by CAN_FilterInit().

#define CAN_FCR1_FSC01 ((uint8_t)0x04)

Definition at line 2355 of file stm8s.h.

Referenced by CAN_FilterInit().

#define CAN_FCR1_FSC10 ((uint8_t)0x20)

Definition at line 2356 of file stm8s.h.

#define CAN_FCR1_FSC11 ((uint8_t)0x40)

Definition at line 2357 of file stm8s.h.

#define CAN_FCR2_FACT2 ((uint8_t)0x01)

Definition at line 2349 of file stm8s.h.

#define CAN_FCR2_FACT3 ((uint8_t)0x10)

Definition at line 2350 of file stm8s.h.

#define CAN_FCR2_FSC20 ((uint8_t)0x02)

Definition at line 2358 of file stm8s.h.

#define CAN_FCR2_FSC21 ((uint8_t)0x04)

Definition at line 2359 of file stm8s.h.

#define CAN_FCR2_FSC30 ((uint8_t)0x20)

Definition at line 2360 of file stm8s.h.

#define CAN_FCR2_FSC31 ((uint8_t)0x40)

Definition at line 2361 of file stm8s.h.

#define CAN_FCR3_FACT4 ((uint8_t)0x01)

Definition at line 2351 of file stm8s.h.

#define CAN_FCR3_FACT5 ((uint8_t)0x10)

Definition at line 2352 of file stm8s.h.

#define CAN_FCR3_FSC40 ((uint8_t)0x02)

Definition at line 2362 of file stm8s.h.

#define CAN_FCR3_FSC41 ((uint8_t)0x04)

Definition at line 2363 of file stm8s.h.

#define CAN_FCR3_FSC50 ((uint8_t)0x20)

Definition at line 2364 of file stm8s.h.

#define CAN_FCR3_FSC51 ((uint8_t)0x40)

Definition at line 2365 of file stm8s.h.

#define CAN_FMR1_FMH0 ((uint8_t)0x02)

Definition at line 2333 of file stm8s.h.

#define CAN_FMR1_FMH1 ((uint8_t)0x08)

Definition at line 2335 of file stm8s.h.

#define CAN_FMR1_FMH2 ((uint8_t)0x20)

Definition at line 2337 of file stm8s.h.

#define CAN_FMR1_FMH3 ((uint8_t)0x80)

Definition at line 2339 of file stm8s.h.

#define CAN_FMR1_FML0 ((uint8_t)0x01)

Definition at line 2332 of file stm8s.h.

#define CAN_FMR1_FML1 ((uint8_t)0x04)

Definition at line 2334 of file stm8s.h.

#define CAN_FMR1_FML2 ((uint8_t)0x10)

Definition at line 2336 of file stm8s.h.

#define CAN_FMR1_FML3 ((uint8_t)0x40)

Definition at line 2338 of file stm8s.h.

#define CAN_FMR2_FMH4 ((uint8_t)0x02)

Definition at line 2342 of file stm8s.h.

#define CAN_FMR2_FMH5 ((uint8_t)0x08)

Definition at line 2344 of file stm8s.h.

#define CAN_FMR2_FML4 ((uint8_t)0x01)

Definition at line 2341 of file stm8s.h.

#define CAN_FMR2_FML5 ((uint8_t)0x04)

Definition at line 2343 of file stm8s.h.

#define CAN_IER_FFIE ((uint8_t)0x04)

Definition at line 2260 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_IER_FMPIE ((uint8_t)0x02)

Definition at line 2259 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_IER_FOVIE ((uint8_t)0x08)

Definition at line 2261 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_IER_TMEIE ((uint8_t)0x01)

Definition at line 2258 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_IER_WKUIE ((uint8_t)0x80)

Definition at line 2262 of file stm8s.h.

Referenced by CAN_GetITStatus().

#define CAN_MCR_ABOM ((uint8_t)0x40)

Definition at line 2224 of file stm8s.h.

#define CAN_MCR_AWUM ((uint8_t)0x20)

Definition at line 2223 of file stm8s.h.

#define CAN_MCR_INRQ ((uint8_t)0x01)

Definition at line 2218 of file stm8s.h.

Referenced by CAN_DeInit(), CAN_Init(), CAN_OperatingModeRequest(), and CAN_Sleep().

#define CAN_MCR_NART ((uint8_t)0x10)

Definition at line 2222 of file stm8s.h.

#define CAN_MCR_RFLM ((uint8_t)0x08)

Definition at line 2221 of file stm8s.h.

#define CAN_MCR_SLEEP ((uint8_t)0x02)

Definition at line 2219 of file stm8s.h.

Referenced by CAN_OperatingModeRequest(), CAN_Sleep(), and CAN_WakeUp().

#define CAN_MCR_TTCM ((uint8_t)0x80)

Definition at line 2225 of file stm8s.h.

Referenced by CAN_TTComModeCmd().

#define CAN_MCR_TXFP ((uint8_t)0x04)

Definition at line 2220 of file stm8s.h.

#define CAN_MCSR_ABRQ ((uint8_t)0x02)

Definition at line 2280 of file stm8s.h.

Referenced by CAN_CancelTransmit().

#define CAN_MCSR_ALST ((uint8_t)0x10)

Definition at line 2283 of file stm8s.h.

#define CAN_MCSR_RQCP ((uint8_t)0x04)

Definition at line 2281 of file stm8s.h.

#define CAN_MCSR_TERR ((uint8_t)0x20)

Definition at line 2284 of file stm8s.h.

#define CAN_MCSR_TXOK ((uint8_t)0x08)

Definition at line 2282 of file stm8s.h.

#define CAN_MCSR_TXRQ ((uint8_t)0x01)

Definition at line 2279 of file stm8s.h.

Referenced by CAN_Transmit().

#define CAN_MDLCR_DLC ((uint8_t)0x0F)

Definition at line 2286 of file stm8s.h.

#define CAN_MDLCR_TGT ((uint8_t)0x80)

Definition at line 2287 of file stm8s.h.

Referenced by CAN_TTComModeCmd().

#define CAN_MIDR1_IDE ((uint8_t)0x40)

Definition at line 2290 of file stm8s.h.

#define CAN_MIDR1_RTR ((uint8_t)0x20)

Definition at line 2289 of file stm8s.h.

#define CAN_MSR_ERRI ((uint8_t)0x04)

Definition at line 2230 of file stm8s.h.

Referenced by CAN_ClearITPendingBit().

#define CAN_MSR_INAK ((uint8_t)0x01)

Definition at line 2228 of file stm8s.h.

Referenced by CAN_Init(), CAN_OperatingModeRequest(), and CAN_Sleep().

#define CAN_MSR_RX ((uint8_t)0x20)

Definition at line 2233 of file stm8s.h.

#define CAN_MSR_SLAK ((uint8_t)0x02)

Definition at line 2229 of file stm8s.h.

Referenced by CAN_OperatingModeRequest(), CAN_Sleep(), and CAN_WakeUp().

#define CAN_MSR_TX ((uint8_t)0x10)

Definition at line 2232 of file stm8s.h.

#define CAN_MSR_WKUI ((uint8_t)0x08)

Definition at line 2231 of file stm8s.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_PSR_PS0 ((uint8_t)0x01)

Definition at line 2274 of file stm8s.h.

#define CAN_PSR_PS1 ((uint8_t)0x02)

Definition at line 2275 of file stm8s.h.

#define CAN_PSR_PS2 ((uint8_t)0x04)

Definition at line 2276 of file stm8s.h.

#define CAN_RECR_REC0 ((uint8_t)0x01)

Definition at line 2322 of file stm8s.h.

#define CAN_RECR_REC1 ((uint8_t)0x02)

Definition at line 2323 of file stm8s.h.

#define CAN_RECR_REC2 ((uint8_t)0x04)

Definition at line 2324 of file stm8s.h.

#define CAN_RECR_REC3 ((uint8_t)0x08)

Definition at line 2325 of file stm8s.h.

#define CAN_RECR_REC4 ((uint8_t)0x10)

Definition at line 2326 of file stm8s.h.

#define CAN_RECR_REC5 ((uint8_t)0x20)

Definition at line 2327 of file stm8s.h.

#define CAN_RECR_REC6 ((uint8_t)0x40)

Definition at line 2328 of file stm8s.h.

#define CAN_RECR_REC7 ((uint8_t)0x80)

Definition at line 2329 of file stm8s.h.

#define CAN_RFR_FMP01 ((uint8_t)0x03)

Definition at line 2252 of file stm8s.h.

Referenced by CAN_GetITStatus(), and CAN_MessagePending().

#define CAN_RFR_FOVR ((uint8_t)0x10)

Definition at line 2254 of file stm8s.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_RFR_FULL ((uint8_t)0x08)

Definition at line 2253 of file stm8s.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_RFR_RFOM ((uint8_t)0x20)

Definition at line 2255 of file stm8s.h.

Referenced by CAN_FIFORelease().

#define CAN_TECR_TEC0 ((uint8_t)0x01)

Definition at line 2312 of file stm8s.h.

#define CAN_TECR_TEC1 ((uint8_t)0x02)

Definition at line 2313 of file stm8s.h.

#define CAN_TECR_TEC2 ((uint8_t)0x04)

Definition at line 2314 of file stm8s.h.

#define CAN_TECR_TEC3 ((uint8_t)0x08)

Definition at line 2315 of file stm8s.h.

#define CAN_TECR_TEC4 ((uint8_t)0x10)

Definition at line 2316 of file stm8s.h.

#define CAN_TECR_TEC5 ((uint8_t)0x20)

Definition at line 2317 of file stm8s.h.

#define CAN_TECR_TEC6 ((uint8_t)0x40)

Definition at line 2318 of file stm8s.h.

#define CAN_TECR_TEC7 ((uint8_t)0x80)

Definition at line 2319 of file stm8s.h.

#define CAN_TPR_CODE0 ((uint8_t)0x01)

Definition at line 2244 of file stm8s.h.

#define CAN_TPR_LOW0 ((uint8_t)0x20)

Definition at line 2248 of file stm8s.h.

#define CAN_TPR_LOW1 ((uint8_t)0x40)

Definition at line 2249 of file stm8s.h.

#define CAN_TPR_LOW2 ((uint8_t)0x80)

Definition at line 2250 of file stm8s.h.

#define CAN_TPR_TME0 ((uint8_t)0x04)

Definition at line 2245 of file stm8s.h.

Referenced by CAN_Transmit(), and CAN_TransmitStatus().

#define CAN_TPR_TME1 ((uint8_t)0x08)

Definition at line 2246 of file stm8s.h.

Referenced by CAN_Transmit(), and CAN_TransmitStatus().

#define CAN_TPR_TME2 ((uint8_t)0x10)

Definition at line 2247 of file stm8s.h.

Referenced by CAN_Transmit(), and CAN_TransmitStatus().

#define CAN_TSR_RQCP0 ((uint8_t)0x01)

Definition at line 2236 of file stm8s.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_RQCP012 ((uint8_t)0x07)

Definition at line 2239 of file stm8s.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_TSR_RQCP1 ((uint8_t)0x02)

Definition at line 2237 of file stm8s.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_RQCP2 ((uint8_t)0x04)

Definition at line 2238 of file stm8s.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_TXOK0 ((uint8_t)0x10)

Definition at line 2240 of file stm8s.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_TXOK1 ((uint8_t)0x20)

Definition at line 2241 of file stm8s.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_TXOK2 ((uint8_t)0x40)

Definition at line 2242 of file stm8s.h.

Referenced by CAN_TransmitStatus().


STM8S/A Standard Peripherals Drivers: CAN_Registers_Reset_Value

Defines

CAN_Registers_Reset_Value

Defines

#define | CAN_BTR1_RESET_VALUE ((uint8_t)0x40)
#define | CAN_BTR2_RESET_VALUE ((uint8_t)0x23)
#define | CAN_DGR_RESET_VALUE ((uint8_t)0x0C)
#define | CAN_EIER_RESET_VALUE ((uint8_t)0x00)
#define | CAN_ESR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FCR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FMR1_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FMR2_RESET_VALUE ((uint8_t)0x00)
#define | CAN_IER_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MCR_RESET_VALUE ((uint8_t)0x02)
#define | CAN_MCSR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MDLC_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MFMI_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MSR_RESET_VALUE ((uint8_t)0x02)
#define | CAN_PSR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_RECR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_RFR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_TECR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_TPR_RESET_VALUE ((uint8_t)0x0C)
#define | CAN_TSR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define CAN_BTR1_RESET_VALUE ((uint8_t)0x40)

Definition at line 2390 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_BTR2_RESET_VALUE ((uint8_t)0x23)

Definition at line 2391 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_DGR_RESET_VALUE ((uint8_t)0x0C)

Definition at line 2383 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_EIER_RESET_VALUE ((uint8_t)0x00)

Definition at line 2387 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_ESR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2386 of file stm8s.h.

Referenced by CAN_ClearITPendingBit(), and CAN_DeInit().

#define CAN_FCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2394 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_FMR1_RESET_VALUE ((uint8_t)0x00)

Definition at line 2392 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_FMR2_RESET_VALUE ((uint8_t)0x00)

Definition at line 2393 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_IER_RESET_VALUE ((uint8_t)0x00)

Definition at line 2382 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_MCR_RESET_VALUE ((uint8_t)0x02)

Definition at line 2377 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_MCSR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2398 of file stm8s.h.

#define CAN_MDLC_RESET_VALUE ((uint8_t)0x00)

Definition at line 2397 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_MFMI_RESET_VALUE ((uint8_t)0x00)

Definition at line 2396 of file stm8s.h.

#define CAN_MSR_RESET_VALUE ((uint8_t)0x02)

Definition at line 2378 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_PSR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2384 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_RECR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2389 of file stm8s.h.

#define CAN_RFR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2381 of file stm8s.h.

Referenced by CAN_DeInit().

#define CAN_TECR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2388 of file stm8s.h.

#define CAN_TPR_RESET_VALUE ((uint8_t)0x0C)

Definition at line 2380 of file stm8s.h.

#define CAN_TSR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2379 of file stm8s.h.

Referenced by CAN_DeInit().


STM8S/A Standard Peripherals Drivers: CFG_Registers_Reset_Value

Defines

CFG_Registers_Reset_Value

Defines

#define CFG_GCR_RESET_VALUE ((uint8_t)0x00)

Define Documentation

#define CFG_GCR_RESET_VALUE ((uint8_t)0x00)

Definition at line 2418 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: CFG_Registers_Bits_Definition

Defines

CFG_Registers_Bits_Definition

Defines

#define | CFG_GCR_AL ((uint8_t)0x02)
#define | CFG_GCR_SWD ((uint8_t)0x01)

Define Documentation

#define CFG_GCR_AL ((uint8_t)0x02)

Activation Level bit mask

Definition at line 2429 of file stm8s.h.

#define CFG_GCR_SWD ((uint8_t)0x01)

Swim disable bit mask

Definition at line 2428 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: MAP_FILE_Base_Addresses

Defines

MAP_FILE_Base_Addresses

Defines

#define | ADC1_BaseAddress 0x53E0
#define | ADC2_BaseAddress 0x5400
#define | AWU_BaseAddress 0x50F0
#define | BEEP_BaseAddress 0x50F3
#define | CAN_BaseAddress 0x5420
#define | CFG_BaseAddress 0x7F60
#define | CLK_BaseAddress 0x50C0
#define | DM_BaseAddress 0x7F90
#define | EXTI_BaseAddress 0x50A0
#define | FLASH_BaseAddress 0x505A
#define | GPIOA_BaseAddress 0x5000
#define | GPIOB_BaseAddress 0x5005
#define | GPIOC_BaseAddress 0x500A
#define | GPIOD_BaseAddress 0x500F
#define | GPIOE_BaseAddress 0x5014
#define | GPIOF_BaseAddress 0x5019
#define | GPIOG_BaseAddress 0x501E
#define | GPIOH_BaseAddress 0x5023
#define | GPIOI_BaseAddress 0x5028
#define | I2C_BaseAddress 0x5210
#define | ITC_BaseAddress 0x7F70
#define | IWDG_BaseAddress 0x50E0
#define | OPT_BaseAddress 0x4800
#define | RST_BaseAddress 0x50B3
#define | SPI_BaseAddress 0x5200
#define | TIM1_BaseAddress 0x5250
#define | TIM2_BaseAddress 0x5300
#define | TIM3_BaseAddress 0x5320
#define | TIM4_BaseAddress 0x5340
#define | TIM5_BaseAddress 0x5300
#define | TIM6_BaseAddress 0x5340
#define | UART1_BaseAddress 0x5230
#define | UART2_BaseAddress 0x5240
#define | UART3_BaseAddress 0x5240
#define | WWDG_BaseAddress 0x50D1

Define Documentation

#define ADC1_BaseAddress 0x53E0

Definition at line 2475 of file stm8s.h.

Referenced by ADC1_GetBufferValue().

#define ADC2_BaseAddress 0x5400

Definition at line 2476 of file stm8s.h.

#define AWU_BaseAddress 0x50F0

Definition at line 2462 of file stm8s.h.

#define BEEP_BaseAddress 0x50F3

Definition at line 2463 of file stm8s.h.

#define CAN_BaseAddress 0x5420

Definition at line 2477 of file stm8s.h.

#define CFG_BaseAddress 0x7F60

Definition at line 2478 of file stm8s.h.

#define CLK_BaseAddress 0x50C0

Definition at line 2459 of file stm8s.h.

#define DM_BaseAddress 0x7F90

Definition at line 2480 of file stm8s.h.

#define EXTI_BaseAddress 0x50A0

Definition at line 2457 of file stm8s.h.

#define FLASH_BaseAddress 0x505A

Definition at line 2456 of file stm8s.h.

#define GPIOA_BaseAddress 0x5000

Definition at line 2447 of file stm8s.h.

#define GPIOB_BaseAddress 0x5005

Definition at line 2448 of file stm8s.h.

#define GPIOC_BaseAddress 0x500A

Definition at line 2449 of file stm8s.h.

#define GPIOD_BaseAddress 0x500F

Definition at line 2450 of file stm8s.h.

#define GPIOE_BaseAddress 0x5014

Definition at line 2451 of file stm8s.h.

#define GPIOF_BaseAddress 0x5019

Definition at line 2452 of file stm8s.h.

#define GPIOG_BaseAddress 0x501E

Definition at line 2453 of file stm8s.h.

#define GPIOH_BaseAddress 0x5023

Definition at line 2454 of file stm8s.h.

#define GPIOI_BaseAddress 0x5028

Definition at line 2455 of file stm8s.h.

#define I2C_BaseAddress 0x5210

Definition at line 2465 of file stm8s.h.

#define ITC_BaseAddress 0x7F70

Definition at line 2479 of file stm8s.h.

#define IWDG_BaseAddress 0x50E0

Definition at line 2461 of file stm8s.h.

#define OPT_BaseAddress 0x4800

Definition at line 2446 of file stm8s.h.

#define RST_BaseAddress 0x50B3

Definition at line 2458 of file stm8s.h.

#define SPI_BaseAddress 0x5200

Definition at line 2464 of file stm8s.h.

#define TIM1_BaseAddress 0x5250

Definition at line 2469 of file stm8s.h.

#define TIM2_BaseAddress 0x5300

Definition at line 2470 of file stm8s.h.

#define TIM3_BaseAddress 0x5320

Definition at line 2471 of file stm8s.h.

#define TIM4_BaseAddress 0x5340

Definition at line 2472 of file stm8s.h.

#define TIM5_BaseAddress 0x5300

Definition at line 2473 of file stm8s.h.

#define TIM6_BaseAddress 0x5340

Definition at line 2474 of file stm8s.h.

#define UART1_BaseAddress 0x5230

Definition at line 2466 of file stm8s.h.

#define UART2_BaseAddress 0x5240

Definition at line 2467 of file stm8s.h.

#define UART3_BaseAddress 0x5240

Definition at line 2468 of file stm8s.h.

#define WWDG_BaseAddress 0x50D1

Definition at line 2460 of file stm8s.h.


STM8S/A Standard Peripherals Drivers: ADC1_Exported_Types

Enumerations

ADC1_Exported_Types

Enumerations

enum | ADC1_Align_TypeDef { ADC1_ALIGN_LEFT = (uint8_t)0x00, ADC1_ALIGN_RIGHT = (uint8_t)0x08 }

ADC1 data alignment.

More...
enum ADC1_Channel_TypeDef {
ADC1_CHANNEL_0 = (uint8_t)0x00, ADC1_CHANNEL_1 = (uint8_t)0x01, ADC1_CHANNEL_2 = (uint8_t)0x02, ADC1_CHANNEL_3 = (uint8_t)0x03,
ADC1_CHANNEL_4 = (uint8_t)0x04, ADC1_CHANNEL_5 = (uint8_t)0x05, ADC1_CHANNEL_6 = (uint8_t)0x06, ADC1_CHANNEL_7 = (uint8_t)0x07,
ADC1_CHANNEL_8 = (uint8_t)0x08, ADC1_CHANNEL_9 = (uint8_t)0x09, ADC1_CHANNEL_12 = (uint8_t)0x0C
}

ADC1 analog channel selection.

More...
enum | ADC1_ConvMode_TypeDef { ADC1_CONVERSIONMODE_SINGLE = (uint8_t)0x00, ADC1_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 }

ADC1 conversion mode selection.

More...
enum | ADC1_ExtTrig_TypeDef { ADC1_EXTTRIG_TIM = (uint8_t)0x00, ADC1_EXTTRIG_GPIO = (uint8_t)0x10 }

ADC1 External conversion trigger event selection.

More...
enum ADC1_Flag_TypeDef {
ADC1_FLAG_OVR = (uint8_t)0x41, ADC1_FLAG_AWD = (uint8_t)0x40, ADC1_FLAG_AWS0 = (uint8_t)0x10, ADC1_FLAG_AWS1 = (uint8_t)0x11,
ADC1_FLAG_AWS2 = (uint8_t)0x12, ADC1_FLAG_AWS3 = (uint8_t)0x13, ADC1_FLAG_AWS4 = (uint8_t)0x14, ADC1_FLAG_AWS5 = (uint8_t)0x15,
ADC1_FLAG_AWS6 = (uint8_t)0x16, ADC1_FLAG_AWS7 = (uint8_t)0x17, ADC1_FLAG_AWS8 = (uint8_t)0x18, ADC1_FLAG_AWS9 = (uint8_t)0x19,
ADC1_FLAG_AWS12 = (uint8_t)0x1C, ADC1_FLAG_EOC = (uint8_t)0x80
}

ADC1 Flags.

More...
enum ADC1_IT_TypeDef {
ADC1_IT_AWDIE = (uint16_t)0x010, ADC1_IT_EOCIE = (uint16_t)0x020, ADC1_IT_AWD = (uint16_t)0x140, ADC1_IT_AWS0 = (uint16_t)0x110,
ADC1_IT_AWS1 = (uint16_t)0x111, ADC1_IT_AWS2 = (uint16_t)0x112, ADC1_IT_AWS3 = (uint16_t)0x113, ADC1_IT_AWS4 = (uint16_t)0x114,
ADC1_IT_AWS5 = (uint16_t)0x115, ADC1_IT_AWS6 = (uint16_t)0x116, ADC1_IT_AWS7 = (uint16_t)0x117, ADC1_IT_AWS8 = (uint16_t)0x118,
ADC1_IT_AWS9 = (uint16_t)0x119, ADC1_IT_AWS12 = (uint16_t)0x11C, ADC1_IT_EOC = (uint16_t)0x080
}

ADC1 Interrupt source.

More...
enum ADC1_PresSel_TypeDef {
ADC1_PRESSEL_FCPU_D2 = (uint8_t)0x00, ADC1_PRESSEL_FCPU_D3 = (uint8_t)0x10, ADC1_PRESSEL_FCPU_D4 = (uint8_t)0x20, ADC1_PRESSEL_FCPU_D6 = (uint8_t)0x30,
ADC1_PRESSEL_FCPU_D8 = (uint8_t)0x40, ADC1_PRESSEL_FCPU_D10 = (uint8_t)0x50, ADC1_PRESSEL_FCPU_D12 = (uint8_t)0x60, ADC1_PRESSEL_FCPU_D18 = (uint8_t)0x70
}

ADC1 clock prescaler selection.

More...
enum ADC1_SchmittTrigg_TypeDef {
ADC1_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, ADC1_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, ADC1_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, ADC1_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03,
ADC1_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, ADC1_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, ADC1_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, ADC1_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07,
ADC1_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, ADC1_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, ADC1_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, ADC1_SCHMITTTRIG_ALL = (uint8_t)0xFF
}

ADC1 schmitt Trigger.

More...

Enumeration Type Documentation

enum ADC1_Align_TypeDef

ADC1 data alignment.

Enumerator:
ADC1_ALIGN_LEFT

Data alignment left.

ADC1_ALIGN_RIGHT

Data alignment right.

Definition at line 62 of file stm8s_adc1.h.

enum ADC1_Channel_TypeDef

ADC1 analog channel selection.

Enumerator:
ADC1_CHANNEL_0

Analog channel 0.

ADC1_CHANNEL_1

Analog channel 1.

ADC1_CHANNEL_2

Analog channel 2.

ADC1_CHANNEL_3

Analog channel 3.

ADC1_CHANNEL_4

Analog channel 4.

ADC1_CHANNEL_5

Analog channel 5.

ADC1_CHANNEL_6

Analog channel 6.

ADC1_CHANNEL_7

Analog channel 7.

ADC1_CHANNEL_8

Analog channel 8.

ADC1_CHANNEL_9

Analog channel 9.

ADC1_CHANNEL_12

Analog channel 12.

Definition at line 149 of file stm8s_adc1.h.

enum ADC1_ConvMode_TypeDef

ADC1 conversion mode selection.

Enumerator:
ADC1_CONVERSIONMODE_SINGLE

Single conversion mode.

ADC1_CONVERSIONMODE_CONTINUOUS

Continuous conversion mode.

Definition at line 139 of file stm8s_adc1.h.

enum ADC1_ExtTrig_TypeDef

ADC1 External conversion trigger event selection.

Enumerator:
ADC1_EXTTRIG_TIM

Conversion from Internal TIM1 TRGO event.

ADC1_EXTTRIG_GPIO

Conversion from External interrupt on ADC_ETR pin.

Definition at line 53 of file stm8s_adc1.h.

enum ADC1_Flag_TypeDef

ADC1 Flags.

Enumerator:
ADC1_FLAG_OVR

Overrun status flag.

ADC1_FLAG_AWD

Analog WDG status.

ADC1_FLAG_AWS0

Analog channel 0 status.

ADC1_FLAG_AWS1

Analog channel 1 status.

ADC1_FLAG_AWS2

Analog channel 2 status.

ADC1_FLAG_AWS3

Analog channel 3 status.

ADC1_FLAG_AWS4

Analog channel 4 status.

ADC1_FLAG_AWS5

Analog channel 5 status.

ADC1_FLAG_AWS6

Analog channel 6 status.

ADC1_FLAG_AWS7

Analog channel 7 status.

ADC1_FLAG_AWS8

Analog channel 8 status.

ADC1_FLAG_AWS9

Analog channel 9 status.

ADC1_FLAG_AWS12

Analog channel 12 status.

ADC1_FLAG_EOC

EOC falg.

Definition at line 95 of file stm8s_adc1.h.

enum ADC1_IT_TypeDef

ADC1 Interrupt source.

Enumerator:
ADC1_IT_AWDIE

Analog WDG interrupt enable.

ADC1_IT_EOCIE

EOC interrupt enable.

ADC1_IT_AWD

Analog WDG status.

ADC1_IT_AWS0

Analog channel 0 status.

ADC1_IT_AWS1

Analog channel 1 status.

ADC1_IT_AWS2

Analog channel 2 status.

ADC1_IT_AWS3

Analog channel 3 status.

ADC1_IT_AWS4

Analog channel 4 status.

ADC1_IT_AWS5

Analog channel 5 status.

ADC1_IT_AWS6

Analog channel 6 status.

ADC1_IT_AWS7

Analog channel 7 status.

ADC1_IT_AWS8

Analog channel 8 status.

ADC1_IT_AWS9

Analog channel 9 status.

ADC1_IT_AWS12

Analog channel 12 status.

ADC1_IT_EOC

EOC pending bit.

Definition at line 71 of file stm8s_adc1.h.

enum ADC1_PresSel_TypeDef

ADC1 clock prescaler selection.

Enumerator:
ADC1_PRESSEL_FCPU_D2

Prescaler selection fADC1 = fcpu/2.

ADC1_PRESSEL_FCPU_D3

Prescaler selection fADC1 = fcpu/3.

ADC1_PRESSEL_FCPU_D4

Prescaler selection fADC1 = fcpu/4.

ADC1_PRESSEL_FCPU_D6

Prescaler selection fADC1 = fcpu/6.

ADC1_PRESSEL_FCPU_D8

Prescaler selection fADC1 = fcpu/8.

ADC1_PRESSEL_FCPU_D10

Prescaler selection fADC1 = fcpu/10.

ADC1_PRESSEL_FCPU_D12

Prescaler selection fADC1 = fcpu/12.

ADC1_PRESSEL_FCPU_D18

Prescaler selection fADC1 = fcpu/18.

Definition at line 38 of file stm8s_adc1.h.

enum ADC1_SchmittTrigg_TypeDef

ADC1 schmitt Trigger.

Enumerator:
ADC1_SCHMITTTRIG_CHANNEL0

Schmitt trigger disable on AIN0.

ADC1_SCHMITTTRIG_CHANNEL1

Schmitt trigger disable on AIN1.

ADC1_SCHMITTTRIG_CHANNEL2

Schmitt trigger disable on AIN2.

ADC1_SCHMITTTRIG_CHANNEL3

Schmitt trigger disable on AIN3.

ADC1_SCHMITTTRIG_CHANNEL4

Schmitt trigger disable on AIN4.

ADC1_SCHMITTTRIG_CHANNEL5

Schmitt trigger disable on AIN5.

ADC1_SCHMITTTRIG_CHANNEL6

Schmitt trigger disable on AIN6.

ADC1_SCHMITTTRIG_CHANNEL7

Schmitt trigger disable on AIN7.

ADC1_SCHMITTTRIG_CHANNEL8

Schmitt trigger disable on AIN8.

ADC1_SCHMITTTRIG_CHANNEL9

Schmitt trigger disable on AIN9.

ADC1_SCHMITTTRIG_CHANNEL12

Schmitt trigger disable on AIN12.

ADC1_SCHMITTTRIG_ALL

Schmitt trigger disable on All channels.

Definition at line 118 of file stm8s_adc1.h.


STM8S/A Standard Peripherals Drivers: ADC1_Private_Macros

Defines

ADC1_Private_Macros

Macros used by the assert function to check the different functions parameters. More...

Defines

#define | IS_ADC1_ALIGN_OK(ALIGN)
Macro used by the assert function to check the different alignment modes.
#define | IS_ADC1_BUFFER_OK(BUFFER) ((BUFFER) <= (uint8_t)0x09)
Macro used by the assert function to check the possible buffer values.
#define | IS_ADC1_CHANNEL_OK(CHANNEL)
Macro used by the assert function to check the different channels values.
#define | IS_ADC1_CONVERSIONMODE_OK(MODE)
Macro used by the assert function to check the different conversion modes.
#define | IS_ADC1_EXTTRIG_OK(EXTRIG)
Macro used by the assert function to check the different external trigger values.
#define | IS_ADC1_FLAG_OK(FLAG)
Macro used by the assert function to check the ADC1 Flag.
#define | IS_ADC1_IT_OK(IT)
Macro used by the assert function to check the Interrupt source.
#define | IS_ADC1_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the ADC1 pending bits.
#define | IS_ADC1_PRESSEL_OK(PRESCALER)
Macro used by the assert function to check the different prescaler's values.
#define | IS_ADC1_SCHMITTTRIG_OK(SCHMITTTRIG)
Macro used by the assert function to check the different schmitt trigger values.

Detailed Description

Macros used by the assert function to check the different functions parameters.

Define Documentation

#define IS_ADC1_ALIGN_OK ( ALIGN )
Value:
(((ALIGN) == ADC1_ALIGN_LEFT) || \
                                ((ALIGN) == ADC1_ALIGN_RIGHT))

Macro used by the assert function to check the different alignment modes.

Definition at line 201 of file stm8s_adc1.h.

Referenced by ADC1_ConversionConfig(), and ADC1_Init().

#define IS_ADC1_BUFFER_OK ( BUFFER ) ((BUFFER) <= (uint8_t)0x09)

Macro used by the assert function to check the possible buffer values.

Definition at line 284 of file stm8s_adc1.h.

Referenced by ADC1_GetBufferValue().

#define IS_ADC1_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == ADC1_CHANNEL_0) || \
                                    ((CHANNEL) == ADC1_CHANNEL_1) || \
                                    ((CHANNEL) == ADC1_CHANNEL_2) || \
                                    ((CHANNEL) == ADC1_CHANNEL_3) || \
                                    ((CHANNEL) == ADC1_CHANNEL_4) || \
                                    ((CHANNEL) == ADC1_CHANNEL_5) || \
                                    ((CHANNEL) == ADC1_CHANNEL_6) || \
                                    ((CHANNEL) == ADC1_CHANNEL_7) || \
                                    ((CHANNEL) == ADC1_CHANNEL_8) || \
                                    ((CHANNEL) == ADC1_CHANNEL_12) || \
                                    ((CHANNEL) == ADC1_CHANNEL_9))

Macro used by the assert function to check the different channels values.

Definition at line 269 of file stm8s_adc1.h.

Referenced by ADC1_AWDChannelConfig(), ADC1_ConversionConfig(), ADC1_GetAWDChannelStatus(), and ADC1_Init().

#define IS_ADC1_CONVERSIONMODE_OK ( MODE )
Value:
(((MODE) == ADC1_CONVERSIONMODE_SINGLE) || \
                                        ((MODE) == ADC1_CONVERSIONMODE_CONTINUOUS))

Macro used by the assert function to check the different conversion modes.

Definition at line 263 of file stm8s_adc1.h.

Referenced by ADC1_ConversionConfig(), and ADC1_Init().

#define IS_ADC1_EXTTRIG_OK ( EXTRIG )
Value:
(((EXTRIG) == ADC1_EXTTRIG_TIM) || \
                                   ((EXTRIG) == ADC1_EXTTRIG_GPIO))

Macro used by the assert function to check the different external trigger values.

Definition at line 195 of file stm8s_adc1.h.

Referenced by ADC1_ExternalTriggerConfig(), and ADC1_Init().

#define IS_ADC1_FLAG_OK ( FLAG )
Value:
(((FLAG) == ADC1_FLAG_EOC)|| \
                              ((FLAG) == ADC1_FLAG_OVR) || \
                              ((FLAG) == ADC1_FLAG_AWD) || \
                              ((FLAG) == ADC1_FLAG_AWS0) || \
                              ((FLAG) == ADC1_FLAG_AWS1) || \
                              ((FLAG) == ADC1_FLAG_AWS2) || \
                              ((FLAG) == ADC1_FLAG_AWS3) || \
                              ((FLAG) == ADC1_FLAG_AWS4) || \
                              ((FLAG) == ADC1_FLAG_AWS5) || \
                              ((FLAG) == ADC1_FLAG_AWS6) || \
                              ((FLAG) == ADC1_FLAG_AWS7) || \
                              ((FLAG) == ADC1_FLAG_AWS8) || \
                              ((FLAG) == ADC1_FLAG_AWS9))

Macro used by the assert function to check the ADC1 Flag.

Definition at line 213 of file stm8s_adc1.h.

Referenced by ADC1_ClearFlag(), and ADC1_GetFlagStatus().

#define IS_ADC1_IT_OK ( IT )
Value:
(((IT) == ADC1_IT_EOCIE) || \
                          ((IT) == ADC1_IT_AWDIE))

Macro used by the assert function to check the Interrupt source.

Definition at line 207 of file stm8s_adc1.h.

Referenced by ADC1_ITConfig().

#define IS_ADC1_ITPENDINGBIT_OK ( ITPENDINGBIT )
Value:
(((ITPENDINGBIT) == ADC1_IT_EOC) || \
    ((ITPENDINGBIT) == ADC1_IT_AWD) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS0) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS1) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS2) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS3) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS4) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS5) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS6) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS7) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS8) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS12) || \
    ((ITPENDINGBIT) == ADC1_IT_AWS9))

Macro used by the assert function to check the ADC1 pending bits.

Definition at line 230 of file stm8s_adc1.h.

Referenced by ADC1_ClearITPendingBit(), and ADC1_GetITStatus().

#define IS_ADC1_PRESSEL_OK ( PRESCALER )
Value:
(((PRESCALER) == ADC1_PRESSEL_FCPU_D2) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D3) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D4) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D6) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D8) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D10) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D12) || \
                                      ((PRESCALER) == ADC1_PRESSEL_FCPU_D18))

Macro used by the assert function to check the different prescaler's values.

Definition at line 183 of file stm8s_adc1.h.

Referenced by ADC1_Init(), and ADC1_PrescalerConfig().

#define IS_ADC1_SCHMITTTRIG_OK ( SCHMITTTRIG )
Value:
(((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL0) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL1) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL2) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL3) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL4) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL5) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL6) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL7) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL8) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL12) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_ALL) || \
    ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL9))

Macro used by the assert function to check the different schmitt trigger values.

Definition at line 247 of file stm8s_adc1.h.

Referenced by ADC1_Init(), and ADC1_SchmittTriggerConfig().


STM8S/A Standard Peripherals Drivers: ADC1_Exported_Functions

Functions

ADC1_Exported_Functions

Functions

void | ADC1_AWDChannelConfig (ADC1_Channel_TypeDef Channel, FunctionalState NewState)
Enables or disables the analog watchdog for the given channel.
void | ADC1_ClearFlag (ADC1_Flag_TypeDef Flag)
Clear the specified ADC1 Flag.
void | ADC1_ClearITPendingBit (ADC1_IT_TypeDef ITPendingBit)
Clear the ADC1 End of Conversion pending bit.
void | ADC1_Cmd (FunctionalState NewState)
Enables or Disables the ADC1 peripheral.
void | ADC1_ConversionConfig (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)
Configure the ADC1 conversion on selected channel.
void | ADC1_DataBufferCmd (FunctionalState NewState)
Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.
void | ADC1_DeInit (void)
Deinitializes the ADC1 peripheral registers to their default reset values.
void | ADC1_ExternalTriggerConfig (ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
Configure the ADC1 conversion on external trigger event.
FlagStatus | ADC1_GetAWDChannelStatus (ADC1_Channel_TypeDef Channel)
Checks the specified analog watchdog channel status.
uint16_t | ADC1_GetBufferValue (uint8_t Buffer)
Get one sample of measured signal.
uint16_t | ADC1_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC1_GetFlagStatus (ADC1_Flag_TypeDef Flag)
Checks the specified ADC1 flag status.
ITStatus | ADC1_GetITStatus (ADC1_IT_TypeDef ITPendingBit)
Returns the specified pending bit status.
void | ADC1_Init (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)
Initializes the ADC1 peripheral according to the specified parameters.
void | ADC1_ITConfig (ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)
Enables or disables the ADC1 interrupt.
void | ADC1_PrescalerConfig (ADC1_PresSel_TypeDef ADC1_Prescaler)
Configure the ADC1 prescaler division factor.
void | ADC1_ScanModeCmd (FunctionalState NewState)
Enables or Disables the ADC1 scan mode.
void | ADC1_SchmittTriggerConfig (ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC1 Schmitt Trigger on a selected channel.
void | ADC1_SetHighThreshold (uint16_t Threshold)
Sets the high threshold of the analog watchdog.
void | ADC1_SetLowThreshold (uint16_t Threshold)
Sets the low threshold of the analog watchdog.
void | ADC1_StartConversion (void)
Start ADC1 conversion.

Function Documentation

void ADC1_AWDChannelConfig | ( | ADC1_Channel_TypeDef | Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the analog watchdog for the given channel.

Parameters:
Channel | specifies the desired Channel. It can be set of the values of ADC1_Channel_TypeDef.
NewState | specifies the analog watchdog new state. can have one of the values of FunctionalState.
Return values:
None

Definition at line 427 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_CHANNEL_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_ClearFlag ( ADC1_Flag_TypeDef Flag )

Clear the specified ADC1 Flag.

Parameters:
Flag,: ADC1 flag. can be one of the values of ADC1_Flag_TypeDef.
Return values:
None

Definition at line 591 of file stm8s_adc1.c.

References IS_ADC1_FLAG_OK.

void ADC1_ClearITPendingBit ( ADC1_IT_TypeDef ITPendingBit )

Clear the ADC1 End of Conversion pending bit.

Parameters:
ITPendingBit : the IT pending bit to clear. This parameter can be one of the following values:

  • ADC1_IT_AWD : Analog WDG IT status
  • ADC1_IT_AWS0 : Analog channel 0 IT status
  • ADC1_IT_AWS1 : Analog channel 1 IT status
  • ADC1_IT_AWS2 : Analog channel 2 IT status
  • ADC1_IT_AWS3 : Analog channel 3 IT status
  • ADC1_IT_AWS4 : Analog channel 4 IT status
  • ADC1_IT_AWS5 : Analog channel 5 IT status
  • ADC1_IT_AWS6 : Analog channel 6 IT status
  • ADC1_IT_AWS7 : Analog channel 7 IT status
  • ADC1_IT_AWS8 : Analog channel 8 IT status
  • ADC1_IT_AWS9 : Analog channel 9 IT status
  • ADC1_IT_EOC : EOC pending bit
Return values:
None

Definition at line 687 of file stm8s_adc1.c.

References IS_ADC1_ITPENDINGBIT_OK.

void ADC1_Cmd ( FunctionalState NewState )

Enables or Disables the ADC1 peripheral.

Parameters:
NewState,: specifies the peripheral enabled or disabled state.
Return values:
None

Definition at line 126 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_ConversionConfig | ( | ADC1_ConvMode_TypeDef | ADC1_ConversionMode,
 |  | ADC1_Channel_TypeDef | ADC1_Channel,
 |  | ADC1_Align_TypeDef | ADC1_Align
 | ) |  |

Configure the ADC1 conversion on selected channel.

Parameters:
ADC1_ConversionMode | Specifies the conversion type. It can be set of the values of ADC1_ConvMode_TypeDef
ADC1_Channel | specifies the ADC1 Channel. It can be set of the values of ADC1_Channel_TypeDef
ADC1_Align | specifies the conerted data alignment. It can be set of the values of ADC1_Align_TypeDef
Return values:
None

Definition at line 300 of file stm8s_adc1.c.

References ADC1_CONVERSIONMODE_CONTINUOUS, IS_ADC1_ALIGN_OK, IS_ADC1_CHANNEL_OK, and IS_ADC1_CONVERSIONMODE_OK.

Referenced by ADC1_Init().

void ADC1_DataBufferCmd ( FunctionalState NewState )

Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.

Parameters:
NewState,: specifies the selected mode enabled or disabled state.
Return values:
None

Definition at line 170 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_DeInit ( void )

Deinitializes the ADC1 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 48 of file stm8s_adc1.c.

void ADC1_ExternalTriggerConfig | ( | ADC1_ExtTrig_TypeDef | ADC1_ExtTrigger,
 |  | FunctionalState | NewState
 | ) |  |

Configure the ADC1 conversion on external trigger event.

Full description:
The selected external trigger evant can be enabled or disabled.
Parameters:
ADC1_ExtTrigger | to select the External trigger event. can have one of the values of ADC1_ExtTrig_TypeDef.
NewState | to enable/disable the selected external trigger can have one of the values of FunctionalState.
Return values:
None

Definition at line 342 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_EXTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC1_Init().

FlagStatus ADC1_GetAWDChannelStatus ( ADC1_Channel_TypeDef Channel )

Checks the specified analog watchdog channel status.

Parameters:
Channel,: specify the channel of which to check the analog watchdog can be one of the values of ADC1_Channel_TypeDef.
Return values:
FlagStatus Status of the analog watchdog.

Definition at line 526 of file stm8s_adc1.c.

References IS_ADC1_CHANNEL_OK.

uint16_t ADC1_GetBufferValue ( uint8_t Buffer )

Get one sample of measured signal.

Parameters:
Buffer specifies the buffer to read.
Return values:
BufferValue,: value read from the given buffer.
Required preconditions:
ADC1 conversion finished.

Definition at line 488 of file stm8s_adc1.c.

References ADC1_BaseAddress, and IS_ADC1_BUFFER_OK.

uint16_t ADC1_GetConversionValue ( void )

Get one sample of measured signal.

Parameters:
None
Return values:
ConversionValue,: value of the measured signal.
Required preconditions:
ADC1 conversion finished.

Definition at line 390 of file stm8s_adc1.c.

FlagStatus ADC1_GetFlagStatus ( ADC1_Flag_TypeDef Flag )

Checks the specified ADC1 flag status.

Parameters:
Flag,: ADC1 flag. can be one of the values of ADC1_Flag_TypeDef.
Return values:
FlagStatus Status of the ADC1 flag.

Definition at line 551 of file stm8s_adc1.c.

References IS_ADC1_FLAG_OK.

ITStatus ADC1_GetITStatus ( ADC1_IT_TypeDef ITPendingBit )

Returns the specified pending bit status.

Parameters:
ITPendingBit : the IT pending bit to check. This parameter can be one of the following values:

  • ADC1_IT_AWD : Analog WDG IT status
  • ADC1_IT_AWS0 : Analog channel 0 IT status
  • ADC1_IT_AWS1 : Analog channel 1 IT status
  • ADC1_IT_AWS2 : Analog channel 2 IT status
  • ADC1_IT_AWS3 : Analog channel 3 IT status
  • ADC1_IT_AWS4 : Analog channel 4 IT status
  • ADC1_IT_AWS5 : Analog channel 5 IT status
  • ADC1_IT_AWS6 : Analog channel 6 IT status
  • ADC1_IT_AWS7 : Analog channel 7 IT status
  • ADC1_IT_AWS8 : Analog channel 8 IT status
  • ADC1_IT_AWS9 : Analog channel 9 IT status
  • ADC1_IT_EOC : EOC pending bit
Return values:
ITStatus,: status of the specified pending bit.

Definition at line 640 of file stm8s_adc1.c.

References IS_ADC1_ITPENDINGBIT_OK, and RESET.

void ADC1_Init | ( | ADC1_ConvMode_TypeDef | ADC1_ConversionMode,
 |  | ADC1_Channel_TypeDef | ADC1_Channel,
 |  | ADC1_PresSel_TypeDef | ADC1_PrescalerSelection,
 |  | ADC1_ExtTrig_TypeDef | ADC1_ExtTrigger,
 |  | FunctionalState | ADC1_ExtTriggerState,
 |  | ADC1_Align_TypeDef | ADC1_Align,
 |  | ADC1_SchmittTrigg_TypeDef | ADC1_SchmittTriggerChannel,
 |  | FunctionalState | ADC1_SchmittTriggerState
 | ) |  |

Initializes the ADC1 peripheral according to the specified parameters.

Parameters:
ADC1_ConversionMode,: specifies the conversion mode can be one of the values of ADC1_ConvMode_TypeDef.
ADC1_Channel,: specifies the channel to convert can be one of the values of ADC1_Channel_TypeDef.
ADC1_PrescalerSelection,: specifies the ADC1 prescaler can be one of the values of ADC1_PresSel_TypeDef.
ADC1_ExtTrigger,: specifies the external trigger can be one of the values of ADC1_ExtTrig_TypeDef.
ADC1_ExtTriggerState,: specifies the external trigger new state can be one of the values of FunctionalState.
ADC1_Align,: specifies the converted data alignment can be one of the values of ADC1_Align_TypeDef.
ADC1_SchmittTriggerChannel,: specifies the schmitt trigger channel can be one of the values of ADC1_SchmittTrigg_TypeDef.
ADC1_SchmittTriggerState,: specifies the schmitt trigger state can be one of the values of FunctionalState.
Return values:
None

Definition at line 85 of file stm8s_adc1.c.

References ADC1_ConversionConfig(), ADC1_ExternalTriggerConfig(), ADC1_PrescalerConfig(), ADC1_SchmittTriggerConfig(), IS_ADC1_ALIGN_OK, IS_ADC1_CHANNEL_OK, IS_ADC1_CONVERSIONMODE_OK, IS_ADC1_EXTTRIG_OK, IS_ADC1_PRESSEL_OK, IS_ADC1_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_ITConfig | ( | ADC1_IT_TypeDef | ADC1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC1 interrupt.

Parameters:
ADC1_IT specifies the name of the interrupt to enable or disable. This parameter can be one of the following values:

  • ADC1_IT_AWDITEN : Analog WDG interrupt enable
  • ADC1_IT_EOCITEN : EOC iterrupt enable
NewState specifies the state of the interrupt to apply.
Return values:
None

Definition at line 196 of file stm8s_adc1.c.

References DISABLE, IS_ADC1_IT_OK, and IS_FUNCTIONALSTATE_OK.

void ADC1_PrescalerConfig ( ADC1_PresSel_TypeDef ADC1_Prescaler )

Configure the ADC1 prescaler division factor.

Parameters:
ADC1_Prescaler,: the selected precaler. It can be one of the values of ADC1_PresSel_TypeDef.
Return values:
None

Definition at line 222 of file stm8s_adc1.c.

References IS_ADC1_PRESSEL_OK.

Referenced by ADC1_Init().

void ADC1_ScanModeCmd ( FunctionalState NewState )

Enables or Disables the ADC1 scan mode.

Parameters:
NewState,: specifies the selected mode enabled or disabled state.
Return values:
None

Definition at line 148 of file stm8s_adc1.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC1_SchmittTriggerConfig | ( | ADC1_SchmittTrigg_TypeDef | ADC1_SchmittTriggerChannel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC1 Schmitt Trigger on a selected channel.

Parameters:
ADC1_SchmittTriggerChannel | specifies the desired Channel. It can be set of the values of ADC1_SchmittTrigg_TypeDef.
NewState | specifies Channel new status. can have one of the values of FunctionalState.
Return values:
None

Definition at line 244 of file stm8s_adc1.c.

References ADC1_SCHMITTTRIG_ALL, ADC1_SCHMITTTRIG_CHANNEL8, DISABLE, IS_ADC1_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC1_Init().

void ADC1_SetHighThreshold ( uint16_t Threshold )

Sets the high threshold of the analog watchdog.

Parameters:
Threshold specifies the high threshold value. this value depends on the reference voltage range.
Return values:
None

Definition at line 463 of file stm8s_adc1.c.

void ADC1_SetLowThreshold ( uint16_t Threshold )

Sets the low threshold of the analog watchdog.

Parameters:
Threshold specifies the low threshold value. this value depends on the reference voltage range.
Return values:
None

Definition at line 475 of file stm8s_adc1.c.

void ADC1_StartConversion ( void )

Start ADC1 conversion.

Full description:
This function triggers the start of conversion, after ADC1 configuration.
Parameters:
None
Return values:
None
Required preconditions:
Enable the ADC1 peripheral before calling this function

Definition at line 378 of file stm8s_adc1.c.


STM8S/A Standard Peripherals Drivers: ADC2_Exported_Types

Enumerations

ADC2_Exported_Types

Enumerations

enum | ADC2_Align_TypeDef { ADC2_ALIGN_LEFT = (uint8_t)0x00, ADC2_ALIGN_RIGHT = (uint8_t)0x08 }

ADC2 data alignment.

More...
enum ADC2_Channel_TypeDef {
ADC2_CHANNEL_0 = (uint8_t)0x00, ADC2_CHANNEL_1 = (uint8_t)0x01, ADC2_CHANNEL_2 = (uint8_t)0x02, ADC2_CHANNEL_3 = (uint8_t)0x03,
ADC2_CHANNEL_4 = (uint8_t)0x04, ADC2_CHANNEL_5 = (uint8_t)0x05, ADC2_CHANNEL_6 = (uint8_t)0x06, ADC2_CHANNEL_7 = (uint8_t)0x07,
ADC2_CHANNEL_8 = (uint8_t)0x08, ADC2_CHANNEL_9 = (uint8_t)0x09, ADC2_CHANNEL_10 = (uint8_t)0x0A, ADC2_CHANNEL_11 = (uint8_t)0x0B,
ADC2_CHANNEL_12 = (uint8_t)0x0C, ADC2_CHANNEL_13 = (uint8_t)0x0D, ADC2_CHANNEL_14 = (uint8_t)0x0E, ADC2_CHANNEL_15 = (uint8_t)0x0F
}

ADC2 analog channel selection.

More...
enum | ADC2_ConvMode_TypeDef { ADC2_CONVERSIONMODE_SINGLE = (uint8_t)0x00, ADC2_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 }

ADC2 conversion mode selection.

More...
enum | ADC2_ExtTrig_TypeDef { ADC2_EXTTRIG_TIM = (uint8_t)0x00, ADC2_EXTTRIG_GPIO = (uint8_t)0x01 }

ADC2 External conversion trigger event selection.

More...
enum ADC2_PresSel_TypeDef {
ADC2_PRESSEL_FCPU_D2 = (uint8_t)0x00, ADC2_PRESSEL_FCPU_D3 = (uint8_t)0x10, ADC2_PRESSEL_FCPU_D4 = (uint8_t)0x20, ADC2_PRESSEL_FCPU_D6 = (uint8_t)0x30,
ADC2_PRESSEL_FCPU_D8 = (uint8_t)0x40, ADC2_PRESSEL_FCPU_D10 = (uint8_t)0x50, ADC2_PRESSEL_FCPU_D12 = (uint8_t)0x60, ADC2_PRESSEL_FCPU_D18 = (uint8_t)0x70
}

ADC2 clock prescaler selection.

More...
enum ADC2_SchmittTrigg_TypeDef {
ADC2_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, ADC2_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, ADC2_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, ADC2_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03,
ADC2_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, ADC2_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, ADC2_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, ADC2_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07,
ADC2_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, ADC2_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, ADC2_SCHMITTTRIG_CHANNEL10 = (uint8_t)0x0A, ADC2_SCHMITTTRIG_CHANNEL11 = (uint8_t)0x0B,
ADC2_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, ADC2_SCHMITTTRIG_CHANNEL13 = (uint8_t)0x0D, ADC2_SCHMITTTRIG_CHANNEL14 = (uint8_t)0x0E, ADC2_SCHMITTTRIG_CHANNEL15 = (uint8_t)0x0F,
ADC2_SCHMITTTRIG_ALL = (uint8_t)0x1F
}

ADC2 schmitt Trigger.

More...

Enumeration Type Documentation

enum ADC2_Align_TypeDef

ADC2 data alignment.

Enumerator:
ADC2_ALIGN_LEFT

Data alignment left.

ADC2_ALIGN_RIGHT

Data alignment right.

Definition at line 62 of file stm8s_adc2.h.

enum ADC2_Channel_TypeDef

ADC2 analog channel selection.

Enumerator:
ADC2_CHANNEL_0

Analog channel 0.

ADC2_CHANNEL_1

Analog channel 1.

ADC2_CHANNEL_2

Analog channel 2.

ADC2_CHANNEL_3

Analog channel 3.

ADC2_CHANNEL_4

Analog channel 4.

ADC2_CHANNEL_5

Analog channel 5.

ADC2_CHANNEL_6

Analog channel 6.

ADC2_CHANNEL_7

Analog channel 7.

ADC2_CHANNEL_8

Analog channel 8.

ADC2_CHANNEL_9

Analog channel 9.

ADC2_CHANNEL_10

Analog channel 10.

ADC2_CHANNEL_11

Analog channel 11.

ADC2_CHANNEL_12

Analog channel 12.

ADC2_CHANNEL_13

Analog channel 13.

ADC2_CHANNEL_14

Analog channel 14.

ADC2_CHANNEL_15

Analog channel 15.

Definition at line 104 of file stm8s_adc2.h.

enum ADC2_ConvMode_TypeDef

ADC2 conversion mode selection.

Enumerator:
ADC2_CONVERSIONMODE_SINGLE

Single conversion mode.

ADC2_CONVERSIONMODE_CONTINUOUS

Continuous conversion mode.

Definition at line 95 of file stm8s_adc2.h.

enum ADC2_ExtTrig_TypeDef

ADC2 External conversion trigger event selection.

Enumerator:
ADC2_EXTTRIG_TIM

Conversion from Internal TIM TRGO event.

ADC2_EXTTRIG_GPIO

Conversion from External interrupt on ADC_ETR pin.

Definition at line 54 of file stm8s_adc2.h.

enum ADC2_PresSel_TypeDef

ADC2 clock prescaler selection.

Enumerator:
ADC2_PRESSEL_FCPU_D2

Prescaler selection fADC2 = fcpu/2.

ADC2_PRESSEL_FCPU_D3

Prescaler selection fADC2 = fcpu/3.

ADC2_PRESSEL_FCPU_D4

Prescaler selection fADC2 = fcpu/4.

ADC2_PRESSEL_FCPU_D6

Prescaler selection fADC2 = fcpu/6.

ADC2_PRESSEL_FCPU_D8

Prescaler selection fADC2 = fcpu/8.

ADC2_PRESSEL_FCPU_D10

Prescaler selection fADC2 = fcpu/10.

ADC2_PRESSEL_FCPU_D12

Prescaler selection fADC2 = fcpu/12.

ADC2_PRESSEL_FCPU_D18

Prescaler selection fADC2 = fcpu/18.

Definition at line 40 of file stm8s_adc2.h.

enum ADC2_SchmittTrigg_TypeDef

ADC2 schmitt Trigger.

Enumerator:
ADC2_SCHMITTTRIG_CHANNEL0

Schmitt trigger disable on AIN0.

ADC2_SCHMITTTRIG_CHANNEL1

Schmitt trigger disable on AIN1.

ADC2_SCHMITTTRIG_CHANNEL2

Schmitt trigger disable on AIN2.

ADC2_SCHMITTTRIG_CHANNEL3

Schmitt trigger disable on AIN3.

ADC2_SCHMITTTRIG_CHANNEL4

Schmitt trigger disable on AIN4.

ADC2_SCHMITTTRIG_CHANNEL5

Schmitt trigger disable on AIN5.

ADC2_SCHMITTTRIG_CHANNEL6

Schmitt trigger disable on AIN6.

ADC2_SCHMITTTRIG_CHANNEL7

Schmitt trigger disable on AIN7.

ADC2_SCHMITTTRIG_CHANNEL8

Schmitt trigger disable on AIN8.

ADC2_SCHMITTTRIG_CHANNEL9

Schmitt trigger disable on AIN9.

ADC2_SCHMITTTRIG_CHANNEL10

Schmitt trigger disable on AIN10.

ADC2_SCHMITTTRIG_CHANNEL11

Schmitt trigger disable on AIN11.

ADC2_SCHMITTTRIG_CHANNEL12

Schmitt trigger disable on AIN12.

ADC2_SCHMITTTRIG_CHANNEL13

Schmitt trigger disable on AIN13.

ADC2_SCHMITTTRIG_CHANNEL14

Schmitt trigger disable on AIN14.

ADC2_SCHMITTTRIG_CHANNEL15

Schmitt trigger disable on AIN15.

ADC2_SCHMITTTRIG_ALL

Schmitt trigger disable on all channels.

Definition at line 70 of file stm8s_adc2.h.


STM8S/A Standard Peripherals Drivers: ADC2_Private_Macros

Defines

ADC2_Private_Macros

Macros used by the assert function to check the different functions parameters. More...

Defines

#define | IS_ADC2_ALIGN_OK(ALIGN)
Macro used by the assert function to check the different alignement modes.
#define | IS_ADC2_CHANNEL_OK(CHANNEL)
Macro used by the assert function to check the different channels values.
#define | IS_ADC2_CONVERSIONMODE_OK(MODE)
Macro used by the assert function to check the different conversion modes.
#define | IS_ADC2_EXTTRIG_OK(EXTRIG)
Macro used by the assert function to check the different external trigger values.
#define | IS_ADC2_PRESSEL_OK(PRESCALER)
Macro used by the assert function to check the different prescaler's values.
#define | IS_ADC2_SCHMITTTRIG_OK(SCHMITTTRIG)
Macro used by the assert function to check the different schmitt trigger values.

Detailed Description

Macros used by the assert function to check the different functions parameters.

Define Documentation

#define IS_ADC2_ALIGN_OK ( ALIGN )
Value:
(((ALIGN) == ADC2_ALIGN_LEFT) || \
                                ((ALIGN) == ADC2_ALIGN_RIGHT))

Macro used by the assert function to check the different alignement modes.

Definition at line 159 of file stm8s_adc2.h.

Referenced by ADC2_ConversionConfig(), and ADC2_Init().

#define IS_ADC2_CHANNEL_OK ( CHANNEL )
Value:
(((CHANNEL) == ADC2_CHANNEL_0) || \
                                    ((CHANNEL) == ADC2_CHANNEL_1) || \
                                    ((CHANNEL) == ADC2_CHANNEL_2) || \
                                    ((CHANNEL) == ADC2_CHANNEL_3) || \
                                    ((CHANNEL) == ADC2_CHANNEL_4) || \
                                    ((CHANNEL) == ADC2_CHANNEL_5) || \
                                    ((CHANNEL) == ADC2_CHANNEL_6) || \
                                    ((CHANNEL) == ADC2_CHANNEL_7) || \
                                    ((CHANNEL) == ADC2_CHANNEL_8) || \
                                    ((CHANNEL) == ADC2_CHANNEL_9) || \
                                    ((CHANNEL) == ADC2_CHANNEL_10) || \
                                    ((CHANNEL) == ADC2_CHANNEL_11) || \
                                    ((CHANNEL) == ADC2_CHANNEL_12) || \
                                    ((CHANNEL) == ADC2_CHANNEL_13) || \
                                    ((CHANNEL) == ADC2_CHANNEL_14) || \
                                    ((CHANNEL) == ADC2_CHANNEL_15))

Macro used by the assert function to check the different channels values.

Definition at line 193 of file stm8s_adc2.h.

Referenced by ADC2_ConversionConfig(), and ADC2_Init().

#define IS_ADC2_CONVERSIONMODE_OK ( MODE )
Value:
(((MODE) == ADC2_CONVERSIONMODE_SINGLE) || \
                                        ((MODE) == ADC2_CONVERSIONMODE_CONTINUOUS))

Macro used by the assert function to check the different conversion modes.

Definition at line 187 of file stm8s_adc2.h.

Referenced by ADC2_ConversionConfig(), and ADC2_Init().

#define IS_ADC2_EXTTRIG_OK ( EXTRIG )
Value:
(((EXTRIG) == ADC2_EXTTRIG_TIM) || \
                                                                   ((EXTRIG) == ADC2_EXTTRIG_GPIO))

Macro used by the assert function to check the different external trigger values.

Definition at line 153 of file stm8s_adc2.h.

Referenced by ADC2_ExternalTriggerConfig(), and ADC2_Init().

#define IS_ADC2_PRESSEL_OK ( PRESCALER )
Value:
(((PRESCALER) == ADC2_PRESSEL_FCPU_D2) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D3) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D4) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D6) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D8) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D10) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D12) || \
                                      ((PRESCALER) == ADC2_PRESSEL_FCPU_D18))

Macro used by the assert function to check the different prescaler's values.

Definition at line 141 of file stm8s_adc2.h.

Referenced by ADC2_Init(), and ADC2_PrescalerConfig().

#define IS_ADC2_SCHMITTTRIG_OK ( SCHMITTTRIG )
Value:
(((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL0) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL1) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL2) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL3) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL4) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL5) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL6) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL7) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL8) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL9) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL10) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL11) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL12) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL13) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL14) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL15) || \
    ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_ALL))

Macro used by the assert function to check the different schmitt trigger values.

Definition at line 166 of file stm8s_adc2.h.

Referenced by ADC2_Init(), and ADC2_SchmittTriggerConfig().


STM8S/A Standard Peripherals Drivers: ADC2_Exported_Functions

Functions

ADC2_Exported_Functions

Functions

void | ADC2_ClearFlag (void)
Clear the ADC2 EOC Flag.
void | ADC2_ClearITPendingBit (void)
Clear the ADC2 End of Conversion pending bit.
void | ADC2_Cmd (FunctionalState NewState)
Enables or Disables the ADC2 peripheral.
void | ADC2_ConversionConfig (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)
Configure the ADC2 conversion on selected channel.
void | ADC2_DeInit (void)
Deinitializes the ADC2 peripheral registers to their default reset values.
void | ADC2_ExternalTriggerConfig (ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)
Configure the ADC2 conversion on external trigger event.
uint16_t | ADC2_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC2_GetFlagStatus (void)
Checks the ADC2 EOC flag status.
ITStatus | ADC2_GetITStatus (void)
Returns the EOC pending bit status.
void | ADC2_Init (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)
Initializes the ADC2 peripheral according to the specified parameters.
void | ADC2_ITConfig (FunctionalState NewState)
Enables or disables the ADC2 interrupt.
void | ADC2_PrescalerConfig (ADC2_PresSel_TypeDef ADC2_Prescaler)
Configure the ADC2 prescaler division factor.
void | ADC2_SchmittTriggerConfig (ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC2 Schmitt Trigger on a selected channel.
void | ADC2_StartConversion (void)
Start ADC2 conversion.

Function Documentation

void ADC2_ClearFlag ( void )

Clear the ADC2 EOC Flag.

Parameters:
None
Return values:
None

Definition at line 378 of file stm8s_adc2.c.

void ADC2_ClearITPendingBit ( void )

Clear the ADC2 End of Conversion pending bit.

Parameters:
None
Return values:
None

Definition at line 399 of file stm8s_adc2.c.

void ADC2_Cmd ( FunctionalState NewState )

Enables or Disables the ADC2 peripheral.

Parameters:
NewState,: specifies the peripheral enabled or disabled state.
Return values:
None

Definition at line 118 of file stm8s_adc2.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC2_ConversionConfig | ( | ADC2_ConvMode_TypeDef | ADC2_ConversionMode,
 |  | ADC2_Channel_TypeDef | ADC2_Channel,
 |  | ADC2_Align_TypeDef | ADC2_Align
 | ) |  |

Configure the ADC2 conversion on selected channel.

Parameters:
ADC2_ConversionMode | Specifies the conversion type. It can be set of the values of ADC2_ConvMode_TypeDef
ADC2_Channel | specifies the ADC2 Channel. It can be set of the values of ADC2_Channel_TypeDef
ADC2_Align | specifies the converted data alignment. It can be set of the values of ADC2_Align_TypeDef
Return values:
None

Definition at line 242 of file stm8s_adc2.c.

References ADC2_CONVERSIONMODE_CONTINUOUS, IS_ADC2_ALIGN_OK, IS_ADC2_CHANNEL_OK, and IS_ADC2_CONVERSIONMODE_OK.

Referenced by ADC2_Init().

void ADC2_DeInit ( void )

Deinitializes the ADC2 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 48 of file stm8s_adc2.c.

void ADC2_ExternalTriggerConfig | ( | ADC2_ExtTrig_TypeDef | ADC2_ExtTrigger,
 |  | FunctionalState | NewState
 | ) |  |

Configure the ADC2 conversion on external trigger event.

Full description:
The selected external trigger event can be enabled or disabled.
Parameters:
ADC2_ExtTrigger | to select the External trigger event. can have one of the values of ADC2_ExtTrig_TypeDef.
NewState | to enable/disable the selected external trigger can have one of the values of FunctionalState.
Return values:
None

Definition at line 284 of file stm8s_adc2.c.

References DISABLE, IS_ADC2_EXTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC2_Init().

uint16_t ADC2_GetConversionValue ( void )

Get one sample of measured signal.

Parameters:
None
Return values:
ConversionValue,: value of the measured signal.
Required preconditions:
ADC2 conversion finished.

Definition at line 332 of file stm8s_adc2.c.

FlagStatus ADC2_GetFlagStatus ( void )

Checks the ADC2 EOC flag status.

Parameters:
None
Return values:
FlagStatus Status of the ADC2 EOC flag.

Definition at line 366 of file stm8s_adc2.c.

ITStatus ADC2_GetITStatus ( void )

Returns the EOC pending bit status.

Parameters:
None
Return values:
FlagStatus,: status of the EOC pending bit.

Definition at line 389 of file stm8s_adc2.c.

void ADC2_Init | ( | ADC2_ConvMode_TypeDef | ADC2_ConversionMode,
 |  | ADC2_Channel_TypeDef | ADC2_Channel,
 |  | ADC2_PresSel_TypeDef | ADC2_PrescalerSelection,
 |  | ADC2_ExtTrig_TypeDef | ADC2_ExtTrigger,
 |  | FunctionalState | ADC2_ExtTriggerState,
 |  | ADC2_Align_TypeDef | ADC2_Align,
 |  | ADC2_SchmittTrigg_TypeDef | ADC2_SchmittTriggerChannel,
 |  | FunctionalState | ADC2_SchmittTriggerState
 | ) |  |

Initializes the ADC2 peripheral according to the specified parameters.

Parameters:
ADC2_ConversionMode,: specifies the conversion mode can be one of the values of ADC2_ConvMode_TypeDef.
ADC2_Channel,: specifies the channel to convert can be one of the values of ADC2_Channel_TypeDef.
ADC2_PrescalerSelection,: specifies the ADC2 prescaler can be one of the values of ADC2_PresSel_TypeDef.
ADC2_ExtTrigger,: specifies the external trigger can be one of the values of ADC2_ExtTrig_TypeDef.
ADC2_ExtTriggerState,: specifies the external trigger new state can be one of the values of FunctionalState.
ADC2_Align,: specifies the converted data alignment can be one of the values of ADC2_Align_TypeDef.
ADC2_SchmittTriggerChannel,: specifies the schmitt trigger channel can be one of the values of ADC2_SchmittTrigg_TypeDef.
ADC2_SchmittTriggerState,: specifies the schmitt trigger state can be one of the values of FunctionalState.
Return values:
None

Definition at line 77 of file stm8s_adc2.c.

References ADC2_ConversionConfig(), ADC2_ExternalTriggerConfig(), ADC2_PrescalerConfig(), ADC2_SchmittTriggerConfig(), IS_ADC2_ALIGN_OK, IS_ADC2_CHANNEL_OK, IS_ADC2_CONVERSIONMODE_OK, IS_ADC2_EXTTRIG_OK, IS_ADC2_PRESSEL_OK, IS_ADC2_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

void ADC2_ITConfig ( FunctionalState NewState )

Enables or disables the ADC2 interrupt.

Parameters:
NewState specifies the state of ADC2 interrupt.
Return values:
None

Definition at line 140 of file stm8s_adc2.c.

References DISABLE, and IS_FUNCTIONALSTATE_OK.

void ADC2_PrescalerConfig ( ADC2_PresSel_TypeDef ADC2_Prescaler )

Configure the ADC2 prescaler division factor.

Parameters:
ADC2_Prescaler,: the selected prescaler. It can be one of the values of ADC2_PresSel_TypeDef.
Return values:
None

Definition at line 165 of file stm8s_adc2.c.

References IS_ADC2_PRESSEL_OK.

Referenced by ADC2_Init().

void ADC2_SchmittTriggerConfig | ( | ADC2_SchmittTrigg_TypeDef | ADC2_SchmittTriggerChannel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADC2 Schmitt Trigger on a selected channel.

Parameters:
ADC2_SchmittTriggerChannel | specifies the desired Channel. It can be set of the values of ADC2_SchmittTrigg_TypeDef.
NewState | specifies the Channel ADC2 Schmitt Trigger new status. can have one of the values of FunctionalState.
Return values:
None

Definition at line 187 of file stm8s_adc2.c.

References ADC2_SCHMITTTRIG_ALL, ADC2_SCHMITTTRIG_CHANNEL8, DISABLE, IS_ADC2_SCHMITTTRIG_OK, and IS_FUNCTIONALSTATE_OK.

Referenced by ADC2_Init().

void ADC2_StartConversion ( void )

Start ADC2 conversion.

Full description:
This function triggers the start of conversion, after ADC2 configuration.
Parameters:
None
Return values:
None
Required preconditions:
Enable the ADC2 peripheral before calling this function

Definition at line 320 of file stm8s_adc2.c.


STM8S/A Standard Peripherals Drivers: AWU_Exported_Types

Enumerations

AWU_Exported_Types

Enumerations

enum AWU_Timebase_TypeDef {
AWU_TIMEBASE_NO_IT = (uint8_t)0, AWU_TIMEBASE_250US = (uint8_t)1, AWU_TIMEBASE_500US = (uint8_t)2, AWU_TIMEBASE_1MS = (uint8_t)3,
AWU_TIMEBASE_2MS = (uint8_t)4, AWU_TIMEBASE_4MS = (uint8_t)5, AWU_TIMEBASE_8MS = (uint8_t)6, AWU_TIMEBASE_16MS = (uint8_t)7,
AWU_TIMEBASE_32MS = (uint8_t)8, AWU_TIMEBASE_64MS = (uint8_t)9, AWU_TIMEBASE_128MS = (uint8_t)10, AWU_TIMEBASE_256MS = (uint8_t)11,
AWU_TIMEBASE_512MS = (uint8_t)12, AWU_TIMEBASE_1S = (uint8_t)13, AWU_TIMEBASE_2S = (uint8_t)14, AWU_TIMEBASE_12S = (uint8_t)15,
AWU_TIMEBASE_30S = (uint8_t)16
}

AWU TimeBase selection.

More...

Enumeration Type Documentation

enum AWU_Timebase_TypeDef

AWU TimeBase selection.

Enumerator:
AWU_TIMEBASE_NO_IT

No AWU interrupt selected

AWU_TIMEBASE_250US

AWU Timebase equals 0.25 ms

AWU_TIMEBASE_500US

AWU Timebase equals 0.5 ms

AWU_TIMEBASE_1MS

AWU Timebase equals 1 ms

AWU_TIMEBASE_2MS

AWU Timebase equals 2 ms

AWU_TIMEBASE_4MS

AWU Timebase equals 4 ms

AWU_TIMEBASE_8MS

AWU Timebase equals 8 ms

AWU_TIMEBASE_16MS

AWU Timebase equals 16 ms

AWU_TIMEBASE_32MS

AWU Timebase equals 32 ms

AWU_TIMEBASE_64MS

AWU Timebase equals 64 ms

AWU_TIMEBASE_128MS

AWU Timebase equals 128 ms

AWU_TIMEBASE_256MS

AWU Timebase equals 256 ms

AWU_TIMEBASE_512MS

AWU Timebase equals 512 ms

AWU_TIMEBASE_1S

AWU Timebase equals 1 s

AWU_TIMEBASE_2S

AWU Timebase equals 2 s

AWU_TIMEBASE_12S

AWU Timebase equals 12 s

AWU_TIMEBASE_30S

AWU Timebase equals 30 s

Definition at line 39 of file stm8s_awu.h.


STM8S/A Standard Peripherals Drivers: AWU_Exported_Constants

Defines

AWU_Exported_Constants

Defines

#define | LSI_FREQUENCY_MAX ((uint32_t)150000)
#define | LSI_FREQUENCY_MIN ((uint32_t)110000)

Define Documentation

#define LSI_FREQUENCY_MAX ((uint32_t)150000)

LSI maximum value in Hertz

Definition at line 71 of file stm8s_awu.h.

#define LSI_FREQUENCY_MIN ((uint32_t)110000)

LSI minimum value in Hertz

Definition at line 70 of file stm8s_awu.h.


STM8S/A Standard Peripherals Drivers: AWU_Private_Macros

Defines

AWU_Private_Macros

Defines

#define | IS_AWU_TIMEBASE_OK(TB)
Macro used by the assert function to check the different functions parameters.
#define | IS_LSI_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the LSI frequency (in Hz)

Define Documentation

#define IS_AWU_TIMEBASE_OK ( TB )
Value:
(((TB) == AWU_TIMEBASE_NO_IT) || \
   ((TB) == AWU_TIMEBASE_250US) || \
   ((TB) == AWU_TIMEBASE_500US) || \
   ((TB) == AWU_TIMEBASE_1MS)   || \
   ((TB) == AWU_TIMEBASE_2MS)   || \
   ((TB) == AWU_TIMEBASE_4MS)   || \
   ((TB) == AWU_TIMEBASE_8MS)   || \
   ((TB) == AWU_TIMEBASE_16MS)  || \
   ((TB) == AWU_TIMEBASE_32MS)  || \
   ((TB) == AWU_TIMEBASE_64MS)  || \
   ((TB) == AWU_TIMEBASE_128MS) || \
   ((TB) == AWU_TIMEBASE_256MS) || \
   ((TB) == AWU_TIMEBASE_512MS) || \
   ((TB) == AWU_TIMEBASE_1S)    || \
   ((TB) == AWU_TIMEBASE_2S)    || \
   ((TB) == AWU_TIMEBASE_12S)   || \
   ((TB) == AWU_TIMEBASE_30S))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert function to check the AWU timebases

Definition at line 92 of file stm8s_awu.h.

Referenced by AWU_Init().

#define IS_LSI_FREQUENCY_OK ( FREQ )
Value:
(((FREQ) >= LSI_FREQUENCY_MIN) && \
   ((FREQ) <= LSI_FREQUENCY_MAX))

Macro used by the assert function to check the LSI frequency (in Hz)

Definition at line 114 of file stm8s_awu.h.

Referenced by AWU_LSICalibrationConfig(), and BEEP_LSICalibrationConfig().


STM8S/A Standard Peripherals Drivers: AWU_Exported_Functions

Functions

AWU_Exported_Functions

Functions

void | AWU_Cmd (FunctionalState NewState)
Enable or disable the AWU peripheral.
void | AWU_DeInit (void)
Deinitializes the AWU peripheral registers to their default reset values.
FlagStatus | AWU_GetFlagStatus (void)
Returns status of the AWU peripheral flag.
void | AWU_IdleModeEnable (void)
Configures AWU in Idle mode to reduce power consumption.
void | AWU_Init (AWU_Timebase_TypeDef AWU_TimeBase)
Initializes the AWU peripheral according to the specified parameters.
void | AWU_LSICalibrationConfig (uint32_t LSIFreqHz)
Update APR register with the measured LSI frequency.

Function Documentation

void AWU_Cmd ( FunctionalState NewState )

Enable or disable the AWU peripheral.

Parameters:
NewState Indicates the new state of the AWU peripheral.
Return values:
None
Required preconditions:
Initialisation of AWU and LS RC calibration must be done before.

Definition at line 108 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUEN, and DISABLE.

void AWU_DeInit ( void )

Deinitializes the AWU peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 67 of file stm8s_awu.c.

References AWU, AWU_APR_RESET_VALUE, AWU_CSR_RESET_VALUE, and AWU_TBR_RESET_VALUE.

FlagStatus AWU_GetFlagStatus ( void )

Returns status of the AWU peripheral flag.

Parameters:
None
Return values:
FlagStatus : Status of the AWU flag. This parameter can be any of the FlagStatus enumeration.

Definition at line 180 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUF, RESET, and SET.

void AWU_IdleModeEnable ( void )

Configures AWU in Idle mode to reduce power consumption.

Parameters:
None
Return values:
None

Definition at line 165 of file stm8s_awu.c.

References AWU, AWU_CSR_AWUEN, and AWU_TBR_AWUTB.

void AWU_Init ( AWU_Timebase_TypeDef AWU_TimeBase )

Initializes the AWU peripheral according to the specified parameters.

Parameters:
AWU_TimeBase : Time base selection (interval between AWU interrupts). can be one of the values of AWU_Timebase_TypeDef.
Return values:
None
Required preconditions:
The LS RC calibration must be performed before calling this function.

Definition at line 82 of file stm8s_awu.c.

References APR_Array, AWU, AWU_APR_APR, AWU_CSR_AWUEN, AWU_TBR_AWUTB, IS_AWU_TIMEBASE_OK, and TBR_Array.

void AWU_LSICalibrationConfig ( uint32_t LSIFreqHz )

Update APR register with the measured LSI frequency.

Note on the APR calculation:
A is the integer part of lsifreqkhz/4 and x the decimal part. x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1] but we know that A + x = lsifreqkhz/4 ==> 4x = lsifreqkhz-4A so [F1] can be written : 4A >= (lsifreqkhz-4A)(1+2A)
Parameters:
LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
Return values:
None
Required preconditions:
  • AWU must be disabled to avoid unwanted interrupts.

Definition at line 135 of file stm8s_awu.c.

References AWU, and IS_LSI_FREQUENCY_OK.


STM8S/A Standard Peripherals Drivers: BEEP_Exported_Types

Enumerations

BEEP_Exported_Types

Enumerations

enum BEEP_Frequency_TypeDef { BEEP_FREQUENCY_1KHZ = (uint8_t)0x00, BEEP_FREQUENCY_2KHZ = (uint8_t)0x40, BEEP_FREQUENCY_4KHZ = (uint8_t)0x80 }

BEEP Frequency selection.

More...

Enumeration Type Documentation

enum BEEP_Frequency_TypeDef

BEEP Frequency selection.

Enumerator:
BEEP_FREQUENCY_1KHZ

Beep signal output frequency equals to 1 KHz

BEEP_FREQUENCY_2KHZ

Beep signal output frequency equals to 2 KHz

BEEP_FREQUENCY_4KHZ

Beep signal output frequency equals to 4 KHz

Definition at line 39 of file stm8s_beep.h.


STM8S/A Standard Peripherals Drivers: BEEP_Exported_Constants

Defines

BEEP_Exported_Constants

Defines

#define | BEEP_CALIBRATION_DEFAULT ((uint8_t)0x0B)
#define | LSI_FREQUENCY_MAX ((uint32_t)150000)
#define | LSI_FREQUENCY_MIN ((uint32_t)110000)

Define Documentation

#define BEEP_CALIBRATION_DEFAULT ((uint8_t)0x0B)

Default value when calibration is not done

Definition at line 55 of file stm8s_beep.h.

Referenced by BEEP_Init().

#define LSI_FREQUENCY_MAX ((uint32_t)150000)

LSI maximum value in Hertz

Definition at line 58 of file stm8s_beep.h.

#define LSI_FREQUENCY_MIN ((uint32_t)110000)

LSI minimum value in Hertz

Definition at line 57 of file stm8s_beep.h.


STM8S/A Standard Peripherals Drivers: BEEP_Private_Macros

Defines

BEEP_Private_Macros

Defines

#define | IS_BEEP_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the different functions parameters.
#define | IS_LSI_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the LSI frequency (in Hz).

Define Documentation

#define IS_BEEP_FREQUENCY_OK ( FREQ )
Value:
(((FREQ) == BEEP_FREQUENCY_1KHZ) || \
   ((FREQ) == BEEP_FREQUENCY_2KHZ) || \
   ((FREQ) == BEEP_FREQUENCY_4KHZ))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert function to check the BEEP frequencies.

Definition at line 78 of file stm8s_beep.h.

Referenced by BEEP_Init().

#define IS_LSI_FREQUENCY_OK ( FREQ )
Value:
(((FREQ) >= LSI_FREQUENCY_MIN) && \
   ((FREQ) <= LSI_FREQUENCY_MAX))

Macro used by the assert function to check the LSI frequency (in Hz).

Definition at line 86 of file stm8s_beep.h.


STM8S/A Standard Peripherals Drivers: BEEP_Exported_Functions

Functions

BEEP_Exported_Functions

Functions

void | BEEP_Cmd (FunctionalState NewState)
Enable or disable the BEEP function.
void | BEEP_DeInit (void)
Deinitializes the BEEP peripheral registers to their default reset values.
void | BEEP_Init (BEEP_Frequency_TypeDef BEEP_Frequency)
Initializes the BEEP function according to the specified parameters.
void | BEEP_LSICalibrationConfig (uint32_t LSIFreqHz)
Update CSR register with the measured LSI frequency.

Function Documentation

void BEEP_Cmd ( FunctionalState NewState )

Enable or disable the BEEP function.

Parameters:
NewState Indicates the new state of the BEEP function.
Return values:
None
Required preconditions:
Initialisation of BEEP and LS RC calibration must be done before.

Definition at line 87 of file stm8s_beep.c.

References BEEP, BEEP_CSR_BEEPEN, and DISABLE.

void BEEP_DeInit ( void )

Deinitializes the BEEP peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 48 of file stm8s_beep.c.

References BEEP, and BEEP_CSR_RESET_VALUE.

void BEEP_Init ( BEEP_Frequency_TypeDef BEEP_Frequency )

Initializes the BEEP function according to the specified parameters.

Parameters:
BEEP_Frequency Frequency selection. can be one of the values of BEEP_Frequency_TypeDef.
Return values:
None
Required preconditions:
The LS RC calibration must be performed before calling this function.

Definition at line 61 of file stm8s_beep.c.

References BEEP, BEEP_CALIBRATION_DEFAULT, BEEP_CSR_BEEPDIV, BEEP_CSR_BEEPSEL, and IS_BEEP_FREQUENCY_OK.

void BEEP_LSICalibrationConfig ( uint32_t LSIFreqHz )

Update CSR register with the measured LSI frequency.

Note on the APR calculation:
A is the integer part of LSIFreqkHz/4 and x the decimal part. x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1] but we know that A + x = LSIFreqkHz/4 ==> 4x = LSIFreqkHz-4A so [F1] can be written : 4A >= (LSIFreqkHz-4A)(1+2A)
Parameters:
LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
Return values:
None
Required preconditions:
  • BEEP must be disabled to avoid unwanted interrupts.

Definition at line 114 of file stm8s_beep.c.

References BEEP, BEEP_CSR_BEEPDIV, and IS_LSI_FREQUENCY_OK.


STM8S/A Standard Peripherals Drivers: CAN_Exported_Types

Enumerations

CAN_Exported_Types

Enumerations

enum CAN_BitSeg1_TypeDef {
CAN_BitSeg1_1TimeQuantum = ((uint8_t)0x00), CAN_BitSeg1_2TimeQuantum = ((uint8_t)0x01), CAN_BitSeg1_3TimeQuantum = ((uint8_t)0x02), CAN_BitSeg1_4TimeQuantum = ((uint8_t)0x03),
CAN_BitSeg1_5TimeQuantum = ((uint8_t)0x04), CAN_BitSeg1_6TimeQuantum = ((uint8_t)0x05), CAN_BitSeg1_7TimeQuantum = ((uint8_t)0x06), CAN_BitSeg1_8TimeQuantum = ((uint8_t)0x07),
CAN_BitSeg1_9TimeQuantum = ((uint8_t)0x08), CAN_BitSeg1_10TimeQuantum = ((uint8_t)0x09), CAN_BitSeg1_11TimeQuantum = ((uint8_t)0x0A), CAN_BitSeg1_12TimeQuantum = ((uint8_t)0x0B),
CAN_BitSeg1_13TimeQuantum = ((uint8_t)0x0C), CAN_BitSeg1_14TimeQuantum = ((uint8_t)0x0D), CAN_BitSeg1_15TimeQuantum = ((uint8_t)0x0E), CAN_BitSeg1_16TimeQuantum = ((uint8_t)0x0F)
}

time quantum in bit segment 1

More...
enum CAN_BitSeg2_TypeDef {
CAN_BitSeg2_1TimeQuantum = ((uint8_t)0x00), CAN_BitSeg2_2TimeQuantum = ((uint8_t)0x10), CAN_BitSeg2_3TimeQuantum = ((uint8_t)0x20), CAN_BitSeg2_4TimeQuantum = ((uint8_t)0x30),
CAN_BitSeg2_5TimeQuantum = ((uint8_t)0x40), CAN_BitSeg2_6TimeQuantum = ((uint8_t)0x50), CAN_BitSeg2_7TimeQuantum = ((uint8_t)0x60), CAN_BitSeg2_8TimeQuantum = ((uint8_t)0x70)
}

time quantum in bit segment 2

More...
enum CAN_ErrorCode_TypeDef {
CAN_ErrorCode_NoErr = ((uint8_t)0x00), CAN_ErrorCode_StuffErr = ((uint8_t)0x10), CAN_ErrorCode_FormErr = ((uint8_t)0x20), CAN_ErrorCode_ACKErr = ((uint8_t)0x30),
CAN_ErrorCode_BitRecessiveErr = ((uint8_t)0x40), CAN_ErrorCode_BitDominantErr = ((uint8_t)0x50), CAN_ErrorCode_CRCErr = ((uint8_t)0x60), CAN_ErrorCode_SoftwareSetErr = ((uint8_t)0x70)
}

CAN Error Code description.

More...
enum | CAN_FilterMode_TypeDef { CAN_FilterMode_IdMask = ((uint8_t)0x00), CAN_FilterMode_IdMask_IdList = ((uint8_t)0x10), CAN_FilterMode_IdList_IdMask = ((uint8_t)0x11), CAN_FilterMode_IdList = ((uint8_t)0x01) }

CAN filter mode.

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enum CAN_FilterNumber_TypeDef {
CAN_FilterNumber_0 = ((uint8_t)0x00), CAN_FilterNumber_1 = ((uint8_t)0x01), CAN_FilterNumber_2 = ((uint8_t)0x02), CAN_FilterNumber_3 = ((uint8_t)0x03),
CAN_FilterNumber_4 = ((uint8_t)0x04), CAN_FilterNumber_5 = ((uint8_t)0x05)
}

CAN filter number.

More...
enum | CAN_FilterScale_TypeDef { CAN_FilterScale_8Bit = ((uint8_t)0x00), CAN_FilterScale_16_8Bit = ((uint8_t)0x02), CAN_FilterScale_16Bit = ((uint8_t)0x04), CAN_FilterScale_32Bit = ((uint8_t)0x06) }

CAN filter scale.

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enum CAN_FLAG_TypeDef {
CAN_FLAG_RQCP0 = ((uint16_t)0x3401), CAN_FLAG_RQCP1 = ((uint16_t)0x3402), CAN_FLAG_RQCP2 = ((uint16_t)0x3404), CAN_FLAG_FMP = ((uint16_t)0x1203),
CAN_FLAG_FF = ((uint16_t)0x3208), CAN_FLAG_FOV = ((uint16_t)0x3210), CAN_FLAG_WKU = ((uint16_t)0x3108), CAN_FLAG_EWG = ((uint16_t)0x1001),
CAN_FLAG_EPV = ((uint16_t)0x1002), CAN_FLAG_BOF = ((uint16_t)0x1004), CAN_FLAG_LEC = ((uint16_t)0x3070)
}

CAN flags.

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enum | CAN_Id_TypeDef { CAN_Id_Standard = ((uint8_t)0x00), CAN_Id_Extended = ((uint8_t)0x40) }

CAN identifier type.

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enum | CAN_InitStatus_TypeDef { CAN_InitStatus_Failed = 0, CAN_InitStatus_Success = ! CAN_InitStatus_Failed }

CAN sleep constants.

More...
enum CAN_IT_TypeDef {
CAN_IT_TME = ((uint16_t)0x0001), CAN_IT_FMP = ((uint16_t)0x0002), CAN_IT_FF = ((uint16_t)0x0004), CAN_IT_FOV = ((uint16_t)0x0008),
CAN_IT_WKU = ((uint16_t)0x0080), CAN_IT_ERR = ((uint16_t)0x4000), CAN_IT_EWG = ((uint16_t)0x0100), CAN_IT_EPV = ((uint16_t)0x0200),
CAN_IT_BOF = ((uint16_t)0x0400), CAN_IT_LEC = ((uint16_t)0x0800)
}

CAN interrupts.

More...
enum CAN_MasterCtrl_TypeDef {
CAN_MasterCtrl_AllDisabled = ((uint8_t)0x00), CAN_MasterCtrl_AllEnabled = ((uint8_t)0xFC), CAN_MasterCtrl_TimeTriggerCOMMode = ((uint8_t)0x80), CAN_MasterCtrl_AutoBusOffManagement = ((uint8_t)0x40),
CAN_MasterCtrl_AutoWakeUpMode = ((uint8_t)0x20), CAN_MasterCtrl_NoAutoReTx = ((uint8_t)0x10), CAN_MasterCtrl_RxFifoLockedMode = ((uint8_t)0x08), CAN_MasterCtrl_TxFifoPriority = ((uint8_t)0x04)
}

CAN Time Triggered Communication mode.

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enum | CAN_Mode_TypeDef { CAN_Mode_Normal = ((uint8_t)0x00), CAN_Mode_LoopBack = ((uint8_t)0x01), CAN_Mode_Silent = ((uint8_t)0x02), CAN_Mode_Silent_LoopBack = ((uint8_t)0x03) }

CAN mode options.

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enum | CAN_ModeStatus_TypeDef { CAN_ModeStatus_Failed = ((uint8_t)0x00), CAN_ModeStatus_Success = ! CAN_ModeStatus_Failed }

CAN operating mode status.

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enum | CAN_NbrPendingMessage_TypeDef { CAN_NbrPendingMessage_0 = ((uint8_t)0x00), CAN_NbrPendingMessage_1 = ((uint8_t)0x01), CAN_NbrPendingMessage_2 = ((uint8_t)0x02), CAN_NbrPendingMessage_3 = ((uint8_t)0x03) }

CAN Pending Messages number.

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enum | CAN_OperatingMode_TypeDef { CAN_OperatingMode_Initialization = ((uint8_t)0x00), CAN_OperatingMode_Normal = ((uint8_t)0x01), CAN_OperatingMode_Sleep = ((uint8_t)0x02) }

CAN operating mode.

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enum CAN_Page_TypeDef {
CAN_Page_TxMailBox0 = ((uint8_t) 0), CAN_Page_TxMailBox1 = ((uint8_t) 1), CAN_Page_TxMailBox2 = ((uint8_t) 5), CAN_Page_Filter01 = ((uint8_t) 2),
CAN_Page_Filter23 = ((uint8_t) 3), CAN_Page_Filter45 = ((uint8_t) 4), CAN_Page_Config = ((uint8_t) 6), CAN_Page_RxFifo = ((uint8_t) 7)
}

CAN Page Mapping.

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enum | CAN_RTR_TypeDef { CAN_RTR_Data = ((uint8_t)0x00), CAN_RTR_Remote = ((uint8_t)0x20) }

CAN remote transmission request.

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enum | CAN_Sleep_TypeDef { CAN_Sleep_Failed = ((uint8_t)0x00), CAN_Sleep_Ok = ((uint8_t)0x01) }

CAN sleep Status.

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enum | CAN_ST7Compatibility_TypeDef { CAN_ST7Compatibility_Enable = ((uint8_t)0x00), CAN_ST7Compatibility_Disable = ((uint8_t)0x10) }

CAN ST7 Compatibility.

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enum | CAN_SynJumpWidth_TypeDef { CAN_SynJumpWidth_1TimeQuantum = ((uint8_t)0x00), CAN_SynJumpWidth_2TimeQuantum = ((uint8_t)0x40), CAN_SynJumpWidth_3TimeQuantum = ((uint8_t)0x80), CAN_SynJumpWidth_4TimeQuantum = ((uint8_t)0xC0) }

CAN synchronisation jump width (SJW)

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enum | CAN_TransmitMailBox_TypeDef { CAN_TransmitMailBox_0 = ((uint8_t) 0x00), CAN_TransmitMailBox_1 = ((uint8_t) 0x01), CAN_TransmitMailBox_2 = ((uint8_t) 0x05) }

CAN Tx mailboxes.

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enum CAN_TxStatus_TypeDef {
CAN_TxStatus_Failed = ((uint8_t)0xF0), CAN_TxStatus_Ok = ((uint8_t)0xF1), CAN_TxStatus_Pending = ((uint8_t)0xF2), CAN_TxStatus_NoMailBox = ((uint8_t)0xF4),
CAN_TxStatus_MailBoxEmpty = ((uint8_t)0xF5), CAN_TxStatus_MailBox0Ok = ((uint8_t)0x00), CAN_TxStatus_MailBox1Ok = ((uint8_t)0x01), CAN_TxStatus_MailBox2Ok = ((uint8_t)0x05)
}

CAN transmit Status.

More...
enum | CAN_WakeUp_TypeDef { CAN_WakeUp_Failed = ((uint8_t)0x00), CAN_WakeUp_Ok = ((uint8_t)0x01) }

CAN wake up status.

More...

Enumeration Type Documentation

enum CAN_BitSeg1_TypeDef

time quantum in bit segment 1

Enumerator:
CAN_BitSeg1_1TimeQuantum

1 time quantum

CAN_BitSeg1_2TimeQuantum

2 time quantum

CAN_BitSeg1_3TimeQuantum

3 time quantum

CAN_BitSeg1_4TimeQuantum

4 time quantum

CAN_BitSeg1_5TimeQuantum

5 time quantum

CAN_BitSeg1_6TimeQuantum

6 time quantum

CAN_BitSeg1_7TimeQuantum

7 time quantum

CAN_BitSeg1_8TimeQuantum

8 time quantum

CAN_BitSeg1_9TimeQuantum

9 time quantum

CAN_BitSeg1_10TimeQuantum

10 time quantum

CAN_BitSeg1_11TimeQuantum

11 time quantum

CAN_BitSeg1_12TimeQuantum

12 time quantum

CAN_BitSeg1_13TimeQuantum

13 time quantum

CAN_BitSeg1_14TimeQuantum

14 time quantum

CAN_BitSeg1_15TimeQuantum

15 time quantum

CAN_BitSeg1_16TimeQuantum

16 time quantum

Definition at line 120 of file stm8s_can.h.

enum CAN_BitSeg2_TypeDef

time quantum in bit segment 2

Enumerator:
CAN_BitSeg2_1TimeQuantum

1 time quantum

CAN_BitSeg2_2TimeQuantum

2 time quantum

CAN_BitSeg2_3TimeQuantum

3 time quantum

CAN_BitSeg2_4TimeQuantum

4 time quantum

CAN_BitSeg2_5TimeQuantum

5 time quantum

CAN_BitSeg2_6TimeQuantum

6 time quantum

CAN_BitSeg2_7TimeQuantum

7 time quantum

CAN_BitSeg2_8TimeQuantum

8 time quantum

Definition at line 142 of file stm8s_can.h.

enum CAN_ErrorCode_TypeDef

CAN Error Code description.

Enumerator:
CAN_ErrorCode_NoErr

No Error

CAN_ErrorCode_StuffErr

Stuff Error

CAN_ErrorCode_FormErr

Form Error

CAN_ErrorCode_ACKErr

Acknowledgment Error

CAN_ErrorCode_BitRecessiveErr

Bit Recessive Error

CAN_ErrorCode_BitDominantErr

Bit Dominant Error

CAN_ErrorCode_CRCErr

CRC Error

CAN_ErrorCode_SoftwareSetErr

Software Set Error

Definition at line 305 of file stm8s_can.h.

enum CAN_FilterMode_TypeDef

CAN filter mode.

Enumerator:
CAN_FilterMode_IdMask

id/mask mode

CAN_FilterMode_IdMask_IdList

Id/Mask mode First and IdList mode second

CAN_FilterMode_IdList_IdMask

IdList mode First and IdMask mode second

CAN_FilterMode_IdList

identifier list mode

Definition at line 169 of file stm8s_can.h.

enum CAN_FilterNumber_TypeDef

CAN filter number.

Enumerator:
CAN_FilterNumber_0

Filter number 0

CAN_FilterNumber_1

Filter number 1

CAN_FilterNumber_2

Filter number 2

CAN_FilterNumber_3

Filter number 3

CAN_FilterNumber_4

Filter number 4

CAN_FilterNumber_5

Filter number 5

Definition at line 157 of file stm8s_can.h.

enum CAN_FilterScale_TypeDef

CAN filter scale.

Enumerator:
CAN_FilterScale_8Bit

8-bit filter scale

CAN_FilterScale_16_8Bit

16/8-bit filter scale

CAN_FilterScale_16Bit

16-bit filter scale

CAN_FilterScale_32Bit

32-bit filter scale

Definition at line 179 of file stm8s_can.h.

enum CAN_FLAG_TypeDef

CAN flags.

Enumerator:
CAN_FLAG_RQCP0

Request MailBox0 Flag

CAN_FLAG_RQCP1

Request MailBox1 Flag

CAN_FLAG_RQCP2

Request MailBox2 Flag

CAN_FLAG_FMP

FIFO Message Pending Flag

CAN_FLAG_FF

FIFO Full Flag

CAN_FLAG_FOV

FIFO Overrun Flag

CAN_FLAG_WKU

wake up Flag

CAN_FLAG_EWG

Error Warning Flag

CAN_FLAG_EPV

Error Passive Flag

CAN_FLAG_BOF

Bus-Off Flag

CAN_FLAG_LEC

Last error code Flag

Definition at line 254 of file stm8s_can.h.

enum CAN_Id_TypeDef

CAN identifier type.

Enumerator:
CAN_Id_Standard

Standard Id

CAN_Id_Extended

Extended Id

Definition at line 209 of file stm8s_can.h.

enum CAN_InitStatus_TypeDef

CAN sleep constants.

Enumerator:
CAN_InitStatus_Failed

CAN initialization failed

CAN_InitStatus_Success

CAN initialization OK

Definition at line 60 of file stm8s_can.h.

enum CAN_IT_TypeDef

CAN interrupts.

Enumerator:
CAN_IT_TME

Transmit mailbox empty interrupt

CAN_IT_FMP

FIFO message pending interrupt

CAN_IT_FF

FIFO full interrupt

CAN_IT_FOV

FIFO overrun interrupt

CAN_IT_WKU

Wake-up interrupt

CAN_IT_ERR

Genaral Error interrupt

CAN_IT_EWG

Error warning interrupt

CAN_IT_EPV

Error passive interrupt

CAN_IT_BOF

Bus-off interrupt

CAN_IT_LEC

Last error code interrupt

Definition at line 277 of file stm8s_can.h.

enum CAN_MasterCtrl_TypeDef

CAN Time Triggered Communication mode.

Enumerator:
CAN_MasterCtrl_AllDisabled

CAN ALL Master Control Option are DISABLED

CAN_MasterCtrl_AllEnabled

CAN ALL Master Control Option are DISABLED

CAN_MasterCtrl_TimeTriggerCOMMode

CAN Time Triggered Communication mode ENABLED

CAN_MasterCtrl_AutoBusOffManagement

CAN Auto Bus Off Management ENABLED

CAN_MasterCtrl_AutoWakeUpMode

CAN Automatic WakeUp Mode ENABLED , sleep mode is left automatically by hardware

CAN_MasterCtrl_NoAutoReTx

CAN Non Automatic Retransmission ENABLED, MSG will be transmitted only once

CAN_MasterCtrl_RxFifoLockedMode

CAN Recieve FIFO Locked against overrun ENABLED

CAN_MasterCtrl_TxFifoPriority

CAN Transmit FIFO Priority driven by the request order (not by the identifier of the MSG)

Definition at line 86 of file stm8s_can.h.

enum CAN_Mode_TypeDef

CAN mode options.

Enumerator:
CAN_Mode_Normal

normal mode

CAN_Mode_LoopBack

loopback mode

CAN_Mode_Silent

silent mode

CAN_Mode_Silent_LoopBack

loopback combined with silent mode

Definition at line 100 of file stm8s_can.h.

enum CAN_ModeStatus_TypeDef

CAN operating mode status.

Enumerator:
CAN_ModeStatus_Failed

CAN entring the specific mode failed

CAN_ModeStatus_Success

CAN entring the specific mode Succeed

Definition at line 77 of file stm8s_can.h.

enum CAN_NbrPendingMessage_TypeDef

CAN Pending Messages number.

Enumerator:
CAN_NbrPendingMessage_0

No Msg Pending

CAN_NbrPendingMessage_1

1 Msg Pending

CAN_NbrPendingMessage_2

2 Msg Pending

CAN_NbrPendingMessage_3

3 Msg Pending

Definition at line 199 of file stm8s_can.h.

enum CAN_OperatingMode_TypeDef

CAN operating mode.

Enumerator:
CAN_OperatingMode_Initialization

Initialization mode

CAN_OperatingMode_Normal

Normal mode

CAN_OperatingMode_Sleep

sleep mode

Definition at line 68 of file stm8s_can.h.

enum CAN_Page_TypeDef

CAN Page Mapping.

Enumerator:
CAN_Page_TxMailBox0

CAN TX mailbox 0 reg page

CAN_Page_TxMailBox1

CAN TX mailbox 1 reg page

CAN_Page_TxMailBox2

CAN TX mailbox 2 reg page

CAN_Page_Filter01

CAN Filters 0 & 1 reg page

CAN_Page_Filter23

CAN Filters 2 & 3 reg page

CAN_Page_Filter45

CAN Filters 4 & 5 reg page

CAN_Page_Config

CAN Configuration control/status reg page

CAN_Page_RxFifo

CAN RX FIFO registers page

Definition at line 43 of file stm8s_can.h.

enum CAN_RTR_TypeDef

CAN remote transmission request.

Enumerator:
CAN_RTR_Data

Data frame

CAN_RTR_Remote

Remote frame

Definition at line 217 of file stm8s_can.h.

enum CAN_Sleep_TypeDef

CAN sleep Status.

Enumerator:
CAN_Sleep_Failed

CAN did not enter the sleep mode

CAN_Sleep_Ok

CAN entered the sleep mode

Definition at line 239 of file stm8s_can.h.

enum CAN_ST7Compatibility_TypeDef

CAN ST7 Compatibility.

Enumerator:
CAN_ST7Compatibility_Enable

CAN is compatible with ST7 beCAN (only 2 mailboxes are availble)

CAN_ST7Compatibility_Disable

CAN is not compatible with ST7 beCAN ( 3 mailboxes are availble)

Definition at line 297 of file stm8s_can.h.

enum CAN_SynJumpWidth_TypeDef

CAN synchronisation jump width (SJW)

Enumerator:
CAN_SynJumpWidth_1TimeQuantum

1 time quantum

CAN_SynJumpWidth_2TimeQuantum

2 time quantum

CAN_SynJumpWidth_3TimeQuantum

3 time quantum

CAN_SynJumpWidth_4TimeQuantum

4 time quantum

Definition at line 110 of file stm8s_can.h.

enum CAN_TransmitMailBox_TypeDef

CAN Tx mailboxes.

Enumerator:
CAN_TransmitMailBox_0

CAN TX mailbox 0 reg page

CAN_TransmitMailBox_1

CAN TX mailbox 1 reg page

CAN_TransmitMailBox_2

CAN TX mailbox 2 reg page

Definition at line 190 of file stm8s_can.h.

enum CAN_TxStatus_TypeDef

CAN transmit Status.

Enumerator:
CAN_TxStatus_Failed

CAN transmission failed

CAN_TxStatus_Ok

CAN transmission succeeded

CAN_TxStatus_Pending

CAN transmission pending

CAN_TxStatus_NoMailBox

CAN cell did not provide an empty mailbox

CAN_TxStatus_MailBoxEmpty

CAN Tx mailbox is Empty

CAN_TxStatus_MailBox0Ok

CAN transmission succeeded by mail box 1

CAN_TxStatus_MailBox1Ok

CAN transmission succeeded by mail box 2

CAN_TxStatus_MailBox2Ok

CAN transmission succeeded by mail box 3

Definition at line 225 of file stm8s_can.h.

enum CAN_WakeUp_TypeDef

CAN wake up status.

Enumerator:
CAN_WakeUp_Failed

CAN did not leave the sleep mode

CAN_WakeUp_Ok

CAN leaved the sleep mode

Definition at line 246 of file stm8s_can.h.


STM8S/A Standard Peripherals Drivers: CAN_Private_Macros

Defines

CAN_Private_Macros

Defines

#define | CAN_IT_CONFIG_MASK ~(uint16_t)(CAN_IT_TME|CAN_IT_FMP|CAN_IT_FF|CAN_IT_FOV|CAN_IT_WKU|CAN_IT_EWG|CAN_IT_EPV|CAN_IT_BOF|CAN_IT_LEC|CAN_IT_ERR)
Macro used by the assert function in order to check the CAN Configuration interrupts.
#define | IS_CAN_BITSEG1_OK(BS1) ((BS1) <= CAN_BitSeg1_16TimeQuantum)
Macro used by the assert function in order to check time quantum in bit segment 1 .
#define | IS_CAN_BITSEG2_OK(BS2) ((((BS2) >= CAN_BitSeg2_2TimeQuantum) && ((BS2) <= CAN_BitSeg2_8TimeQuantum))|| ((BS2) == CAN_BitSeg2_1TimeQuantum))
Macro used by the assert function in order to check time quantum in bit segment 2.
#define | IS_CAN_DLC_OK(DLC) ((DLC) <= CAN_DLC_MAX)
Macro used by the assert function in order to check the DLC to be sent.
#define | IS_CAN_EXTID_OK(EXTID) ((EXTID) <= ((uint32_t)CAN_EXTID_SIZE))
Macro used by the assert function in order to check the Extended ID to be sent.
#define | IS_CAN_FILTER_MODE_OK(MODE)
Macro used by the assert function in order to check CAN filter mode.
#define | IS_CAN_FILTER_NUMBER_OK(NUMBER)
Macro used by the assert function in order to check CAN filter number.
#define | IS_CAN_FILTER_SCALE_OK(SCALE)
Macro used by the assert function in order to check CAN filter scale.
#define | IS_CAN_FLAG_CLEAR_OK(FLAG)
Macro used by the assert function in order to check CAN flags which can be cleared by CAN_ClearFlag.
#define | IS_CAN_FLAG_STATUS_OK(FLAG)
Macro used by the assert function in order to check CAN flags which can be got by CAN_GetFlagStatus.
#define | IS_CAN_IDTYPE_OK(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended))
Macro used by the assert function in order to check the type of the ID to be sent.
#define | IS_CAN_IT_CONFIG_OK(IT) (((IT) != 0x0000) && ((uint16_t)((uint16_t)(IT) & (uint16_t)CAN_IT_CONFIG_MASK) == 0x0000))
#define | IS_CAN_IT_PENDING_BIT_OK(IT)
Macro used by the assert function in order to check the CAN Pending bit interrupts.
#define | IS_CAN_IT_STATUS_OK(IT)
Macro used by the assert function in order to check the CAN status interrupts.
#define | IS_CAN_LAST_ERROR_CODE_OK(CODE) (((CODE) & 0x8F) == 0x00)
Macro used by the assert function in order to check the Last Error Code.
#define | IS_CAN_MASTERCTRL_OK(MODE)
Macro used by the assert function in order to check CAN Time Triggered Communication mode.
#define | IS_CAN_MODE_OK(MODE)
Macro used by the assert function in order to check CAN mode options .
#define | IS_CAN_OPERATINGMODE_OK(MODE)
Macro used by the assert function in order to check CAN operating mode.
#define | IS_CAN_PRESCALER_OK(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 64))
Macro used by the assert function in order to check CAN clock prescaler.
#define | IS_CAN_RTR_OK(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
Macro used by the assert function in order to check CAN transmission Frame Type.
#define | IS_CAN_ST7_COMPATIBILITY_OK(STATE) (((STATE) == CAN_ST7Compatibility_Enable) || ((STATE) == CAN_ST7Compatibility_Disable))
Macro used by the assert function in order to check the CAN ST7 Compatibility parameters.
#define | IS_CAN_STDID_OK(STDID) ((STDID) <= ((uint16_t)CAN_STDID_SIZE))
Macro used by the assert function in order to check the Standard ID to be sent.
#define | IS_CAN_SYNJUMPWIDTH_OK(SJW)
Macro used by the assert function in order to check the CAN synchronisation jump width (SJW).
#define | IS_CAN_TRANSMITMAILBOX_OK(TRANSMITMAILBOX)
Macro used by the assert function in order to check CAN Tx mailboxes.

Define Documentation

#define CAN_IT_CONFIG_MASK ~(uint16_t)(CAN_IT_TME|CAN_IT_FMP|CAN_IT_FF|CAN_IT_FOV|CAN_IT_WKU|CAN_IT_EWG|CAN_IT_EPV|CAN_IT_BOF|CAN_IT_LEC|CAN_IT_ERR)

Macro used by the assert function in order to check the CAN Configuration interrupts.

Definition at line 429 of file stm8s_can.h.

#define IS_CAN_BITSEG1_OK ( BS1 ) ((BS1) <= CAN_BitSeg1_16TimeQuantum)

Macro used by the assert function in order to check time quantum in bit segment 1 .

Definition at line 351 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_BITSEG2_OK ( BS2 ) ((((BS2) >= CAN_BitSeg2_2TimeQuantum) && ((BS2) <= CAN_BitSeg2_8TimeQuantum))|| ((BS2) == CAN_BitSeg2_1TimeQuantum))

Macro used by the assert function in order to check time quantum in bit segment 2.

Definition at line 355 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_DLC_OK ( DLC ) ((DLC) <= CAN_DLC_MAX)

Macro used by the assert function in order to check the DLC to be sent.

Definition at line 400 of file stm8s_can.h.

Referenced by CAN_GetReceivedData(), and CAN_Transmit().

#define IS_CAN_EXTID_OK ( EXTID ) ((EXTID) <= ((uint32_t)CAN_EXTID_SIZE))

Macro used by the assert function in order to check the Extended ID to be sent.

Definition at line 396 of file stm8s_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_FILTER_MODE_OK ( MODE )
Value:
(((MODE) == CAN_FilterMode_IdMask) || \
                                     ((MODE) == CAN_FilterMode_IdMask_IdList) || \
                                     ((MODE) == CAN_FilterMode_IdList_IdMask) || \
                                  ((MODE) == CAN_FilterMode_IdList))

Macro used by the assert function in order to check CAN filter mode.

Definition at line 372 of file stm8s_can.h.

Referenced by CAN_FilterInit().

#define IS_CAN_FILTER_NUMBER_OK ( NUMBER )
Value:
(((NUMBER) == CAN_FilterNumber_0) || \
                                       ((NUMBER) == CAN_FilterNumber_1) || \
                                       ((NUMBER) == CAN_FilterNumber_2) || \
                                       ((NUMBER) == CAN_FilterNumber_3) || \
                                       ((NUMBER) == CAN_FilterNumber_4) || \
                                       ((NUMBER) == CAN_FilterNumber_5))

Macro used by the assert function in order to check CAN filter number.

Definition at line 363 of file stm8s_can.h.

Referenced by CAN_FilterInit().

#define IS_CAN_FILTER_SCALE_OK ( SCALE )
Value:
(((SCALE) == CAN_FilterScale_8Bit)|| \
                                    ((SCALE) == CAN_FilterScale_16_8Bit) ||\
                                    ((SCALE) == CAN_FilterScale_16Bit  )||\
                                    ((SCALE) == CAN_FilterScale_32Bit))

Macro used by the assert function in order to check CAN filter scale.

Definition at line 379 of file stm8s_can.h.

Referenced by CAN_FilterInit().

#define IS_CAN_FLAG_CLEAR_OK ( FLAG )
Value:
(((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_RQCP1) ||\
                                    ((FLAG) == CAN_FLAG_RQCP2) ||  ((FLAG) == CAN_FLAG_FF)   ||\
                                    ((FLAG) == CAN_FLAG_FOV)  ||  ((FLAG) == CAN_FLAG_WKU) ||\
                                    ((FLAG) == CAN_FLAG_LEC))

Macro used by the assert function in order to check CAN flags which can be cleared by CAN_ClearFlag.

Definition at line 422 of file stm8s_can.h.

Referenced by CAN_ClearFlag().

#define IS_CAN_FLAG_STATUS_OK ( FLAG )
Value:
(((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_RQCP1) ||\
                                  ((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_FMP) ||\
                                  ((FLAG) == CAN_FLAG_FF) || ((FLAG) == CAN_FLAG_FOV) ||\
                                  ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_EWG) ||\
                                  ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_BOF) ||\
                                  ((FLAG) == CAN_FLAG_LEC))

Macro used by the assert function in order to check CAN flags which can be got by CAN_GetFlagStatus.

Definition at line 413 of file stm8s_can.h.

Referenced by CAN_GetFlagStatus().

#define IS_CAN_IDTYPE_OK ( IDTYPE ) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended))

Macro used by the assert function in order to check the type of the ID to be sent.

Definition at line 404 of file stm8s_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_IT_CONFIG_OK ( IT ) (((IT) != 0x0000) && ((uint16_t)((uint16_t)(IT) & (uint16_t)CAN_IT_CONFIG_MASK) == 0x0000))

Definition at line 430 of file stm8s_can.h.

Referenced by CAN_ITConfig().

#define IS_CAN_IT_PENDING_BIT_OK ( IT )
Value:
(((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF)  ||\
                                      ((IT) == CAN_IT_FOV)  || ((IT) == CAN_IT_WKU) ||\
                                      ((IT) == CAN_IT_ERR)  || ((IT) == CAN_IT_EWG) ||\
                                      ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)||\
                                      ((IT) == CAN_IT_LEC))

Macro used by the assert function in order to check the CAN Pending bit interrupts.

Definition at line 442 of file stm8s_can.h.

Referenced by CAN_ClearITPendingBit().

#define IS_CAN_IT_STATUS_OK ( IT )
Value:
(((IT) == CAN_IT_TME)   || ((IT) == CAN_IT_FMP) ||\
                             ((IT) == CAN_IT_FF)    || ((IT) == CAN_IT_FOV) || \
                             ((IT) == CAN_IT_WKU)   || ((IT) == CAN_IT_ERR)  || \
                             ((IT) == CAN_IT_EWG)   || ((IT) == CAN_IT_EPV)  || \
                             ((IT) == CAN_IT_BOF)   || ((IT) == CAN_IT_LEC)  )

Macro used by the assert function in order to check the CAN status interrupts.

Definition at line 434 of file stm8s_can.h.

Referenced by CAN_GetITStatus().

#define IS_CAN_LAST_ERROR_CODE_OK ( CODE ) (((CODE) & 0x8F) == 0x00)

Macro used by the assert function in order to check the Last Error Code.

Definition at line 450 of file stm8s_can.h.

#define IS_CAN_MASTERCTRL_OK ( MODE )
Value:
(((MODE) == CAN_MasterCtrl_AllDisabled) || \
                                    (((MODE) <= CAN_MasterCtrl_AllEnabled) && ((MODE) >= CAN_MasterCtrl_TxFifoPriority)))

Macro used by the assert function in order to check CAN Time Triggered Communication mode.

Definition at line 336 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_MODE_OK ( MODE )
Value:
(((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
                           ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))

Macro used by the assert function in order to check CAN mode options .

Definition at line 341 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_OPERATINGMODE_OK ( MODE )
Value:
(((MODE) == CAN_OperatingMode_Initialization) ||\
                                    ((MODE) == CAN_OperatingMode_Normal)|| \
                        ((MODE) == CAN_OperatingMode_Sleep))

Macro used by the assert function in order to check CAN operating mode.

Definition at line 330 of file stm8s_can.h.

Referenced by CAN_OperatingModeRequest().

#define IS_CAN_PRESCALER_OK ( PRESCALER ) (((PRESCALER) >= 1) && ((PRESCALER) <= 64))

Macro used by the assert function in order to check CAN clock prescaler.

Definition at line 359 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_RTR_OK ( RTR ) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))

Macro used by the assert function in order to check CAN transmission Frame Type.

Definition at line 408 of file stm8s_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_ST7_COMPATIBILITY_OK ( STATE ) (((STATE) == CAN_ST7Compatibility_Enable) || ((STATE) == CAN_ST7Compatibility_Disable))

Macro used by the assert function in order to check the CAN ST7 Compatibility parameters.

Definition at line 326 of file stm8s_can.h.

Referenced by CAN_ST7CompatibilityCmd().

#define IS_CAN_STDID_OK ( STDID ) ((STDID) <= ((uint16_t)CAN_STDID_SIZE))

Macro used by the assert function in order to check the Standard ID to be sent.

Definition at line 392 of file stm8s_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_SYNJUMPWIDTH_OK ( SJW )
Value:
(((SJW) == CAN_SynJumpWidth_1TimeQuantum) || ((SJW) == CAN_SynJumpWidth_2TimeQuantum)|| \
                         ((SJW) == CAN_SynJumpWidth_3TimeQuantum) || ((SJW) == CAN_SynJumpWidth_4TimeQuantum))

Macro used by the assert function in order to check the CAN synchronisation jump width (SJW).

Definition at line 346 of file stm8s_can.h.

Referenced by CAN_Init().

#define IS_CAN_TRANSMITMAILBOX_OK ( TRANSMITMAILBOX )
Value:
(((TRANSMITMAILBOX) == CAN_TransmitMailBox_0) || \
                                                 ((TRANSMITMAILBOX) == CAN_TransmitMailBox_1) || \
                                                 ((TRANSMITMAILBOX) == CAN_TransmitMailBox_2))

Macro used by the assert function in order to check CAN Tx mailboxes.

Definition at line 386 of file stm8s_can.h.

Referenced by CAN_CancelTransmit(), and CAN_TransmitStatus().


STM8S/A Standard Peripherals Drivers: CAN_Exported_Functions

Functions

CAN_Exported_Functions

Functions

void | CAN_CancelTransmit (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_FLAG_TypeDef CAN_Flag)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_IT_TypeDef CAN_IT)
Clears the CAN’s interrupt pending bits.
void | CAN_DeInit (void)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (void)
Releases the CAN FIFO.
void | CAN_FilterInit (CAN_FilterNumber_TypeDef CAN_FilterNumber, FunctionalState CAN_FilterActivation, CAN_FilterMode_TypeDef CAN_FilterMode, CAN_FilterScale_TypeDef CAN_FilterScale, uint8_t CAN_FilterID1, uint8_t CAN_FilterID2, uint8_t CAN_FilterID3, uint8_t CAN_FilterID4, uint8_t CAN_FilterIDMask1, uint8_t CAN_FilterIDMask2, uint8_t CAN_FilterIDMask3, uint8_t CAN_FilterIDMask4)
Initializes the CAN peripheral Filter according to the specified parameters.
FlagStatus | CAN_GetFlagStatus (CAN_FLAG_TypeDef CAN_Flag)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_IT_TypeDef CAN_IT)
Checks whether the specified CAN interrupt has occurred or not.
CAN_ErrorCode_TypeDef | CAN_GetLastErrorCode (void)
Gets the Last Error Code.
uint16_t | CAN_GetMessageTimeStamp (void)
Returns the Received time stamp.
uint8_t | CAN_GetReceivedData (uint8_t CAN_DataIndex)
Gets the CAN Data of the received message.
uint8_t | CAN_GetReceivedDLC (void)
Gets the CAN DLC of the received message.
uint8_t | CAN_GetReceivedFMI (void)
Gets the CAN FMI of the received message.
uint32_t | CAN_GetReceivedId (void)
Gets the CAN Id of the received message.
CAN_Id_TypeDef | CAN_GetReceivedIDE (void)
Gets the CAN IDE of the received message.
CAN_RTR_TypeDef | CAN_GetReceivedRTR (void)
Gets the CAN RTR of the received message.
CAN_Page_TypeDef | CAN_GetSelectedPage (void)
Gets the selected registers page.
CAN_InitStatus_TypeDef | CAN_Init (CAN_MasterCtrl_TypeDef CAN_MasterCtrl, CAN_Mode_TypeDef CAN_Mode, CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth, CAN_BitSeg1_TypeDef CAN_BitSeg1, CAN_BitSeg2_TypeDef CAN_BitSeg2, uint8_t CAN_Prescaler)
Initializes the CAN peripheral according to the specified parameters.
void | CAN_ITConfig (CAN_IT_TypeDef CAN_IT, FunctionalState NewState)
Enables or disables the specified CAN interrupts.
CAN_NbrPendingMessage_TypeDef | CAN_MessagePending (void)
Returns the number of pending messages.
CAN_ModeStatus_TypeDef | CAN_OperatingModeRequest (CAN_OperatingMode_TypeDef CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (void)
Receives a message which contains CAN Id, IDE, RTR DLC, datas and FMI number.
void | CAN_SelectPage (CAN_Page_TypeDef CAN_Page)
Sets the registers page to be selected.
CAN_Sleep_TypeDef | CAN_Sleep (void)
Enters the Sleep low power mode.
void | CAN_ST7CompatibilityCmd (CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)
Enables or Disables the ST7 CAN Compatibility.
CAN_TxStatus_TypeDef | CAN_Transmit (uint32_t CAN_Id, CAN_Id_TypeDef CAN_IDE, CAN_RTR_TypeDef CAN_RTR, uint8_t CAN_DLC, uint8_t *CAN_Data)
Initiates the transmission of a message.
CAN_TxStatus_TypeDef | CAN_TransmitStatus (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
CAN_WakeUp_TypeDef | CAN_WakeUp (void)
Wakes the CAN up.

Function Documentation

void CAN_CancelTransmit ( CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox )

Cancels a transmit request.

Parameters:
TransmitMailbox : the Transmission mailbox, can be one of CAN_TransmitMailBox_TypeDef
Return values:
None

Definition at line 718 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_MCSR_ABRQ, CAN_SelectPage(), and IS_CAN_TRANSMITMAILBOX_OK.

void CAN_ClearFlag ( CAN_FLAG_TypeDef CAN_Flag )

Clears the CAN's pending flags.

Parameters:
CAN_FLAG : Flag to be cleared, can be one of the following parameters: CAN_FLAG_RQCP0 Request MailBox0 Flag CAN_FLAG_RQCP1 Request MailBox1 Flag CAN_FLAG_RQCP2 Request MailBox2 Flag CAN_FLAG_FF FIFO Full Flag CAN_FLAG_FOV FIFO Overrun Flag CAN_FLAG_WKU wake up Flag CAN_FLAG_LEC Last error code Flag
Return values:
None

Definition at line 1073 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), IS_CAN_FLAG_CLEAR_OK, and RESET.

void CAN_ClearITPendingBit ( CAN_IT_TypeDef CAN_IT )

Clears the CAN’s interrupt pending bits.

Parameters:
CAN_IT,: specifies the interrupt pending bit to clear, can be one of the following parameters: CAN_IT_TME = Transmit mailbox empty interrupt CAN_IT_FF =FIFO full interrupt CAN_IT_FOV =FIFO overrun interrupt CAN_IT_WKU =Wake-up interrupt CAN_IT_ERR =General Error interrupt CAN_IT_EWG =Error warning interrupt CAN_IT_EPV =Error passive interrupt CAN_IT_BOF = Bus-off interrupt CAN_IT_LEC =Last error code interrupt
Return values:
None

Definition at line 1344 of file stm8s_can.c.

References CAN_ESR_RESET_VALUE, CAN_GetSelectedPage(), CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF, CAN_IT_FOV, CAN_IT_LEC, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_ERRI, CAN_MSR_WKUI, CAN_Page_Config, CAN_RFR_FOVR, CAN_RFR_FULL, CAN_SelectPage(), CAN_TSR_RQCP012, and IS_CAN_IT_PENDING_BIT_OK.

void CAN_DeInit ( void )

Deinitializes the CAN peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 56 of file stm8s_can.c.

References CAN_BTR1_RESET_VALUE, CAN_BTR2_RESET_VALUE, CAN_DGR_RESET_VALUE, CAN_EIER_RESET_VALUE, CAN_ESR_RESET_VALUE, CAN_FCR_RESET_VALUE, CAN_FMR1_RESET_VALUE, CAN_FMR2_RESET_VALUE, CAN_IER_RESET_VALUE, CAN_MCR_INRQ, CAN_MCR_RESET_VALUE, CAN_MDLC_RESET_VALUE, CAN_MSR_RESET_VALUE, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingModeRequest(), CAN_Page_Config, CAN_Page_RxFifo, CAN_Page_TxMailBox0, CAN_Page_TxMailBox1, CAN_Page_TxMailBox2, CAN_PSR_RESET_VALUE, CAN_RFR_RESET_VALUE, and CAN_TSR_RESET_VALUE.

void CAN_FIFORelease ( void )

Releases the CAN FIFO.

Parameters:
None
Return values:
None

Definition at line 736 of file stm8s_can.c.

References CAN_RFR_RFOM.

Referenced by CAN_Receive().

void CAN_FilterInit | ( | CAN_FilterNumber_TypeDef | CAN_FilterNumber,
 |  | FunctionalState | CAN_FilterActivation,
 |  | CAN_FilterMode_TypeDef | CAN_FilterMode,
 |  | CAN_FilterScale_TypeDef | CAN_FilterScale,
 |  | uint8_t | CAN_FilterID1,
 |  | uint8_t | CAN_FilterID2,
 |  | uint8_t | CAN_FilterID3,
 |  | uint8_t | CAN_FilterID4,
 |  | uint8_t | CAN_FilterIDMask1,
 |  | uint8_t | CAN_FilterIDMask2,
 |  | uint8_t | CAN_FilterIDMask3,
 |  | uint8_t | CAN_FilterIDMask4
 | ) |  |

Initializes the CAN peripheral Filter according to the specified parameters.

Parameters:
CAN_FilterNumber | : CAN Filter number , can be one of CAN_FilterNumber_TypeDef
CAN_FilterActivation | : CAN Filter Activation state , can be one of FunctionalState
CAN_FilterMode | : CAN Filter Mode , can be one of CAN_FilterMode_TypeDef
CAN_FilterScale | : CAN Filter Scale , can be one of CAN_FilterScale_TypeDef
CAN_FilterID1 | : CAN Filter ID 1 , can be a value from 0x00 to 0xFF
CAN_FilterID2 | : CAN Filter ID 2 , can be a value from 0x00 to 0xFF
CAN_FilterID3 | : CAN Filter ID 3 , can be a value from 0x00 to 0xFF
CAN_FilterID4 | : CAN Filter ID 4 , can be a value from 0x00 to 0xFF
CAN_FilterIDMask1 | : CAN Filter ID 1/ Mask 1 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask2 | : CAN Filter ID 2/ Mask 2 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask3 | : CAN Filter ID 3/ Mask 3 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
CAN_FilterIDMask4 | : CAN Filter ID 4/ Mask 4 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
Return values:
None

Definition at line 188 of file stm8s_can.c.

References CAN_FCR1_FSC00, CAN_FCR1_FSC01, CAN_FilterMode_IdList, CAN_FilterMode_IdList_IdMask, CAN_FilterMode_IdMask, CAN_FilterNumber_0, CAN_FilterNumber_1, CAN_FilterNumber_2, CAN_FilterNumber_3, CAN_FilterNumber_4, CAN_FilterScale_16_8Bit, CAN_FilterScale_16Bit, CAN_FilterScale_32Bit, CAN_FilterScale_8Bit, CAN_GetSelectedPage(), CAN_IDLIST_IDMASK_MASK, CAN_IDMASK_IDLIST_MASK, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingModeRequest(), CAN_Page_Config, CAN_Page_Filter01, CAN_Page_Filter23, CAN_Page_Filter45, CAN_SelectPage(), DISABLE, IS_CAN_FILTER_MODE_OK, IS_CAN_FILTER_NUMBER_OK, IS_CAN_FILTER_SCALE_OK, and IS_FUNCTIONALSTATE_OK.

FlagStatus CAN_GetFlagStatus ( CAN_FLAG_TypeDef CAN_Flag )

Checks whether the specified CAN flag is set or not.

Parameters:
CAN_FLAG,: specifies the flag to check, can be one of CAN_FLAG_TypeDef enumeration.
Return values:
The new state of CAN_FLAG which can be one of FlagStatus.

Definition at line 1115 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), IS_CAN_FLAG_STATUS_OK, RESET, and SET.

ITStatus CAN_GetITStatus ( CAN_IT_TypeDef CAN_IT )

Checks whether the specified CAN interrupt has occurred or not.

Parameters:
CAN_IT,: specifies the CAN interrupt source to check, can be one of CAN_IT_TypeDef.
Return values:
The new state of CAN_IT, which can be one of ITStatus.

Definition at line 1199 of file stm8s_can.c.

References CAN_EIER_BOFIE, CAN_EIER_EPVIE, CAN_EIER_ERRIE, CAN_EIER_EWGIE, CAN_EIER_LECIE, CAN_ESR_BOFF, CAN_ESR_EPVF, CAN_ESR_EWGF, CAN_ESR_LEC, CAN_GetSelectedPage(), CAN_IER_FFIE, CAN_IER_FMPIE, CAN_IER_FOVIE, CAN_IER_TMEIE, CAN_IER_WKUIE, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF, CAN_IT_FMP, CAN_IT_FOV, CAN_IT_LEC, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_WKUI, CAN_Page_Config, CAN_RFR_FMP01, CAN_RFR_FOVR, CAN_RFR_FULL, CAN_SelectPage(), CAN_TSR_RQCP012, CheckITStatus(), IS_CAN_IT_STATUS_OK, and RESET.

CAN_ErrorCode_TypeDef CAN_GetLastErrorCode ( void )

Gets the Last Error Code.

Parameters:
None
Return values:
Error Code.

Definition at line 1047 of file stm8s_can.c.

References CAN_ErrorCode_NoErr, CAN_ESR_LEC, CAN_GetSelectedPage(), CAN_Page_Config, and CAN_SelectPage().

uint16_t CAN_GetMessageTimeStamp ( void )

Returns the Received time stamp.

Parameters:
None
Return values:
uint16_t the received time stamp.

Definition at line 896 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_RxFifo, and CAN_SelectPage().

uint8_t CAN_GetReceivedData ( uint8_t CAN_DataIndex )

Gets the CAN Data of the received message.

Parameters:
CAN_DataIndexe : number of the received Data, it can be an integer between 0 to 7.
Return values:
the received CAN message ith Data.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 872 of file stm8s_can.c.

References _Data, and IS_CAN_DLC_OK.

uint8_t CAN_GetReceivedDLC ( void )

Gets the CAN DLC of the received message.

Parameters:
None
Return values:
the received CAN message DLC.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 858 of file stm8s_can.c.

References _DLC.

uint8_t CAN_GetReceivedFMI ( void )

Gets the CAN FMI of the received message.

Parameters:
None
Return values:
the received CAN message FMI.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 886 of file stm8s_can.c.

References _FMI.

uint32_t CAN_GetReceivedId ( void )

Gets the CAN Id of the received message.

Parameters:
None
Return values:
the received CAN message Id.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 819 of file stm8s_can.c.

References _Id.

CAN_Id_TypeDef CAN_GetReceivedIDE ( void )

Gets the CAN IDE of the received message.

Parameters:
None
Return values:
the received CAN message IDE.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 832 of file stm8s_can.c.

References _IDE.

CAN_RTR_TypeDef CAN_GetReceivedRTR ( void )

Gets the CAN RTR of the received message.

Parameters:
None
Return values:
the received CAN message RTR.
Required preconditions:
This function is used to get data loaded by CAN_Receive function. Before using this function, CAN_Receive function must be called.

Definition at line 845 of file stm8s_can.c.

References _RTR.

CAN_Page_TypeDef CAN_GetSelectedPage ( void )

Gets the selected registers page.

Parameters:
None
Return values:
the selected page which can be one of the CAN_Page_TypeDef.

Definition at line 1405 of file stm8s_can.c.

Referenced by CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_FilterInit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetMessageTimeStamp(), CAN_Init(), CAN_ITConfig(), CAN_Receive(), CAN_Transmit(), and CAN_TTComModeCmd().

CAN_InitStatus_TypeDef CAN_Init | ( | CAN_MasterCtrl_TypeDef | CAN_MasterCtrl,
 |  | CAN_Mode_TypeDef | CAN_Mode,
 |  | CAN_SynJumpWidth_TypeDef | CAN_SynJumpWidth,
 |  | CAN_BitSeg1_TypeDef | CAN_BitSeg1,
 |  | CAN_BitSeg2_TypeDef | CAN_BitSeg2,
 |  | uint8_t | CAN_Prescaler
 | ) |  |

Initializes the CAN peripheral according to the specified parameters.

Parameters:
CAN_MasterCtrl | : Master control option, can be one or a combination of CAN_MasterCtrl_TypeDef.
CAN_Mode | : CAN mode , can be one of CAN_Mode_TypeDef.
CAN_SynJumpWidth | : CAN Synchronisation Jump Width , can be one of CAN_SynJumpWidth_TypeDef.
CAN_BitSeg1 | : CAN bit segment 1 , can be one of CAN_BitSeg1_TypeDef.
CAN_BitSeg2 | : CAN bit segment 2 , can be one of CAN_BitSeg2_TypeDef.
CAN_Prescaler | : CAN Baud Rate Prescaler , can be a value from 0x01 to 0xFF.
Return values:
Indicates if initialization is succeed. it can be one of CAN_InitStatus_TypeDef enumeration.

Definition at line 100 of file stm8s_can.c.

References CAN_ACKNOWLEDGE_TIMEOUT, CAN_GetSelectedPage(), CAN_InitStatus_Failed, CAN_InitStatus_Success, CAN_MCR_INRQ, CAN_MSR_INAK, CAN_Page_Config, CAN_SelectPage(), IS_CAN_BITSEG1_OK, IS_CAN_BITSEG2_OK, IS_CAN_MASTERCTRL_OK, IS_CAN_MODE_OK, IS_CAN_PRESCALER_OK, and IS_CAN_SYNJUMPWIDTH_OK.

void CAN_ITConfig | ( | CAN_IT_TypeDef | CAN_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified CAN interrupts.

Parameters:
CAN_IT,: specifies the CAN interrupt sources to be enabled or disabled.
NewState : CAN_IT new state , can be one of FunctionalState
Return values:
None

Definition at line 481 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_Page_Config, CAN_SelectPage(), DISABLE, IS_CAN_IT_CONFIG_OK, and IS_FUNCTIONALSTATE_OK.

CAN_NbrPendingMessage_TypeDef CAN_MessagePending ( void )

Returns the number of pending messages.

Return values:
Number of pending messages.

Definition at line 746 of file stm8s_can.c.

References CAN_NbrPendingMessage_0, and CAN_RFR_FMP01.

CAN_ModeStatus_TypeDef CAN_OperatingModeRequest ( CAN_OperatingMode_TypeDef CAN_OperatingMode )

Select the CAN Operation mode.

Parameters:
CAN_OperatingMode CAN Operating Mode , this parameter can be one of CAN_OperatingMode_TypeDef enumeration.
Return values:
the status of the requested mode which can be

  • CAN_ModeStatus_Failed CAN failed entring the specific mode
  • CAN_ModeStatus_Success CAN Succeed entring the specific mode

Definition at line 969 of file stm8s_can.c.

References CAN_ACKNOWLEDGE_TIMEOUT, CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MODE_MASK, CAN_ModeStatus_Failed, CAN_ModeStatus_Success, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingMode_Sleep, and IS_CAN_OPERATINGMODE_OK.

Referenced by CAN_DeInit(), and CAN_FilterInit().

void CAN_Receive ( void )

Receives a message which contains CAN Id, IDE, RTR DLC, datas and FMI number.

In order to get these data, use CAN_GetReceivedId(), CAN_GetReceivedIDE(), CAN_GetReceivedRTR(), CAN_GetReceivedDLC(), CAN_GetReceivedFMI() and CAN_GetReceivedData() functions.

Parameters:
None
Return values:
None

Definition at line 761 of file stm8s_can.c.

References _Data, _DLC, _FMI, _Id, _IDE, _RTR, CAN_EXTID_SIZE, CAN_FIFORelease(), CAN_GetSelectedPage(), CAN_Id_Extended, CAN_Id_Standard, CAN_Page_RxFifo, CAN_SelectPage(), and CAN_STDID_SIZE.

void CAN_SelectPage ( CAN_Page_TypeDef CAN_Page )

Sets the registers page to be selected.

Parameters:
the selected page which can be one of the CAN_Page_TypeDef.
Return values:
None

Definition at line 1415 of file stm8s_can.c.

Referenced by CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_FilterInit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetMessageTimeStamp(), CAN_Init(), CAN_ITConfig(), CAN_Receive(), CAN_Transmit(), and CAN_TTComModeCmd().

CAN_Sleep_TypeDef CAN_Sleep ( void )

Enters the Sleep low power mode.

Parameters:
None
Return values:
CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an other case.

Definition at line 918 of file stm8s_can.c.

References CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_Sleep_Failed, and CAN_Sleep_Ok.

void CAN_ST7CompatibilityCmd ( CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility )

Enables or Disables the ST7 CAN Compatibility.

if the ST7 compatibility is Enabled, CAN provides only 2 mailboxes. if the ST7 compatibility is Disabled, CAN provides 3 mailboxes.

Parameters:
CAN_ST7Compatibility : CAN ST7 Compatibility , this parameter can be one of CAN_ST7Compatibility_TypeDef enumeration.
Return values:
None

Definition at line 519 of file stm8s_can.c.

References CAN_DGR_TXM2E, and IS_CAN_ST7_COMPATIBILITY_OK.

CAN_TxStatus_TypeDef CAN_Transmit | ( | uint32_t | CAN_Id,
 |  | CAN_Id_TypeDef | CAN_IDE,
 |  | CAN_RTR_TypeDef | CAN_RTR,
 |  | uint8_t | CAN_DLC,
 |  | uint8_t * | CAN_Data
 | ) |  |

Initiates the transmission of a message.

Parameters:
CAN_Id | the ID number of the message, its size depends on CAN_IDE value.
[in] | CAN_IDE | the ID type of the message, this parameter can be one of the CAN_Id_TypeDef enumeration.
[in] | CAN_RTR | the message type, this parameter can be one of the CAN_RTR_TypeDef enumeration.
[in] | CAN_DLC | the number of data in the message type, this parameter can be a value between 0 to 7.
[in] | CAN_Data | pointer to a the uint8_t table which contains data to sent.
Return values:
Transmit Status, this returned value can be one of the CAN_TxStatus_TypeDef enumeration.

Definition at line 581 of file stm8s_can.c.

References CAN_EXTID_SIZE, CAN_GetSelectedPage(), CAN_Id_Standard, CAN_MCSR_TXRQ, CAN_SelectPage(), CAN_STDID_SIZE, CAN_TPR_TME0, CAN_TPR_TME1, CAN_TPR_TME2, CAN_TxStatus_MailBox0Ok, CAN_TxStatus_MailBox1Ok, CAN_TxStatus_MailBox2Ok, CAN_TxStatus_NoMailBox, IS_CAN_DLC_OK, IS_CAN_EXTID_OK, IS_CAN_IDTYPE_OK, IS_CAN_RTR_OK, and IS_CAN_STDID_OK.

CAN_TxStatus_TypeDef CAN_TransmitStatus ( CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox )

Checks the transmission of a message.

Parameters:
TransmitMailbox,: the number of the mailbox that is used for transmission, can be on of CAN_TransmitMailBox_TypeDef.
Return values:
CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.

Definition at line 666 of file stm8s_can.c.

References CAN_TPR_TME0, CAN_TPR_TME1, CAN_TPR_TME2, CAN_TransmitMailBox_0, CAN_TransmitMailBox_1, CAN_TransmitMailBox_2, CAN_TSR_RQCP0, CAN_TSR_RQCP1, CAN_TSR_RQCP2, CAN_TSR_TXOK0, CAN_TSR_TXOK1, CAN_TSR_TXOK2, CAN_TxStatus_Failed, CAN_TxStatus_MailBoxEmpty, CAN_TxStatus_Ok, CAN_TxStatus_Pending, and IS_CAN_TRANSMITMAILBOX_OK.

void CAN_TTComModeCmd ( FunctionalState NewState )

Enables or disables the CAN Time TriggerOperation communication mode.

Parameters:
NewState : Mode new state , can be one of FunctionalState
Return values:
None

Definition at line 535 of file stm8s_can.c.

References CAN_GetSelectedPage(), CAN_MCR_TTCM, CAN_MDLCR_TGT, CAN_Page_RxFifo, CAN_Page_TxMailBox0, CAN_Page_TxMailBox1, CAN_Page_TxMailBox2, CAN_SelectPage(), DISABLE, and IS_FUNCTIONALSTATE_OK.

CAN_WakeUp_TypeDef CAN_WakeUp ( void )

Wakes the CAN up.

Parameters:
None
Return values:
CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an other case.

Definition at line 942 of file stm8s_can.c.

References CAN_MCR_SLEEP, CAN_MSR_SLAK, CAN_WakeUp_Failed, and CAN_WakeUp_Ok.


STM8S/A Standard Peripherals Drivers: CLK_Exported_Types

Enumerations

CLK_Exported_Types

Enumerations

enum | CLK_CSSConfig_TypeDef { CLK_CSSCONFIG_ENABLEWITHIT = (uint8_t)0x05, CLK_CSSCONFIG_ENABLE = (uint8_t)0x01, CLK_CSSCONFIG_DISABLE = (uint8_t)0x00 }

Clock security system configuration.

More...
enum | CLK_CurrentClockState_TypeDef { CLK_CURRENTCLOCKSTATE_DISABLE = (uint8_t)0x00, CLK_CURRENTCLOCKSTATE_ENABLE = (uint8_t)0x01 }

Current Clock State.

More...
enum CLK_Flag_TypeDef {
CLK_FLAG_LSIRDY = (uint16_t)0x0110, CLK_FLAG_HSIRDY = (uint16_t)0x0102, CLK_FLAG_HSERDY = (uint16_t)0x0202, CLK_FLAG_SWIF = (uint16_t)0x0308,
CLK_FLAG_SWBSY = (uint16_t)0x0301, CLK_FLAG_CSSD = (uint16_t)0x0408, CLK_FLAG_AUX = (uint16_t)0x0402, CLK_FLAG_CCOBSY = (uint16_t)0x0504,
CLK_FLAG_CCORDY = (uint16_t)0x0502
}

CLK Flags.

More...
enum CLK_HSITrimValue_TypeDef {
CLK_HSITRIMVALUE_0 = (uint8_t)0x00, CLK_HSITRIMVALUE_1 = (uint8_t)0x01, CLK_HSITRIMVALUE_2 = (uint8_t)0x02, CLK_HSITRIMVALUE_3 = (uint8_t)0x03,
CLK_HSITRIMVALUE_4 = (uint8_t)0x04, CLK_HSITRIMVALUE_5 = (uint8_t)0x05, CLK_HSITRIMVALUE_6 = (uint8_t)0x06, CLK_HSITRIMVALUE_7 = (uint8_t)0x07
}

CLK HSI Calibration Value.

More...
enum | CLK_IT_TypeDef { CLK_IT_CSSD = (uint8_t)0x0C, CLK_IT_SWIF = (uint8_t)0x1C }

CLK interrupt configuration and Flags cleared by software.

More...
enum CLK_Output_TypeDef {
CLK_OUTPUT_HSI = (uint8_t)0x00, CLK_OUTPUT_LSI = (uint8_t)0x02, CLK_OUTPUT_HSE = (uint8_t)0x04, CLK_OUTPUT_CPU = (uint8_t)0x08,
CLK_OUTPUT_CPUDIV2 = (uint8_t)0x0A, CLK_OUTPUT_CPUDIV4 = (uint8_t)0x0C, CLK_OUTPUT_CPUDIV8 = (uint8_t)0x0E, CLK_OUTPUT_CPUDIV16 = (uint8_t)0x10,
CLK_OUTPUT_CPUDIV32 = (uint8_t)0x12, CLK_OUTPUT_CPUDIV64 = (uint8_t)0x14, CLK_OUTPUT_HSIRC = (uint8_t)0x16, CLK_OUTPUT_MASTER = (uint8_t)0x18,
CLK_OUTPUT_OTHERS = (uint8_t)0x1A
}

CLK Clock Output.

More...
enum CLK_Peripheral_TypeDef {
CLK_PERIPHERAL_I2C = (uint8_t)0x00, CLK_PERIPHERAL_SPI = (uint8_t)0x01, CLK_PERIPHERAL_UART1 = (uint8_t)0x03, CLK_PERIPHERAL_UART2 = (uint8_t)0x03,
CLK_PERIPHERAL_UART3 = (uint8_t)0x03, CLK_PERIPHERAL_TIMER6 = (uint8_t)0x04, CLK_PERIPHERAL_TIMER4 = (uint8_t)0x04, CLK_PERIPHERAL_TIMER5 = (uint8_t)0x05,
CLK_PERIPHERAL_TIMER2 = (uint8_t)0x05, CLK_PERIPHERAL_TIMER3 = (uint8_t)0x06, CLK_PERIPHERAL_TIMER1 = (uint8_t)0x07, CLK_PERIPHERAL_AWU = (uint8_t)0x12,
CLK_PERIPHERAL_ADC = (uint8_t)0x13, CLK_PERIPHERAL_CAN = (uint8_t)0x17
}

CLK Enable peripheral.

More...
enum CLK_Prescaler_TypeDef {
CLK_PRESCALER_HSIDIV1 = (uint8_t)0x00, CLK_PRESCALER_HSIDIV2 = (uint8_t)0x08, CLK_PRESCALER_HSIDIV4 = (uint8_t)0x10, CLK_PRESCALER_HSIDIV8 = (uint8_t)0x18,
CLK_PRESCALER_CPUDIV1 = (uint8_t)0x80, CLK_PRESCALER_CPUDIV2 = (uint8_t)0x81, CLK_PRESCALER_CPUDIV4 = (uint8_t)0x82, CLK_PRESCALER_CPUDIV8 = (uint8_t)0x83,
CLK_PRESCALER_CPUDIV16 = (uint8_t)0x84, CLK_PRESCALER_CPUDIV32 = (uint8_t)0x85, CLK_PRESCALER_CPUDIV64 = (uint8_t)0x86, CLK_PRESCALER_CPUDIV128 = (uint8_t)0x87
}

CLK Clock Divisor.

More...
enum | CLK_Source_TypeDef { CLK_SOURCE_HSI = (uint8_t)0xE1, CLK_SOURCE_LSI = (uint8_t)0xD2, CLK_SOURCE_HSE = (uint8_t)0xB4 }

CLK Clock Source.

More...
enum | CLK_SWIMDivider_TypeDef { CLK_SWIMDIVIDER_2 = (uint8_t)0x00, CLK_SWIMDIVIDER_OTHER = (uint8_t)0x01 }

SWIM Clock divider.

More...
enum | CLK_SwitchMode_TypeDef { CLK_SWITCHMODE_MANUAL = (uint8_t)0x00, CLK_SWITCHMODE_AUTO = (uint8_t)0x01 }

Switch Mode Auto, Manual.

More...

Enumeration Type Documentation

enum CLK_CSSConfig_TypeDef

Clock security system configuration.

Enumerator:
CLK_CSSCONFIG_ENABLEWITHIT

Enable CSS with detection interrupt

CLK_CSSCONFIG_ENABLE

Enable CSS without detection interrupt

CLK_CSSCONFIG_DISABLE

Leave CSS desactivated (to be used in CLK_Init() function)

Definition at line 55 of file stm8s_clk.h.

enum CLK_CurrentClockState_TypeDef

Current Clock State.

Enumerator:
CLK_CURRENTCLOCKSTATE_DISABLE

Current clock disable

CLK_CURRENTCLOCKSTATE_ENABLE

Current clock enable

Definition at line 47 of file stm8s_clk.h.

enum CLK_Flag_TypeDef

CLK Flags.

Enumerator:
CLK_FLAG_LSIRDY

Low speed internal oscillator ready Flag

CLK_FLAG_HSIRDY

High speed internal oscillator ready Flag

CLK_FLAG_HSERDY

High speed external oscillator ready Flag

CLK_FLAG_SWIF

Clock switch interrupt Flag

CLK_FLAG_SWBSY

Switch busy Flag

CLK_FLAG_CSSD

Clock security system detection Flag

CLK_FLAG_AUX

Auxiliary oscillator connected to master clock

CLK_FLAG_CCOBSY

Configurable clock output busy

CLK_FLAG_CCORDY

Configurable clock output ready

Definition at line 145 of file stm8s_clk.h.

enum CLK_HSITrimValue_TypeDef

CLK HSI Calibration Value.

Enumerator:
CLK_HSITRIMVALUE_0

HSI Calibtation Value 0

CLK_HSITRIMVALUE_1

HSI Calibtation Value 1

CLK_HSITRIMVALUE_2

HSI Calibtation Value 2

CLK_HSITRIMVALUE_3

HSI Calibtation Value 3

CLK_HSITRIMVALUE_4

HSI Calibtation Value 4

CLK_HSITRIMVALUE_5

HSI Calibtation Value 5

CLK_HSITRIMVALUE_6

HSI Calibtation Value 6

CLK_HSITRIMVALUE_7

HSI Calibtation Value 7

Definition at line 73 of file stm8s_clk.h.

enum CLK_IT_TypeDef

CLK interrupt configuration and Flags cleared by software.

Enumerator:
CLK_IT_CSSD

Clock security system detection Flag

CLK_IT_SWIF

Clock switch interrupt Flag

Definition at line 161 of file stm8s_clk.h.

enum CLK_Output_TypeDef

CLK Clock Output.

Enumerator:
CLK_OUTPUT_HSI

Clock Output HSI

CLK_OUTPUT_LSI

Clock Output LSI

CLK_OUTPUT_HSE

Clock Output HSE

CLK_OUTPUT_CPU

Clock Output CPU

CLK_OUTPUT_CPUDIV2

Clock Output CPU/2

CLK_OUTPUT_CPUDIV4

Clock Output CPU/4

CLK_OUTPUT_CPUDIV8

Clock Output CPU/8

CLK_OUTPUT_CPUDIV16

Clock Output CPU/16

CLK_OUTPUT_CPUDIV32

Clock Output CPU/32

CLK_OUTPUT_CPUDIV64

Clock Output CPU/64

CLK_OUTPUT_HSIRC

Clock Output HSI RC

CLK_OUTPUT_MASTER

Clock Output Master

CLK_OUTPUT_OTHERS

Clock Output OTHER

Definition at line 87 of file stm8s_clk.h.

enum CLK_Peripheral_TypeDef

CLK Enable peripheral.

Enumerator:
CLK_PERIPHERAL_I2C

Peripheral Clock Enable 1, I2C

CLK_PERIPHERAL_SPI

Peripheral Clock Enable 1, SPI

CLK_PERIPHERAL_UART1

Peripheral Clock Enable 1, UART1

CLK_PERIPHERAL_UART2

Peripheral Clock Enable 1, UART2

CLK_PERIPHERAL_UART3

Peripheral Clock Enable 1, UART3

CLK_PERIPHERAL_TIMER6

Peripheral Clock Enable 1, Timer6

CLK_PERIPHERAL_TIMER4

Peripheral Clock Enable 1, Timer4

CLK_PERIPHERAL_TIMER5

Peripheral Clock Enable 1, Timer5

CLK_PERIPHERAL_TIMER2

Peripheral Clock Enable 1, Timer2

CLK_PERIPHERAL_TIMER3

Peripheral Clock Enable 1, Timer3

CLK_PERIPHERAL_TIMER1

Peripheral Clock Enable 1, Timer1

CLK_PERIPHERAL_AWU

Peripheral Clock Enable 2, AWU

CLK_PERIPHERAL_ADC

Peripheral Clock Enable 2, ADC

CLK_PERIPHERAL_CAN

Peripheral Clock Enable 2, CAN

Definition at line 112 of file stm8s_clk.h.

enum CLK_Prescaler_TypeDef

CLK Clock Divisor.

Enumerator:
CLK_PRESCALER_HSIDIV1

High speed internal clock prescaler: 1

CLK_PRESCALER_HSIDIV2

High speed internal clock prescaler: 2

CLK_PRESCALER_HSIDIV4

High speed internal clock prescaler: 4

CLK_PRESCALER_HSIDIV8

High speed internal clock prescaler: 8

CLK_PRESCALER_CPUDIV1

CPU clock division factors 1

CLK_PRESCALER_CPUDIV2

CPU clock division factors 2

CLK_PRESCALER_CPUDIV4

CPU clock division factors 4

CLK_PRESCALER_CPUDIV8

CPU clock division factors 8

CLK_PRESCALER_CPUDIV16

CPU clock division factors 16

CLK_PRESCALER_CPUDIV32

CPU clock division factors 32

CLK_PRESCALER_CPUDIV64

CPU clock division factors 64

CLK_PRESCALER_CPUDIV128

CPU clock division factors 128

Definition at line 174 of file stm8s_clk.h.

enum CLK_Source_TypeDef

CLK Clock Source.

Enumerator:
CLK_SOURCE_HSI

Clock Source HSI.

CLK_SOURCE_LSI

Clock Source LSI.

CLK_SOURCE_HSE

Clock Source HSE.

Definition at line 64 of file stm8s_clk.h.

enum CLK_SWIMDivider_TypeDef

SWIM Clock divider.

Enumerator:
CLK_SWIMDIVIDER_2

SWIM clock is divided by 2

CLK_SWIMDIVIDER_OTHER

SWIM clock is not divided by 2

Definition at line 192 of file stm8s_clk.h.

enum CLK_SwitchMode_TypeDef

Switch Mode Auto, Manual.

Enumerator:
CLK_SWITCHMODE_MANUAL

Enable the manual clock switching mode

CLK_SWITCHMODE_AUTO

Enable the automatic clock switching mode

Definition at line 39 of file stm8s_clk.h.


STM8S/A Standard Peripherals Drivers: CLK_Exported_Constants

Defines

CLK_Exported_Constants

Defines

#define CLK_TIMEOUT ((uint16_t)0x491)

Define Documentation

#define CLK_TIMEOUT ((uint16_t)0x491)

Timeout for the clock switch operation.

Definition at line 206 of file stm8s_clk.h.

Referenced by CLK_ClockSwitchConfig().


STM8S/A Standard Peripherals Drivers: CLK_Private_Macros

Defines

CLK_Private_Macros

Defines

#define | IS_CLK_CSSCONFIG_OK(CSSVALUE)
Macros used by the assert function in order to check the CSS configuration.
#define | IS_CLK_CURRENTCLOCKSTATE_OK(STATE)
Macros used by the assert function in order to check the current clock state.
#define | IS_CLK_FLAG_OK(FLAG)
Macros used by the assert function in order to check the different clock flags.
#define | IS_CLK_HSIPRESCALER_OK(PRESCALER)
Macros used by the assert function in order to check the different HSI prescaler values.
#define | IS_CLK_HSITRIMVALUE_OK(TRIMVALUE)
Macros used by the assert function in order to check the different HSI trimming values.
#define | IS_CLK_IT_OK(IT) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF))
Macros used by the assert function in order to check the different clock IT pending bits.
#define | IS_CLK_OUTPUT_OK(OUTPUT)
Macros used by the assert function in order to check the different clocks to output.
#define | IS_CLK_PERIPHERAL_OK(PERIPHERAL)
Macros used by the assert function in order to check the different peripheral's clock.
#define | IS_CLK_PRESCALER_OK(PRESCALER)
Macros used by the assert function in order to check the different clock prescaler values.
#define | IS_CLK_SOURCE_OK(SOURCE)
Macros used by the assert function in order to check the different clock sources.
#define | IS_CLK_SWIMDIVIDER_OK(SWIMDIVIDER) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER))
Macros used by the assert function in order to check the different SWIM dividers values.
#define | IS_CLK_SWITCHMODE_OK(MODE) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO))
Macros used by the assert function in order to check the different functions parameters.

Define Documentation

#define IS_CLK_CSSCONFIG_OK ( CSSVALUE )
Value:
(((CSSVALUE) == CLK_CSSCONFIG_ENABLEWITHIT) ||\
                                       ((CSSVALUE) == CLK_CSSCONFIG_ENABLE) ||\
                                       ((CSSVALUE) == CLK_CSSCONFIG_DISABLE))

Macros used by the assert function in order to check the CSS configuration.

Definition at line 234 of file stm8s_clk.h.

#define IS_CLK_CURRENTCLOCKSTATE_OK ( STATE )
Value:
(((STATE) == CLK_CURRENTCLOCKSTATE_DISABLE) ||\
                                            ((STATE) == CLK_CURRENTCLOCKSTATE_ENABLE))

Macros used by the assert function in order to check the current clock state.

Definition at line 228 of file stm8s_clk.h.

Referenced by CLK_ClockSwitchConfig().

#define IS_CLK_FLAG_OK ( FLAG )
Value:
(((FLAG) == CLK_FLAG_LSIRDY) ||\
                              ((FLAG) == CLK_FLAG_HSIRDY) ||\
                              ((FLAG) == CLK_FLAG_HSERDY) ||\
                              ((FLAG) == CLK_FLAG_SWIF) ||\
                              ((FLAG) == CLK_FLAG_SWBSY) ||\
                              ((FLAG) == CLK_FLAG_CSSD) ||\
                              ((FLAG) == CLK_FLAG_AUX) ||\
                              ((FLAG) == CLK_FLAG_CCOBSY) ||\
                              ((FLAG) == CLK_FLAG_CCORDY))

Macros used by the assert function in order to check the different clock flags.

Definition at line 295 of file stm8s_clk.h.

Referenced by CLK_GetFlagStatus().

#define IS_CLK_HSIPRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\
    ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\
    ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\
    ((PRESCALER) == CLK_PRESCALER_HSIDIV8))

Macros used by the assert function in order to check the different HSI prescaler values.

Definition at line 313 of file stm8s_clk.h.

Referenced by CLK_HSIPrescalerConfig().

#define IS_CLK_HSITRIMVALUE_OK ( TRIMVALUE )
Value:
(((TRIMVALUE) == CLK_HSITRIMVALUE_0) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_1) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_2) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_3) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_4) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_5) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_6) ||\
    ((TRIMVALUE) == CLK_HSITRIMVALUE_7))

Macros used by the assert function in order to check the different HSI trimming values.

Definition at line 248 of file stm8s_clk.h.

Referenced by CLK_AdjustHSICalibrationValue().

#define IS_CLK_IT_OK ( IT ) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF))

Macros used by the assert function in order to check the different clock IT pending bits.

Definition at line 308 of file stm8s_clk.h.

Referenced by CLK_ClearITPendingBit(), CLK_GetITStatus(), and CLK_ITConfig().

#define IS_CLK_OUTPUT_OK ( OUTPUT )
Value:
(((OUTPUT) == CLK_OUTPUT_HSI) ||\
                                  ((OUTPUT) == CLK_OUTPUT_HSE) ||\
                                  ((OUTPUT) == CLK_OUTPUT_LSI) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPU) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV2) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV4) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV8) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV16) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV32) ||\
                                  ((OUTPUT) == CLK_OUTPUT_CPUDIV64) ||\
                                  ((OUTPUT) == CLK_OUTPUT_HSIRC) ||\
                                  ((OUTPUT) == CLK_OUTPUT_MASTER) ||\
                                  ((OUTPUT) == CLK_OUTPUT_OTHERS))

Macros used by the assert function in order to check the different clocks to output.

Definition at line 260 of file stm8s_clk.h.

Referenced by CLK_CCOConfig().

#define IS_CLK_PERIPHERAL_OK ( PERIPHERAL )
Value:
(((PERIPHERAL) == CLK_PERIPHERAL_I2C) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_SPI) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_UART3) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_UART2) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_UART1) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER4) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER2) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER5) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER6) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER3) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_TIMER1) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_CAN) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_ADC) ||\
    ((PERIPHERAL) == CLK_PERIPHERAL_AWU))

Macros used by the assert function in order to check the different peripheral's clock.

Definition at line 277 of file stm8s_clk.h.

Referenced by CLK_PeripheralClockConfig().

#define IS_CLK_PRESCALER_OK ( PRESCALER )
Value:
(((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\
                                        ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\
                                        ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\
                                        ((PRESCALER) == CLK_PRESCALER_HSIDIV8) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV1) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV2) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV4) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV8) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV16) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV32) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV64) ||\
                                        ((PRESCALER) == CLK_PRESCALER_CPUDIV128))

Macros used by the assert function in order to check the different clock prescaler values.

Definition at line 321 of file stm8s_clk.h.

Referenced by CLK_SYSCLKConfig().

#define IS_CLK_SOURCE_OK ( SOURCE )
Value:
(((SOURCE) == CLK_SOURCE_HSI) ||\
                                  ((SOURCE) == CLK_SOURCE_LSI) ||\
                                  ((SOURCE) == CLK_SOURCE_HSE))

Macros used by the assert function in order to check the different clock sources.

Definition at line 241 of file stm8s_clk.h.

Referenced by CLK_ClockSwitchConfig().

#define IS_CLK_SWIMDIVIDER_OK ( SWIMDIVIDER ) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER))

Macros used by the assert function in order to check the different SWIM dividers values.

Definition at line 337 of file stm8s_clk.h.

Referenced by CLK_SWIMConfig().

#define IS_CLK_SWITCHMODE_OK ( MODE ) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO))

Macros used by the assert function in order to check the different functions parameters.

Macros used by the assert function in order to check the clock switching modes.

Definition at line 223 of file stm8s_clk.h.

Referenced by CLK_ClockSwitchConfig().


STM8S/A Standard Peripherals Drivers: CLK_Exported_functions

Functions

CLK_Exported_functions

Functions

void | CLK_AdjustHSICalibrationValue (CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | CLK_CCOCmd (FunctionalState NewState)
Enables or disablle the Configurable Clock Output (CCO).
void | CLK_CCOConfig (CLK_Output_TypeDef CLK_CCO)
Output the selected clock on a dedicated I/O pin.
void | CLK_ClearITPendingBit (CLK_IT_TypeDef CLK_IT)
Clears the CLK’s interrupt pending bits.
void | CLK_ClockSecuritySystemEnable (void)
Enables the Clock Security System.
void | CLK_ClockSwitchCmd (FunctionalState NewState)
Starts or Stops manually the clock switch execution.
ErrorStatus | CLK_ClockSwitchConfig (CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
configures the Switch from one clock to another
void | CLK_DeInit (void)
Deinitializes the CLK peripheral registers to their default reset values.
void | CLK_FastHaltWakeUpCmd (FunctionalState NewState)
Configures the High Speed Internal oscillator (HSI).
uint32_t | CLK_GetClockFreq (void)
This function returns the frequencies of different on chip clocks.
FlagStatus | CLK_GetFlagStatus (CLK_Flag_TypeDef CLK_FLAG)
Checks whether the specified CLK flag is set or not.
ITStatus | CLK_GetITStatus (CLK_IT_TypeDef CLK_IT)
Checks whether the specified CLK interrupt has is enabled or not.
CLK_Source_TypeDef | CLK_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | CLK_HSECmd (FunctionalState NewState)
Enable or Disable the External High Speed oscillator (HSE).
void | CLK_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | CLK_HSIPrescalerConfig (CLK_Prescaler_TypeDef HSIPrescaler)
Configures the HSI clock dividers.
void | CLK_ITConfig (CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
Enables or disables the specified CLK interrupts.
void | CLK_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | CLK_PeripheralClockConfig (CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
Enables or disables the specified peripheral CLK.
void | CLK_SlowActiveHaltWakeUpCmd (FunctionalState NewState)
Configures the slow active halt wake up.
void | CLK_SWIMConfig (CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
Configures the SWIM clock frequency on the fly.
void | CLK_SYSCLKConfig (CLK_Prescaler_TypeDef CLK_Prescaler)
Configures the HSI and CPU clock dividers.
void | CLK_SYSCLKEmergencyClear (void)
Reset the SWBSY flag (SWICR Reister)

Function Documentation

void CLK_AdjustHSICalibrationValue ( CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue )

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Full description:
Parameters:
CLK_HSICalibrationValue calibration trimming value. can be one of the values of CLK_HSITrimValue_TypeDef
Return values:
None

Definition at line 616 of file stm8s_clk.c.

References CLK, CLK_HSITRIMR_HSITRIM, and IS_CLK_HSITRIMVALUE_OK.

void CLK_CCOCmd ( FunctionalState NewState )

Enables or disablle the Configurable Clock Output (CCO).

Parameters:
NewState : New state of CCEN bit (CCO register). This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 192 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_CCOConfig ( CLK_Output_TypeDef CLK_CCO )

Output the selected clock on a dedicated I/O pin.

Parameters:
CLK_CCO : Specifies the clock source. This parameter can be any of the CLK_Output_TypeDef enumeration.
Return values:
None
Required preconditions:
The dedicated I/O pin must be set at 1 in the corresponding Px_CR1 register
to be set as input with pull-up or push-pull output.

Definition at line 439 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, CLK_CCOR_CCOSEL, and IS_CLK_OUTPUT_OK.

void CLK_ClearITPendingBit ( CLK_IT_TypeDef CLK_IT )

Clears the CLK’s interrupt pending bits.

Parameters:
CLK_IT specifies the interrupt pending bits. can be one of the values of CLK_IT_TypeDef
Return values:
None

Definition at line 747 of file stm8s_clk.c.

References CLK, CLK_CSSR_CSSD, CLK_IT_CSSD, CLK_SWCR_SWIF, and IS_CLK_IT_OK.

void CLK_ClockSecuritySystemEnable ( void )

Enables the Clock Security System.

Full description:
once CSS is enabled it cannot be disabled until the next reset.
Parameters:
None
Return values:
None

Definition at line 557 of file stm8s_clk.c.

References CLK, and CLK_CSSR_CSSEN.

void CLK_ClockSwitchCmd ( FunctionalState NewState )

Starts or Stops manually the clock switch execution.

Full description:
NewState parameter set the SWEN.
Parameters:
NewState new state of SWEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 218 of file stm8s_clk.c.

References CLK, CLK_SWCR_SWEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

ErrorStatus CLK_ClockSwitchConfig | ( | CLK_SwitchMode_TypeDef | CLK_SwitchMode,
 |  | CLK_Source_TypeDef | CLK_NewClock,
 |  | FunctionalState | ITState,
 |  | CLK_CurrentClockState_TypeDef | CLK_CurrentClockState
 | ) |  |

configures the Switch from one clock to another

Parameters:
CLK_SwitchMode | select the clock switch mode. It can be set of the values of CLK_SwitchMode_TypeDef
CLK_NewClock | choice of the future clock. It can be set of the values of CLK_Source_TypeDef
NewState | Enable or Disable the Clock Switch interrupt.
CLK_CurrentClockState | current clock to switch OFF or to keep ON. It can be set of the values of CLK_CurrentClockState_TypeDef
Return values:
ErrorStatus this shows the clock switch status (ERROR/SUCCESS).

Definition at line 319 of file stm8s_clk.c.

References CLK, CLK_CURRENTCLOCKSTATE_DISABLE, CLK_ECKR_HSEEN, CLK_ICKR_HSIEN, CLK_ICKR_LSIEN, CLK_SOURCE_HSE, CLK_SOURCE_HSI, CLK_SOURCE_LSI, CLK_SWCR_SWBSY, CLK_SWCR_SWEN, CLK_SWCR_SWIEN, CLK_SWITCHMODE_AUTO, CLK_TIMEOUT, DISABLE, ERROR, IS_CLK_CURRENTCLOCKSTATE_OK, IS_CLK_SOURCE_OK, IS_CLK_SWITCHMODE_OK, IS_FUNCTIONALSTATE_OK, and SUCCESS.

void CLK_DeInit ( void )

Deinitializes the CLK peripheral registers to their default reset values.

Parameters:
None
Return values:
None
Warning:
Resetting the CCOR register:
When the CCOEN bit is set, the reset of the CCOR register require two consecutive write instructions in order to reset first the CCOEN bit and the second one is to reset the CCOSEL bits.

Definition at line 66 of file stm8s_clk.c.

References CLK, CLK_CCOR_CCOEN, CLK_CCOR_RESET_VALUE, CLK_CKDIVR_RESET_VALUE, CLK_CSSR_RESET_VALUE, CLK_ECKR_RESET_VALUE, CLK_HSITRIMR_RESET_VALUE, CLK_ICKR_RESET_VALUE, CLK_PCKENR1_RESET_VALUE, CLK_PCKENR2_RESET_VALUE, CLK_SWCR_RESET_VALUE, CLK_SWIMCCR_RESET_VALUE, and CLK_SWR_RESET_VALUE.

void CLK_FastHaltWakeUpCmd ( FunctionalState NewState )

Configures the High Speed Internal oscillator (HSI).

Full description:
If CLK_FastHaltWakeup is enabled, HSI oscillator is automatically switched-on (HSIEN=1) and selected as next clock master (CKM=SWI=HSI) when resuming from HALT/ActiveHalt modes.
Parameters:
NewState this parameter is the Wake-up Mode state.
Return values:
None

Definition at line 95 of file stm8s_clk.c.

References CLK, CLK_ICKR_FHWU, DISABLE, and IS_FUNCTIONALSTATE_OK.

uint32_t CLK_GetClockFreq ( void )

This function returns the frequencies of different on chip clocks.

Parameters:
None
Return values:
the master clock frequency

Definition at line 579 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_HSIDIV, CLK_SOURCE_HSI, CLK_SOURCE_LSI, HSE_VALUE, HSI_VALUE, HSIDivFactor, and LSI_VALUE.

Referenced by UART1_Init(), UART2_Init(), and UART3_Init().

FlagStatus CLK_GetFlagStatus ( CLK_Flag_TypeDef CLK_FLAG )

Checks whether the specified CLK flag is set or not.

Full description:
Parameters:
CLK_FLAG Flag to check. can be one of the values of CLK_Flag_TypeDef
Return values:
FlagStatus,status of the checked flag

Definition at line 648 of file stm8s_clk.c.

References CLK, IS_CLK_FLAG_OK, RESET, and SET.

ITStatus CLK_GetITStatus ( CLK_IT_TypeDef CLK_IT )

Checks whether the specified CLK interrupt has is enabled or not.

Parameters:
CLK_IT specifies the CLK interrupt. can be one of the values of CLK_IT_TypeDef
Return values:
ITStatus,new state of CLK_IT (SET or RESET).

Definition at line 703 of file stm8s_clk.c.

References CLK, CLK_IT_SWIF, IS_CLK_IT_OK, RESET, and SET.

CLK_Source_TypeDef CLK_GetSYSCLKSource ( void )

Returns the clock source used as system clock.

Parameters:
None
Return values:
Clock source used. can be one of the values of CLK_Source_TypeDef

Definition at line 569 of file stm8s_clk.c.

References CLK.

void CLK_HSECmd ( FunctionalState NewState )

Enable or Disable the External High Speed oscillator (HSE).

Parameters:
NewState new state of HSEEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 119 of file stm8s_clk.c.

References CLK, CLK_ECKR_HSEEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_HSICmd ( FunctionalState NewState )

Enables or disables the Internal High Speed oscillator (HSI).

Parameters:
NewState new state of HSIEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 143 of file stm8s_clk.c.

References CLK, CLK_ICKR_HSIEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_HSIPrescalerConfig ( CLK_Prescaler_TypeDef HSIPrescaler )

Configures the HSI clock dividers.

Parameters:
HSIPrescaler : Specifies the HSI clock divider to apply. This parameter can be any of the CLK_Prescaler_TypeDef enumeration.
Return values:
None

Definition at line 416 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_HSIDIV, and IS_CLK_HSIPRESCALER_OK.

void CLK_ITConfig | ( | CLK_IT_TypeDef | CLK_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified CLK interrupts.

Parameters:
CLK_IT | This parameter specifies the interrupt sources. It can be one of the values of CLK_IT_TypeDef.
NewState | New state of the Interrupt. Value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 464 of file stm8s_clk.c.

References CLK, CLK_CSSR_CSSDIE, CLK_IT_CSSD, CLK_IT_SWIF, CLK_SWCR_SWIEN, DISABLE, IS_CLK_IT_OK, and IS_FUNCTIONALSTATE_OK.

void CLK_LSICmd ( FunctionalState NewState )

Enables or disables the Internal Low Speed oscillator (LSI).

Parameters:
NewState new state of LSIEN, value accepted ENABLE, DISABLE.
Return values:
None

Definition at line 167 of file stm8s_clk.c.

References CLK, CLK_ICKR_LSIEN, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_PeripheralClockConfig | ( | CLK_Peripheral_TypeDef | CLK_Peripheral,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified peripheral CLK.

Parameters:
CLK_Peripheral | : This parameter specifies the peripheral clock to gate. This parameter can be any of the CLK_Peripheral_TypeDef enumeration.
NewState | : New state of specified peripheral clock. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 272 of file stm8s_clk.c.

References CLK, DISABLE, IS_CLK_PERIPHERAL_OK, and IS_FUNCTIONALSTATE_OK.

void CLK_SlowActiveHaltWakeUpCmd ( FunctionalState NewState )

Configures the slow active halt wake up.

Parameters:
NewState,: specifies the Slow Active Halt wake up state. can be set of the following values:

  • DISABLE: Slow Active Halt mode disabled;
  • ENABLE: Slow Active Halt mode enabled.
Return values:
None

Definition at line 245 of file stm8s_clk.c.

References CLK, CLK_ICKR_SWUAH, DISABLE, and IS_FUNCTIONALSTATE_OK.

void CLK_SWIMConfig ( CLK_SWIMDivider_TypeDef CLK_SWIMDivider )

Configures the SWIM clock frequency on the fly.

Parameters:
CLK_SWIMDivider Specifies the SWIM clock divider to apply. can be one of the value of CLK_SWIMDivider_TypeDef
Return values:
None

Definition at line 531 of file stm8s_clk.c.

References CLK, CLK_SWIMCCR_SWIMDIV, CLK_SWIMDIVIDER_2, and IS_CLK_SWIMDIVIDER_OK.

void CLK_SYSCLKConfig ( CLK_Prescaler_TypeDef CLK_Prescaler )

Configures the HSI and CPU clock dividers.

Parameters:
ClockPrescaler Specifies the HSI or CPU clock divider to apply.
Return values:
None

Definition at line 507 of file stm8s_clk.c.

References CLK, CLK_CKDIVR_CPUDIV, CLK_CKDIVR_HSIDIV, and IS_CLK_PRESCALER_OK.

void CLK_SYSCLKEmergencyClear ( void )

Reset the SWBSY flag (SWICR Reister)

Full description:
This function reset SWBSY flag in order to reset clock switch operations (target oscillator is broken, stabilization is longing too much, etc.). If at the same time
software attempts to set SWEN and clear SWBSY, SWBSY action takes precedence.
Parameters:
None
Return values:
None

Definition at line 636 of file stm8s_clk.c.

References CLK, and CLK_SWCR_SWBSY.


STM8S/A Standard Peripherals Drivers: EXTI_Exported_Types

Enumerations

EXTI_Exported_Types

Enumerations

enum EXTI_Port_TypeDef {
EXTI_PORT_GPIOA = (uint8_t)0x00, EXTI_PORT_GPIOB = (uint8_t)0x01, EXTI_PORT_GPIOC = (uint8_t)0x02, EXTI_PORT_GPIOD = (uint8_t)0x03,
EXTI_PORT_GPIOE = (uint8_t)0x04
}

EXTI PortNum possible values.

More...
enum | EXTI_Sensitivity_TypeDef { EXTI_SENSITIVITY_FALL_LOW = (uint8_t)0x00, EXTI_SENSITIVITY_RISE_ONLY = (uint8_t)0x01, EXTI_SENSITIVITY_FALL_ONLY = (uint8_t)0x02, EXTI_SENSITIVITY_RISE_FALL = (uint8_t)0x03 }

EXTI Sensitivity values for PORTA to PORTE.

More...
enum | EXTI_TLISensitivity_TypeDef { EXTI_TLISENSITIVITY_FALL_ONLY = (uint8_t)0x00, EXTI_TLISENSITIVITY_RISE_ONLY = (uint8_t)0x04 }

EXTI Sensitivity values for TLI.

More...

Enumeration Type Documentation

enum EXTI_Port_TypeDef

EXTI PortNum possible values.

Enumerator:
EXTI_PORT_GPIOA

GPIO Port A

EXTI_PORT_GPIOB

GPIO Port B

EXTI_PORT_GPIOC

GPIO Port C

EXTI_PORT_GPIOD

GPIO Port D

EXTI_PORT_GPIOE

GPIO Port E

Definition at line 56 of file stm8s_exti.h.

enum EXTI_Sensitivity_TypeDef

EXTI Sensitivity values for PORTA to PORTE.

Enumerator:
EXTI_SENSITIVITY_FALL_LOW

Interrupt on Falling edge and Low level

EXTI_SENSITIVITY_RISE_ONLY

Interrupt on Rising edge only

EXTI_SENSITIVITY_FALL_ONLY

Interrupt on Falling edge only

EXTI_SENSITIVITY_RISE_FALL

Interrupt on Rising and Falling edges

Definition at line 38 of file stm8s_exti.h.

enum EXTI_TLISensitivity_TypeDef

EXTI Sensitivity values for TLI.

Enumerator:
EXTI_TLISENSITIVITY_FALL_ONLY

Top Level Interrupt on Falling edge only

EXTI_TLISENSITIVITY_RISE_ONLY

Top Level Interrupt on Rising edge only

Definition at line 48 of file stm8s_exti.h.


STM8S/A Standard Peripherals Drivers: EXTI_Private_Macros

Defines

EXTI_Private_Macros

Defines

#define | IS_EXTI_PINMASK_OK(PinMask) ((((PinMask) & (uint8_t)0x00) == (uint8_t)0x00) && ((PinMask) != (uint8_t)0x00))
Macro used by the assert function in order to check the different values of the EXTI PinMask.
#define | IS_EXTI_PORT_OK(PORT)
Macro used by the assert function in order to check the different Port values.
#define | IS_EXTI_SENSITIVITY_OK(SensitivityValue)
Macro used by the assert function in order to check the different sensitivity values for PORTA to PORTE.
#define | IS_EXTI_TLISENSITIVITY_OK(SensitivityValue)
Macro used by the assert function in order to check the different sensitivity values for TLI.

Define Documentation

#define IS_EXTI_PINMASK_OK ( PinMask ) ((((PinMask) & (uint8_t)0x00) == (uint8_t)0x00) && ((PinMask) != (uint8_t)0x00))

Macro used by the assert function in order to check the different values of the EXTI PinMask.

Definition at line 103 of file stm8s_exti.h.

#define IS_EXTI_PORT_OK ( PORT )
Value:
(((PORT) == EXTI_PORT_GPIOA) ||\
   ((PORT) == EXTI_PORT_GPIOB) ||\
   ((PORT) == EXTI_PORT_GPIOC) ||\
   ((PORT) == EXTI_PORT_GPIOD) ||\
   ((PORT) == EXTI_PORT_GPIOE))

Macro used by the assert function in order to check the different Port values.

Definition at line 93 of file stm8s_exti.h.

Referenced by EXTI_GetExtIntSensitivity(), and EXTI_SetExtIntSensitivity().

#define IS_EXTI_SENSITIVITY_OK ( SensitivityValue )
Value:
(((SensitivityValue) == EXTI_SENSITIVITY_FALL_LOW) || \
   ((SensitivityValue) == EXTI_SENSITIVITY_RISE_ONLY) || \
   ((SensitivityValue) == EXTI_SENSITIVITY_FALL_ONLY) || \
   ((SensitivityValue) == EXTI_SENSITIVITY_RISE_FALL))

Macro used by the assert function in order to check the different sensitivity values for PORTA to PORTE.

Definition at line 77 of file stm8s_exti.h.

Referenced by EXTI_SetExtIntSensitivity().

#define IS_EXTI_TLISENSITIVITY_OK ( SensitivityValue )
Value:
(((SensitivityValue) == EXTI_TLISENSITIVITY_FALL_ONLY) || \
   ((SensitivityValue) == EXTI_TLISENSITIVITY_RISE_ONLY))

Macro used by the assert function in order to check the different sensitivity values for TLI.

Definition at line 86 of file stm8s_exti.h.

Referenced by EXTI_SetTLISensitivity().


STM8S/A Standard Peripherals Drivers: EXTI_Exported_Functions

Functions

EXTI_Exported_Functions

Functions

void | EXTI_DeInit (void)
Deinitializes the external interrupt control registers to their default reset value.
EXTI_Sensitivity_TypeDef | EXTI_GetExtIntSensitivity (EXTI_Port_TypeDef Port)
Get the external interrupt sensitivity of the selected port.
EXTI_TLISensitivity_TypeDef | EXTI_GetTLISensitivity (void)
Get the TLI interrupt sensitivity.
void | EXTI_SetExtIntSensitivity (EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)
Set the external interrupt sensitivity of the selected port.
void | EXTI_SetTLISensitivity (EXTI_TLISensitivity_TypeDef SensitivityValue)
Set the TLI interrupt sensitivity.

Function Documentation

void EXTI_DeInit ( void )

Deinitializes the external interrupt control registers to their default reset value.

Parameters:
None
Return values:
None

Definition at line 47 of file stm8s_exti.c.

References EXTI, EXTI_CR1_RESET_VALUE, and EXTI_CR2_RESET_VALUE.

EXTI_Sensitivity_TypeDef EXTI_GetExtIntSensitivity ( EXTI_Port_TypeDef Port )

Get the external interrupt sensitivity of the selected port.

Parameters:
Port The port number to access.
Return values:
EXTI_Sensitivity_TypeDef The external interrupt sensitivity of the selected port.

Definition at line 121 of file stm8s_exti.c.

References EXTI, EXTI_CR1_PAIS, EXTI_CR1_PBIS, EXTI_CR1_PCIS, EXTI_CR1_PDIS, EXTI_CR2_PEIS, EXTI_PORT_GPIOA, EXTI_PORT_GPIOB, EXTI_PORT_GPIOC, EXTI_PORT_GPIOD, EXTI_PORT_GPIOE, and IS_EXTI_PORT_OK.

EXTI_TLISensitivity_TypeDef EXTI_GetTLISensitivity ( void )

Get the TLI interrupt sensitivity.

Parameters:
None
Return values:
EXTI_TLISensitivity_TypeDef The TLI interrupt sensitivity read.

Definition at line 157 of file stm8s_exti.c.

References EXTI, and EXTI_CR2_TLIS.

void EXTI_SetExtIntSensitivity | ( | EXTI_Port_TypeDef | Port,
 |  | EXTI_Sensitivity_TypeDef | SensitivityValue
 | ) |  |

Set the external interrupt sensitivity of the selected port.

Warning:
  • The modification of external interrupt sensitivity is only possible when the interrupts are disabled.
  • The normal behavior is to disable the interrupts before calling this function, and re-enable them after.
Parameters:
Port | The port number to access.
SensitivityValue | The external interrupt sensitivity value to set.
Return values:
None
Required preconditions:
Global interrupts must be disabled before calling this function.

Definition at line 64 of file stm8s_exti.c.

References EXTI, EXTI_CR1_PAIS, EXTI_CR1_PBIS, EXTI_CR1_PCIS, EXTI_CR1_PDIS, EXTI_CR2_PEIS, EXTI_PORT_GPIOA, EXTI_PORT_GPIOB, EXTI_PORT_GPIOC, EXTI_PORT_GPIOD, EXTI_PORT_GPIOE, IS_EXTI_PORT_OK, and IS_EXTI_SENSITIVITY_OK.

void EXTI_SetTLISensitivity ( EXTI_TLISensitivity_TypeDef SensitivityValue )

Set the TLI interrupt sensitivity.

Parameters:
SensitivityValue The TLI interrupt sensitivity value.
Return values:
None
Required preconditions:
Global interrupts must be disabled before calling this function.

Definition at line 106 of file stm8s_exti.c.

References EXTI, EXTI_CR2_TLIS, and IS_EXTI_TLISENSITIVITY_OK.


STM8S/A Standard Peripherals Drivers: FLASH_Exported_Constants

Defines

FLASH_Exported_Constants

Defines

#define | FLASH_OPTIONBYTE_ERROR ((uint16_t)0x5555)
#define | FLASH_PROG_START_PHYSICAL_ADDRESS ((uint32_t)0x008000)
#define | FLASH_RASS_KEY1 ((uint8_t)0x56)
#define | FLASH_RASS_KEY2 ((uint8_t)0xAE)
#define | OPTION_BYTE_END_PHYSICAL_ADDRESS ((uint16_t)0x487F)
#define | OPTION_BYTE_START_PHYSICAL_ADDRESS ((uint16_t)0x4800)

Define Documentation

#define FLASH_OPTIONBYTE_ERROR ((uint16_t)0x5555)

Error code option byte (if value read is not equal to complement value read)

Definition at line 69 of file stm8s_flash.h.

Referenced by FLASH_ReadOptionByte().

#define FLASH_PROG_START_PHYSICAL_ADDRESS ((uint32_t)0x008000)

Program memory: start address

Definition at line 35 of file stm8s_flash.h.

#define FLASH_RASS_KEY1 ((uint8_t)0x56)

First RASS key

Definition at line 64 of file stm8s_flash.h.

Referenced by FLASH_Unlock().

#define FLASH_RASS_KEY2 ((uint8_t)0xAE)

Second RASS key

Definition at line 65 of file stm8s_flash.h.

Referenced by FLASH_Unlock().

#define OPTION_BYTE_END_PHYSICAL_ADDRESS ((uint16_t)0x487F)

Definition at line 68 of file stm8s_flash.h.

#define OPTION_BYTE_START_PHYSICAL_ADDRESS ((uint16_t)0x4800)

Definition at line 67 of file stm8s_flash.h.


STM8S/A Standard Peripherals Drivers: FLASH_Exported_Types

Enumerations

FLASH_Exported_Types

Enumerations

enum | FLASH_Flag_TypeDef { FLASH_FLAG_DUL = (uint8_t)0x08, FLASH_FLAG_EOP = (uint8_t)0x04, FLASH_FLAG_PUL = (uint8_t)0x02, FLASH_FLAG_WR_PG_DIS = (uint8_t)0x01 }

FLASH flags definition

  • Warning : FLAG value = mapping position register.
More...
enum | FLASH_LPMode_TypeDef { FLASH_LPMODE_POWERDOWN = (uint8_t)0x04, FLASH_LPMODE_STANDBY = (uint8_t)0x08, FLASH_LPMODE_POWERDOWN_STANDBY = (uint8_t)0x00, FLASH_LPMODE_STANDBY_POWERDOWN = (uint8_t)0x0C }

FLASH Low Power mode select.

More...
enum | FLASH_MemType_TypeDef { FLASH_MEMTYPE_PROG = (uint8_t)0xFD, FLASH_MEMTYPE_DATA = (uint8_t)0xF7 }

FLASH Memory types.

More...
enum | FLASH_ProgramMode_TypeDef { FLASH_PROGRAMMODE_STANDARD = (uint8_t)0x00, FLASH_PROGRAMMODE_FAST = (uint8_t)0x10 }

FLASH programming modes.

More...
enum | FLASH_ProgramTime_TypeDef { FLASH_PROGRAMTIME_STANDARD = (uint8_t)0x00, FLASH_PROGRAMTIME_TPROG = (uint8_t)0x01 }

FLASH fixed programming time.

More...
enum | FLASH_Status_TypeDef { FLASH_STATUS_SUCCESSFUL_OPERATION = (uint8_t)0x04, FLASH_STATUS_TIMEOUT = (uint8_t)0x02, FLASH_STATUS_WRITE_PROTECTION_ERROR = (uint8_t)0x01 }

FLASH status of the last operation.

More...

Enumeration Type Documentation

enum FLASH_Flag_TypeDef

FLASH flags definition

  • Warning : FLAG value = mapping position register.

Enumerator:
FLASH_FLAG_DUL

Data EEPROM unlocked flag

FLASH_FLAG_EOP

End of programming (write or erase operation) flag

FLASH_FLAG_PUL

Flash Program memory unlocked flag

FLASH_FLAG_WR_PG_DIS

Write attempted to protected page flag

Definition at line 133 of file stm8s_flash.h.

enum FLASH_LPMode_TypeDef

FLASH Low Power mode select.

Enumerator:
FLASH_LPMODE_POWERDOWN

HALT: Power-Down / ACTIVE-HALT: Power-Down

FLASH_LPMODE_STANDBY

HALT: Standby / ACTIVE-HALT: Standby

FLASH_LPMODE_POWERDOWN_STANDBY

HALT: Power-Down / ACTIVE-HALT: Standby

FLASH_LPMODE_STANDBY_POWERDOWN

HALT: Standby / ACTIVE-HALT: Power-Down

Definition at line 108 of file stm8s_flash.h.

enum FLASH_MemType_TypeDef

FLASH Memory types.

Enumerator:
FLASH_MEMTYPE_PROG

Program memory

FLASH_MEMTYPE_DATA

Data EEPROM memory

Definition at line 84 of file stm8s_flash.h.

enum FLASH_ProgramMode_TypeDef

FLASH programming modes.

Enumerator:
FLASH_PROGRAMMODE_STANDARD

Standard programming mode

FLASH_PROGRAMMODE_FAST

Fast programming mode

Definition at line 92 of file stm8s_flash.h.

enum FLASH_ProgramTime_TypeDef

FLASH fixed programming time.

Enumerator:
FLASH_PROGRAMTIME_STANDARD

Standard programming time fixed at 1/2 tprog

FLASH_PROGRAMTIME_TPROG

Programming time fixed at tprog

Definition at line 100 of file stm8s_flash.h.

enum FLASH_Status_TypeDef

FLASH status of the last operation.

Enumerator:
FLASH_STATUS_SUCCESSFUL_OPERATION

End of operation flag

FLASH_STATUS_TIMEOUT

Time out error

FLASH_STATUS_WRITE_PROTECTION_ERROR

Write attempted to protected page

Definition at line 119 of file stm8s_flash.h.


STM8S/A Standard Peripherals Drivers: FLASH_Private_Macros

Defines

FLASH_Private_Macros

Macros used by the assert function in order to check the different functions parameters. More...

Defines

#define | IS_FLASH_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom and flash program Address.
#define | IS_FLASH_DATA_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom Address.
#define | IS_FLASH_DATA_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_DATA_BLOCKS_NUMBER)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom Block number.
#define | IS_FLASH_FLAGS_OK(FLAG)
Macro used by the assert function in order to check the different flags values.
#define | IS_FLASH_LOW_POWER_MODE_OK(LPMODE)
Macro used by the assert function in order to check the different sensitivity values for the low power mode.
#define | IS_FLASH_PROG_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the flash program Address.
#define | IS_FLASH_PROG_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_PROG_BLOCKS_NUMBER)
Macro used by the assert function in order to check the different sensitivity values for the flash program Block number.
#define | IS_FLASH_PROGRAM_MODE_OK(MODE)
Macro used by the assert function in order to check the different sensitivity values for the flash program mode.
#define | IS_FLASH_PROGRAM_TIME_OK(TIME)
Macro used by the assert function in order to check the program time mode.
#define | IS_MEMORY_TYPE_OK(MEMTYPE)
Macro used by the assert function in order to check the different sensitivity values for the flash memory type.
#define | IS_OPTION_BYTE_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the option bytes Address.

Detailed Description

Macros used by the assert function in order to check the different functions parameters.

Define Documentation

#define IS_FLASH_ADDRESS_OK ( ADDRESS )
Value:
((((ADDRESS) >= FLASH_PROG_START_PHYSICAL_ADDRESS) && ((ADDRESS) <= FLASH_PROG_END_PHYSICAL_ADDRESS)) || \
                                     (((ADDRESS) >= FLASH_DATA_START_PHYSICAL_ADDRESS) && ((ADDRESS) <= FLASH_DATA_END_PHYSICAL_ADDRESS)))

Macro used by the assert function in order to check the different sensitivity values for the data eeprom and flash program Address.

Definition at line 173 of file stm8s_flash.h.

Referenced by FLASH_EraseByte(), FLASH_ProgramByte(), FLASH_ProgramWord(), and FLASH_ReadByte().

#define IS_FLASH_DATA_ADDRESS_OK ( ADDRESS )
Value:
(((ADDRESS) >= FLASH_DATA_START_PHYSICAL_ADDRESS) && \
    ((ADDRESS) <= FLASH_DATA_END_PHYSICAL_ADDRESS))

Macro used by the assert function in order to check the different sensitivity values for the data eeprom Address.

Definition at line 167 of file stm8s_flash.h.

#define IS_FLASH_DATA_BLOCK_NUMBER_OK ( BLOCKNUM ) ((BLOCKNUM) < FLASH_DATA_BLOCKS_NUMBER)

Macro used by the assert function in order to check the different sensitivity values for the data eeprom Block number.

Definition at line 184 of file stm8s_flash.h.

#define IS_FLASH_FLAGS_OK ( FLAG )
Value:
(((FLAG) == FLASH_FLAG_DUL) || \
                                 ((FLAG) == FLASH_FLAG_EOP) || \
                                 ((FLAG) == FLASH_FLAG_PUL) || \
                                 ((FLAG) == FLASH_FLAG_WR_PG_DIS))

Macro used by the assert function in order to check the different flags values.

Definition at line 236 of file stm8s_flash.h.

Referenced by FLASH_GetFlagStatus().

#define IS_FLASH_LOW_POWER_MODE_OK ( LPMODE )
Value:
(((LPMODE) == FLASH_LPMODE_POWERDOWN) || \
    ((LPMODE) == FLASH_LPMODE_STANDBY) || \
    ((LPMODE) == FLASH_LPMODE_POWERDOWN_STANDBY) || \
    ((LPMODE) == FLASH_LPMODE_STANDBY_POWERDOWN))

Macro used by the assert function in order to check the different sensitivity values for the low power mode.

Definition at line 212 of file stm8s_flash.h.

Referenced by FLASH_SetLowPowerMode().

#define IS_FLASH_PROG_ADDRESS_OK ( ADDRESS )
Value:
(((ADDRESS) >= FLASH_PROG_START_PHYSICAL_ADDRESS) && \
    ((ADDRESS) <= FLASH_PROG_END_PHYSICAL_ADDRESS))

Macro used by the assert function in order to check the different sensitivity values for the flash program Address.

Definition at line 160 of file stm8s_flash.h.

#define IS_FLASH_PROG_BLOCK_NUMBER_OK ( BLOCKNUM ) ((BLOCKNUM) < FLASH_PROG_BLOCKS_NUMBER)

Macro used by the assert function in order to check the different sensitivity values for the flash program Block number.

Definition at line 179 of file stm8s_flash.h.

#define IS_FLASH_PROGRAM_MODE_OK ( MODE )
Value:
(((MODE) == FLASH_PROGRAMMODE_STANDARD) || \
                                        ((MODE) == FLASH_PROGRAMMODE_FAST))

Macro used by the assert function in order to check the different sensitivity values for the flash program mode.

Definition at line 197 of file stm8s_flash.h.

#define IS_FLASH_PROGRAM_TIME_OK ( TIME )
Value:
(((TIME) == FLASH_PROGRAMTIME_STANDARD) || \
                                        ((TIME) == FLASH_PROGRAMTIME_TPROG))

Macro used by the assert function in order to check the program time mode.

Definition at line 204 of file stm8s_flash.h.

Referenced by FLASH_SetProgrammingTime().

#define IS_MEMORY_TYPE_OK ( MEMTYPE )
Value:
(((MEMTYPE) == FLASH_MEMTYPE_PROG) || \
                                    ((MEMTYPE) == FLASH_MEMTYPE_DATA))

Macro used by the assert function in order to check the different sensitivity values for the flash memory type.

Definition at line 190 of file stm8s_flash.h.

Referenced by FLASH_Lock(), and FLASH_Unlock().

#define IS_OPTION_BYTE_ADDRESS_OK ( ADDRESS )
Value:
(((ADDRESS) >= OPTION_BYTE_START_PHYSICAL_ADDRESS) && \
    ((ADDRESS) <= OPTION_BYTE_END_PHYSICAL_ADDRESS))

Macro used by the assert function in order to check the different sensitivity values for the option bytes Address.

Definition at line 221 of file stm8s_flash.h.

Referenced by FLASH_EraseOptionByte(), FLASH_ProgramOptionByte(), and FLASH_ReadOptionByte().


STM8S/A Standard Peripherals Drivers: FLASH_Exported_Functions

Functions

FLASH_Exported_Functions

Functions

void | FLASH_DeInit (void)
Deinitializes the FLASH registers to their default reset values.
void | FLASH_EraseByte (uint32_t Address)
Erases one byte in the program or data EEPROM memory.
void | FLASH_EraseOptionByte (uint16_t Address)
Erases option byte.
uint32_t | FLASH_GetBootSize (void)
Returns the Boot memory size in bytes.
FlagStatus | FLASH_GetFlagStatus (FLASH_Flag_TypeDef FLASH_FLAG)
Checks whether the specified SPI flag is set or not.
FLASH_LPMode_TypeDef | FLASH_GetLowPowerMode (void)
Returns the Flash behaviour type in low power mode.
FLASH_ProgramTime_TypeDef | FLASH_GetProgrammingTime (void)
Returns the fixed programming time.
void | FLASH_ITConfig (FunctionalState NewState)
Enables or Disables the Flash interrupt mode.
void | FLASH_Lock (FLASH_MemType_TypeDef FLASH_MemType)
Locks the program or data EEPROM memory.
void | FLASH_ProgramByte (uint32_t Address, uint8_t Data)
Programs one byte in program or data EEPROM memory.
void | FLASH_ProgramOptionByte (uint16_t Address, uint8_t Data)
Programs option byte.
void | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs one word (4 bytes) in program or data EEPROM memory.
uint8_t | FLASH_ReadByte (uint32_t Address)
Reads any byte from flash memory.
uint16_t | FLASH_ReadOptionByte (uint16_t Address)
Reads one option byte.
void | FLASH_SetLowPowerMode (FLASH_LPMode_TypeDef FLASH_LPMode)
Select the Flash behaviour in low power mode.
void | FLASH_SetProgrammingTime (FLASH_ProgramTime_TypeDef FLASH_ProgTime)
Sets the fixed programming time.
void | FLASH_Unlock (FLASH_MemType_TypeDef FLASH_MemType)
Unlocks the program or data EEPROM memory.
IN_RAM (void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType, FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer))
IN_RAM (FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType))
IN_RAM (void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType))

Function Documentation

void FLASH_DeInit ( void )

Deinitializes the FLASH registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 120 of file stm8s_flash.c.

References FLASH, FLASH_CR1_RESET_VALUE, FLASH_CR2_RESET_VALUE, FLASH_IAPSR_DUL, FLASH_IAPSR_PUL, and FLASH_NCR2_RESET_VALUE.

void FLASH_EraseByte ( uint32_t Address )

Erases one byte in the program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address : Address of the byte to erase
Return values:
None

Definition at line 158 of file stm8s_flash.c.

References FLASH_CLEAR_BYTE, IS_FLASH_ADDRESS_OK, and PointerAttr.

void FLASH_EraseOptionByte ( uint16_t Address )

Erases option byte.

Parameters:
Address : Option byte address to erase
Return values:
None

Definition at line 265 of file stm8s_flash.c.

References FLASH, FLASH_CLEAR_BYTE, FLASH_CR2_OPT, FLASH_MEMTYPE_PROG, FLASH_NCR2_NOPT, FLASH_SET_BYTE, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

uint32_t FLASH_GetBootSize ( void )

Returns the Boot memory size in bytes.

Parameters:
None
Return values:
Boot memory size in bytes

Definition at line 387 of file stm8s_flash.c.

References FLASH.

FlagStatus FLASH_GetFlagStatus ( FLASH_Flag_TypeDef FLASH_FLAG )

Checks whether the specified SPI flag is set or not.

Parameters:
FLASH_FLAG : Specifies the flag to check. This parameter can be any of the FLASH_Flag_TypeDef enumeration.
Return values:
FlagStatus : Indicates the state of FLASH_FLAG. This parameter can be any of the FlagStatus enumeration.
Note:
This function can clear the EOP, WR_PG_DIS flags in the IAPSR register.

Definition at line 412 of file stm8s_flash.c.

References FLASH, IS_FLASH_FLAGS_OK, RESET, and SET.

FLASH_LPMode_TypeDef FLASH_GetLowPowerMode ( void )

Returns the Flash behaviour type in low power mode.

Parameters:
None
Return values:
FLASH_LPMode_TypeDef Flash behaviour type in low power mode

Definition at line 367 of file stm8s_flash.c.

References FLASH, FLASH_CR1_AHALT, and FLASH_CR1_HALT.

FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime ( void )

Returns the fixed programming time.

Parameters:
None
Return values:
FLASH_ProgramTime_TypeDef Fixed programming time value

Definition at line 377 of file stm8s_flash.c.

References FLASH, and FLASH_CR1_FIX.

void FLASH_ITConfig ( FunctionalState NewState )

Enables or Disables the Flash interrupt mode.

Parameters:
NewState : The new state of the flash interrupt mode This parameter can be a value of FunctionalState enumeration.
Return values:
None

Definition at line 136 of file stm8s_flash.c.

References DISABLE, FLASH, FLASH_CR1_IE, and IS_FUNCTIONALSTATE_OK.

void FLASH_Lock ( FLASH_MemType_TypeDef FLASH_MemType )

Locks the program or data EEPROM memory.

Parameters:
FLASH_MemType : Memory type This parameter can be a value of FLASH_MemType_TypeDef
Return values:
None

Definition at line 106 of file stm8s_flash.c.

References FLASH, and IS_MEMORY_TYPE_OK.

void FLASH_ProgramByte | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  |

Programs one byte in program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address | : Address where the byte will be programmed
Data | : Value to be programmed
Return values:
None

Definition at line 176 of file stm8s_flash.c.

References IS_FLASH_ADDRESS_OK, and PointerAttr.

void FLASH_ProgramOptionByte | ( | uint16_t | Address,
 |  | uint8_t | Data
 | ) |  |

Programs option byte.

Parameters:
Address | : option byte address to program
Data | : Value to write
Return values:
None

Definition at line 232 of file stm8s_flash.c.

References FLASH, FLASH_CR2_OPT, FLASH_MEMTYPE_PROG, FLASH_NCR2_NOPT, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

void FLASH_ProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs one word (4 bytes) in program or data EEPROM memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address | : The address where the data will be programmed
Data | : Value to be programmed
Return values:
None

Definition at line 207 of file stm8s_flash.c.

References FLASH, FLASH_CR2_WPRG, FLASH_NCR2_NWPRG, IS_FLASH_ADDRESS_OK, and PointerAttr.

uint8_t FLASH_ReadByte ( uint32_t Address )

Reads any byte from flash memory.

Note:
PointerAttr define is declared in the stm8s.h file to select if the pointer will be declared as near (2 bytes) or far (3 bytes).
Parameters:
Address : Address to read
Return values:
Value of the byte

Definition at line 190 of file stm8s_flash.c.

References IS_FLASH_ADDRESS_OK, and PointerAttr.

uint16_t FLASH_ReadOptionByte ( uint16_t Address )

Reads one option byte.

Parameters:
Address option byte address to read.
Return values:
Option byte read value + its complement

Definition at line 297 of file stm8s_flash.c.

References FLASH_OPTIONBYTE_ERROR, IS_OPTION_BYTE_ADDRESS_OK, and NEAR.

void FLASH_SetLowPowerMode ( FLASH_LPMode_TypeDef FLASH_LPMode )

Select the Flash behaviour in low power mode.

Parameters:
FLASH_LPMode Low power mode selection This parameter can be any of the FLASH_LPMode_TypeDef values.
Return values:
None

Definition at line 335 of file stm8s_flash.c.

References FLASH, FLASH_CR1_AHALT, FLASH_CR1_HALT, and IS_FLASH_LOW_POWER_MODE_OK.

void FLASH_SetProgrammingTime ( FLASH_ProgramTime_TypeDef FLASH_ProgTime )

Sets the fixed programming time.

Parameters:
FLASH_ProgTime Indicates the programming time to be fixed This parameter can be any of the FLASH_ProgramTime_TypeDef values.
Return values:
None

Definition at line 353 of file stm8s_flash.c.

References FLASH, FLASH_CR1_FIX, and IS_FLASH_PROGRAM_TIME_OK.

void FLASH_Unlock ( FLASH_MemType_TypeDef FLASH_MemType )

Unlocks the program or data EEPROM memory.

Parameters:
FLASH_MemType : Memory type to unlock This parameter can be a value of FLASH_MemType_TypeDef
Return values:
None

Definition at line 81 of file stm8s_flash.c.

References FLASH, FLASH_MEMTYPE_PROG, FLASH_RASS_KEY1, FLASH_RASS_KEY2, and IS_MEMORY_TYPE_OK.

IN_RAM ( void FLASH_ProgramBlockuint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType, FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer )
IN_RAM ( FLASH_Status_TypeDef FLASH_WaitForLastOperationFLASH_MemType_TypeDef FLASH_MemType )
IN_RAM ( void FLASH_EraseBlockuint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType )
 All the functions declared below must be executed from RAM exclusively, except
 for the FLASH_WaitForLastOperation function which can be executed from Flash.

 Steps of the execution from RAM differs from one toolchain to another.
 for more details refer to stm8s_flash.c file.

 To enable execution from RAM you can either uncomment the following define
 in the stm8s.h file or define it in your toolchain compiler preprocessor
 - #define RAM_EXECUTION  (1)


STM8S/A Standard Peripherals Drivers: GPIO_Exported_Types

Enumerations

GPIO_Exported_Types

Enumerations

enum GPIO_Mode_TypeDef {
GPIO_MODE_IN_FL_NO_IT = (uint8_t)0x00, GPIO_MODE_IN_PU_NO_IT = (uint8_t)0x40, GPIO_MODE_IN_FL_IT = (uint8_t)0x20, GPIO_MODE_IN_PU_IT = (uint8_t)0x60,
GPIO_MODE_OUT_OD_LOW_FAST = (uint8_t)0xA0, GPIO_MODE_OUT_PP_LOW_FAST = (uint8_t)0xE0, GPIO_MODE_OUT_OD_LOW_SLOW = (uint8_t)0x80, GPIO_MODE_OUT_PP_LOW_SLOW = (uint8_t)0xC0,
GPIO_MODE_OUT_OD_HIZ_FAST = (uint8_t)0xB0, GPIO_MODE_OUT_PP_HIGH_FAST = (uint8_t)0xF0, GPIO_MODE_OUT_OD_HIZ_SLOW = (uint8_t)0x90, GPIO_MODE_OUT_PP_HIGH_SLOW = (uint8_t)0xD0
}

GPIO modes.

More...
enum GPIO_Pin_TypeDef {
GPIO_PIN_0 = ((uint8_t)0x01), GPIO_PIN_1 = ((uint8_t)0x02), GPIO_PIN_2 = ((uint8_t)0x04), GPIO_PIN_3 = ((uint8_t)0x08),
GPIO_PIN_4 = ((uint8_t)0x10), GPIO_PIN_5 = ((uint8_t)0x20), GPIO_PIN_6 = ((uint8_t)0x40), GPIO_PIN_7 = ((uint8_t)0x80),
GPIO_PIN_LNIB = ((uint8_t)0x0F), GPIO_PIN_HNIB = ((uint8_t)0xF0), GPIO_PIN_ALL = ((uint8_t)0xFF)
}

Definition of the GPIO pins.

More...

Enumeration Type Documentation

enum GPIO_Mode_TypeDef

GPIO modes.

Bits definitions:

  • Bit 7: 0 = INPUT mode 1 = OUTPUT mode 1 = PULL-UP (input) or PUSH-PULL (output)
  • Bit 5: 0 = No external interrupt (input) or No slope control (output) 1 = External interrupt (input) or Slow control enabled (output)
  • Bit 4: 0 = Low level (output) 1 = High level (output push-pull) or HI-Z (output open-drain)
Enumerator:
GPIO_MODE_IN_FL_NO_IT

Input floating, no external interrupt

GPIO_MODE_IN_PU_NO_IT

Input pull-up, no external interrupt

GPIO_MODE_IN_FL_IT

Input floating, external interrupt

GPIO_MODE_IN_PU_IT

Input pull-up, external interrupt

GPIO_MODE_OUT_OD_LOW_FAST

Output open-drain, low level, 10MHz

GPIO_MODE_OUT_PP_LOW_FAST

Output push-pull, low level, 10MHz

GPIO_MODE_OUT_OD_LOW_SLOW

Output open-drain, low level, 2MHz

GPIO_MODE_OUT_PP_LOW_SLOW

Output push-pull, low level, 2MHz

GPIO_MODE_OUT_OD_HIZ_FAST

Output open-drain, high-impedance level,10MHz

GPIO_MODE_OUT_PP_HIGH_FAST

Output push-pull, high level, 10MHz

GPIO_MODE_OUT_OD_HIZ_SLOW

Output open-drain, high-impedance level, 2MHz

GPIO_MODE_OUT_PP_HIGH_SLOW

Output push-pull, high level, 2MHz

Definition at line 48 of file stm8s_gpio.h.

enum GPIO_Pin_TypeDef

Definition of the GPIO pins.

Used by the GPIO_Init function in order to select the pins to be initialized.

Enumerator:
GPIO_PIN_0

Pin 0 selected

GPIO_PIN_1

Pin 1 selected

GPIO_PIN_2

Pin 2 selected

GPIO_PIN_3

Pin 3 selected

GPIO_PIN_4

Pin 4 selected

GPIO_PIN_5

Pin 5 selected

GPIO_PIN_6

Pin 6 selected

GPIO_PIN_7

Pin 7 selected

GPIO_PIN_LNIB

Low nibble pins selected

GPIO_PIN_HNIB

High nibble pins selected

GPIO_PIN_ALL

All pins selected

Definition at line 69 of file stm8s_gpio.h.


STM8S/A Standard Peripherals Drivers: GPIO_Private_Macros

Defines

GPIO_Private_Macros

Defines

#define | IS_GPIO_MODE_OK(MODE)
Macro used by the assert function to check the different functions parameters.
#define | IS_GPIO_PIN_OK(PIN) ((PIN) != (uint8_t)0x00)
Macro used by the assert function in order to check the different values of GPIO_Pins.

Define Documentation

#define IS_GPIO_MODE_OK ( MODE )
Value:
(((MODE) == GPIO_MODE_IN_FL_NO_IT)    || \
   ((MODE) == GPIO_MODE_IN_PU_NO_IT)    || \
   ((MODE) == GPIO_MODE_IN_FL_IT)       || \
   ((MODE) == GPIO_MODE_IN_PU_IT)       || \
   ((MODE) == GPIO_MODE_OUT_OD_LOW_FAST)  || \
   ((MODE) == GPIO_MODE_OUT_PP_LOW_FAST)  || \
   ((MODE) == GPIO_MODE_OUT_OD_LOW_SLOW)  || \
   ((MODE) == GPIO_MODE_OUT_PP_LOW_SLOW)  || \
   ((MODE) == GPIO_MODE_OUT_OD_HIZ_FAST)  || \
   ((MODE) == GPIO_MODE_OUT_PP_HIGH_FAST)  || \
   ((MODE) == GPIO_MODE_OUT_OD_HIZ_SLOW)  || \
   ((MODE) == GPIO_MODE_OUT_PP_HIGH_SLOW))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert function in order to check the different values of GPIOMode_TypeDef.

Definition at line 104 of file stm8s_gpio.h.

Referenced by GPIO_Init().

#define IS_GPIO_PIN_OK ( PIN ) ((PIN) != (uint8_t)0x00)

Macro used by the assert function in order to check the different values of GPIO_Pins.

Definition at line 122 of file stm8s_gpio.h.

Referenced by GPIO_ExternalPullUpConfig(), and GPIO_Init().


STM8S/A Standard Peripherals Drivers: GPIO_Exported_Functions

Functions

GPIO_Exported_Functions

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ExternalPullUpConfig (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
Configures the external pull-up on GPIOx pins.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
Initializes the GPIOx according to the specified parameters.
uint8_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
BitStatus | GPIO_ReadInputPin (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
Reads the specified GPIO input data pin.
uint8_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint8_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteHigh (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes high level to the specified GPIO pins.
void | GPIO_WriteLow (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes low level to the specified GPIO pins.
void | GPIO_WriteReverse (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes reverse level to the specified GPIO pins.

Function Documentation

void GPIO_DeInit ( GPIO_TypeDef * GPIOx )

Deinitializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: Select the GPIO peripheral number (x = A to I).
Return values:
None

Definition at line 47 of file stm8s_gpio.c.

References GPIO_struct::CR1, GPIO_struct::CR2, GPIO_struct::DDR, GPIO_CR1_RESET_VALUE, GPIO_CR2_RESET_VALUE, GPIO_DDR_RESET_VALUE, GPIO_ODR_RESET_VALUE, and GPIO_struct::ODR.

void GPIO_ExternalPullUpConfig | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin,
 |  | FunctionalState | NewState
 | ) |  |

Configures the external pull-up on GPIOx pins.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : Specifies the pin number
NewState | : The new state of the pull up pin.
Return values:
None

Definition at line 219 of file stm8s_gpio.c.

References GPIO_struct::CR1, DISABLE, IS_FUNCTIONALSTATE_OK, and IS_GPIO_PIN_OK.

void GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin,
 |  | GPIO_Mode_TypeDef | GPIO_Mode
 | ) |  |

Initializes the GPIOx according to the specified parameters.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : This parameter contains the pin number, it can be any value of the GPIO_Pin_TypeDef enumeration.
GPIO_Mode | : This parameter can be a value of the GPIO_Mode_TypeDef enumeration.
Return values:
None

Definition at line 65 of file stm8s_gpio.c.

References GPIO_struct::CR1, GPIO_struct::CR2, GPIO_struct::DDR, IS_GPIO_MODE_OK, IS_GPIO_PIN_OK, and GPIO_struct::ODR.

uint8_t GPIO_ReadInputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO input data port.

Note:
The port must be configured in input mode.
Parameters:
GPIOx : Select the GPIO peripheral number (x = A to I).
Return values:
GPIO input data port value.

Definition at line 196 of file stm8s_gpio.c.

References GPIO_struct::IDR.

BitStatus GPIO_ReadInputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | GPIO_Pin
 | ) |  |

Reads the specified GPIO input data pin.

Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_Pin | : Specifies the pin number.
Return values:
BitStatus : GPIO input pin status.

Definition at line 207 of file stm8s_gpio.c.

References GPIO_struct::IDR.

uint8_t GPIO_ReadOutputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO output data port.

Note:
The port must be configured in input mode.
Parameters:
GPIOx : Select the GPIO peripheral number (x = A to I).
Return values:
GPIO output data port value.

Definition at line 185 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_Write | ( | GPIO_TypeDef * | GPIOx,
 |  | uint8_t | PortVal
 | ) |  |

Writes data to the specified GPIO data port.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
GPIO_PortVal | : Specifies the value to be written to the port output data register.
Return values:
None

Definition at line 135 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteHigh | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes high level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be turned high to the port output. data register.
Return values:
None

Definition at line 148 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteLow | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes low level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be turned low to the port output. data register.
Return values:
None

Definition at line 161 of file stm8s_gpio.c.

References GPIO_struct::ODR.

void GPIO_WriteReverse | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_Pin_TypeDef | PortPins
 | ) |  |

Writes reverse level to the specified GPIO pins.

Note:
The port must be configured in output mode.
Parameters:
GPIOx | : Select the GPIO peripheral number (x = A to I).
PortPins | : Specifies the pins to be reversed to the port output. data register.
Return values:
None

Definition at line 174 of file stm8s_gpio.c.

References GPIO_struct::ODR.


STM8S/A Standard Peripherals Drivers: I2C_Exported_Types

Enumerations

I2C_Exported_Types

Enumerations

enum | I2C_Ack_TypeDef { I2C_ACK_NONE = (uint8_t)0x00, I2C_ACK_CURR = (uint8_t)0x01, I2C_ACK_NEXT = (uint8_t)0x02 }

I2C Acknowledgement configuration.

More...
enum | I2C_AddMode_TypeDef { I2C_ADDMODE_7BIT = (uint8_t)0x00, I2C_ADDMODE_10BIT = (uint8_t)0x80 }

I2C Addressing Mode (slave mode only)

More...
enum | I2C_Direction_TypeDef { I2C_DIRECTION_TX = (uint8_t)0x00, I2C_DIRECTION_RX = (uint8_t)0x01 }

I2C transfer direction Warning: the values correspond to the ADD0 bit position in the OARL register.

More...
enum | I2C_DutyCycle_TypeDef { I2C_DUTYCYCLE_2 = (uint8_t)0x00, I2C_DUTYCYCLE_16_9 = (uint8_t)0x40 }

I2C duty cycle (fast mode only)

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enum I2C_Event_TypeDef {
I2C_EVENT_MASTER_MODE_SELECT = (uint16_t)0x0301, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = (uint16_t)0x0302, I2C_EVENT_MASTER_MODE_ADDRESS10 = (uint16_t)0x0308,
I2C_EVENT_MASTER_BYTE_RECEIVED = (uint16_t)0x0340, I2C_EVENT_MASTER_BYTE_TRANSMITTING = (uint16_t)0x0780, I2C_EVENT_MASTER_BYTE_TRANSMITTED = (uint16_t)0x0784, I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = (uint16_t)0x0202,
I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682, I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = (uint16_t)0x1200, I2C_EVENT_SLAVE_BYTE_RECEIVED = (uint16_t)0x0240, I2C_EVENT_SLAVE_STOP_DETECTED = (uint16_t)0x0010,
I2C_EVENT_SLAVE_BYTE_TRANSMITTED = (uint16_t)0x0684, I2C_EVENT_SLAVE_BYTE_TRANSMITTING = (uint16_t)0x0680, I2C_EVENT_SLAVE_ACK_FAILURE = (uint16_t)0x0004
}

I2C possible events Values convention: 0xXXYY XX = Event SR3 corresponding value YY = Event SR1 corresponding value.

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enum I2C_Flag_TypeDef {
I2C_FLAG_TXEMPTY = (uint16_t)0x0180, I2C_FLAG_RXNOTEMPTY = (uint16_t)0x0140, I2C_FLAG_STOPDETECTION = (uint16_t)0x0110, I2C_FLAG_HEADERSENT = (uint16_t)0x0108,
I2C_FLAG_TRANSFERFINISHED = (uint16_t)0x0104, I2C_FLAG_ADDRESSSENTMATCHED = (uint16_t)0x0102, I2C_FLAG_STARTDETECTION = (uint16_t)0x0101, I2C_FLAG_WAKEUPFROMHALT = (uint16_t)0x0220,
I2C_FLAG_OVERRUNUNDERRUN = (uint16_t)0x0208, I2C_FLAG_ACKNOWLEDGEFAILURE = (uint16_t)0x0204, I2C_FLAG_ARBITRATIONLOSS = (uint16_t)0x0202, I2C_FLAG_BUSERROR = (uint16_t)0x0201,
I2C_FLAG_GENERALCALL = (uint16_t)0x0310, I2C_FLAG_TRANSMITTERRECEIVER = (uint16_t)0x0304, I2C_FLAG_BUSBUSY = (uint16_t)0x0302, I2C_FLAG_MASTERSLAVE = (uint16_t)0x0301
}

I2C Flags.

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enum | I2C_IT_TypeDef { I2C_IT_ERR = (uint8_t)0x01, I2C_IT_EVT = (uint8_t)0x02, I2C_IT_BUF = (uint8_t)0x04 }

I2C Interrupt sources Warning: the values correspond to the bit position in the ITR register.

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enum I2C_ITPendingBit_TypeDef {
I2C_ITPENDINGBIT_TXEMPTY = (uint16_t)0x1680, I2C_ITPENDINGBIT_RXNOTEMPTY = (uint16_t)0x1640, I2C_ITPENDINGBIT_STOPDETECTION = (uint16_t)0x1210, I2C_ITPENDINGBIT_HEADERSENT = (uint16_t)0x1208,
I2C_ITPENDINGBIT_TRANSFERFINISHED = (uint16_t)0x1204, I2C_ITPENDINGBIT_ADDRESSSENTMATCHED = (uint16_t)0x1202, I2C_ITPENDINGBIT_STARTDETECTION = (uint16_t)0x1201, I2C_ITPENDINGBIT_WAKEUPFROMHALT = (uint16_t)0x2220,
I2C_ITPENDINGBIT_OVERRUNUNDERRUN = (uint16_t)0x2108, I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE = (uint16_t)0x2104, I2C_ITPENDINGBIT_ARBITRATIONLOSS = (uint16_t)0x2102, I2C_ITPENDINGBIT_BUSERROR = (uint16_t)0x2101
}

I2C Pending bits Elements values convention: 0xXYZZ X = SRx registers index X = 1 : SR1 X = 2 : SR2 Y = Position of the corresponding Interrupt ZZ = flag mask in the dedicated register(X register)

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Enumeration Type Documentation

enum I2C_Ack_TypeDef

I2C Acknowledgement configuration.

Enumerator:
I2C_ACK_NONE

No acknowledge

I2C_ACK_CURR

Acknowledge on the current byte

I2C_ACK_NEXT

Acknowledge on the next byte

Definition at line 47 of file stm8s_i2c.h.

enum I2C_AddMode_TypeDef

I2C Addressing Mode (slave mode only)

Enumerator:
I2C_ADDMODE_7BIT

7-bit slave address (10-bit address not acknowledged)

I2C_ADDMODE_10BIT

10-bit slave address (7-bit address not acknowledged)

Definition at line 57 of file stm8s_i2c.h.

enum I2C_Direction_TypeDef

I2C transfer direction Warning: the values correspond to the ADD0 bit position in the OARL register.

Enumerator:
I2C_DIRECTION_TX

Transmission direction

I2C_DIRECTION_RX

Reception direction

Definition at line 78 of file stm8s_i2c.h.

enum I2C_DutyCycle_TypeDef

I2C duty cycle (fast mode only)

Enumerator:
I2C_DUTYCYCLE_2

Fast mode Tlow/THigh = 2

I2C_DUTYCYCLE_16_9

Fast mode Tlow/Thigh = 16/9

Definition at line 38 of file stm8s_i2c.h.

enum I2C_Event_TypeDef

I2C possible events Values convention: 0xXXYY XX = Event SR3 corresponding value YY = Event SR1 corresponding value.

Note:
if Event = EV3_2 the rule above does not apply YY = Event SR2 corresponding value
Enumerator:
I2C_EVENT_MASTER_MODE_SELECT

Communication start.

After sending the START condition (I2C_GenerateSTART() function) the master has to wait for this event. It means that the Start condition has been correctly released on the I2C bus (the bus is free, no other devices is communicating). BUSY, MSL and SB flag

I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED

Address Acknowledge.

After checking on EV5 (start condition correctly released on the bus), the master sends the address of the slave(s) with which it will communicate (I2C_Send7bitAddress() function, it also determines the direction of the communication: Master transmitter or Receiver). Then the master has to wait that a slave acknowledges his address. If an acknowledge is sent on the bus, one of the following events will be set:

1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.

2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set

3) In case of 10-Bit addressing mode, the master (just after generating the START and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() function). Then master should wait on EV9. It means that the 10-bit addressing header has been correctly sent on the bus. Then master should send the second part of the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master should wait for event EV6. BUSY, MSL, ADDR, TXE and TRA flags

I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED

BUSY, MSL and ADDR flags

I2C_EVENT_MASTER_MODE_ADDRESS10

BUSY, MSL and ADD10 flags

I2C_EVENT_MASTER_BYTE_RECEIVED

Communication events.

If a communication is established (START condition generated and slave address acknowledged) then the master has to check on one of the following events for communication procedures:

1) Master Receiver mode: The master has to wait on the event EV7 then to read the data received from the slave (I2C_ReceiveData() function).

2) Master Transmitter mode: The master has to send data (I2C_SendData() function) then to wait on event EV8 or EV8_2. These two events are similar:

  • EV8 means that the data has been written in the data register and is being shifted out.
  • EV8_2 means that the data has been physically shifted out and output on the bus. In most cases, using EV8 is sufficient for the application. Using EV8_2 leads to a slower communication but ensures more reliable test. EV8_2 is also more suitable than EV8 for testing on the last data transmission (before Stop condition generation).
Note:
In case the user software does not guarantee that this event EV7 is managed before the current byte end of transfer, then user may check on EV7 and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower. BUSY, MSL and RXNE flags
I2C_EVENT_MASTER_BYTE_TRANSMITTING

TRA, BUSY, MSL, TXE flags

I2C_EVENT_MASTER_BYTE_TRANSMITTED

EV8_2: TRA, BUSY, MSL, TXE and BTF flags

I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED

Communication start events.

Wait on one of these events at the start of the communication. It means that the I2C peripheral detected a Start condition on the bus (generated by master device) followed by the peripheral address. The peripheral generates an ACK condition on the bus (if the acknowledge feature is enabled through function I2C_AcknowledgeConfig()) and the events listed above are set :

1) In normal case (only one address managed by the slave), when the address sent by the master matches the own address of the peripheral (configured by I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set (where XXX could be TRANSMITTER or RECEIVER).

2) In case the address sent by the master is General Call (address 0x00) and if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. BUSY and ADDR flags

I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED

TRA, BUSY, TXE and ADDR flags

I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED

EV2: GENCALL and BUSY flags

I2C_EVENT_SLAVE_BYTE_RECEIVED

Communication events.

Wait on one of these events when EV1 has already been checked :

  • Slave RECEIVER mode:
    • EV2: When the application is expecting a data byte to be received.
    • EV4: When the application is expecting the end of the communication: master sends a stop condition and data transmission is stopped.
  • Slave Transmitter mode:
    • EV3: When a byte has been transmitted by the slave and the application is expecting the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be used when the user software doesn't guarantee the EV3 is managed before the current byte end of tranfer.
    • EV3_2: When the master sends a NACK in order to tell slave that data transmission shall end (before sending the STOP condition). In this case slave has to stop sending data bytes and expect a Stop condition on the bus.
Note:
In case the user software does not guarantee that the event EV2 is managed before the current byte end of transfer, then user may check on EV2 and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower. BUSY and RXNE flags
I2C_EVENT_SLAVE_STOP_DETECTED

STOPF flag

I2C_EVENT_SLAVE_BYTE_TRANSMITTED

TRA, BUSY, TXE and BTF flags

I2C_EVENT_SLAVE_BYTE_TRANSMITTING

TRA, BUSY and TXE flags

I2C_EVENT_SLAVE_ACK_FAILURE

AF flag

Definition at line 157 of file stm8s_i2c.h.

enum I2C_Flag_TypeDef

I2C Flags.

Elements values convention: 0xXXYY X = SRx registers index X = 1 : SR1 X = 2 : SR2 X = 3 : SR3 Y = Flag mask in the register

Enumerator:
I2C_FLAG_TXEMPTY

Transmit Data Register Empty flag

I2C_FLAG_RXNOTEMPTY

Read Data Register Not Empty flag

I2C_FLAG_STOPDETECTION

Stop detected flag

I2C_FLAG_HEADERSENT

10-bit Header sent flag

I2C_FLAG_TRANSFERFINISHED

Data Byte Transfer Finished flag

I2C_FLAG_ADDRESSSENTMATCHED

Address Sent/Matched (master/slave) flag

I2C_FLAG_STARTDETECTION

Start bit sent flag

I2C_FLAG_WAKEUPFROMHALT

Wake Up From Halt Flag

I2C_FLAG_OVERRUNUNDERRUN

Overrun/Underrun flag

I2C_FLAG_ACKNOWLEDGEFAILURE

Acknowledge Failure Flag

I2C_FLAG_ARBITRATIONLOSS

Arbitration Loss Flag

I2C_FLAG_BUSERROR

Misplaced Start or Stop condition

I2C_FLAG_GENERALCALL

General Call header received Flag

I2C_FLAG_TRANSMITTERRECEIVER

Transmitter Receiver Flag

I2C_FLAG_BUSBUSY

Bus Busy Flag

I2C_FLAG_MASTERSLAVE

Master Slave Flag

Definition at line 94 of file stm8s_i2c.h.

enum I2C_IT_TypeDef

I2C Interrupt sources Warning: the values correspond to the bit position in the ITR register.

Enumerator:
I2C_IT_ERR

Error Interruption

I2C_IT_EVT

Event Interruption

I2C_IT_BUF

Buffer Interruption

Definition at line 67 of file stm8s_i2c.h.

enum I2C_ITPendingBit_TypeDef

I2C Pending bits Elements values convention: 0xXYZZ X = SRx registers index X = 1 : SR1 X = 2 : SR2 Y = Position of the corresponding Interrupt ZZ = flag mask in the dedicated register(X register)

Enumerator:
I2C_ITPENDINGBIT_TXEMPTY

Transmit Data Register Empty

I2C_ITPENDINGBIT_RXNOTEMPTY

Read Data Register Not Empty

I2C_ITPENDINGBIT_STOPDETECTION

Stop detected

I2C_ITPENDINGBIT_HEADERSENT

10-bit Header sent

I2C_ITPENDINGBIT_TRANSFERFINISHED

Data Byte Transfer Finished

I2C_ITPENDINGBIT_ADDRESSSENTMATCHED

Address Sent/Matched (master/slave)

I2C_ITPENDINGBIT_STARTDETECTION

Start bit sent

I2C_ITPENDINGBIT_WAKEUPFROMHALT

Wake Up From Halt

I2C_ITPENDINGBIT_OVERRUNUNDERRUN

Overrun/Underrun

I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE

Acknowledge Failure

I2C_ITPENDINGBIT_ARBITRATIONLOSS

Arbitration Loss

I2C_ITPENDINGBIT_BUSERROR

Misplaced Start or Stop condition

Definition at line 129 of file stm8s_i2c.h.


STM8S/A Standard Peripherals Drivers: I2C_Exported_Constants

Defines

I2C_Exported_Constants

Defines

#define | I2C_MAX_FAST_FREQ ((uint32_t)400000)
#define | I2C_MAX_INPUT_FREQ ((uint8_t)16)
#define | I2C_MAX_STANDARD_FREQ ((uint32_t)100000)

Define Documentation

#define I2C_MAX_FAST_FREQ ((uint32_t)400000)

Definition at line 330 of file stm8s_i2c.h.

#define I2C_MAX_INPUT_FREQ ((uint8_t)16)

Definition at line 334 of file stm8s_i2c.h.

#define I2C_MAX_STANDARD_FREQ ((uint32_t)100000)

Definition at line 329 of file stm8s_i2c.h.

Referenced by I2C_Init().


STM8S/A Standard Peripherals Drivers: I2C_Private_Macros

Defines

I2C_Private_Macros

Defines

#define | IS_I2C_ACK_OK(ACK)
Macro used by the assert function to check the different acknowledgement configuration.
#define | IS_I2C_ADDMODE_OK(ADDMODE)
Macro used by the assert function to check the different I2C addressing modes.
#define | IS_I2C_ADDRESS_OK(ADD) (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)
#define | IS_I2C_CLEAR_FLAG_OK(FLAG)
Macro used by the assert function to check the I2C flags to clear.
#define | IS_I2C_CLEAR_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the different I2C possible pending bits to clear by writing 0.
#define | IS_I2C_DIRECTION_OK(DIR)
Macro used by the assert function to check the different I2C communcation direction.
#define | IS_I2C_DUTYCYCLE_OK(DUTY)
Macro used by the assert function to check the different functions parameters.
#define | IS_I2C_EVENT_OK(EVENT)
Macro used by the assert function to check the different I2C possible events.
#define | IS_I2C_FLAG_OK(FLAG)
Macro used by the assert function to check the different I2C flags.
#define | IS_I2C_INPUT_CLOCK_FREQ_OK(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_INPUT_FREQ))
Macro used by the assert function to check that I2C Input clock frequency must be between 1MHz and 50MHz.
#define | IS_I2C_INTERRUPT_OK(IT)
Macro used by the assert function to check the different I2C interrupt types.
#define | IS_I2C_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the different I2C possible pending bits.
#define | IS_I2C_OUTPUT_CLOCK_FREQ_OK(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))
Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.
#define | IS_I2C_OWN_ADDRESS_OK(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
Macro used by the assert function to check the different I2C possible own address.

Define Documentation

#define IS_I2C_ACK_OK ( ACK )
Value:
(((ACK) == I2C_ACK_NONE) || \
   ((ACK) == I2C_ACK_CURR) || \
   ((ACK) == I2C_ACK_NEXT))

Macro used by the assert function to check the different acknowledgement configuration.

Definition at line 362 of file stm8s_i2c.h.

Referenced by I2C_AcknowledgeConfig(), and I2C_Init().

#define IS_I2C_ADDMODE_OK ( ADDMODE )
Value:
(((ADDMODE) == I2C_ADDMODE_7BIT) || \
   ((ADDMODE) == I2C_ADDMODE_10BIT))

Macro used by the assert function to check the different I2C addressing modes.

Definition at line 370 of file stm8s_i2c.h.

Referenced by I2C_Init().

#define IS_I2C_ADDRESS_OK ( ADD ) (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)

Definition at line 474 of file stm8s_i2c.h.

Referenced by I2C_Send7bitAddress().

#define IS_I2C_CLEAR_FLAG_OK ( FLAG )
Value:
((((uint16_t)(FLAG) & (uint16_t)0xFD00) == 0x00) \
                                     && ((uint16_t)(FLAG) != 0x00))

Macro used by the assert function to check the I2C flags to clear.

Definition at line 416 of file stm8s_i2c.h.

Referenced by I2C_ClearFlag().

#define IS_I2C_CLEAR_ITPENDINGBIT_OK ( ITPENDINGBIT )
Value:
(((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT)     || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN)    || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS)    || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))

Macro used by the assert function to check the different I2C possible pending bits to clear by writing 0.

Definition at line 440 of file stm8s_i2c.h.

Referenced by I2C_ClearITPendingBit().

#define IS_I2C_DIRECTION_OK ( DIR )
Value:
(((DIR) == I2C_DIRECTION_TX) || \
   ((DIR) == I2C_DIRECTION_RX))

Macro used by the assert function to check the different I2C communcation direction.

Definition at line 388 of file stm8s_i2c.h.

Referenced by I2C_Send7bitAddress().

#define IS_I2C_DUTYCYCLE_OK ( DUTY )
Value:
(((DUTY) == I2C_DUTYCYCLE_2) || \
   ((DUTY) == I2C_DUTYCYCLE_16_9))

Macro used by the assert function to check the different functions parameters.

Macro used by the assert function to check the different I2C duty cycles.

Definition at line 355 of file stm8s_i2c.h.

Referenced by I2C_FastModeDutyCycleConfig(), and I2C_Init().

#define IS_I2C_EVENT_OK ( EVENT )
Value:
(((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_GENERALCALL)) || \
                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_GENERALCALL)) || \
                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE) || \
                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10))

Macro used by the assert function to check the different I2C possible events.

Definition at line 450 of file stm8s_i2c.h.

Referenced by I2C_CheckEvent().

#define IS_I2C_FLAG_OK ( FLAG )
Value:
(((FLAG) == I2C_FLAG_TXEMPTY)         || \
   ((FLAG) == I2C_FLAG_RXNOTEMPTY)       || \
   ((FLAG) == I2C_FLAG_STOPDETECTION)      || \
   ((FLAG) == I2C_FLAG_HEADERSENT)       || \
   ((FLAG) == I2C_FLAG_TRANSFERFINISHED)   || \
   ((FLAG) == I2C_FLAG_ADDRESSSENTMATCHED)  || \
   ((FLAG) == I2C_FLAG_STARTDETECTION)    || \
   ((FLAG) == I2C_FLAG_WAKEUPFROMHALT)    || \
   ((FLAG) == I2C_FLAG_OVERRUNUNDERRUN)    || \
   ((FLAG) == I2C_FLAG_ACKNOWLEDGEFAILURE)  || \
   ((FLAG) == I2C_FLAG_ARBITRATIONLOSS)    || \
   ((FLAG) == I2C_FLAG_BUSERROR)       || \
   ((FLAG) == I2C_FLAG_GENERALCALL)      || \
   ((FLAG) == I2C_FLAG_TRANSMITTERRECEIVER) || \
   ((FLAG) == I2C_FLAG_BUSBUSY) || \
   ((FLAG) == I2C_FLAG_MASTERSLAVE))

Macro used by the assert function to check the different I2C flags.

Definition at line 395 of file stm8s_i2c.h.

Referenced by I2C_GetFlagStatus().

#define IS_I2C_INPUT_CLOCK_FREQ_OK ( FREQ ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_INPUT_FREQ))

Macro used by the assert function to check that I2C Input clock frequency must be between 1MHz and 50MHz.

Definition at line 480 of file stm8s_i2c.h.

Referenced by I2C_Init().

#define IS_I2C_INTERRUPT_OK ( IT )
Value:
(((IT) == I2C_IT_ERR)     || \
   ((IT) == I2C_IT_EVT)     || \
   ((IT) == I2C_IT_BUF)     || \
   ((IT) == (I2C_IT_ERR | I2C_IT_EVT)) || \
   ((IT) == (I2C_IT_ERR | I2C_IT_BUF)) || \
   ((IT) == (I2C_IT_EVT | I2C_IT_BUF)) || \
   ((IT) == (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR)))

Macro used by the assert function to check the different I2C interrupt types.

Definition at line 377 of file stm8s_i2c.h.

Referenced by I2C_ITConfig().

#define IS_I2C_ITPENDINGBIT_OK ( ITPENDINGBIT )
Value:
(((ITPENDINGBIT) == I2C_ITPENDINGBIT_TXEMPTY)                                           || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_RXNOTEMPTY)                             || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STOPDETECTION)                  || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_HEADERSENT)                             || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_TRANSFERFINISHED)       || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ADDRESSSENTMATCHED) || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STARTDETECTION)                 || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT)                 || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN)                || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS)                || \
    ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))

Macro used by the assert function to check the different I2C possible pending bits.

Definition at line 422 of file stm8s_i2c.h.

Referenced by I2C_GetITStatus().

#define IS_I2C_OUTPUT_CLOCK_FREQ_OK ( FREQ ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))

Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.

Definition at line 487 of file stm8s_i2c.h.

Referenced by I2C_Init().

#define IS_I2C_OWN_ADDRESS_OK ( ADDRESS ) ((ADDRESS) <= (uint16_t)0x03FF)

Macro used by the assert function to check the different I2C possible own address.

Definition at line 470 of file stm8s_i2c.h.

Referenced by I2C_Init().


STM8S/A Standard Peripherals Drivers: I2C_Exported_Functions

Functions

I2C_Exported_Functions

Functions

void | I2C_AcknowledgeConfig (I2C_Ack_TypeDef Ack)
Enable or Disable the I2C acknowledge and position acknowledge feature.
ErrorStatus | I2C_CheckEvent (I2C_Event_TypeDef I2C_Event)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_Flag_TypeDef I2C_FLAG)
Clear flags.
void | I2C_ClearITPendingBit (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Clear IT pending bit.
void | I2C_Cmd (FunctionalState NewState)
Enables or disables the I2C peripheral.
void | I2C_DeInit (void)
Deinitializes the I2C peripheral registers to their default reset values.
void | I2C_FastModeDutyCycleConfig (I2C_DutyCycle_TypeDef I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (FunctionalState NewState)
Enables or disables the I2C General Call feature.
void | I2C_GenerateSTART (FunctionalState NewState)
Generates I2C communication START condition.
void | I2C_GenerateSTOP (FunctionalState NewState)
Generates I2C communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_Flag_TypeDef I2C_Flag)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Checks whether the specified I2C interrupt has occurred or not.
I2C_Event_TypeDef | I2C_GetLastEvent (void)
2) Advanced state monitoring
void | I2C_Init (uint32_t OutputClockFrequencyHz, uint16_t OwnAddress, I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack, I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz)
Initializes the I2C according to the specified parameters in standard or fast mode.
void | I2C_ITConfig (I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupt.
uint8_t | I2C_ReceiveData (void)
Returns the most recent received data.
void | I2C_Send7bitAddress (uint8_t Address, I2C_Direction_TypeDef Direction)
Transmits the 7-bit address (to select the) slave device.
void | I2C_SendData (uint8_t Data)
Send a byte by writing in the DR register.
void | I2C_SoftwareResetCmd (FunctionalState NewState)
Enables or disables I2C software reset.
void | I2C_StretchClockCmd (FunctionalState NewState)
Enables or disables the I2C clock stretching.

Function Documentation

void I2C_AcknowledgeConfig ( I2C_Ack_TypeDef Ack )

Enable or Disable the I2C acknowledge and position acknowledge feature.

Note:
This function must be called before data reception start
Parameters:
Ack : Specifies the acknowledge mode to apply. This parameter can be any of the I2C_Ack_TypeDef enumeration.
Return values:
None

Definition at line 343 of file stm8s_i2c.c.

References I2C, I2C_ACK_CURR, I2C_ACK_NONE, I2C_CR2_ACK, I2C_CR2_POS, and IS_I2C_ACK_OK.

Referenced by I2C_Init().

ErrorStatus I2C_CheckEvent ( I2C_Event_TypeDef I2C_Event )

I2C State Monitoring Functions.

This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints:

1) Basic state monitoring: Using I2C_CheckEvent() function: It compares the status registers (SR1, SR2 and SR3) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status.

  • When to use:
    • This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0016).
    • It is also suitable for users who need to define their own events.
  • Limitations:
    • If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler.
Note:
For error management, it is advised to use the following functions:
  • I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  • I2C_IRQHandler() which is called when the I2C interurpts occur.
  • I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_IRQHandler() function in order to determine which error occured.
  • I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status.

2) Advanced state monitoring: Using the function I2C_GetLastEvent() which returns the image of both SR1 & SR3 status registers in a single word (uint16_t) (Status Register 3 value is shifted left by 8 bits and concatenated to Status Register 1).

  • When to use:
    • This function is suitable for the same applications above but it allows to overcome the limitations of I2C_GetFlagStatus() function (see below). The returned value could be compared to events already defined in the library (stm8s_i2c.h) or to custom values defined by user.
    • This function is suitable when multiple flags are monitored at the same time.
    • At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function).
  • Limitations:
    • User may need to define his own events.
    • Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags).

3) Flag-based state monitoring: Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...).

  • When to use:
    • This function could be used for specific applications or in debug phase.
    • It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags).
  • Limitations:
    • When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones.
    • Function may need to be called twice or more in order to monitor one single event.

1) Basic state monitoring

This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints:

1) Basic state monitoring: Using I2C_CheckEvent() function: It compares the status registers (SR1, SR2 and SR3) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status.

  • When to use:
    • This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0016).
    • It is also suitable for users who need to define their own events.
  • Limitations:
    • If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler.
Note:
For error management, it is advised to use the following functions:
  • I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  • I2C_IRQHandler() which is called when the I2C interurpts occur.
  • I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2C_IRQHandler() function in order to determine which error occured.
  • I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status.

2) Advanced state monitoring: Using the function I2C_GetLastEvent() which returns the image of both SR1 & SR3 status registers in a single word (uint16_t) (Status Register 3 value is shifted left by 8 bits and concatenated to Status Register 1).

  • When to use:
    • This function is suitable for the same applications above but it allows to overcome the limitations of I2C_GetFlagStatus() function (see below). The returned value could be compared to events already defined in the library (stm8s_i2c.h) or to custom values defined by user.
    • This function is suitable when multiple flags are monitored at the same time.
    • At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function).
  • Limitations:
    • User may need to define his own events.
    • Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags).

3) Flag-based state monitoring: Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...).

  • When to use:
    • This function could be used for specific applications or in debug phase.
    • It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags).
  • Limitations:
    • When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones.
    • Function may need to be called twice or more in order to monitor one single event.

For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.

1) Basic state monitoring Checks whether the last I2C Event is equal to the one passed as parameter.

Parameters:
I2C_EVENT,: specifies the event to be checked. This parameter can be one of the following values:

  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
  • I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
  • I2C_EVENT_SLAVE_STOP_DETECTED : EV4
  • I2C_EVENT_MASTER_MODE_SELECT : EV5
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
Note:
: For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Last event is equal to the I2C_EVENT
  • ERROR: Last event is different from the I2C_EVENT

Definition at line 579 of file stm8s_i2c.c.

References __IO, ERROR, I2C, I2C_EVENT_SLAVE_ACK_FAILURE, I2C_SR2_AF, IS_I2C_EVENT_OK, and SUCCESS.

void I2C_ClearFlag ( I2C_Flag_TypeDef I2C_FLAG )

Clear flags.

Parameters:
I2C_Flag : Specifies the flag to clear This parameter can be any combination of the following values:

  • I2C_FLAG_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_FLAG_BUSERROR: Bus error flag.
Note:
Notes:
  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_CR2 register.
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the second byte of the address in DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to I2C_SR3 register ((void)(I2C->SR3)).
  • SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 760 of file stm8s_i2c.c.

References FLAG_Mask, I2C, and IS_I2C_CLEAR_FLAG_OK.

void I2C_ClearITPendingBit ( I2C_ITPendingBit_TypeDef I2C_ITPendingBit )

Clear IT pending bit.

Parameters:
I2C_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun interrupt (Slave mode)
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure interrupt
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost interrupt (Master mode)
  • I2C_ITPENDINGBIT_BUSERROR: Bus error interrupt

Notes:

  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_CR2 register (I2C_AcknowledgeConfig() to configure the I2C peripheral Acknowledge).
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second byte of the address in I2C_DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to I2C_SR3 register ((void)(I2C->SR3)).
  • SB (Start Bit) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
    Return values:
    None

Definition at line 873 of file stm8s_i2c.c.

References FLAG_Mask, I2C, and IS_I2C_CLEAR_ITPENDINGBIT_OK.

void I2C_Cmd ( FunctionalState NewState )

Enables or disables the I2C peripheral.

Parameters:
NewState : Indicate the new I2C peripheral state. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 196 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_PE, and IS_FUNCTIONALSTATE_OK.

void I2C_DeInit ( void )

Deinitializes the I2C peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 61 of file stm8s_i2c.c.

References I2C, I2C_CCRH_RESET_VALUE, I2C_CCRL_RESET_VALUE, I2C_CR1_RESET_VALUE, I2C_CR2_RESET_VALUE, I2C_FREQR_RESET_VALUE, I2C_ITR_RESET_VALUE, I2C_OARH_RESET_VALUE, I2C_OARL_RESET_VALUE, and I2C_TRISER_RESET_VALUE.

void I2C_FastModeDutyCycleConfig ( I2C_DutyCycle_TypeDef I2C_DutyCycle )

Selects the specified I2C fast mode duty cycle.

Parameters:
I2C_DutyCycle : Specifies the duty cycle to apply. This parameter can be any of the I2C_DutyCycle_TypeDef enumeration.
Return values:
None

Definition at line 405 of file stm8s_i2c.c.

References I2C, I2C_CCRH_DUTY, I2C_DUTYCYCLE_16_9, and IS_I2C_DUTYCYCLE_OK.

void I2C_GeneralCallCmd ( FunctionalState NewState )

Enables or disables the I2C General Call feature.

Parameters:
NewState : State of the General Call feature. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 220 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_ENGC, and IS_FUNCTIONALSTATE_OK.

void I2C_GenerateSTART ( FunctionalState NewState )

Generates I2C communication START condition.

Note:
CCR must be programmed, i.e. I2C_Init function must have been called with a valid I2C_ClockSpeed
Parameters:
NewState : Enable or disable the start condition. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 246 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_START, and IS_FUNCTIONALSTATE_OK.

void I2C_GenerateSTOP ( FunctionalState NewState )

Generates I2C communication STOP condition.

Parameters:
NewState : Enable or disable the stop condition. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 270 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_STOP, and IS_FUNCTIONALSTATE_OK.

FlagStatus I2C_GetFlagStatus ( I2C_Flag_TypeDef I2C_Flag )

3) Flag-based state monitoring

Checks whether the specified I2C flag is set or not.

Parameters:
I2C_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • I2C_FLAG_GENERALCALL: General call header flag (Slave mode)
  • I2C_FLAG_TRANSMITTERRECEIVER: Transmitter/Receiver flag
  • I2C_FLAG_BUSBUSY: Bus busy flag
  • I2C_FLAG_MASTERSLAVE: Master/Slave flag
  • I2C_FLAG_WAKEUPFROMHALT: Wake up from HALT flag
  • I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_FLAG_BUSERROR: Bus error flag
  • I2C_FLAG_TXEMPTY: Data register empty flag (Transmitter)
  • I2C_FLAG_RXNOTEMPTY: Data register not empty (Receiver) flag
  • I2C_FLAG_STOPDETECTION: Stop detection flag (Slave mode)
  • I2C_FLAG_HEADERSENT: 10-bit header sent flag (Master mode)
  • I2C_FLAG_TRANSFERFINISHED: Byte transfer finished flag
  • I2C_FLAG_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL” Address matched flag (Slave mode)”ENDAD”
  • I2C_FLAG_STARTDETECTION: Start bit flag (Master mode)
Return values:
The new state of I2C_FLAG (SET or RESET).

Definition at line 680 of file stm8s_i2c.c.

References I2C, IS_I2C_FLAG_OK, RESET, and SET.

ITStatus I2C_GetITStatus ( I2C_ITPendingBit_TypeDef I2C_ITPendingBit )

Checks whether the specified I2C interrupt has occurred or not.

Parameters:
I2C_ITPendingBit,: specifies the interrupt source to check. This parameter can be one of the following values:

  • I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure flag
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
  • I2C_ITPENDINGBIT_BUSERROR: Bus error flag
  • I2C_ITPENDINGBIT_TXEMPTY: Data register empty flag (Transmitter)
  • I2C_ITPENDINGBIT_RXNOTEMPTY: Data register not empty (Receiver) flag
  • I2C_ITPENDINGBIT_STOPDETECTION: Stop detection flag (Slave mode)
  • I2C_ITPENDINGBIT_HEADERSENT: 10-bit header sent flag (Master mode)
  • I2C_ITPENDINGBIT_TRANSFERFINISHED: Byte transfer finished flag
  • I2C_ITPENDINGBIT_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL” Address matched flag (Slave mode)“ENDAD”
  • I2C_ITPENDINGBIT_STARTDETECTION: Start bit flag (Master mode)
Return values:
The new state of I2C_ITPendingBit This parameter can be any of the ITStatus enumeration.

Definition at line 792 of file stm8s_i2c.c.

References __IO, I2C, IS_I2C_ITPENDINGBIT_OK, ITEN_Mask, REGISTER_Mask, REGISTER_SR1_Index, RESET, and SET.

I2C_Event_TypeDef I2C_GetLastEvent ( void )

2) Advanced state monitoring

Returns the last I2C Event.

Note:
: For detailed description of Events, please refer to section I2C_Events in stm8s_i2c.h file.
Return values:
The last event This parameter can be any of the I2C_Event_TypeDef enumeration.

Definition at line 629 of file stm8s_i2c.c.

References __IO, I2C, I2C_EVENT_SLAVE_ACK_FAILURE, and I2C_SR2_AF.

void I2C_Init | ( | uint32_t | OutputClockFrequencyHz,
 |  | uint16_t | OwnAddress,
 |  | I2C_DutyCycle_TypeDef | I2C_DutyCycle,
 |  | I2C_Ack_TypeDef | Ack,
 |  | I2C_AddMode_TypeDef | AddMode,
 |  | uint8_t | InputClockFrequencyMHz
 | ) |  |

Initializes the I2C according to the specified parameters in standard or fast mode.

Parameters:
OutputClockFrequencyHz | : Specifies the output clock frequency in Hz.
OwnAddress | : Specifies the own address.
I2C_DutyCycle | : Specifies the duty cycle to apply in fast mode. This parameter can be any of the I2C_DutyCycle_TypeDef enumeration.
Note:
This parameter don't have impact when the OutputClockFrequency lower than 100KHz.
Parameters:
Ack | : Specifies the acknowledge mode to apply. This parameter can be any of the I2C_Ack_TypeDef enumeration.
AddMode | : Specifies the acknowledge address to apply. This parameter can be any of the I2C_AddMode_TypeDef enumeration.
InputClockFrequencyMHz | : Specifies the input clock frequency in MHz.
Return values:
None

Definition at line 90 of file stm8s_i2c.c.

References I2C, I2C_AcknowledgeConfig(), I2C_CCRH_CCR, I2C_CCRH_DUTY, I2C_CCRH_FS, I2C_CCRL_CCR, I2C_CR1_PE, I2C_DUTYCYCLE_2, I2C_FREQR_FREQ, I2C_MAX_STANDARD_FREQ, I2C_OARH_ADDCONF, IS_I2C_ACK_OK, IS_I2C_ADDMODE_OK, IS_I2C_DUTYCYCLE_OK, IS_I2C_INPUT_CLOCK_FREQ_OK, IS_I2C_OUTPUT_CLOCK_FREQ_OK, and IS_I2C_OWN_ADDRESS_OK.

void I2C_ITConfig | ( | I2C_IT_TypeDef | I2C_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C interrupt.

Parameters:
ITName | : Name of the interrupt to enable or disable. This parameter can be any of the I2C_IT_TypeDef enumeration.
NewState | : State of the interrupt to apply. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 380 of file stm8s_i2c.c.

References DISABLE, I2C, IS_FUNCTIONALSTATE_OK, and IS_I2C_INTERRUPT_OK.

uint8_t I2C_ReceiveData ( void )

Returns the most recent received data.

Parameters:
None
Return values:
uint8_t : The value of the received byte data.

Definition at line 428 of file stm8s_i2c.c.

References I2C.

void I2C_Send7bitAddress | ( | uint8_t | Address,
 |  | I2C_Direction_TypeDef | Direction
 | ) |  |

Transmits the 7-bit address (to select the) slave device.

Parameters:
Address | : Specifies the slave address which will be transmitted.
Direction | : Specifies whether the I2C device will be a Transmitter or a Receiver. This parameter can be any of the I2C_Direction_TypeDef enumeration.
Return values:
None

Definition at line 441 of file stm8s_i2c.c.

References I2C, IS_I2C_ADDRESS_OK, and IS_I2C_DIRECTION_OK.

void I2C_SendData ( uint8_t Data )

Send a byte by writing in the DR register.

Parameters:
Data : Byte to be sent.
Return values:
None

Definition at line 459 of file stm8s_i2c.c.

References I2C.

void I2C_SoftwareResetCmd ( FunctionalState NewState )

Enables or disables I2C software reset.

Parameters:
NewState : Specifies the new state of the I2C software reset. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 294 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR2_SWRST, and IS_FUNCTIONALSTATE_OK.

void I2C_StretchClockCmd ( FunctionalState NewState )

Enables or disables the I2C clock stretching.

Parameters:
NewState : Specifies the new state of the I2C Clock stretching. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 318 of file stm8s_i2c.c.

References DISABLE, I2C, I2C_CR1_NOSTRETCH, and IS_FUNCTIONALSTATE_OK.


STM8S/A Standard Peripherals Drivers: ITC_Exported_Types

Enumerations

ITC_Exported_Types

Enumerations

enum ITC_Irq_TypeDef {
ITC_IRQ_TLI = (uint8_t)0, ITC_IRQ_AWU = (uint8_t)1, ITC_IRQ_CLK = (uint8_t)2, ITC_IRQ_PORTA = (uint8_t)3,
ITC_IRQ_PORTB = (uint8_t)4, ITC_IRQ_PORTC = (uint8_t)5, ITC_IRQ_PORTD = (uint8_t)6, ITC_IRQ_PORTE = (uint8_t)7,
ITC_IRQ_SPI = (uint8_t)10, ITC_IRQ_TIM1_OVF = (uint8_t)11, ITC_IRQ_TIM1_CAPCOM = (uint8_t)12, ITC_IRQ_TIM2_OVF = (uint8_t)13,
ITC_IRQ_TIM2_CAPCOM = (uint8_t)14, ITC_IRQ_TIM3_OVF = (uint8_t)15, ITC_IRQ_TIM3_CAPCOM = (uint8_t)16, ITC_IRQ_UART1_TX = (uint8_t)17,
ITC_IRQ_UART1_RX = (uint8_t)18, ITC_IRQ_I2C = (uint8_t)19, ITC_IRQ_TIM4_OVF = (uint8_t)23, ITC_IRQ_EEPROM_EEC = (uint8_t)24
}

ITC Interrupt Lines selection.

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enum ITC_PriorityLevel_TypeDef { ITC_PRIORITYLEVEL_0 = (uint8_t)0x02, ITC_PRIORITYLEVEL_1 = (uint8_t)0x01, ITC_PRIORITYLEVEL_2 = (uint8_t)0x00, ITC_PRIORITYLEVEL_3 = (uint8_t)0x03 }

ITC Priority Levels selection.

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Enumeration Type Documentation

enum ITC_Irq_TypeDef

ITC Interrupt Lines selection.

Enumerator:
ITC_IRQ_TLI

Software interrupt

ITC_IRQ_AWU

Auto wake up from halt interrupt

ITC_IRQ_CLK

Clock controller interrupt

ITC_IRQ_PORTA

Port A external interrupts

ITC_IRQ_PORTB

Port B external interrupts

ITC_IRQ_PORTC

Port C external interrupts

ITC_IRQ_PORTD

Port D external interrupts

ITC_IRQ_PORTE

Port E external interrupts

ITC_IRQ_SPI

SPI interrupt

ITC_IRQ_TIM1_OVF

TIM1 update/overflow/underflow/trigger/ break interrupt

ITC_IRQ_TIM1_CAPCOM

TIM1 capture/compare interrupt

ITC_IRQ_TIM2_OVF

TIM2 update /overflow interrupt

ITC_IRQ_TIM2_CAPCOM

TIM2 capture/compare interrupt

ITC_IRQ_TIM3_OVF

TIM3 update /overflow interrupt

ITC_IRQ_TIM3_CAPCOM

TIM3 update /overflow interrupt

ITC_IRQ_UART1_TX

USART1 TX interrupt

ITC_IRQ_UART1_RX

USART1 RX interrupt

ITC_IRQ_I2C

I2C interrupt

ITC_IRQ_TIM4_OVF

TIM4 update /overflow interrupt

ITC_IRQ_EEPROM_EEC

Flash interrupt

Definition at line 38 of file stm8s_itc.h.

enum ITC_PriorityLevel_TypeDef

ITC Priority Levels selection.

Enumerator:
ITC_PRIORITYLEVEL_0

Software priority level 0 (cannot be written)

ITC_PRIORITYLEVEL_1

Software priority level 1

ITC_PRIORITYLEVEL_2

Software priority level 2

ITC_PRIORITYLEVEL_3

Software priority level 3

Definition at line 105 of file stm8s_itc.h.


STM8S/A Standard Peripherals Drivers: ITC_Exported_Constants

Defines

ITC_Exported_Constants

Defines

#define CPU_SOFT_INT_DISABLED ((uint8_t)0x28)

Define Documentation

#define CPU_SOFT_INT_DISABLED ((uint8_t)0x28)

Mask for I1 and I0 bits in CPU_CC register

Definition at line 122 of file stm8s_itc.h.


STM8S/A Standard Peripherals Drivers: ITC_Private_Macros

Defines

ITC_Private_Macros

Macros used by the assert function in order to check the different functions parameters. More...

Defines

#define | IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)
#define | IS_ITC_IRQ_OK(IRQ) ((IRQ) <= (uint8_t)24)
#define | IS_ITC_PRIORITY_OK(PriorityValue)

Detailed Description

Macros used by the assert function in order to check the different functions parameters.

Define Documentation

#define IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)

Definition at line 147 of file stm8s_itc.h.

Referenced by ITC_SetSoftwarePriority().

#define IS_ITC_IRQ_OK ( IRQ ) ((IRQ) <= (uint8_t)24)

Definition at line 137 of file stm8s_itc.h.

Referenced by ITC_GetSoftwarePriority(), and ITC_SetSoftwarePriority().

#define IS_ITC_PRIORITY_OK ( PriorityValue )
Value:
(((PriorityValue) == ITC_PRIORITYLEVEL_0) || \
   ((PriorityValue) == ITC_PRIORITYLEVEL_1) || \
   ((PriorityValue) == ITC_PRIORITYLEVEL_2) || \
   ((PriorityValue) == ITC_PRIORITYLEVEL_3))

Definition at line 140 of file stm8s_itc.h.

Referenced by ITC_SetSoftwarePriority().


STM8S/A Standard Peripherals Drivers: ITC_Exported_Functions

Functions

ITC_Exported_Functions

Functions

void | ITC_DeInit (void)
Deinitializes the ITC registers to their default reset value.
uint8_t | ITC_GetCPUCC (void)
Utility function used to read CC register.
uint8_t | ITC_GetSoftIntStatus (void)
Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
ITC_PriorityLevel_TypeDef | ITC_GetSoftwarePriority (ITC_Irq_TypeDef IrqNum)
Gets the software priority of the specified interrupt source.
void | ITC_SetSoftwarePriority (ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
Sets the software priority of the specified interrupt source.

Function Documentation

void ITC_DeInit ( void )

Deinitializes the ITC registers to their default reset value.

Parameters:
None
Return values:
None

Definition at line 74 of file stm8s_itc.c.

References ITC, and ITC_SPRX_RESET_VALUE.

uint8_t ITC_GetCPUCC ( void )

Utility function used to read CC register.

Parameters:
None
Return values:
CPU CC register value

Definition at line 44 of file stm8s_itc.c.

Referenced by ITC_GetSoftIntStatus().

uint8_t ITC_GetSoftIntStatus ( void )

Gets the interrupt software priority bits (I1, I0) value from CPU CC register.

Parameters:
None
Return values:
The interrupt software priority bits value.

Definition at line 91 of file stm8s_itc.c.

References CPU_CC_I1I0, and ITC_GetCPUCC().

ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority ( ITC_Irq_TypeDef IrqNum )

Gets the software priority of the specified interrupt source.

Parameters:
IrqNum : Specifies the peripheral interrupt source.
Return values:
ITC_PriorityLevel_TypeDef : Specifies the software priority of the interrupt source.

Definition at line 101 of file stm8s_itc.c.

References IS_ITC_IRQ_OK, ITC, ITC_IRQ_AWU, ITC_IRQ_CLK, ITC_IRQ_EEPROM_EEC, ITC_IRQ_I2C, ITC_IRQ_PORTA, ITC_IRQ_PORTB, ITC_IRQ_PORTC, ITC_IRQ_PORTD, ITC_IRQ_PORTE, ITC_IRQ_SPI, ITC_IRQ_TIM1_CAPCOM, ITC_IRQ_TIM1_OVF, ITC_IRQ_TIM2_CAPCOM, ITC_IRQ_TIM2_OVF, ITC_IRQ_TIM3_CAPCOM, ITC_IRQ_TIM3_OVF, ITC_IRQ_TIM4_OVF, ITC_IRQ_TLI, ITC_IRQ_UART1_RX, and ITC_IRQ_UART1_TX.

void ITC_SetSoftwarePriority | ( | ITC_Irq_TypeDef | IrqNum,
 |  | ITC_PriorityLevel_TypeDef | PriorityValue
 | ) |  |

Sets the software priority of the specified interrupt source.

Note:
- The modification of the software priority is only possible when the interrupts are disabled.
  • The normal behavior is to disable the interrupt before calling this function, and re-enable it after.
  • The priority level 0 cannot be set (see product specification for more details).
Parameters:
IrqNum | : Specifies the peripheral interrupt source.
PriorityValue | : Specifies the software priority value to set, can be a value of ITC_PriorityLevel_TypeDef .
Return values:
None

Definition at line 208 of file stm8s_itc.c.

References IS_ITC_INTERRUPTS_DISABLED, IS_ITC_IRQ_OK, IS_ITC_PRIORITY_OK, ITC, ITC_IRQ_AWU, ITC_IRQ_CLK, ITC_IRQ_EEPROM_EEC, ITC_IRQ_I2C, ITC_IRQ_PORTA, ITC_IRQ_PORTB, ITC_IRQ_PORTC, ITC_IRQ_PORTD, ITC_IRQ_PORTE, ITC_IRQ_SPI, ITC_IRQ_TIM1_CAPCOM, ITC_IRQ_TIM1_OVF, ITC_IRQ_TIM2_CAPCOM, ITC_IRQ_TIM2_OVF, ITC_IRQ_TIM3_CAPCOM, ITC_IRQ_TIM3_OVF, ITC_IRQ_TIM4_OVF, ITC_IRQ_TLI, ITC_IRQ_UART1_RX, and ITC_IRQ_UART1_TX.


STM8S/A Standard Peripherals Drivers: TIM2_Exported_Functions

Functions

TIM2_Exported_Functions

Functions

void | TIM2_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM2 peripheral Preload register on ARR.
void | TIM2_CCPreloadControl (FunctionalState NewState)
void | TIM2_CCxCmd (TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
Enables or disables the TIM2 Capture Compare Channel x.
void | TIM2_ClearFlag (TIM2_FLAG_TypeDef TIM2_FLAG)
Clears the TIM2’s pending flags.
void | TIM2_ClearITPendingBit (TIM2_IT_TypeDef TIM2_IT)
Clears the TIM2's interrupt pending bits.
void | TIM2_Cmd (FunctionalState NewState)
Enables or disables the TIM2 peripheral.
void | TIM2_DeInit (void)
Deinitializes the TIM2 peripheral registers to their default reset values.
void | TIM2_ForcedOC1Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel1 output waveform to active or inactive level.
void | TIM2_ForcedOC2Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel2 output waveform to active or inactive level.
void | TIM2_ForcedOC3Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel3 output waveform to active or inactive level.
void | TIM2_GenerateEvent (TIM2_EventSource_TypeDef TIM2_EventSource)
Configures the TIM2 event to be generated by software.
uint16_t | TIM2_GetCapture1 (void)
Gets the TIM2 Input Capture 1 value.
uint16_t | TIM2_GetCapture2 (void)
Gets the TIM2 Input Capture 2 value.
uint16_t | TIM2_GetCapture3 (void)
Gets the TIM2 Input Capture 3 value.
uint16_t | TIM2_GetCounter (void)
Gets the TIM2 Counter value.
FlagStatus | TIM2_GetFlagStatus (TIM2_FLAG_TypeDef TIM2_FLAG)
Checks whether the specified TIM2 flag is set or not.
ITStatus | TIM2_GetITStatus (TIM2_IT_TypeDef TIM2_IT)
Checks whether the TIM2 interrupt has occurred or not.
TIM2_Prescaler_TypeDef | TIM2_GetPrescaler (void)
Gets the TIM2 Prescaler value.
void | TIM2_ICInit (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Initializes the TIM2 peripheral according to the specified parameters.
void | TIM2_InternalClockConfig (void)
void | TIM2_ITConfig (TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
Enables or disables the specified TIM2 interrupts.
void | TIM2_OC1Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel1 according to the specified parameters.
void | TIM2_OC1PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 1 polarity.
void | TIM2_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR1.
void | TIM2_OC2Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel2 according to the specified parameters.
void | TIM2_OC2PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 2 polarity.
void | TIM2_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR2.
void | TIM2_OC3Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel3 according to the specified parameters.
void | TIM2_OC3PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 3 polarity.
void | TIM2_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR3.
void | TIM2_PrescalerConfig (TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
Configures the TIM2 Prescaler.
void | TIM2_PWMIConfig (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.
void | TIM2_SelectOCxM (TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
Selects the TIM2 Output Compare Mode.
void | TIM2_SelectOnePulseMode (TIM2_OPMode_TypeDef TIM2_OPMode)
Selects the TIM2’s One Pulse Mode.
void | TIM2_SetAutoreload (uint16_t Autoreload)
Sets the TIM2 Autoreload Register value.
void | TIM2_SetCompare1 (uint16_t Compare1)
Sets the TIM2 Capture Compare1 Register value.
void | TIM2_SetCompare2 (uint16_t Compare2)
Sets the TIM2 Capture Compare2 Register value.
void | TIM2_SetCompare3 (uint16_t Compare3)
Sets the TIM2 Capture Compare3 Register value.
void | TIM2_SetCounter (uint16_t Counter)
Sets the TIM2 Counter Register value.
void | TIM2_SetIC1Prescaler (TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
Sets the TIM2 Input Capture 1 Prescaler.
void | TIM2_SetIC2Prescaler (TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
Sets the TIM2 Input Capture 2 prescaler.
void | TIM2_SetIC3Prescaler (TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
Sets the TIM2 Input Capture 3 prescaler.
void | TIM2_TimeBaseInit (TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period)
Initializes the TIM2 Time Base Unit according to the specified parameters.
void | TIM2_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM2 Update event.
void | TIM2_UpdateRequestConfig (TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
Selects the TIM2 Update Request Interrupt source.

Function Documentation

void TIM2_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM2 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM2 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 567 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_ARPE.

void TIM2_CCPreloadControl ( FunctionalState NewState )
void TIM2_CCxCmd | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM2 Capture Compare Channel x.

Parameters:
TIM2_Channel specifies the TIM2 Channel. This parameter can be one of the following values:

  • TIM2_CHANNEL_1: TIM2 Channel1
  • TIM2_CHANNEL_2: TIM2 Channel2
  • TIM2_CHANNEL_3: TIM2 Channel3
NewState specifies the TIM2 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 759 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM2_CHANNEL_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC2E, TIM2_CCER2_CC3E, TIM2_CHANNEL_1, and TIM2_CHANNEL_2.

void TIM2_ClearFlag ( TIM2_FLAG_TypeDef TIM2_FLAG )

Clears the TIM2’s pending flags.

Parameters:
TIM2_FLAG specifies the flag to clear. This parameter can be one of the following values:

  • TIM2_FLAG_UPDATE: TIM2 update Flag
  • TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
  • TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
  • TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
  • TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
  • TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
  • TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
Return values:
None.

Definition at line 1132 of file stm8s_tim2.c.

References IS_TIM2_CLEAR_FLAG_OK.

void TIM2_ClearITPendingBit ( TIM2_IT_TypeDef TIM2_IT )

Clears the TIM2's interrupt pending bits.

Parameters:
TIM2_IT specifies the pending bit to clear. This parameter can be one of the following values:

  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
Return values:
None.

Definition at line 1188 of file stm8s_tim2.c.

References IS_TIM2_IT_OK.

void TIM2_Cmd ( FunctionalState NewState )

Enables or disables the TIM2 peripheral.

Parameters:
NewState new state of the TIM2 peripheral. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 339 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_CEN.

void TIM2_DeInit ( void )

Deinitializes the TIM2 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 46 of file stm8s_tim2.c.

References TIM2_ARRH_RESET_VALUE, TIM2_ARRL_RESET_VALUE, TIM2_CCER1_RESET_VALUE, TIM2_CCER2_RESET_VALUE, TIM2_CCMR1_RESET_VALUE, TIM2_CCMR2_RESET_VALUE, TIM2_CCMR3_RESET_VALUE, TIM2_CCR1H_RESET_VALUE, TIM2_CCR1L_RESET_VALUE, TIM2_CCR2H_RESET_VALUE, TIM2_CCR2L_RESET_VALUE, TIM2_CCR3H_RESET_VALUE, TIM2_CCR3L_RESET_VALUE, TIM2_CNTRH_RESET_VALUE, TIM2_CNTRL_RESET_VALUE, TIM2_CR1_RESET_VALUE, TIM2_IER_RESET_VALUE, TIM2_PSCR_RESET_VALUE, TIM2_SR1_RESET_VALUE, and TIM2_SR2_RESET_VALUE.

void TIM2_ForcedOC1Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel1 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 512 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_ForcedOC2Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel2 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 531 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_ForcedOC3Config ( TIM2_ForcedAction_TypeDef TIM2_ForcedAction )

Forces the TIM2 Channel3 output waveform to active or inactive level.

Parameters:
TIM2_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM2_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM2_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 550 of file stm8s_tim2.c.

References IS_TIM2_FORCED_ACTION_OK, and TIM2_CCMR_OCM.

void TIM2_GenerateEvent ( TIM2_EventSource_TypeDef TIM2_EventSource )

Configures the TIM2 event to be generated by software.

Parameters:
TIM2_EventSource specifies the event source. This parameter can be one of the following values:

  • TIM2_EVENTSOURCE_UPDATE: TIM2 update Event source
  • TIM2_EVENTSOURCE_CC1: TIM2 Capture Compare 1 Event source
  • TIM2_EVENTSOURCE_CC2: TIM2 Capture Compare 2 Event source
  • TIM2_EVENTSOURCE_CC3: TIM2 Capture Compare 3 Event source
Return values:
None

Definition at line 663 of file stm8s_tim2.c.

References IS_TIM2_EVENT_SOURCE_OK.

uint16_t TIM2_GetCapture1 ( void )

Gets the TIM2 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 1001 of file stm8s_tim2.c.

uint16_t TIM2_GetCapture2 ( void )

Gets the TIM2 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 1021 of file stm8s_tim2.c.

uint16_t TIM2_GetCapture3 ( void )

Gets the TIM2 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 1041 of file stm8s_tim2.c.

uint16_t TIM2_GetCounter ( void )

Gets the TIM2 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 1061 of file stm8s_tim2.c.

FlagStatus TIM2_GetFlagStatus ( TIM2_FLAG_TypeDef TIM2_FLAG )

Checks whether the specified TIM2 flag is set or not.

Parameters:
TIM2_FLAG specifies the flag to check. This parameter can be one of the following values:

  • TIM2_FLAG_UPDATE: TIM2 update Flag
  • TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
  • TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
  • TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
  • TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
  • TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
  • TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
Return values:
FlagStatus The new state of TIM2_FLAG (SET or RESET).

Definition at line 1096 of file stm8s_tim2.c.

References IS_TIM2_GET_FLAG_OK, RESET, and SET.

ITStatus TIM2_GetITStatus ( TIM2_IT_TypeDef TIM2_IT )

Checks whether the TIM2 interrupt has occurred or not.

Parameters:
TIM2_IT specifies the TIM2 interrupt source to check. This parameter can be one of the following values:

  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
Return values:
ITStatus The new state of the TIM2_IT(SET or RESET).

Definition at line 1154 of file stm8s_tim2.c.

References IS_TIM2_GET_IT_OK, RESET, and SET.

TIM2_Prescaler_TypeDef TIM2_GetPrescaler ( void )

Gets the TIM2 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM2_Prescaler_TypeDef.

Definition at line 1076 of file stm8s_tim2.c.

void TIM2_ICInit | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_ICPolarity_TypeDef | TIM2_ICPolarity,
 |  | TIM2_ICSelection_TypeDef | TIM2_ICSelection,
 |  | TIM2_ICPSC_TypeDef | TIM2_ICPrescaler,
 |  | uint8_t | TIM2_ICFilter
 | ) |  |

Initializes the TIM2 peripheral according to the specified parameters.

Parameters:
TIM2_Channel | specifies the Input Capture Channel from TIM2_Channel_TypeDef.
TIM2_ICPolarity | specifies the Input Capture Polarity from TIM2_ICPolarity_TypeDef.
TIM2_ICSelection | specifies the Input Capture Selection from TIM2_ICSelection_TypeDef.
TIM2_ICPrescaler | specifies the Input Capture Prescaler from TIM2_ICPSC_TypeDef.
TIM2_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 210 of file stm8s_tim2.c.

References IS_TIM2_CHANNEL_OK, IS_TIM2_IC_FILTER_OK, IS_TIM2_IC_POLARITY_OK, IS_TIM2_IC_PRESCALER_OK, IS_TIM2_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TIM2_CHANNEL_1, TIM2_CHANNEL_2, TIM2_SetIC1Prescaler(), TIM2_SetIC2Prescaler(), and TIM2_SetIC3Prescaler().

void TIM2_InternalClockConfig ( void )
void TIM2_ITConfig | ( | TIM2_IT_TypeDef | TIM2_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM2 interrupts.

Parameters:
NewState | new state of the TIM2 peripheral. This parameter can be: ENABLE or DISABLE.
TIM2_IT specifies the TIM2 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM2_IT_UPDATE: TIM2 update Interrupt source
  • TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
  • TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
  • TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
NewState | new state of the TIM2 peripheral.
Return values:
None

Definition at line 369 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM2_IT_OK.

void TIM2_OC1Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel1 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 104 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC1P, and TIM2_CCMR_OCM.

void TIM2_OC1PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 1 polarity.

Parameters:
TIM2_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:

  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 681 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER1_CC1P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 590 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_OC2Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel2 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 138 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER1_CC2E, TIM2_CCER1_CC2P, and TIM2_CCMR_OCM.

void TIM2_OC2PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 2 polarity.

Parameters:
TIM2_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:

  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 706 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER1_CC2P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 613 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_OC3Init | ( | TIM2_OCMode_TypeDef | TIM2_OCMode,
 |  | TIM2_OutputState_TypeDef | TIM2_OutputState,
 |  | uint16_t | TIM2_Pulse,
 |  | TIM2_OCPolarity_TypeDef | TIM2_OCPolarity
 | ) |  |

Initializes the TIM2 Channel3 according to the specified parameters.

Parameters:
TIM2_OCMode | specifies the Output Compare mode from TIM2_OCMode_TypeDef.
TIM2_OutputState | specifies the Output State from TIM2_OutputState_TypeDef.
TIM2_Pulse | specifies the Pulse width value.
TIM2_OCPolarity | specifies the Output Compare Polarity from TIM2_OCPolarity_TypeDef.
Return values:
None

Definition at line 175 of file stm8s_tim2.c.

References IS_TIM2_OC_MODE_OK, IS_TIM2_OC_POLARITY_OK, IS_TIM2_OUTPUT_STATE_OK, TIM2_CCER2_CC3E, TIM2_CCER2_CC3P, and TIM2_CCMR_OCM.

void TIM2_OC3PolarityConfig ( TIM2_OCPolarity_TypeDef TIM2_OCPolarity )

Configures the TIM2 Channel 3 polarity.

Parameters:
TIM2_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:

  • TIM2_OCPOLARITY_LOW: Output Compare active low
  • TIM2_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 731 of file stm8s_tim2.c.

References IS_TIM2_OC_POLARITY_OK, TIM2_CCER2_CC3P, and TIM2_OCPOLARITY_HIGH.

void TIM2_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM2 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 636 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CCMR_OCxPE.

void TIM2_PrescalerConfig | ( | TIM2_Prescaler_TypeDef | Prescaler,
 |  | TIM2_PSCReloadMode_TypeDef | TIM2_PSCReloadMode
 | ) |  |

Configures the TIM2 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values

  • TIM2_PRESCALER_1
  • TIM2_PRESCALER_2
  • TIM2_PRESCALER_4
  • TIM2_PRESCALER_8
  • TIM2_PRESCALER_16
  • TIM2_PRESCALER_32
  • TIM2_PRESCALER_64
  • TIM2_PRESCALER_128
  • TIM2_PRESCALER_256
  • TIM2_PRESCALER_512
  • TIM2_PRESCALER_1024
  • TIM2_PRESCALER_2048
  • TIM2_PRESCALER_4096
  • TIM2_PRESCALER_8192
  • TIM2_PRESCALER_16384
  • TIM2_PRESCALER_32768
TIM2_PSCReloadMode specifies the TIM2 Prescaler Reload mode. This parameter can be one of the following values

  • TIM2_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
  • TIM2_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 489 of file stm8s_tim2.c.

References IS_TIM2_PRESCALER_OK, and IS_TIM2_PRESCALER_RELOAD_OK.

void TIM2_PWMIConfig | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_ICPolarity_TypeDef | TIM2_ICPolarity,
 |  | TIM2_ICSelection_TypeDef | TIM2_ICSelection,
 |  | TIM2_ICPSC_TypeDef | TIM2_ICPrescaler,
 |  | uint8_t | TIM2_ICFilter
 | ) |  |

Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM2_Channel | specifies the Input Capture Channel from TIM2_Channel_TypeDef.
TIM2_ICPolarity | specifies the Input Capture Polarity from TIM2_ICPolarity_TypeDef.
TIM2_ICSelection | specifies the Input Capture Selection from TIM2_ICSelection_TypeDef.
TIM2_ICPrescaler | specifies the Input Capture Prescaler from TIM2_ICPSC_TypeDef.
TIM2_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 265 of file stm8s_tim2.c.

References IS_TIM2_IC_POLARITY_OK, IS_TIM2_IC_PRESCALER_OK, IS_TIM2_IC_SELECTION_OK, IS_TIM2_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM2_CHANNEL_1, TIM2_ICPOLARITY_FALLING, TIM2_ICPOLARITY_RISING, TIM2_ICSELECTION_DIRECTTI, TIM2_ICSELECTION_INDIRECTTI, TIM2_SetIC1Prescaler(), and TIM2_SetIC2Prescaler().

void TIM2_SelectOCxM | ( | TIM2_Channel_TypeDef | TIM2_Channel,
 |  | TIM2_OCMode_TypeDef | TIM2_OCMode
 | ) |  |

Selects the TIM2 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM2_CCxCmd and TIM2_CCxNCmd functions.

Parameters:
TIM2_Channel specifies the TIM2 Channel. This parameter can be one of the following values:

  • TIM2_CHANNEL_1: TIM2 Channel1
  • TIM2_CHANNEL_2: TIM2 Channel2
  • TIM2_CHANNEL_3: TIM2 Channel3
TIM2_OCMode specifies the TIM2 Output Compare Mode. This paramter can be one of the following values:

  • TIM2_OCMODE_TIMING
  • TIM2_OCMODE_ACTIVE
  • TIM2_OCMODE_TOGGLE
  • TIM2_OCMODE_PWM1
  • TIM2_OCMODE_PWM2
  • TIM2_FORCEDACTION_ACTIVE
  • TIM2_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 824 of file stm8s_tim2.c.

References IS_TIM2_CHANNEL_OK, IS_TIM2_OCM_OK, TIM2_CCER1_CC1E, TIM2_CCER1_CC2E, TIM2_CCER2_CC3E, TIM2_CCMR_OCM, TIM2_CHANNEL_1, and TIM2_CHANNEL_2.

void TIM2_SelectOnePulseMode ( TIM2_OPMode_TypeDef TIM2_OPMode )

Selects the TIM2’s One Pulse Mode.

Parameters:
TIM2_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values

  • TIM2_OPMODE_SINGLE
  • TIM2_OPMODE_REPETITIVE
Return values:
None

Definition at line 443 of file stm8s_tim2.c.

References IS_TIM2_OPM_MODE_OK, TIM2_CR1_OPM, and TIM2_OPMODE_REPETITIVE.

void TIM2_SetAutoreload ( uint16_t Autoreload )

Sets the TIM2 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 881 of file stm8s_tim2.c.

void TIM2_SetCompare1 ( uint16_t Compare1 )

Sets the TIM2 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 897 of file stm8s_tim2.c.

void TIM2_SetCompare2 ( uint16_t Compare2 )

Sets the TIM2 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 912 of file stm8s_tim2.c.

void TIM2_SetCompare3 ( uint16_t Compare3 )

Sets the TIM2 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 927 of file stm8s_tim2.c.

void TIM2_SetCounter ( uint16_t Counter )

Sets the TIM2 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 866 of file stm8s_tim2.c.

void TIM2_SetIC1Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC1Prescaler )

Sets the TIM2 Input Capture 1 Prescaler.

Parameters:
TIM2_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 946 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

void TIM2_SetIC2Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC2Prescaler )

Sets the TIM2 Input Capture 2 prescaler.

Parameters:
TIM2_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 966 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit(), and TIM2_PWMIConfig().

void TIM2_SetIC3Prescaler ( TIM2_ICPSC_TypeDef TIM2_IC3Prescaler )

Sets the TIM2 Input Capture 3 prescaler.

Parameters:
TIM2_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM2_ICPSC_DIV1: no prescaler
  • TIM2_ICPSC_DIV2: capture is done once every 2 events
  • TIM2_ICPSC_DIV4: capture is done once every 4 events
  • TIM2_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 986 of file stm8s_tim2.c.

References IS_TIM2_IC_PRESCALER_OK, and TIM2_CCMR_ICxPSC.

Referenced by TIM2_ICInit().

void TIM2_TimeBaseInit | ( | TIM2_Prescaler_TypeDef | TIM2_Prescaler,
 |  | uint16_t | TIM2_Period
 | ) |  |

Initializes the TIM2 Time Base Unit according to the specified parameters.

Parameters:
TIM2_Prescaler | specifies the Prescaler from TIM2_Prescaler_TypeDef.
TIM2_Period | specifies the Period value.
Return values:
None

Definition at line 85 of file stm8s_tim2.c.

void TIM2_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM2 Update event.

Parameters:
NewState new state of the TIM2 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 394 of file stm8s_tim2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM2_CR1_UDIS.

void TIM2_UpdateRequestConfig ( TIM2_UpdateSource_TypeDef TIM2_UpdateSource )

Selects the TIM2 Update Request Interrupt source.

Parameters:
TIM2_UpdateSource specifies the Update source. This parameter can be one of the following values

  • TIM2_UPDATESOURCE_REGULAR
  • TIM2_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 418 of file stm8s_tim2.c.

References IS_TIM2_UPDATE_SOURCE_OK, TIM2_CR1_URS, and TIM2_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: TIM5_Exported_Functions

Functions

TIM5_Exported_Functions

Functions

void | TIM5_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM5 peripheral Preload register on ARR.
void | TIM5_CCPreloadControl (FunctionalState NewState)
void | TIM5_CCxCmd (TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)
Enables or disables the TIM5 Capture Compare Channel x.
void | TIM5_ClearFlag (TIM5_FLAG_TypeDef TIM5_FLAG)
Clears the TIM5’s pending flags.
void | TIM5_ClearITPendingBit (TIM5_IT_TypeDef TIM5_IT)
Clears the TIM5's interrupt pending bits.
void | TIM5_Cmd (FunctionalState NewState)
Enables or disables the TIM5 peripheral.
void | TIM5_DeInit (void)
Deinitializes the TIM5 peripheral registers to their default reset values.
void | TIM5_EncoderInterfaceConfig (TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
Configures the TIM5 Encoder Interface.
void | TIM5_ForcedOC1Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel1 output waveform to active or inactive level.
void | TIM5_ForcedOC2Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel2 output waveform to active or inactive level.
void | TIM5_ForcedOC3Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel3 output waveform to active or inactive level.
void | TIM5_GenerateEvent (TIM5_EventSource_TypeDef TIM5_EventSource)
Configures the TIM5 event to be generated by software.
uint16_t | TIM5_GetCapture1 (void)
Gets the TIM5 Input Capture 1 value.
uint16_t | TIM5_GetCapture2 (void)
Gets the TIM5 Input Capture 2 value.
uint16_t | TIM5_GetCapture3 (void)
Gets the TIM5 Input Capture 3 value.
uint16_t | TIM5_GetCounter (void)
Gets the TIM5 Counter value.
FlagStatus | TIM5_GetFlagStatus (TIM5_FLAG_TypeDef TIM5_FLAG)
Checks whether the specified TIM5 flag is set or not.
ITStatus | TIM5_GetITStatus (TIM5_IT_TypeDef TIM5_IT)
Checks whether the TIM5 interrupt has occurred or not.
TIM5_Prescaler_TypeDef | TIM5_GetPrescaler (void)
Gets the TIM5 Prescaler value.
void | TIM5_ICInit (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Initializes the TIM5 peripheral according to the specified parameters.
void | TIM5_InternalClockConfig (void)
Enables the TIM5 internal Clock.
void | TIM5_ITConfig (TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
Enables or disables the specified TIM5 interrupts.
void | TIM5_OC1Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel1 according to the specified parameters.
void | TIM5_OC1PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 1 polarity.
void | TIM5_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR1.
void | TIM5_OC2Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel2 according to the specified parameters.
void | TIM5_OC2PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 2 polarity.
void | TIM5_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR2.
void | TIM5_OC3Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel3 according to the specified parameters.
void | TIM5_OC3PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 3 polarity.
void | TIM5_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR3.
void | TIM5_PrescalerConfig (TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
Configures the TIM5 Prescaler.
void | TIM5_PWMIConfig (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.
void | TIM5_SelectInputTrigger (TIM5_TS_TypeDef TIM5_InputTriggerSource)
Selects the TIM5 Input Trigger source.
void | TIM5_SelectOCxM (TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)
Selects the TIM5 Output Compare Mode.
void | TIM5_SelectOnePulseMode (TIM5_OPMode_TypeDef TIM5_OPMode)
Selects the TIM5’s One Pulse Mode.
void | TIM5_SelectOutputTrigger (TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
Selects the TIM5 Trigger Output Mode.
void | TIM5_SelectSlaveMode (TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
Selects the TIM5 Slave Mode.
void | TIM5_SetAutoreload (uint16_t Autoreload)
Sets the TIM5 Autoreload Register value.
void | TIM5_SetCompare1 (uint16_t Compare1)
Sets the TIM5 Capture Compare1 Register value.
void | TIM5_SetCompare2 (uint16_t Compare2)
Sets the TIM5 Capture Compare2 Register value.
void | TIM5_SetCompare3 (uint16_t Compare3)
Sets the TIM5 Capture Compare3 Register value.
void | TIM5_SetCounter (uint16_t Counter)
Sets the TIM5 Counter Register value.
void | TIM5_SetIC1Prescaler (TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
Sets the TIM5 Input Capture 1 prescaler.
void | TIM5_SetIC2Prescaler (TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
Sets the TIM5 Input Capture 2 prescaler.
void | TIM5_SetIC3Prescaler (TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)
Sets the TIM5 Input Capture 3 prescaler.
void | TIM5_TimeBaseInit (TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period)
Initializes the TIM5 Time Base Unit according to the specified parameters.
void | TIM5_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM5 Update event.
void | TIM5_UpdateRequestConfig (TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
Selects the TIM5 Update Request Interrupt source.

Function Documentation

void TIM5_ARRPreloadConfig ( FunctionalState NewState )

Enables or disables TIM5 peripheral Preload register on ARR.

Parameters:
NewState new state of the TIM5 peripheral Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 568 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_ARPE.

void TIM5_CCPreloadControl ( FunctionalState NewState )
void TIM5_CCxCmd | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM5 Capture Compare Channel x.

Parameters:
TIM5_Channel specifies the TIM5 Channel. This parameter can be one of the following values:

  • TIM5_Channel1: TIM5 Channel1
  • TIM5_Channel2: TIM5 Channel2
  • TIM5_Channel3: TIM5 Channel3
NewState specifies the TIM5 Channel CCxE bit new state. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 760 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, IS_TIM5_CHANNEL_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC2E, TIM5_CCER2_CC3E, TIM5_CHANNEL_1, and TIM5_CHANNEL_2.

void TIM5_ClearFlag ( TIM5_FLAG_TypeDef TIM5_FLAG )

Clears the TIM5’s pending flags.

Parameters:
TIM5_FLAG specifies the flag to clear. This parameter can be one of the following values:

  • TIM5_FLAG_UPDATE: TIM5 update Flag
  • TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
  • TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
  • TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
  • TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
  • TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
  • TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
Return values:
None.

Definition at line 1118 of file stm8s_tim5.c.

References IS_TIM5_CLEAR_FLAG_OK.

void TIM5_ClearITPendingBit ( TIM5_IT_TypeDef TIM5_IT )

Clears the TIM5's interrupt pending bits.

Parameters:
TIM5_IT specifies the pending bit to clear. This parameter can be one of the following values:

  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
Return values:
None.

Definition at line 1174 of file stm8s_tim5.c.

References IS_TIM5_IT_OK.

void TIM5_Cmd ( FunctionalState NewState )

Enables or disables the TIM5 peripheral.

Parameters:
NewState new state of the TIM5 peripheral.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 340 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_CEN.

void TIM5_DeInit ( void )

Deinitializes the TIM5 peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 46 of file stm8s_tim5.c.

References TIM5_ARRH_RESET_VALUE, TIM5_ARRL_RESET_VALUE, TIM5_CCER1_RESET_VALUE, TIM5_CCER2_RESET_VALUE, TIM5_CCMR1_RESET_VALUE, TIM5_CCMR2_RESET_VALUE, TIM5_CCMR3_RESET_VALUE, TIM5_CCR1H_RESET_VALUE, TIM5_CCR1L_RESET_VALUE, TIM5_CCR2H_RESET_VALUE, TIM5_CCR2L_RESET_VALUE, TIM5_CCR3H_RESET_VALUE, TIM5_CCR3L_RESET_VALUE, TIM5_CNTRH_RESET_VALUE, TIM5_CNTRL_RESET_VALUE, TIM5_CR1_RESET_VALUE, TIM5_CR2_RESET_VALUE, TIM5_IER_RESET_VALUE, TIM5_PSCR_RESET_VALUE, TIM5_SMCR_RESET_VALUE, TIM5_SR1_RESET_VALUE, and TIM5_SR2_RESET_VALUE.

void TIM5_EncoderInterfaceConfig | ( | TIM5_EncoderMode_TypeDef | TIM5_EncoderMode,
 |  | TIM5_ICPolarity_TypeDef | TIM5_IC1Polarity,
 |  | TIM5_ICPolarity_TypeDef | TIM5_IC2Polarity
 | ) |  |

Configures the TIM5 Encoder Interface.

Parameters:
TIM5_EncoderMode | : Specifies the TIM5 Encoder Mode. This parameter can be one of the TIM5_EncoderMode_TypeDef enumeration.
TIM5_IC1Polarity | : Specifies the IC1 Polarity. This parameter can be one of the TIM5_ICPolarity_TypeDef enumeration.
TIM5_IC2Polarity | : Specifies the IC2 Polarity. This parameter can be one of the TIM5_ICPolarity_TypeDef enumeration.
Return values:
None

Definition at line 1394 of file stm8s_tim5.c.

References IS_TIM5_ENCODER_MODE_OK, IS_TIM5_IC_POLARITY_OK, TIM5_CCER1_CC1P, TIM5_CCER1_CC2P, TIM5_CCMR_CCxS, TIM5_CCMR_TIxDirect_Set, TIM5_ICPOLARITY_FALLING, TIM5_SMCR_MSM, and TIM5_SMCR_TS.

void TIM5_ForcedOC1Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel1 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC1REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
Return values:
None

Definition at line 513 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_ForcedOC2Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel2 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC2REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
Return values:
None

Definition at line 532 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_ForcedOC3Config ( TIM5_ForcedAction_TypeDef TIM5_ForcedAction )

Forces the TIM5 Channel3 output waveform to active or inactive level.

Parameters:
TIM5_ForcedAction specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM5_FORCEDACTION_ACTIVE: Force active level on OC3REF
  • TIM5_FORCEDACTION_INACTIVE: Force inactive level on OC3REF.
Return values:
None

Definition at line 551 of file stm8s_tim5.c.

References IS_TIM5_FORCED_ACTION_OK, and TIM5_CCMR_OCM.

void TIM5_GenerateEvent ( TIM5_EventSource_TypeDef TIM5_EventSource )

Configures the TIM5 event to be generated by software.

Parameters:
TIM5_EventSource specifies the event source. This parameter can be one of the following values:

  • TIM5_EVENTSOURCE_UPDATE: TIM5 update Event source
  • TIM5_EVENTSOURCE_CC1: TIM5 Capture Compare 1 Event source
  • TIM5_EVENTSOURCE_CC2: TIM5 Capture Compare 2 Event source
  • TIM5_EVENTSOURCE_CC3: TIM5 Capture Compare 3 Event source
Return values:
None

Definition at line 664 of file stm8s_tim5.c.

References IS_TIM5_EVENT_SOURCE_OK.

uint16_t TIM5_GetCapture1 ( void )

Gets the TIM5 Input Capture 1 value.

Parameters:
None
Return values:
Capture Compare 1 Register value.

Definition at line 1002 of file stm8s_tim5.c.

uint16_t TIM5_GetCapture2 ( void )

Gets the TIM5 Input Capture 2 value.

Parameters:
None
Return values:
Capture Compare 2 Register value.

Definition at line 1017 of file stm8s_tim5.c.

uint16_t TIM5_GetCapture3 ( void )

Gets the TIM5 Input Capture 3 value.

Parameters:
None
Return values:
Capture Compare 3 Register value.

Definition at line 1032 of file stm8s_tim5.c.

uint16_t TIM5_GetCounter ( void )

Gets the TIM5 Counter value.

Parameters:
None
Return values:
Counter Register value.

Definition at line 1046 of file stm8s_tim5.c.

FlagStatus TIM5_GetFlagStatus ( TIM5_FLAG_TypeDef TIM5_FLAG )

Checks whether the specified TIM5 flag is set or not.

Parameters:
TIM5_FLAG specifies the flag to check. This parameter can be one of the following values:

  • TIM5_FLAG_UPDATE: TIM5 update Flag
  • TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
  • TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
  • TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
  • TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
  • TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
  • TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
Return values:
FlagStatus The new state of TIM5_FLAG (SET or RESET).

Definition at line 1082 of file stm8s_tim5.c.

References IS_TIM5_GET_FLAG_OK, RESET, and SET.

ITStatus TIM5_GetITStatus ( TIM5_IT_TypeDef TIM5_IT )

Checks whether the TIM5 interrupt has occurred or not.

Parameters:
TIM5_IT specifies the TIM5 interrupt source to check. This parameter can be one of the following values:

  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
Return values:
ITStatus The new state of the TIM5_IT(SET or RESET).

Definition at line 1140 of file stm8s_tim5.c.

References IS_TIM5_GET_IT_OK, RESET, and SET.

TIM5_Prescaler_TypeDef TIM5_GetPrescaler ( void )

Gets the TIM5 Prescaler value.

Parameters:
None
Return values:
Prescaler Register configuration value TIM5_Prescaler_TypeDef .

Definition at line 1061 of file stm8s_tim5.c.

void TIM5_ICInit | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_ICPolarity_TypeDef | TIM5_ICPolarity,
 |  | TIM5_ICSelection_TypeDef | TIM5_ICSelection,
 |  | TIM5_ICPSC_TypeDef | TIM5_ICPrescaler,
 |  | uint8_t | TIM5_ICFilter
 | ) |  |

Initializes the TIM5 peripheral according to the specified parameters.

Parameters:
TIM5_Channel | specifies the Input Capture Channel from TIM5_Channel_TypeDef.
TIM5_ICPolarity | specifies the Input Capture Polarity from TIM5_ICPolarity_TypeDef.
TIM5_ICSelection | specifies theInput Capture Selection from TIM5_ICSelection_TypeDef.
TIM5_ICPrescaler | specifies the Input Capture Prescaler from TIM5_ICPSC_TypeDef.
TIM5_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 211 of file stm8s_tim5.c.

References IS_TIM5_CHANNEL_OK, IS_TIM5_IC_FILTER_OK, IS_TIM5_IC_POLARITY_OK, IS_TIM5_IC_PRESCALER_OK, IS_TIM5_IC_SELECTION_OK, TI1_Config(), TI2_Config(), TI3_Config(), TIM5_CHANNEL_1, TIM5_CHANNEL_2, TIM5_SetIC1Prescaler(), TIM5_SetIC2Prescaler(), and TIM5_SetIC3Prescaler().

void TIM5_InternalClockConfig ( void )

Enables the TIM5 internal Clock.

Parameters:
None
Return values:
None

Definition at line 1311 of file stm8s_tim5.c.

References TIM5_SMCR_SMS.

void TIM5_ITConfig | ( | TIM5_IT_TypeDef | TIM5_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM5 interrupts.

Parameters:
NewState | new state of the TIM5 peripheral. This parameter can be: ENABLE or DISABLE.
TIM5_IT specifies the TIM5 interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM5_IT_UPDATE: TIM5 update Interrupt source
  • TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
  • TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
  • TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
NewState | new state of the TIM5 peripheral.
Return values:
None

Definition at line 370 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_TIM5_IT_OK.

void TIM5_OC1Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel1 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 106 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC1P, and TIM5_CCMR_OCM.

void TIM5_OC1PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 1 polarity.

Parameters:
TIM5_OCPolarity specifies the OC1 Polarity. This parameter can be one of the following values:

  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 682 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER1_CC1P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC1PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR1.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 591 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_OC2Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel2 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 140 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER1_CC2E, TIM5_CCER1_CC2P, and TIM5_CCMR_OCM.

void TIM5_OC2PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 2 polarity.

Parameters:
TIM5_OCPolarity specifies the OC2 Polarity. This parameter can be one of the following values:

  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 707 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER1_CC2P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC2PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR2.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 614 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_OC3Init | ( | TIM5_OCMode_TypeDef | TIM5_OCMode,
 |  | TIM5_OutputState_TypeDef | TIM5_OutputState,
 |  | uint16_t | TIM5_Pulse,
 |  | TIM5_OCPolarity_TypeDef | TIM5_OCPolarity
 | ) |  |

Initializes the TIM5 Channel3 according to the specified parameters.

Parameters:
TIM5_OCMode | specifies the Output Compare mode from TIM5_OCMode_TypeDef.
TIM5_OutputState | specifies the Output State from TIM5_OutputState_TypeDef.
TIM5_Pulse | specifies the Pulse width value.
TIM5_OCPolarity | specifies the Output Compare Polarity from TIM5_OCPolarity_TypeDef.
Return values:
None

Definition at line 177 of file stm8s_tim5.c.

References IS_TIM5_OC_MODE_OK, IS_TIM5_OC_POLARITY_OK, IS_TIM5_OUTPUT_STATE_OK, TIM5_CCER2_CC3E, TIM5_CCER2_CC3P, and TIM5_CCMR_OCM.

void TIM5_OC3PolarityConfig ( TIM5_OCPolarity_TypeDef TIM5_OCPolarity )

Configures the TIM5 Channel 3 polarity.

Parameters:
TIM5_OCPolarity specifies the OC3 Polarity. This parameter can be one of the following values:

  • TIM5_OCPOLARITY_LOW: Output Compare active low
  • TIM5_OCPOLARITY_HIGH: Output Compare active high
Return values:
None

Definition at line 732 of file stm8s_tim5.c.

References IS_TIM5_OC_POLARITY_OK, TIM5_CCER2_CC3P, and TIM5_OCPOLARITY_HIGH.

void TIM5_OC3PreloadConfig ( FunctionalState NewState )

Enables or disables the TIM5 peripheral Preload Register on CCR3.

Parameters:
NewState new state of the Capture Compare Preload register. This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 637 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CCMR_OCxPE.

void TIM5_PrescalerConfig | ( | TIM5_Prescaler_TypeDef | Prescaler,
 |  | TIM5_PSCReloadMode_TypeDef | TIM5_PSCReloadMode
 | ) |  |

Configures the TIM5 Prescaler.

Parameters:
Prescaler specifies the Prescaler Register value This parameter can be one of the following values

  • TIM5_PRESCALER_1
  • TIM5_PRESCALER_2
  • TIM5_PRESCALER_4
  • TIM5_PRESCALER_8
  • TIM5_PRESCALER_16
  • TIM5_PRESCALER_32
  • TIM5_PRESCALER_64
  • TIM5_PRESCALER_128
  • TIM5_PRESCALER_256
  • TIM5_PRESCALER_512
  • TIM5_PRESCALER_1024
  • TIM5_PRESCALER_2048
  • TIM5_PRESCALER_4096
  • TIM5_PRESCALER_8192
  • TIM5_PRESCALER_16384
  • TIM5_PRESCALER_32768
TIM5_PSCReloadMode specifies the TIM5 Prescaler Reload mode. This parameter can be one of the following values

  • TIM5_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediatly.
  • TIM5_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
Return values:
None

Definition at line 490 of file stm8s_tim5.c.

References IS_TIM5_PRESCALER_OK, and IS_TIM5_PRESCALER_RELOAD_OK.

void TIM5_PWMIConfig | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_ICPolarity_TypeDef | TIM5_ICPolarity,
 |  | TIM5_ICSelection_TypeDef | TIM5_ICSelection,
 |  | TIM5_ICPSC_TypeDef | TIM5_ICPrescaler,
 |  | uint8_t | TIM5_ICFilter
 | ) |  |

Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.

Parameters:
TIM5_Channel | specifies the Input Capture Channel from TIM5_Channel_TypeDef.
TIM5_ICPolarity | specifies the Input Capture Polarity from TIM5_ICPolarity_TypeDef.
TIM5_ICSelection | specifies theInput Capture Selection from TIM5_ICSelection_TypeDef.
TIM5_ICPrescaler | specifies the Input Capture Prescaler from TIM5_ICPSC_TypeDef.
TIM5_ICFilter | specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
Return values:
None

Definition at line 266 of file stm8s_tim5.c.

References IS_TIM5_IC_POLARITY_OK, IS_TIM5_IC_PRESCALER_OK, IS_TIM5_IC_SELECTION_OK, IS_TIM5_PWMI_CHANNEL_OK, TI1_Config(), TI2_Config(), TIM5_CHANNEL_1, TIM5_ICPOLARITY_FALLING, TIM5_ICPOLARITY_RISING, TIM5_ICSELECTION_DIRECTTI, TIM5_ICSELECTION_INDIRECTTI, TIM5_SetIC1Prescaler(), and TIM5_SetIC2Prescaler().

void TIM5_SelectInputTrigger ( TIM5_TS_TypeDef TIM5_InputTriggerSource )

Selects the TIM5 Input Trigger source.

Parameters:
TIM5_InputTriggerSource : Specifies Input Trigger source. This parameter can be one of the TIM5_TS_TypeDef enumeration.
Return values:
None

Definition at line 1369 of file stm8s_tim5.c.

References IS_TIM5_TRIGGER_SELECTION_OK, and TIM5_SMCR_TS.

void TIM5_SelectOCxM | ( | TIM5_Channel_TypeDef | TIM5_Channel,
 |  | TIM5_OCMode_TypeDef | TIM5_OCMode
 | ) |  |

Selects the TIM5 Output Compare Mode.

This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM5_CCxCmd and TIM5_CCxNCmd functions.

Parameters:
TIM5_Channel specifies the TIM5 Channel. This parameter can be one of the following values:

  • TIM5_Channel1: TIM5 Channel1
  • TIM5_Channel2: TIM5 Channel2
  • TIM5_Channel3: TIM5 Channel3
TIM5_OCMode specifies the TIM5 Output Compare Mode. This paramter can be one of the following values:

  • TIM5_OCMODE_TIMING
  • TIM5_OCMODE_ACTIVE
  • TIM5_OCMODE_TOGGLE
  • TIM5_OCMODE_PWM1
  • TIM5_OCMODE_PWM2
  • TIM5_FORCEDACTION_ACTIVE
  • TIM5_FORCEDACTION_INACTIVE
Return values:
None

Definition at line 825 of file stm8s_tim5.c.

References IS_TIM5_CHANNEL_OK, IS_TIM5_OCM_OK, TIM5_CCER1_CC1E, TIM5_CCER1_CC2E, TIM5_CCER2_CC3E, TIM5_CCMR_OCM, TIM5_CHANNEL_1, and TIM5_CHANNEL_2.

void TIM5_SelectOnePulseMode ( TIM5_OPMode_TypeDef TIM5_OPMode )

Selects the TIM5’s One Pulse Mode.

Parameters:
TIM5_OPMode specifies the OPM Mode to be used. This parameter can be one of the following values

  • TIM5_OPMODE_SINGLE
  • TIM5_OPMODE_REPETITIVE
Return values:
None

Definition at line 444 of file stm8s_tim5.c.

References IS_TIM5_OPM_MODE_OK, TIM5_CR1_OPM, and TIM5_OPMODE_REPETITIVE.

void TIM5_SelectOutputTrigger ( TIM5_TRGOSource_TypeDef TIM5_TRGOSource )

Selects the TIM5 Trigger Output Mode.

Parameters:
TIM5_TRGOSource : Specifies the Trigger Output source. This parameter can be one of the TIM5_TRGOSource_TypeDef enumeration.
Return values:
None

Definition at line 1323 of file stm8s_tim5.c.

References IS_TIM5_TRGO_SOURCE_OK, and TIM5_CR2_MMS.

void TIM5_SelectSlaveMode ( TIM5_SlaveMode_TypeDef TIM5_SlaveMode )

Selects the TIM5 Slave Mode.

Parameters:
TIM5_SlaveMode : Specifies the TIM5 Slave Mode. This parameter can be one of the TIM5_SlaveMode_TypeDef enumeration.
Return values:
None

Definition at line 1346 of file stm8s_tim5.c.

References IS_TIM5_SLAVE_MODE_OK, and TIM5_SMCR_SMS.

void TIM5_SetAutoreload ( uint16_t Autoreload )

Sets the TIM5 Autoreload Register value.

Parameters:
Autoreload specifies the Autoreload register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 882 of file stm8s_tim5.c.

void TIM5_SetCompare1 ( uint16_t Compare1 )

Sets the TIM5 Capture Compare1 Register value.

Parameters:
Compare1 specifies the Capture Compare1 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 898 of file stm8s_tim5.c.

void TIM5_SetCompare2 ( uint16_t Compare2 )

Sets the TIM5 Capture Compare2 Register value.

Parameters:
Compare2 specifies the Capture Compare2 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 913 of file stm8s_tim5.c.

void TIM5_SetCompare3 ( uint16_t Compare3 )

Sets the TIM5 Capture Compare3 Register value.

Parameters:
Compare3 specifies the Capture Compare3 register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 928 of file stm8s_tim5.c.

void TIM5_SetCounter ( uint16_t Counter )

Sets the TIM5 Counter Register value.

Parameters:
Counter specifies the Counter register new value. This parameter is between 0x0000 and 0xFFFF.
Return values:
None

Definition at line 867 of file stm8s_tim5.c.

void TIM5_SetIC1Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC1Prescaler )

Sets the TIM5 Input Capture 1 prescaler.

Parameters:
TIM5_IC1Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 947 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

void TIM5_SetIC2Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC2Prescaler )

Sets the TIM5 Input Capture 2 prescaler.

Parameters:
TIM5_IC2Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 967 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit(), and TIM5_PWMIConfig().

void TIM5_SetIC3Prescaler ( TIM5_ICPSC_TypeDef TIM5_IC3Prescaler )

Sets the TIM5 Input Capture 3 prescaler.

Parameters:
TIM5_IC3Prescaler specifies the Input Capture prescaler new value This parameter can be one of the following values:

  • TIM5_ICPSC_DIV1: no prescaler
  • TIM5_ICPSC_DIV2: capture is done once every 2 events
  • TIM5_ICPSC_DIV4: capture is done once every 4 events
  • TIM5_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 987 of file stm8s_tim5.c.

References IS_TIM5_IC_PRESCALER_OK, and TIM5_CCMR_ICxPSC.

Referenced by TIM5_ICInit().

void TIM5_TimeBaseInit | ( | TIM5_Prescaler_TypeDef | TIM5_Prescaler,
 |  | uint16_t | TIM5_Period
 | ) |  |

Initializes the TIM5 Time Base Unit according to the specified parameters.

Parameters:
TIM5_Prescaler | specifies the Prescaler from TIM5_Prescaler_TypeDef.
TIM5_Period | specifies the Period value.
Return values:
None

Definition at line 87 of file stm8s_tim5.c.

void TIM5_UpdateDisableConfig ( FunctionalState NewState )

Enables or Disables the TIM5 Update event.

Parameters:
NewState new state of the TIM5 peripheral Preload register.This parameter can be ENABLE or DISABLE.
Return values:
None

Definition at line 395 of file stm8s_tim5.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and TIM5_CR1_UDIS.

void TIM5_UpdateRequestConfig ( TIM5_UpdateSource_TypeDef TIM5_UpdateSource )

Selects the TIM5 Update Request Interrupt source.

Parameters:
TIM5_UpdateSource specifies the Update source. This parameter can be one of the following values

  • TIM5_UPDATESOURCE_REGULAR
  • TIM5_UPDATESOURCE_GLOBAL
Return values:
None

Definition at line 419 of file stm8s_tim5.c.

References IS_TIM5_UPDATE_SOURCE_OK, TIM5_CR1_URS, and TIM5_UPDATESOURCE_GLOBAL.


STM8S/A Standard Peripherals Drivers: IWDG_Public_Functions

Functions

IWDG_Public_Functions

Functions

void | IWDG_Enable (void)
Enables IWDG.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter.
void | IWDG_SetPrescaler (IWDG_Prescaler_TypeDef IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint8_t IWDG_Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
Enables or disables write access to Prescaler and Reload registers.

Function Documentation

void IWDG_Enable ( void )

Enables IWDG.

Parameters:
None
Return values:
None

Definition at line 93 of file stm8s_iwdg.c.

References IWDG, and IWDG_KEY_ENABLE.

void IWDG_ReloadCounter ( void )

Reloads IWDG counter.

Note:
Write access should be enabled
Parameters:
None
Return values:
None

Definition at line 83 of file stm8s_iwdg.c.

References IWDG, and IWDG_KEY_REFRESH.

void IWDG_SetPrescaler ( IWDG_Prescaler_TypeDef IWDG_Prescaler )

Sets IWDG Prescaler value.

Note:
Write access should be enabled
Parameters:
IWDG_Prescaler : Specifies the IWDG Prescaler value. This parameter can be a value of IWDG_Prescaler_TypeDef.
Return values:
None

Definition at line 57 of file stm8s_iwdg.c.

References IS_IWDG_PRESCALER_OK, and IWDG.

void IWDG_SetReload ( uint8_t IWDG_Reload )

Sets IWDG Reload value.

Note:
Write access should be enabled
Parameters:
IWDG_Reload : Reload register value. This parameter must be a number between 0 and 0xFF.
Return values:
None

Definition at line 72 of file stm8s_iwdg.c.

References IWDG.

void IWDG_WriteAccessCmd ( IWDG_WriteAccess_TypeDef IWDG_WriteAccess )

Enables or disables write access to Prescaler and Reload registers.

Parameters:
IWDG_WriteAccess : New state of write access to Prescaler and Reload registers. This parameter can be a value of IWDG_WriteAccess_TypeDef.
Return values:
None

Definition at line 42 of file stm8s_iwdg.c.

References IS_IWDG_WRITEACCESS_MODE_OK, and IWDG.


STM8S/A Standard Peripherals Drivers: UART1_Public_Functions

Functions

UART1_Public_Functions

Functions

void | UART1_ClearFlag (UART1_Flag_TypeDef UART1_FLAG)
Clears the UART1 flags.
void | UART1_ClearITPendingBit (UART1_IT_TypeDef UART1_IT)
Clears the UART1 pending flags.
void | UART1_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART1_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART1_GetFlagStatus (UART1_Flag_TypeDef UART1_FLAG)
Checks whether the specified UART1 flag is set or not.
ITStatus | UART1_GetITStatus (UART1_IT_TypeDef UART1_IT)
Checks whether the specified UART1 interrupt has occurred or not.
void | UART1_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART1_Init (uint32_t BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
Initializes the UART1 according to the specified parameters.
void | UART1_IrDACmd (FunctionalState NewState)
Enables or disables the UART’s IrDA interface.
void | UART1_IrDAConfig (UART1_IrDAMode_TypeDef UART1_IrDAMode)
Configures the UART’s IrDA interface.
void | UART1_ITConfig (UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | UART1_LINBreakDetectionConfig (UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
Sets the UART1 LIN Break detection length.
void | UART1_LINCmd (FunctionalState NewState)
Enables or disables the UART1’s LIN mode.
uint8_t | UART1_ReceiveData8 (void)
Returns the most recent received data by the UART1 peripheral.
uint16_t | UART1_ReceiveData9 (void)
Returns the most recent received data by the UART1 peripheral.
void | UART1_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART1 is in mute mode or not.
void | UART1_SendBreak (void)
Transmits break characters.
void | UART1_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART1 peripheral.
void | UART1_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART peripheral.
void | UART1_SetAddress (uint8_t UART1_Address)
Sets the address of the UART1 node.
void | UART1_SetGuardTime (uint8_t UART1_GuardTime)
Sets the specified UART guard time.
void | UART1_SetPrescaler (uint8_t UART1_Prescaler)
Sets the system clock prescaler.
void | UART1_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART1 Smart Card mode.
void | UART1_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART1_WakeUpConfig (UART1_WakeUp_TypeDef UART1_WakeUp)
Selects the UART1 WakeUp method.

Function Documentation

void UART1_ClearFlag ( UART1_Flag_TypeDef UART1_FLAG )

Clears the UART1 flags.

Parameters:
UART1_FLAG specifies the flag to clear This parameter can be any combination of the following values:

  • UART1_FLAG_LBDF: LIN Break detection flag.
  • UART1_FLAG_RXNE: Receive data register not empty flag.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART1_SR register (UART1_GetFlagStatus())followed by a read operation to UART1_DR register(UART1_ReceiveData8() or UART1_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART1_DR register (UART1_ReceiveData8()or UART1_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART1_SR register (UART1_GetFlagStatus()) followed by a write operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • TXE flag is cleared only by a write to the UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 639 of file stm8s_uart1.c.

References IS_UART1_CLEAR_FLAG_OK, UART1_CR4_LBDF, UART1_FLAG_RXNE, and UART1_SR_RXNE.

void UART1_ClearITPendingBit ( UART1_IT_TypeDef UART1_IT )

Clears the UART1 pending flags.

Parameters:
UART1_IT specifies the pending bit to clear This parameter can be one of the following values:

  • UART1_IT_LBDF: LIN Break detection interrupt
  • UART1_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART1_SR register (UART1_GetITStatus()) followed by a read operation to UART1_DR register (UART1_ReceiveData8() or UART1_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART1_DR register (UART1_ReceiveData8() or UART1_ReceiveData9()).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART1_SR register (UART1_GetITStatus()) followed by a write operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).
  • TXE pending bit is cleared only by a write to the UART1_DR register (UART1_SendData8() or UART1_SendData9()).
    Return values:
    None

Definition at line 768 of file stm8s_uart1.c.

References IS_UART1_CLEAR_IT_OK, UART1_CR4_LBDF, UART1_IT_RXNE, and UART1_SR_RXNE.

void UART1_Cmd ( FunctionalState NewState )

Enable the UART1 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 177 of file stm8s_uart1.c.

References DISABLE, and UART1_CR1_UARTD.

void UART1_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 46 of file stm8s_uart1.c.

References UART1_BRR1_RESET_VALUE, UART1_BRR2_RESET_VALUE, UART1_CR1_RESET_VALUE, UART1_CR2_RESET_VALUE, UART1_CR3_RESET_VALUE, UART1_CR4_RESET_VALUE, UART1_CR5_RESET_VALUE, UART1_GTR_RESET_VALUE, and UART1_PSCR_RESET_VALUE.

FlagStatus UART1_GetFlagStatus ( UART1_Flag_TypeDef UART1_FLAG )

Checks whether the specified UART1 flag is set or not.

Parameters:
UART1_FLAG specifies the flag to check. This parameter can be any of the UART1_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 560 of file stm8s_uart1.c.

References IS_UART1_FLAG_OK, RESET, SET, UART1_FLAG_LBDF, and UART1_FLAG_SBK.

ITStatus UART1_GetITStatus ( UART1_IT_TypeDef UART1_IT )

Checks whether the specified UART1 interrupt has occurred or not.

Parameters:
UART1_IT,: Specifies the UART1 interrupt pending bit to check. This parameter can be one of the following values:

  • UART1_IT_LBDF: LIN Break detection interrupt
  • UART1_IT_TXE: Tansmit Data Register empty interrupt
  • UART1_IT_TC: Transmission complete interrupt
  • UART1_IT_RXNE: Receive Data register not empty interrupt
  • UART1_IT_IDLE: Idle line detection interrupt
  • UART1_IT_OR: OverRun Error interrupt
  • UART1_IT_PE: Parity Error interrupt
Return values:
The new state of UART1_IT (SET or RESET).

Definition at line 668 of file stm8s_uart1.c.

References IS_UART1_GET_IT_OK, RESET, SET, UART1_IT_LBDF, and UART1_IT_PE.

void UART1_HalfDuplexCmd ( FunctionalState NewState )

Enables or disables the UART’s Half Duplex communication.

Parameters:
NewState new state of the UART Communication. This parameter can be: ENABLE or DISABLE.
Return values:
None

< UART1 Half Duplex Enable

< UART1 Half Duplex Disable

Definition at line 258 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_HDSEL.

void UART1_Init | ( | uint32_t | BaudRate,
 |  | UART1_WordLength_TypeDef | WordLength,
 |  | UART1_StopBits_TypeDef | StopBits,
 |  | UART1_Parity_TypeDef | Parity,
 |  | UART1_SyncMode_TypeDef | SyncMode,
 |  | UART1_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART1 according to the specified parameters.

Note:
Configure in Push Pull or Open Drain mode the Tx pin by setting the correct I/O Port register according the product package and line configuration
Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART1_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART1_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART1_Parity_TypeDef enumeration.
SyncMode,: This parameter can be any of the UART1_SyncMode_TypeDef values.
Mode,: This parameter can be any of the UART1_Mode_TypeDef values
Return values:
None

Definition at line 83 of file stm8s_uart1.c.

References CLK_GetClockFreq(), IS_UART1_BAUDRATE_OK, IS_UART1_MODE_OK, IS_UART1_PARITY_OK, IS_UART1_STOPBITS_OK, IS_UART1_SYNCMODE_OK, IS_UART1_WORDLENGTH_OK, UART1_BRR1_DIVM, UART1_BRR2_DIVF, UART1_BRR2_DIVM, UART1_CR1_M, UART1_CR1_PCEN, UART1_CR1_PS, UART1_CR2_REN, UART1_CR2_TEN, UART1_CR3_CKEN, UART1_CR3_CPHA, UART1_CR3_CPOL, UART1_CR3_LBCL, UART1_CR3_STOP, UART1_MODE_RX_ENABLE, UART1_MODE_TX_ENABLE, and UART1_SYNCMODE_CLOCK_DISABLE.

void UART1_IrDACmd ( FunctionalState NewState )

Enables or disables the UART’s IrDA interface.

Parameters:
NewState new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 298 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_IREN.

void UART1_IrDAConfig ( UART1_IrDAMode_TypeDef UART1_IrDAMode )

Configures the UART’s IrDA interface.

Parameters:
UART1_IrDAMode specifies the IrDA mode. This parameter can be any of the UART1_IrDAMode_TypeDef values.
Return values:
None

Definition at line 278 of file stm8s_uart1.c.

References IS_UART1_IRDAMODE_OK, UART1_CR5_IRLP, and UART1_IRDAMODE_NORMAL.

void UART1_ITConfig | ( | UART1_IT_TypeDef | UART1_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART interrupts.

Parameters:
UART1_IT specifies the USART interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • UART1_IT_TXE: Tansmit Data Register empty interrupt
  • UART1_IT_TC: Transmission complete interrupt
  • UART1_IT_RXNE: Receive Data register not empty interrupt
  • UART1_IT_OR: Overrun error interrupt
  • UART1_IT_IDLE: Idle line detection interrupt
  • USRT1_IT_ERR: Error interrupt
NewState new state of the specified USART interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

< Enable the Interrupt bits according to UART1_IT mask

< Disable the interrupt bits according to UART1_IT mask

Definition at line 205 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART1_CONFIG_IT_OK.

void UART1_LINBreakDetectionConfig ( UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength )

Sets the UART1 LIN Break detection length.

Parameters:
UART1_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART1_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 323 of file stm8s_uart1.c.

References IS_UART1_LINBREAKDETECTIONLENGTH_OK, UART1_CR4_LBDL, and UART1_LINBREAKDETECTIONLENGTH_10BITS.

void UART1_LINCmd ( FunctionalState NewState )

Enables or disables the UART1’s LIN mode.

Parameters:
NewState is new state of the UART1 LIN mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 343 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR3_LINEN.

uint8_t UART1_ReceiveData8 ( void )

Returns the most recent received data by the UART1 peripheral.

Parameters:
None
Return values:
The received data.

Definition at line 443 of file stm8s_uart1.c.

uint16_t UART1_ReceiveData9 ( void )

Returns the most recent received data by the UART1 peripheral.

Parameters:
None
Return values:
The received data.

Definition at line 453 of file stm8s_uart1.c.

References UART1_CR1_R8.

void UART1_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART1 is in mute mode or not.

Parameters:
NewState,: new state of the UART1 mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 422 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR2_RWU.

void UART1_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 493 of file stm8s_uart1.c.

References UART1_CR2_SBK.

void UART1_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART1 peripheral.

Parameters:
Data,: The data to transmit.
Return values:
None

Definition at line 466 of file stm8s_uart1.c.

void UART1_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART peripheral.

Parameters:
Data : The data to transmit. This parameter should be lower than 0x1FF.
Return values:
None

< Clear the transmit data bit 8 [8]

< Write the transmit data bit [8]

< Write the transmit data bit [0:7]

Definition at line 478 of file stm8s_uart1.c.

References UART1_CR1_T8.

void UART1_SetAddress ( uint8_t UART1_Address )

Sets the address of the UART1 node.

Parameters:
UART1_Address,: Indicates the address of the UART1 node.
Return values:
None

Definition at line 503 of file stm8s_uart1.c.

References IS_UART1_ADDRESS_OK, and UART1_CR4_ADD.

void UART1_SetGuardTime ( uint8_t UART1_GuardTime )

Sets the specified UART guard time.

Note:
SmartCard Mode should be Enabled
Parameters:
UART1_GuardTime,: specifies the guard time.
Return values:
None

Definition at line 520 of file stm8s_uart1.c.

void UART1_SetPrescaler ( uint8_t UART1_Prescaler )

Sets the system clock prescaler.

Note:
IrDA Low Power mode or smartcard mode should be enabled
This function is related to SmartCard and IrDa mode.
Parameters:
UART1_Prescaler,: specifies the prescaler clock. This parameter can be one of the following values:
IrDA Low Power Mode
The clock source is divided by the value given in the register (8 bits)
  • 0000 0000 Reserved
  • 0000 0001 divides the clock source by 1
  • 0000 0010 divides the clock source by 2
  • ...........................................................
Smart Card Mode
The clock source is divided by the value given in the register (5 significant bits) multiplied by 2
  • 0 0000 Reserved
  • 0 0001 divides the clock source by 2
  • 0 0010 divides the clock source by 4
  • 0 0011 divides the clock source by 6
  • ...........................................................
Return values:
None

Definition at line 548 of file stm8s_uart1.c.

void UART1_SmartCardCmd ( FunctionalState NewState )

Enables or disables the UART1 Smart Card mode.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 364 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_SCEN.

void UART1_SmartCardNACKCmd ( FunctionalState NewState )

Enables or disables NACK transmission.

Note:
This function is valid only for UART1 because is related to SmartCard mode.
Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 387 of file stm8s_uart1.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART1_CR5_NACK.

void UART1_WakeUpConfig ( UART1_WakeUp_TypeDef UART1_WakeUp )

Selects the UART1 WakeUp method.

Parameters:
UART1_WakeUp,: specifies the UART1 wakeup method. This parameter can be any of the UART1_WakeUp_TypeDef values.
Return values:
None

Definition at line 409 of file stm8s_uart1.c.

References IS_UART1_WAKEUP_OK, and UART1_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: UART2_Public_Functions

Functions

UART2_Public_Functions

Functions

void | UART2_ClearFlag (UART2_Flag_TypeDef UART2_FLAG)
Clears the UART2 flags.
void | UART2_ClearITPendingBit (UART2_IT_TypeDef UART2_IT)
Clears the UART2 pending flags.
void | UART2_Cmd (FunctionalState NewState)
Enable the UART2 peripheral.
void | UART2_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART2_GetFlagStatus (UART2_Flag_TypeDef UART2_FLAG)
Checks whether the specified UART2 flag is set or not.
ITStatus | UART2_GetITStatus (UART2_IT_TypeDef UART2_IT)
Checks whether the specified UART2 interrupt has occurred or not.
void | UART2_Init (uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
Initializes the UART2 according to the specified parameters.
void | UART2_IrDACmd (FunctionalState NewState)
Enables or disables the UART2’s IrDA interface.
void | UART2_IrDAConfig (UART2_IrDAMode_TypeDef UART2_IrDAMode)
Configures the UART2’s IrDA interface.
void | UART2_ITConfig (UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
Enables or disables the specified UART2 interrupts.
void | UART2_LINBreakDetectionConfig (UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
Sets the UART2 LIN Break detection length.
void | UART2_LINCmd (FunctionalState NewState)
Enables or disables the UART2 LIN mode.
void | UART2_LINConfig (UART2_LinMode_TypeDef UART2_Mode, UART2_LinAutosync_TypeDef UART2_Autosync, UART2_LinDivUp_TypeDef UART2_DivUp)
Configure the UART2 peripheral.
uint8_t | UART2_ReceiveData8 (void)
Returns the most recent received data by the UART2 peripheral.
uint16_t | UART2_ReceiveData9 (void)
Returns the most recent received data by the UART2 peripheral.
void | UART2_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART2 is in mute mode or not.
void | UART2_SendBreak (void)
Transmits break characters.
void | UART2_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART2 peripheral.
void | UART2_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART2 peripheral.
void | UART2_SetAddress (uint8_t UART2_Address)
Sets the address of the UART2 node.
void | UART2_SetGuardTime (uint8_t UART2_GuardTime)
Sets the specified UART2 guard time.
void | UART2_SetPrescaler (uint8_t UART2_Prescaler)
Sets the system clock prescaler.
void | UART2_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART2 Smart Card mode.
void | UART2_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART2_WakeUpConfig (UART2_WakeUp_TypeDef UART2_WakeUp)
Selects the UART2 WakeUp method.

Function Documentation

void UART2_ClearFlag ( UART2_Flag_TypeDef UART2_FLAG )

Clears the UART2 flags.

Parameters:
UART2_FLAG specifies the flag to clear This parameter can be any combination of the following values:

  • UART2_FLAG_LBDF: LIN Break detection flag.
  • UART2_FLAG_LHDF: LIN Header detection flag.
  • UART2_FLAG_LSF: LIN synchrone field flag.
  • UART2_FLAG_RXNE: Receive data register not empty flag.
Note:
:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART2_SR register (UART2_GetFlagStatus())followed by a read operation to UART2_DR register(UART2_ReceiveData8() or UART2_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART2_DR register (UART2_ReceiveData8()or UART2_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART2_SR register (UART2_GetFlagStatus()) followed by a write operation to UART2_DR register (UART2_SendData8() or UART2_SendData9()).
  • TXE flag is cleared only by a write to the UART2_DR register (UART2_SendData8() or UART2_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 693 of file stm8s_uart2.c.

References IS_UART2_CLEAR_FLAG_OK, UART2_CR4_LBDF, UART2_CR6_LHDF, UART2_CR6_LSF, UART2_FLAG_LBDF, UART2_FLAG_LHDF, UART2_FLAG_RXNE, and UART2_SR_RXNE.

void UART2_ClearITPendingBit ( UART2_IT_TypeDef UART2_IT )

Clears the UART2 pending flags.

Parameters:
UART2_IT specifies the pending bit to clear This parameter can be one of the following values:

  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_LHDF: LIN Header detection interrupt
  • UART2_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART2_SR register (UART2_GetITStatus()) followed by a read operation to UART2_DR register (UART2_ReceiveData8() or UART2_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART2_DR register (UART2_ReceiveData8() or UART2_ReceiveData9()).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART2_SR register (UART2_GetITStatus()) followed by a write operation to UART2_DR register (UART2_SendData8()or UART2_SendData9()).
  • TXE pending bit is cleared only by a write to the UART2_DR register (UART2_SendData8() or UART2_SendData9()).
    Return values:
    None

Definition at line 846 of file stm8s_uart2.c.

References IS_UART2_CLEAR_IT_OK, UART2_CR4_LBDF, UART2_CR6_LHDF, UART2_IT_LBDF, UART2_IT_RXNE, and UART2_SR_RXNE.

void UART2_Cmd ( FunctionalState NewState )

Enable the UART2 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 176 of file stm8s_uart2.c.

References DISABLE, and UART2_CR1_UARTD.

void UART2_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 47 of file stm8s_uart2.c.

References UART2_BRR1_RESET_VALUE, UART2_BRR2_RESET_VALUE, UART2_CR1_RESET_VALUE, UART2_CR2_RESET_VALUE, UART2_CR3_RESET_VALUE, UART2_CR4_RESET_VALUE, UART2_CR5_RESET_VALUE, and UART2_CR6_RESET_VALUE.

FlagStatus UART2_GetFlagStatus ( UART2_Flag_TypeDef UART2_FLAG )

Checks whether the specified UART2 flag is set or not.

Parameters:
UART2_FLAG specifies the flag to check. This parameter can be any of the UART2_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 601 of file stm8s_uart2.c.

References IS_UART2_FLAG_OK, RESET, SET, UART2_FLAG_LBDF, UART2_FLAG_LHDF, UART2_FLAG_LSF, and UART2_FLAG_SBK.

ITStatus UART2_GetITStatus ( UART2_IT_TypeDef UART2_IT )

Checks whether the specified UART2 interrupt has occurred or not.

Parameters:
UART2_IT,: Specifies the UART2 interrupt pending bit to check. This parameter can be one of the following values:

  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_TXE: Tansmit Data Register empty interrupt
  • UART2_IT_TC: Transmission complete interrupt
  • UART2_IT_RXNE: Receive Data register not empty interrupt
  • UART2_IT_IDLE: Idle line detection interrupt
  • UART2_IT_OR: OverRun Error interrupt
  • UART2_IT_PE: Parity Error interrupt
Return values:
The state of UART2_IT (SET or RESET).

Definition at line 732 of file stm8s_uart2.c.

References IS_UART2_GET_IT_OK, RESET, SET, UART2_IT_LBDF, UART2_IT_LHDF, and UART2_IT_PE.

void UART2_Init | ( | uint32_t | BaudRate,
 |  | UART2_WordLength_TypeDef | WordLength,
 |  | UART2_StopBits_TypeDef | StopBits,
 |  | UART2_Parity_TypeDef | Parity,
 |  | UART2_SyncMode_TypeDef | SyncMode,
 |  | UART2_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART2 according to the specified parameters.

Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART2_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART2_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART2_Parity_TypeDef enumeration.
SyncMode,: This parameter can be any of the UART2_SyncMode_TypeDef values.
Mode,: This parameter can be any of the UART2_Mode_TypeDef values
Return values:
None

Definition at line 80 of file stm8s_uart2.c.

References CLK_GetClockFreq(), IS_UART2_BAUDRATE_OK, IS_UART2_MODE_OK, IS_UART2_PARITY_OK, IS_UART2_STOPBITS_OK, IS_UART2_SYNCMODE_OK, IS_UART2_WORDLENGTH_OK, UART2_BRR1_DIVM, UART2_BRR2_DIVF, UART2_BRR2_DIVM, UART2_CR1_M, UART2_CR1_PCEN, UART2_CR1_PS, UART2_CR2_REN, UART2_CR2_TEN, UART2_CR3_CKEN, UART2_CR3_CPHA, UART2_CR3_CPOL, UART2_CR3_LBCL, UART2_CR3_STOP, UART2_MODE_RX_ENABLE, UART2_MODE_TX_ENABLE, and UART2_SYNCMODE_CLOCK_DISABLE.

void UART2_IrDACmd ( FunctionalState NewState )

Enables or disables the UART2’s IrDA interface.

Parameters:
NewState new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 287 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_IREN.

void UART2_IrDAConfig ( UART2_IrDAMode_TypeDef UART2_IrDAMode )

Configures the UART2’s IrDA interface.

Parameters:
UART2_IrDAMode specifies the IrDA mode. This parameter can be any of the UART2_IrDAMode_TypeDef values.
Return values:
None

Definition at line 267 of file stm8s_uart2.c.

References IS_UART2_IRDAMODE_OK, UART2_CR5_IRLP, and UART2_IRDAMODE_NORMAL.

void UART2_ITConfig | ( | UART2_IT_TypeDef | UART2_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified UART2 interrupts.

Parameters:
UART2_IT specifies the UART2 interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • UART2_IT_LBDF: LIN Break detection interrupt
  • UART2_IT_LHDF: LIN Break detection interrupt
  • UART2_IT_TXE: Tansmit Data Register empty interrupt
  • UART2_IT_TC: Transmission complete interrupt
  • UART2_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
  • UART2_IT_IDLE: Idle line detection interrupt
  • UART2_IT_PE: Parity Error interrupt
NewState new state of the specified UART2 interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 206 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART2_CONFIG_IT_OK.

void UART2_LINBreakDetectionConfig ( UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength )

Sets the UART2 LIN Break detection length.

Parameters:
UART2_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART2_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 311 of file stm8s_uart2.c.

References IS_UART2_LINBREAKDETECTIONLENGTH_OK, UART2_CR4_LBDL, and UART2_LINBREAKDETECTIONLENGTH_10BITS.

void UART2_LINCmd ( FunctionalState NewState )

Enables or disables the UART2 LIN mode.

Parameters:
NewState is new state of the UART2 LIN mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 379 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR3_LINEN.

void UART2_LINConfig | ( | UART2_LinMode_TypeDef | UART2_Mode,
 |  | UART2_LinAutosync_TypeDef | UART2_Autosync,
 |  | UART2_LinDivUp_TypeDef | UART2_DivUp
 | ) |  |

Configure the UART2 peripheral.

Parameters:
UART2_Mode | specifies the LIN mode. This parameter can be any of the UART2_LinMode_TypeDef values.
UART2_Autosync | specifies the LIN automatic resynchronization mode. This parameter can be any of the UART2_LinAutosync_TypeDef values.
UART2_DivUp | specifies the LIN divider update method. This parameter can be any of the UART2_LinDivUp_TypeDef values.
Return values:
None

Definition at line 336 of file stm8s_uart2.c.

References IS_UART2_AUTOSYNC_OK, IS_UART2_DIVUP_OK, IS_UART2_SLAVE_OK, UART2_CR6_LASE, UART2_CR6_LDUM, UART2_CR6_LSLV, UART2_LIN_AUTOSYNC_DISABLE, UART2_LIN_DIVUP_LBRR1, and UART2_LIN_MODE_MASTER.

uint8_t UART2_ReceiveData8 ( void )

Returns the most recent received data by the UART2 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 481 of file stm8s_uart2.c.

uint16_t UART2_ReceiveData9 ( void )

Returns the most recent received data by the UART2 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 491 of file stm8s_uart2.c.

References UART2_CR1_R8.

void UART2_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART2 is in mute mode or not.

Parameters:
NewState,: new state of the UART2 mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 460 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR2_RWU.

void UART2_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 534 of file stm8s_uart2.c.

References UART2_CR2_SBK.

void UART2_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART2 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 505 of file stm8s_uart2.c.

void UART2_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART2 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 516 of file stm8s_uart2.c.

References UART2_CR1_T8.

void UART2_SetAddress ( uint8_t UART2_Address )

Sets the address of the UART2 node.

Parameters:
UART2_Address,: Indicates the address of the UART2 node.
Return values:
None

Definition at line 544 of file stm8s_uart2.c.

References IS_UART2_ADDRESS_OK, and UART2_CR4_ADD.

void UART2_SetGuardTime ( uint8_t UART2_GuardTime )

Sets the specified UART2 guard time.

Note:
SmartCard Mode should be Enabled
Parameters:
UART2_GuardTime,: specifies the guard time.
Return values:
None

Definition at line 561 of file stm8s_uart2.c.

void UART2_SetPrescaler ( uint8_t UART2_Prescaler )

Sets the system clock prescaler.

Note:
IrDA Low Power mode or smartcard mode should be enabled
This function is related to SmartCard and IrDa mode.
Parameters:
UART2_Prescaler,: specifies the prescaler clock. This parameter can be one of the following values:
IrDA Low Power Mode
The clock source is divided by the value given in the register (8 bits)
  • 0000 0000 Reserved
  • 0000 0001 divides the clock source by 1
  • 0000 0010 divides the clock source by 2
  • ...........................................................
Smart Card Mode
The clock source is divided by the value given in the register (5 significant bits) multiped by 2
  • 0 0000 Reserved
  • 0 0001 divides the clock source by 2
  • 0 0010 divides the clock source by 4
  • 0 0011 divides the clock source by 6
  • ...........................................................
Return values:
None

Definition at line 589 of file stm8s_uart2.c.

void UART2_SmartCardCmd ( FunctionalState NewState )

Enables or disables the UART2 Smart Card mode.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 400 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_SCEN.

void UART2_SmartCardNACKCmd ( FunctionalState NewState )

Enables or disables NACK transmission.

Parameters:
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 423 of file stm8s_uart2.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART2_CR5_NACK.

void UART2_WakeUpConfig ( UART2_WakeUp_TypeDef UART2_WakeUp )

Selects the UART2 WakeUp method.

Parameters:
UART2_WakeUp,: specifies the UART2 wakeup method. This parameter can be any of the UART2_WakeUp_TypeDef values.
Return values:
None

Definition at line 446 of file stm8s_uart2.c.

References IS_UART2_WAKEUP_OK, and UART2_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: UART3_Public_Functions

Functions

UART3_Public_Functions

Functions

void | UART3_ClearFlag (UART3_Flag_TypeDef UART3_FLAG)
Clears the UART3 flags.
void | UART3_ClearITPendingBit (UART3_IT_TypeDef UART3_IT)
Clears the UART3 pending flags.
void | UART3_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART3_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART3_GetFlagStatus (UART3_Flag_TypeDef UART3_FLAG)
Checks whether the specified UART3 flag is set or not.
ITStatus | UART3_GetITStatus (UART3_IT_TypeDef UART3_IT)
Checks whether the specified UART3 interrupt has occurred or not.
void | UART3_Init (uint32_t BaudRate, UART3_WordLength_TypeDef WordLength, UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, UART3_Mode_TypeDef Mode)
Initializes the UART3 according to the specified parameters.
void | UART3_ITConfig (UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
Enables or disables the specified UART3 interrupts.
void | UART3_LINBreakDetectionConfig (UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
Sets the UART3 LIN Break detection length.
void | UART3_LINCmd (FunctionalState NewState)
Enables or disables the UART3 LIN mode.
void | UART3_LINConfig (UART3_LinMode_TypeDef UART3_Mode, UART3_LinAutosync_TypeDef UART3_Autosync, UART3_LinDivUp_TypeDef UART3_DivUp)
Configure the UART3 peripheral.
uint8_t | UART3_ReceiveData8 (void)
Returns the most recent received data by the UART3 peripheral.
uint16_t | UART3_ReceiveData9 (void)
Returns the most recent received data by the UART3 peripheral.
void | UART3_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART3 is in mute mode or not.
void | UART3_SendBreak (void)
Transmits break characters.
void | UART3_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART3 peripheral.
void | UART3_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART3 peripheral.
void | UART3_SetAddress (uint8_t UART3_Address)
Sets the address of the UART3 node.
void | UART3_WakeUpConfig (UART3_WakeUp_TypeDef UART3_WakeUp)
Selects the UART3 WakeUp method.

Function Documentation

void UART3_ClearFlag ( UART3_Flag_TypeDef UART3_FLAG )

Clears the UART3 flags.

Parameters:
UART3_FLAG specifies the flag to clear This parameter can be any combination of the following values:

  • UART3_FLAG_LBDF: LIN Break detection flag.
  • UART3_FLAG_LHDF: LIN Header detection flag.
  • UART3_FLAG_LSF: LIN synchrone field flag.
  • UART3_FLAG_RXNE: Receive data register not empty flag.
Note:
  • PE (Parity error), FE (Framing error), NF (Noise error), OR (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to UART3_SR register (UART3_GetFlagStatus())followed by a read operation to UART3_DR register(UART3_ReceiveData8() or UART3_ReceiveData9()).
  • RXNE flag can be also cleared by a read to the UART3_DR register (UART3_ReceiveData8()or UART3_ReceiveData9()).
  • TC flag can be also cleared by software sequence: a read operation to UART3_SR register (UART3_GetFlagStatus()) followed by a write operation to UART3_DR register (UART3_SendData8() or UART3_SendData9()).
  • TXE flag is cleared only by a write to the UART3_DR register (UART3_SendData8() or UART3_SendData9()).
  • SBK flag is cleared during the stop bit of break.
    Return values:
    None

Definition at line 546 of file stm8s_uart3.c.

References IS_UART3_CLEAR_FLAG_OK, UART3_CR4_LBDF, UART3_CR6_LHDF, UART3_CR6_LSF, UART3_FLAG_LBDF, UART3_FLAG_LHDF, UART3_FLAG_RXNE, and UART3_SR_RXNE.

void UART3_ClearITPendingBit ( UART3_IT_TypeDef UART3_IT )

Clears the UART3 pending flags.

Parameters:
UART3_IT specifies the pending bit to clear This parameter can be one of the following values:

  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_LHDF: LIN Header detection interrupt
  • UART3_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NF (Noise error), OR (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to UART3_SR register (UART3_GetITStatus()) followed by a read operation to UART3_DR register (UART3_ReceiveData8() or UART3_ReceiveData9()).
  • RXNE pending bit can be also cleared by a read to the UART3_DR register (UART3_ReceiveData8() or UART3_ReceiveData9() ).
  • TC (Transmit complete) pending bit can be cleared by software sequence: a read operation to UART3_SR register (UART3_GetITStatus()) followed by a write operation to UART3_DR register (UART3_SendData8()or UART3_SendData9()).
  • TXE pending bit is cleared only by a write to the UART3_DR register (UART3_SendData8() or UART3_SendData9()).
    Return values:
    None

Definition at line 701 of file stm8s_uart3.c.

References IS_UART3_CLEAR_IT_OK, UART3_CR4_LBDF, UART3_CR6_LHDF, UART3_IT_LBDF, UART3_IT_RXNE, and UART3_SR_RXNE.

void UART3_Cmd ( FunctionalState NewState )

Enable the UART1 peripheral.

Parameters:
NewState : The new state of the UART Communication. This parameter can be any of the FunctionalState enumeration.
Return values:
None

Definition at line 155 of file stm8s_uart3.c.

References DISABLE, and UART3_CR1_UARTD.

void UART3_DeInit ( void )

Deinitializes the UART peripheral.

Parameters:
None
Return values:
None

Definition at line 48 of file stm8s_uart3.c.

References UART3_BRR1_RESET_VALUE, UART3_BRR2_RESET_VALUE, UART3_CR1_RESET_VALUE, UART3_CR2_RESET_VALUE, UART3_CR3_RESET_VALUE, UART3_CR4_RESET_VALUE, and UART3_CR6_RESET_VALUE.

FlagStatus UART3_GetFlagStatus ( UART3_Flag_TypeDef UART3_FLAG )

Checks whether the specified UART3 flag is set or not.

Parameters:
UART3_FLAG specifies the flag to check. This parameter can be any of the UART3_Flag_TypeDef enumeration.
Return values:
FlagStatus (SET or RESET)

Definition at line 454 of file stm8s_uart3.c.

References IS_UART3_FLAG_OK, RESET, SET, UART3_FLAG_LBDF, UART3_FLAG_LHDF, UART3_FLAG_LSF, and UART3_FLAG_SBK.

ITStatus UART3_GetITStatus ( UART3_IT_TypeDef UART3_IT )

Checks whether the specified UART3 interrupt has occurred or not.

Parameters:
UART3_IT,: Specifies the UART3 interrupt pending bit to check. This parameter can be one of the following values:

  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_TXE: Tansmit Data Register empty interrupt
  • UART3_IT_TC: Transmission complete interrupt
  • UART3_IT_RXNE: Receive Data register not empty interrupt
  • UART3_IT_IDLE: Idle line detection interrupt
  • UART3_IT_OR: OverRun Error interrupt
  • UART3_IT_PE: Parity Error interrupt
Return values:
The state of UART3_IT (SET or RESET).

Definition at line 586 of file stm8s_uart3.c.

References IS_UART3_GET_IT_OK, RESET, SET, UART3_IT_LBDF, UART3_IT_LHDF, and UART3_IT_PE.

void UART3_Init | ( | uint32_t | BaudRate,
 |  | UART3_WordLength_TypeDef | WordLength,
 |  | UART3_StopBits_TypeDef | StopBits,
 |  | UART3_Parity_TypeDef | Parity,
 |  | UART3_Mode_TypeDef | Mode
 | ) |  |

Initializes the UART3 according to the specified parameters.

Parameters:
BaudRate,: The baudrate.
WordLength : This parameter can be any of the UART3_WordLength_TypeDef enumeration.
StopBits,: This parameter can be any of the UART3_StopBits_TypeDef enumeration.
Parity,: This parameter can be any of the UART3_Parity_TypeDef enumeration.
Mode,: This parameter can be any of the UART3_Mode_TypeDef values
Return values:
None

Definition at line 78 of file stm8s_uart3.c.

References CLK_GetClockFreq(), IS_UART3_BAUDRATE_OK, IS_UART3_MODE_OK, IS_UART3_PARITY_OK, IS_UART3_STOPBITS_OK, IS_UART3_WORDLENGTH_OK, UART3_BRR1_DIVM, UART3_BRR2_DIVF, UART3_BRR2_DIVM, UART3_CR1_M, UART3_CR1_PCEN, UART3_CR1_PS, UART3_CR2_REN, UART3_CR2_TEN, UART3_CR3_STOP, UART3_MODE_RX_ENABLE, and UART3_MODE_TX_ENABLE.

void UART3_ITConfig | ( | UART3_IT_TypeDef | UART3_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified UART3 interrupts.

Parameters:
UART3_IT specifies the UART3 interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • UART3_IT_LBDF: LIN Break detection interrupt
  • UART3_IT_LHDF: LIN Break detection interrupt
  • UART3_IT_TXE: Tansmit Data Register empty interrupt
  • UART3_IT_TC: Transmission complete interrupt
  • UART3_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
  • UART3_IT_IDLE: Idle line detection interrupt
  • UART3_IT_PE: Parity Error interrupt
NewState new state of the specified UART3 interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 185 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and IS_UART3_CONFIG_IT_OK.

void UART3_LINBreakDetectionConfig ( UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength )

Sets the UART3 LIN Break detection length.

Parameters:
UART3_LINBreakDetectionLength specifies the LIN break detection length. This parameter can be any of the UART3_LINBreakDetectionLength_TypeDef values.
Return values:
None

Definition at line 248 of file stm8s_uart3.c.

References IS_UART3_LINBREAKDETECTIONLENGTH_OK, UART3_CR4_LBDL, and UART3_LINBREAKDETECTIONLENGTH_10BITS.

void UART3_LINCmd ( FunctionalState NewState )

Enables or disables the UART3 LIN mode.

Parameters:
NewState is new state of the UART3 LIN mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 316 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART3_CR3_LINEN.

void UART3_LINConfig | ( | UART3_LinMode_TypeDef | UART3_Mode,
 |  | UART3_LinAutosync_TypeDef | UART3_Autosync,
 |  | UART3_LinDivUp_TypeDef | UART3_DivUp
 | ) |  |

Configure the UART3 peripheral.

Parameters:
UART3_Mode | specifies the LIN mode. This parameter can be any of the UART3_LinMode_TypeDef values.
UART3_Autosync | specifies the LIN automatic resynchronization mode. This parameter can be any of the UART3_LinAutosync_TypeDef values.
UART3_DivUp | specifies the LIN divider update method. This parameter can be any of the UART3_LinDivUp_TypeDef values.
Return values:
None

Definition at line 273 of file stm8s_uart3.c.

References IS_UART3_AUTOSYNC_OK, IS_UART3_DIVUP_OK, IS_UART3_SLAVE_OK, UART3_CR6_LASE, UART3_CR6_LDUM, UART3_CR6_LSLV, UART3_LIN_AUTOSYNC_DISABLE, UART3_LIN_DIVUP_LBRR1, and UART3_LIN_MODE_MASTER.

uint8_t UART3_ReceiveData8 ( void )

Returns the most recent received data by the UART3 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 376 of file stm8s_uart3.c.

uint16_t UART3_ReceiveData9 ( void )

Returns the most recent received data by the UART3 peripheral.

Parameters:
None
Return values:
Received Data

Definition at line 386 of file stm8s_uart3.c.

References UART3_CR1_R8.

void UART3_ReceiverWakeUpCmd ( FunctionalState NewState )

Determines if the UART3 is in mute mode or not.

Parameters:
NewState,: new state of the UART3 mode. This parameter can be ENABLE or DISABLE
Return values:
None

Definition at line 354 of file stm8s_uart3.c.

References DISABLE, IS_FUNCTIONALSTATE_OK, and UART3_CR2_RWU.

void UART3_SendBreak ( void )

Transmits break characters.

Parameters:
None
Return values:
None

Definition at line 427 of file stm8s_uart3.c.

References UART3_CR2_SBK.

void UART3_SendData8 ( uint8_t Data )

Transmits 8 bit data through the UART3 peripheral.

Parameters:
Data the data to transmit.
Return values:
None

Definition at line 399 of file stm8s_uart3.c.

void UART3_SendData9 ( uint16_t Data )

Transmits 9 bit data through the UART3 peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 410 of file stm8s_uart3.c.

References UART3_CR1_T8.

void UART3_SetAddress ( uint8_t UART3_Address )

Sets the address of the UART3 node.

Parameters:
UART3_Address,: Indicates the address of the UART3 node.
Return values:
None

Definition at line 437 of file stm8s_uart3.c.

References IS_UART3_ADDRESS_OK, and UART3_CR4_ADD.

void UART3_WakeUpConfig ( UART3_WakeUp_TypeDef UART3_WakeUp )

Selects the UART3 WakeUp method.

Parameters:
UART3_WakeUp,: specifies the UART3 wakeup method. This parameter can be any of the UART3_WakeUp_TypeDef values.
Return values:
None

Definition at line 339 of file stm8s_uart3.c.

References IS_UART3_WAKEUP_OK, and UART3_CR1_WAKE.


STM8S/A Standard Peripherals Drivers: AWU_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

AWU_struct Struct Reference

Auto Wake Up (AWU) peripheral registers. More...

#include <stm8s.h>

Data Fields

__IO uint8_t | APR
__IO uint8_t | CSR
__IO uint8_t | TBR

Detailed Description

Auto Wake Up (AWU) peripheral registers.

Definition at line 424 of file stm8s.h.

Field Documentation

__IO uint8_t AWU_struct::APR

AWU Asynchronous prescaler buffer

Definition at line 427 of file stm8s.h.

__IO uint8_t AWU_struct::CSR

AWU Control status register

Definition at line 426 of file stm8s.h.

__IO uint8_t AWU_struct::TBR

AWU Time base selection register

Definition at line 428 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: BEEP_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

BEEP_struct Struct Reference

Beeper (BEEP) peripheral registers. More...

#include <stm8s.h>

Data Fields

__IO uint8_t CSR

Detailed Description

Beeper (BEEP) peripheral registers.

Definition at line 464 of file stm8s.h.

Field Documentation

__IO uint8_t BEEP_struct::CSR

BEEP Control status register

Definition at line 466 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: CAN_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CAN_TypeDef Struct Reference

Controller Area Network (CAN) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | DGR
__IO uint8_t | IER
__IO uint8_t | MCR
__IO uint8_t | MSR
union {
struct {
__IO uint8_t BTR1
__IO uint8_t BTR2
__IO uint8_t EIER
__IO uint8_t ESR
__IO uint8_t FCR1
__IO uint8_t FCR2
__IO uint8_t FCR3
__IO uint8_t FMR1
__IO uint8_t FMR2
__IO uint8_t RECR
u8 Reserved1 [2]
u8 Reserved2 [3]
__IO uint8_t TECR
} Config
struct {
__IO uint8_t FR01
__IO uint8_t FR02
__IO uint8_t FR03
__IO uint8_t FR04
__IO uint8_t FR05
__IO uint8_t FR06
__IO uint8_t FR07
__IO uint8_t FR08
__IO uint8_t FR09
__IO uint8_t FR10
__IO uint8_t FR11
__IO uint8_t FR12
__IO uint8_t FR13
__IO uint8_t FR14
__IO uint8_t FR15
__IO uint8_t FR16
} Filter
struct {
__IO uint8_t F0R1
__IO uint8_t F0R2
__IO uint8_t F0R3
__IO uint8_t F0R4
__IO uint8_t F0R5
__IO uint8_t F0R6
__IO uint8_t F0R7
__IO uint8_t F0R8
__IO uint8_t F1R1
__IO uint8_t F1R2
__IO uint8_t F1R3
__IO uint8_t F1R4
__IO uint8_t F1R5
__IO uint8_t F1R6
__IO uint8_t F1R7
__IO uint8_t F1R8
} Filter01
struct {
__IO uint8_t F2R1
__IO uint8_t F2R2
__IO uint8_t F2R3
__IO uint8_t F2R4
__IO uint8_t F2R5
__IO uint8_t F2R6
__IO uint8_t F2R7
__IO uint8_t F2R8
__IO uint8_t F3R1
__IO uint8_t F3R2
__IO uint8_t F3R3
__IO uint8_t F3R4
__IO uint8_t F3R5
__IO uint8_t F3R6
__IO uint8_t F3R7
__IO uint8_t F3R8
} Filter23
struct {
__IO uint8_t F4R1
__IO uint8_t F4R2
__IO uint8_t F4R3
__IO uint8_t F4R4
__IO uint8_t F4R5
__IO uint8_t F4R6
__IO uint8_t F4R7
__IO uint8_t F4R8
__IO uint8_t F5R1
__IO uint8_t F5R2
__IO uint8_t F5R3
__IO uint8_t F5R4
__IO uint8_t F5R5
__IO uint8_t F5R6
__IO uint8_t F5R7
__IO uint8_t F5R8
} Filter45
struct {
__IO uint8_t MDAR1
__IO uint8_t MDAR2
__IO uint8_t MDAR3
__IO uint8_t MDAR4
__IO uint8_t MDAR5
__IO uint8_t MDAR6
__IO uint8_t MDAR7
__IO uint8_t MDAR8
__IO uint8_t MDLCR
__IO uint8_t MFMI
__IO uint8_t MIDR1
__IO uint8_t MIDR2
__IO uint8_t MIDR3
__IO uint8_t MIDR4
__IO uint8_t MTSRH
__IO uint8_t MTSRL
} RxFIFO
struct {
__IO uint8_t MCSR
__IO uint8_t MDAR1
__IO uint8_t MDAR2
__IO uint8_t MDAR3
__IO uint8_t MDAR4
__IO uint8_t MDAR5
__IO uint8_t MDAR6
__IO uint8_t MDAR7
__IO uint8_t MDAR8
__IO uint8_t MDLCR
__IO uint8_t MIDR1
__IO uint8_t MIDR2
__IO uint8_t MIDR3
__IO uint8_t MIDR4
__IO uint8_t MTSRH
__IO uint8_t MTSRL
} TxMailbox
} Page
__IO uint8_t | PSR
__IO uint8_t | RFR
__IO uint8_t | TPR
__IO uint8_t | TSR

Detailed Description

Controller Area Network (CAN)

Definition at line 2050 of file stm8s.h.

Field Documentation

__IO uint8_t CAN_TypeDef::BTR1

Definition at line 2179 of file stm8s.h.

__IO uint8_t CAN_TypeDef::BTR2

Definition at line 2180 of file stm8s.h.

struct { ... } CAN_TypeDef::Config
__IO uint8_t CAN_TypeDef::DGR

CAN diagnosis register

Definition at line 2058 of file stm8s.h.

__IO uint8_t CAN_TypeDef::EIER

Definition at line 2176 of file stm8s.h.

__IO uint8_t CAN_TypeDef::ESR

Definition at line 2175 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R1

Definition at line 2109 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R2

Definition at line 2110 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R3

Definition at line 2111 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R4

Definition at line 2112 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R5

Definition at line 2113 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R6

Definition at line 2114 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R7

Definition at line 2115 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F0R8

Definition at line 2116 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R1

Definition at line 2118 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R2

Definition at line 2119 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R3

Definition at line 2120 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R4

Definition at line 2121 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R5

Definition at line 2122 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R6

Definition at line 2123 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R7

Definition at line 2124 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F1R8

Definition at line 2125 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R1

Definition at line 2131 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R2

Definition at line 2132 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R3

Definition at line 2133 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R4

Definition at line 2134 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R5

Definition at line 2135 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R6

Definition at line 2136 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R7

Definition at line 2137 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F2R8

Definition at line 2138 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R1

Definition at line 2140 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R2

Definition at line 2141 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R3

Definition at line 2142 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R4

Definition at line 2143 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R5

Definition at line 2144 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R6

Definition at line 2145 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R7

Definition at line 2146 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F3R8

Definition at line 2147 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R1

Definition at line 2153 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R2

Definition at line 2154 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R3

Definition at line 2155 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R4

Definition at line 2156 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R5

Definition at line 2157 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R6

Definition at line 2158 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R7

Definition at line 2159 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F4R8

Definition at line 2160 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R1

Definition at line 2162 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R2

Definition at line 2163 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R3

Definition at line 2164 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R4

Definition at line 2165 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R5

Definition at line 2166 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R6

Definition at line 2167 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R7

Definition at line 2168 of file stm8s.h.

__IO uint8_t CAN_TypeDef::F5R8

Definition at line 2169 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FCR1

Definition at line 2184 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FCR2

Definition at line 2185 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FCR3

Definition at line 2186 of file stm8s.h.

struct { ... } CAN_TypeDef::Filter
struct { ... } CAN_TypeDef::Filter01
struct { ... } CAN_TypeDef::Filter23
struct { ... } CAN_TypeDef::Filter45
__IO uint8_t CAN_TypeDef::FMR1

Definition at line 2182 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FMR2

Definition at line 2183 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR01

Definition at line 2086 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR02

Definition at line 2087 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR03

Definition at line 2088 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR04

Definition at line 2089 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR05

Definition at line 2090 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR06

Definition at line 2091 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR07

Definition at line 2092 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR08

Definition at line 2093 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR09

Definition at line 2095 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR10

Definition at line 2096 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR11

Definition at line 2097 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR12

Definition at line 2098 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR13

Definition at line 2099 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR14

Definition at line 2100 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR15

Definition at line 2101 of file stm8s.h.

__IO uint8_t CAN_TypeDef::FR16

Definition at line 2102 of file stm8s.h.

__IO uint8_t CAN_TypeDef::IER

CAN interrupt enable register

Definition at line 2057 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MCR

CAN master control register

Definition at line 2052 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MCSR

Definition at line 2065 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR1

Definition at line 2071 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR2

Definition at line 2072 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR3

Definition at line 2073 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR4

Definition at line 2074 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR5

Definition at line 2075 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR6

Definition at line 2076 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR7

Definition at line 2077 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDAR8

Definition at line 2078 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MDLCR

Definition at line 2066 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MFMI

Definition at line 2193 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MIDR1

Definition at line 2067 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MIDR2

Definition at line 2068 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MIDR3

Definition at line 2069 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MIDR4

Definition at line 2070 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MSR

CAN master status register

Definition at line 2053 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MTSRH

Definition at line 2080 of file stm8s.h.

__IO uint8_t CAN_TypeDef::MTSRL

Definition at line 2079 of file stm8s.h.

union { ... } CAN_TypeDef::Page
__IO uint8_t CAN_TypeDef::PSR

CAN page selection register

Definition at line 2059 of file stm8s.h.

__IO uint8_t CAN_TypeDef::RECR

Definition at line 2178 of file stm8s.h.

u8 CAN_TypeDef::Reserved1[2]

Definition at line 2181 of file stm8s.h.

u8 CAN_TypeDef::Reserved2[3]

Definition at line 2187 of file stm8s.h.

__IO uint8_t CAN_TypeDef::RFR

CAN receive FIFO register

Definition at line 2056 of file stm8s.h.

struct { ... } CAN_TypeDef::RxFIFO
__IO uint8_t CAN_TypeDef::TECR

Definition at line 2177 of file stm8s.h.

__IO uint8_t CAN_TypeDef::TPR

CAN transmit priority register

Definition at line 2055 of file stm8s.h.

__IO uint8_t CAN_TypeDef::TSR

CAN transmit status register

Definition at line 2054 of file stm8s.h.

struct { ... } CAN_TypeDef::TxMailbox
The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: CFG_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CFG_struct Struct Reference

Configuration Registers (CFG) More...

#include <stm8s.h>

Data Fields

__IO uint8_t GCR

Detailed Description

Configuration Registers (CFG)

Definition at line 2408 of file stm8s.h.

Field Documentation

__IO uint8_t CFG_struct::GCR

Global Configuration register

Definition at line 2410 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: CLK_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CLK_struct Struct Reference

Clock Controller (CLK) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CCOR
__IO uint8_t | CKDIVR
__IO uint8_t | CMSR
__IO uint8_t | CSSR
__IO uint8_t | ECKR
__IO uint8_t | HSITRIMR
__IO uint8_t | ICKR
__IO uint8_t | PCKENR1
__IO uint8_t | PCKENR2
uint8_t RESERVED
uint8_t RESERVED1
__IO uint8_t | SWCR
__IO uint8_t | SWIMCCR
__IO uint8_t | SWR

Detailed Description

Clock Controller (CLK)

Definition at line 492 of file stm8s.h.

Field Documentation

__IO uint8_t CLK_struct::CCOR

Configurable Clock Output Register

Definition at line 503 of file stm8s.h.

__IO uint8_t CLK_struct::CKDIVR

Clock Divider Register

Definition at line 500 of file stm8s.h.

__IO uint8_t CLK_struct::CMSR

Clock Master Status Register

Definition at line 497 of file stm8s.h.

__IO uint8_t CLK_struct::CSSR

Clock Security System Register

Definition at line 502 of file stm8s.h.

__IO uint8_t CLK_struct::ECKR

External Clocks Control Register

Definition at line 495 of file stm8s.h.

__IO uint8_t CLK_struct::HSITRIMR

HSI Calibration Trimmer Register

Definition at line 506 of file stm8s.h.

__IO uint8_t CLK_struct::ICKR

Internal Clocks Control Register

Definition at line 494 of file stm8s.h.

__IO uint8_t CLK_struct::PCKENR1

Peripheral Clock Gating Register 1

Definition at line 501 of file stm8s.h.

__IO uint8_t CLK_struct::PCKENR2

Peripheral Clock Gating Register 2

Definition at line 504 of file stm8s.h.

uint8_t CLK_struct::RESERVED

Reserved byte

Definition at line 496 of file stm8s.h.

uint8_t CLK_struct::RESERVED1

Reserved byte

Definition at line 505 of file stm8s.h.

__IO uint8_t CLK_struct::SWCR

Switch Control Register

Definition at line 499 of file stm8s.h.

__IO uint8_t CLK_struct::SWIMCCR

SWIM clock control register

Definition at line 507 of file stm8s.h.

__IO uint8_t CLK_struct::SWR

Clock Master Switch Register

Definition at line 498 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: EXTI_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

EXTI_struct Struct Reference

External Interrupt Controller (EXTI) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CR1
__IO uint8_t | CR2

Detailed Description

External Interrupt Controller (EXTI)

Definition at line 1457 of file stm8s.h.

Field Documentation

__IO uint8_t EXTI_struct::CR1

External Interrupt Control Register for PORTA to PORTD

Definition at line 1459 of file stm8s.h.

__IO uint8_t EXTI_struct::CR2

External Interrupt Control Register for PORTE and TLI

Definition at line 1460 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: FLASH_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FLASH_struct Struct Reference

FLASH program and Data memory (FLASH) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | DUKR
__IO uint8_t | FPR
__IO uint8_t | IAPSR
__IO uint8_t | NCR2
__IO uint8_t | NFPR
__IO uint8_t | PUKR
uint8_t RESERVED1
uint8_t RESERVED2
uint8_t RESERVED3

Detailed Description

FLASH program and Data memory (FLASH)

Definition at line 1498 of file stm8s.h.

Field Documentation

__IO uint8_t FLASH_struct::CR1

Flash control register 1

Definition at line 1500 of file stm8s.h.

__IO uint8_t FLASH_struct::CR2

Flash control register 2

Definition at line 1501 of file stm8s.h.

__IO uint8_t FLASH_struct::DUKR

Data EEPROM unprotection register

Definition at line 1510 of file stm8s.h.

__IO uint8_t FLASH_struct::FPR

Flash protection register

Definition at line 1503 of file stm8s.h.

__IO uint8_t FLASH_struct::IAPSR

Flash in-application programming status register

Definition at line 1505 of file stm8s.h.

__IO uint8_t FLASH_struct::NCR2

Flash complementary control register 2

Definition at line 1502 of file stm8s.h.

__IO uint8_t FLASH_struct::NFPR

Flash complementary protection register

Definition at line 1504 of file stm8s.h.

__IO uint8_t FLASH_struct::PUKR

Flash program memory unprotection register

Definition at line 1508 of file stm8s.h.

uint8_t FLASH_struct::RESERVED1

Reserved byte

Definition at line 1506 of file stm8s.h.

uint8_t FLASH_struct::RESERVED2

Reserved byte

Definition at line 1507 of file stm8s.h.

uint8_t FLASH_struct::RESERVED3

Reserved byte

Definition at line 1509 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: I2C_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

I2C_struct Struct Reference

Inter-Integrated Circuit (I2C) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CCRH
__IO uint8_t | CCRL
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | DR
__IO uint8_t | FREQR
__IO uint8_t | ITR
__IO uint8_t | OARH
__IO uint8_t | OARL
uint8_t RESERVED1
uint8_t RESERVED2
__IO uint8_t | SR1
__IO uint8_t | SR2
__IO uint8_t | SR3
__IO uint8_t | TRISER

Detailed Description

Inter-Integrated Circuit (I2C)

Definition at line 1312 of file stm8s.h.

Field Documentation

__IO uint8_t I2C_struct::CCRH

I2C clock control register high

Definition at line 1326 of file stm8s.h.

__IO uint8_t I2C_struct::CCRL

I2C clock control register low

Definition at line 1325 of file stm8s.h.

__IO uint8_t I2C_struct::CR1

I2C control register 1

Definition at line 1314 of file stm8s.h.

__IO uint8_t I2C_struct::CR2

I2C control register 2

Definition at line 1315 of file stm8s.h.

__IO uint8_t I2C_struct::DR

I2C data register

Definition at line 1320 of file stm8s.h.

__IO uint8_t I2C_struct::FREQR

I2C frequency register

Definition at line 1316 of file stm8s.h.

__IO uint8_t I2C_struct::ITR

I2C interrupt register

Definition at line 1324 of file stm8s.h.

__IO uint8_t I2C_struct::OARH

I2C own address register MSB

Definition at line 1318 of file stm8s.h.

__IO uint8_t I2C_struct::OARL

I2C own address register LSB

Definition at line 1317 of file stm8s.h.

uint8_t I2C_struct::RESERVED1

Reserved byte

Definition at line 1319 of file stm8s.h.

uint8_t I2C_struct::RESERVED2

Reserved byte

Definition at line 1328 of file stm8s.h.

__IO uint8_t I2C_struct::SR1

I2C status register 1

Definition at line 1321 of file stm8s.h.

__IO uint8_t I2C_struct::SR2

I2C status register 2

Definition at line 1322 of file stm8s.h.

__IO uint8_t I2C_struct::SR3

I2C status register 3

Definition at line 1323 of file stm8s.h.

__IO uint8_t I2C_struct::TRISER

I2C maximum rise time register

Definition at line 1327 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: ITC_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

ITC_struct Struct Reference

Interrupt Controller (ITC) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ISPR1
__IO uint8_t | ISPR2
__IO uint8_t | ISPR3
__IO uint8_t | ISPR4
__IO uint8_t | ISPR5
__IO uint8_t | ISPR6
__IO uint8_t | ISPR7
__IO uint8_t | ISPR8

Detailed Description

Interrupt Controller (ITC)

Definition at line 1419 of file stm8s.h.

Field Documentation

__IO uint8_t ITC_struct::ISPR1

Interrupt Software Priority register 1

Definition at line 1421 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR2

Interrupt Software Priority register 2

Definition at line 1422 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR3

Interrupt Software Priority register 3

Definition at line 1423 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR4

Interrupt Software Priority register 4

Definition at line 1424 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR5

Interrupt Software Priority register 5

Definition at line 1425 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR6

Interrupt Software Priority register 6

Definition at line 1426 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR7

Interrupt Software Priority register 7

Definition at line 1427 of file stm8s.h.

__IO uint8_t ITC_struct::ISPR8

Interrupt Software Priority register 8

Definition at line 1428 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: IWDG_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

IWDG_struct Struct Reference

Independent Watchdog (IWDG) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | KR
__IO uint8_t | PR
__IO uint8_t | RLR

Detailed Description

Independent Watchdog (IWDG)

Definition at line 1593 of file stm8s.h.

Field Documentation

__IO uint8_t IWDG_struct::KR

Key Register

Definition at line 1595 of file stm8s.h.

__IO uint8_t IWDG_struct::PR

Prescaler Register

Definition at line 1596 of file stm8s.h.

__IO uint8_t IWDG_struct::RLR

Reload Register

Definition at line 1597 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: OPT_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

OPT_struct Struct Reference

Option Bytes (OPT) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | NOPT1
__IO uint8_t | NOPT2
__IO uint8_t | NOPT3
__IO uint8_t | NOPT4
__IO uint8_t | NOPT5
__IO uint8_t | NOPT7
__IO uint8_t | OPT0
__IO uint8_t | OPT1
__IO uint8_t | OPT2
__IO uint8_t | OPT3
__IO uint8_t | OPT4
__IO uint8_t | OPT5
__IO uint8_t | OPT7
uint8_t RESERVED1
uint8_t RESERVED2

Detailed Description

Option Bytes (OPT)

Definition at line 1568 of file stm8s.h.

Field Documentation

__IO uint8_t OPT_struct::NOPT1

Complementary Option byte 1

Definition at line 1572 of file stm8s.h.

__IO uint8_t OPT_struct::NOPT2

Complementary Option byte 2

Definition at line 1574 of file stm8s.h.

__IO uint8_t OPT_struct::NOPT3

Complementary Option byte 3

Definition at line 1576 of file stm8s.h.

__IO uint8_t OPT_struct::NOPT4

Complementary Option byte 4

Definition at line 1578 of file stm8s.h.

__IO uint8_t OPT_struct::NOPT5

Complementary Option byte 5

Definition at line 1580 of file stm8s.h.

__IO uint8_t OPT_struct::NOPT7

Complementary Option byte 7

Definition at line 1584 of file stm8s.h.

__IO uint8_t OPT_struct::OPT0

Option byte 0: Read-out protection (not accessible in IAP mode)

Definition at line 1570 of file stm8s.h.

__IO uint8_t OPT_struct::OPT1

Option byte 1: User boot code

Definition at line 1571 of file stm8s.h.

__IO uint8_t OPT_struct::OPT2

Option byte 2: Alternate function remapping

Definition at line 1573 of file stm8s.h.

__IO uint8_t OPT_struct::OPT3

Option byte 3: Watchdog option

Definition at line 1575 of file stm8s.h.

__IO uint8_t OPT_struct::OPT4

Option byte 4: Clock option

Definition at line 1577 of file stm8s.h.

__IO uint8_t OPT_struct::OPT5

Option byte 5: HSE clock startup

Definition at line 1579 of file stm8s.h.

__IO uint8_t OPT_struct::OPT7

Option byte 7: flash wait states

Definition at line 1583 of file stm8s.h.

uint8_t OPT_struct::RESERVED1

Reserved Option byte

Definition at line 1581 of file stm8s.h.

uint8_t OPT_struct::RESERVED2

Reserved Option byte

Definition at line 1582 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: RST_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RST_struct Struct Reference

Reset Controller (RST) More...

#include <stm8s.h>

Data Fields

__IO uint8_t SR

Detailed Description

Reset Controller (RST)

Definition at line 1655 of file stm8s.h.

Field Documentation

__IO uint8_t RST_struct::SR

Reset status register

Definition at line 1657 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: SPI_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SPI_struct Struct Reference

Serial Peripheral Interface (SPI) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | CRCPR
__IO uint8_t | DR
__IO uint8_t | ICR
__IO uint8_t | RXCRCR
__IO uint8_t | SR
__IO uint8_t | TXCRCR

Detailed Description

Serial Peripheral Interface (SPI)

Definition at line 1680 of file stm8s.h.

Field Documentation

__IO uint8_t SPI_struct::CR1

SPI control register 1

Definition at line 1682 of file stm8s.h.

__IO uint8_t SPI_struct::CR2

SPI control register 2

Definition at line 1683 of file stm8s.h.

__IO uint8_t SPI_struct::CRCPR

SPI CRC polynomial register

Definition at line 1687 of file stm8s.h.

__IO uint8_t SPI_struct::DR

SPI data I/O register

Definition at line 1686 of file stm8s.h.

__IO uint8_t SPI_struct::ICR

SPI interrupt control register

Definition at line 1684 of file stm8s.h.

__IO uint8_t SPI_struct::RXCRCR

SPI Rx CRC register

Definition at line 1688 of file stm8s.h.

__IO uint8_t SPI_struct::SR

SPI status register

Definition at line 1685 of file stm8s.h.

__IO uint8_t SPI_struct::TXCRCR

SPI Tx CRC register

Definition at line 1689 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM1_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM1_struct Struct Reference

16-bit timer with complementary PWM outputs (TIM1) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARRH
__IO uint8_t | ARRL
__IO uint8_t | BKR
__IO uint8_t | CCER1
__IO uint8_t | CCER2
__IO uint8_t | CCMR1
__IO uint8_t | CCMR2
__IO uint8_t | CCMR3
__IO uint8_t | CCMR4
__IO uint8_t | CCR1H
__IO uint8_t | CCR1L
__IO uint8_t | CCR2H
__IO uint8_t | CCR2L
__IO uint8_t | CCR3H
__IO uint8_t | CCR3L
__IO uint8_t | CCR4H
__IO uint8_t | CCR4L
__IO uint8_t | CNTRH
__IO uint8_t | CNTRL
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | DTR
__IO uint8_t | EGR
__IO uint8_t | ETR
__IO uint8_t | IER
__IO uint8_t | OISR
__IO uint8_t | PSCRH
__IO uint8_t | PSCRL
__IO uint8_t | RCR
__IO uint8_t | SMCR
__IO uint8_t | SR1
__IO uint8_t | SR2

Detailed Description

16-bit timer with complementary PWM outputs (TIM1)

Definition at line 596 of file stm8s.h.

Field Documentation

__IO uint8_t TIM1_struct::ARRH

auto-reload register high

Definition at line 616 of file stm8s.h.

__IO uint8_t TIM1_struct::ARRL

auto-reload register low

Definition at line 617 of file stm8s.h.

__IO uint8_t TIM1_struct::BKR

Break Register

Definition at line 627 of file stm8s.h.

__IO uint8_t TIM1_struct::CCER1

CC enable register 1

Definition at line 610 of file stm8s.h.

__IO uint8_t TIM1_struct::CCER2

CC enable register 2

Definition at line 611 of file stm8s.h.

__IO uint8_t TIM1_struct::CCMR1

CC mode register 1

Definition at line 606 of file stm8s.h.

__IO uint8_t TIM1_struct::CCMR2

CC mode register 2

Definition at line 607 of file stm8s.h.

__IO uint8_t TIM1_struct::CCMR3

CC mode register 3

Definition at line 608 of file stm8s.h.

__IO uint8_t TIM1_struct::CCMR4

CC mode register 4

Definition at line 609 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR1H

capture/compare register 1 high

Definition at line 619 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR1L

capture/compare register 1 low

Definition at line 620 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR2H

capture/compare register 2 high

Definition at line 621 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR2L

capture/compare register 2 low

Definition at line 622 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR3H

capture/compare register 3 high

Definition at line 623 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR3L

capture/compare register 3 low

Definition at line 624 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR4H

capture/compare register 3 high

Definition at line 625 of file stm8s.h.

__IO uint8_t TIM1_struct::CCR4L

capture/compare register 3 low

Definition at line 626 of file stm8s.h.

__IO uint8_t TIM1_struct::CNTRH

counter high

Definition at line 612 of file stm8s.h.

__IO uint8_t TIM1_struct::CNTRL

counter low

Definition at line 613 of file stm8s.h.

__IO uint8_t TIM1_struct::CR1

control register 1

Definition at line 598 of file stm8s.h.

__IO uint8_t TIM1_struct::CR2

control register 2

Definition at line 599 of file stm8s.h.

__IO uint8_t TIM1_struct::DTR

dead-time register

Definition at line 628 of file stm8s.h.

__IO uint8_t TIM1_struct::EGR

event generation register

Definition at line 605 of file stm8s.h.

__IO uint8_t TIM1_struct::ETR

external trigger register

Definition at line 601 of file stm8s.h.

__IO uint8_t TIM1_struct::IER

interrupt enable register

Definition at line 602 of file stm8s.h.

__IO uint8_t TIM1_struct::OISR

Output idle register

Definition at line 629 of file stm8s.h.

__IO uint8_t TIM1_struct::PSCRH

prescaler high

Definition at line 614 of file stm8s.h.

__IO uint8_t TIM1_struct::PSCRL

prescaler low

Definition at line 615 of file stm8s.h.

__IO uint8_t TIM1_struct::RCR

Repetition Counter register

Definition at line 618 of file stm8s.h.

__IO uint8_t TIM1_struct::SMCR

Synchro mode control register

Definition at line 600 of file stm8s.h.

__IO uint8_t TIM1_struct::SR1

status register 1

Definition at line 603 of file stm8s.h.

__IO uint8_t TIM1_struct::SR2

status register 2

Definition at line 604 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM2_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM2_struct Struct Reference

16-bit timer (TIM2) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARRH
__IO uint8_t | ARRL
__IO uint8_t | CCER1
__IO uint8_t | CCER2
__IO uint8_t | CCMR1
__IO uint8_t | CCMR2
__IO uint8_t | CCMR3
__IO uint8_t | CCR1H
__IO uint8_t | CCR1L
__IO uint8_t | CCR2H
__IO uint8_t | CCR2L
__IO uint8_t | CCR3H
__IO uint8_t | CCR3L
__IO uint8_t | CNTRH
__IO uint8_t | CNTRL
__IO uint8_t | CR1
__IO uint8_t | EGR
__IO uint8_t | IER
__IO uint8_t | PSCR
__IO uint8_t | SR1
__IO uint8_t | SR2

Detailed Description

16-bit timer (TIM2)

Definition at line 808 of file stm8s.h.

Field Documentation

__IO uint8_t TIM2_struct::ARRH

auto-reload register high

Definition at line 827 of file stm8s.h.

__IO uint8_t TIM2_struct::ARRL

auto-reload register low

Definition at line 828 of file stm8s.h.

__IO uint8_t TIM2_struct::CCER1

CC enable register 1

Definition at line 822 of file stm8s.h.

__IO uint8_t TIM2_struct::CCER2

CC enable register 2

Definition at line 823 of file stm8s.h.

__IO uint8_t TIM2_struct::CCMR1

CC mode register 1

Definition at line 819 of file stm8s.h.

__IO uint8_t TIM2_struct::CCMR2

CC mode register 2

Definition at line 820 of file stm8s.h.

__IO uint8_t TIM2_struct::CCMR3

CC mode register 3

Definition at line 821 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR1H

capture/compare register 1 high

Definition at line 829 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR1L

capture/compare register 1 low

Definition at line 830 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR2H

capture/compare register 2 high

Definition at line 831 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR2L

capture/compare register 2 low

Definition at line 832 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR3H

capture/compare register 3 high

Definition at line 833 of file stm8s.h.

__IO uint8_t TIM2_struct::CCR3L

capture/compare register 3 low

Definition at line 834 of file stm8s.h.

__IO uint8_t TIM2_struct::CNTRH

counter high

Definition at line 824 of file stm8s.h.

__IO uint8_t TIM2_struct::CNTRL

counter low

Definition at line 825 of file stm8s.h.

__IO uint8_t TIM2_struct::CR1

control register 1

Definition at line 810 of file stm8s.h.

__IO uint8_t TIM2_struct::EGR

event generation register

Definition at line 818 of file stm8s.h.

__IO uint8_t TIM2_struct::IER

interrupt enable register

Definition at line 815 of file stm8s.h.

__IO uint8_t TIM2_struct::PSCR

prescaler register

Definition at line 826 of file stm8s.h.

__IO uint8_t TIM2_struct::SR1

status register 1

Definition at line 816 of file stm8s.h.

__IO uint8_t TIM2_struct::SR2

status register 2

Definition at line 817 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM3_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM3_struct Struct Reference

16-bit timer (TIM3) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARRH
__IO uint8_t | ARRL
__IO uint8_t | CCER1
__IO uint8_t | CCMR1
__IO uint8_t | CCMR2
__IO uint8_t | CCR1H
__IO uint8_t | CCR1L
__IO uint8_t | CCR2H
__IO uint8_t | CCR2L
__IO uint8_t | CNTRH
__IO uint8_t | CNTRL
__IO uint8_t | CR1
__IO uint8_t | EGR
__IO uint8_t | IER
__IO uint8_t | PSCR
__IO uint8_t | SR1
__IO uint8_t | SR2

Detailed Description

16-bit timer (TIM3)

Definition at line 936 of file stm8s.h.

Field Documentation

__IO uint8_t TIM3_struct::ARRH

auto-reload register high

Definition at line 949 of file stm8s.h.

__IO uint8_t TIM3_struct::ARRL

auto-reload register low

Definition at line 950 of file stm8s.h.

__IO uint8_t TIM3_struct::CCER1

CC enable register 1

Definition at line 945 of file stm8s.h.

__IO uint8_t TIM3_struct::CCMR1

CC mode register 1

Definition at line 943 of file stm8s.h.

__IO uint8_t TIM3_struct::CCMR2

CC mode register 2

Definition at line 944 of file stm8s.h.

__IO uint8_t TIM3_struct::CCR1H

capture/compare register 1 high

Definition at line 951 of file stm8s.h.

__IO uint8_t TIM3_struct::CCR1L

capture/compare register 1 low

Definition at line 952 of file stm8s.h.

__IO uint8_t TIM3_struct::CCR2H

capture/compare register 2 high

Definition at line 953 of file stm8s.h.

__IO uint8_t TIM3_struct::CCR2L

capture/compare register 2 low

Definition at line 954 of file stm8s.h.

__IO uint8_t TIM3_struct::CNTRH

counter high

Definition at line 946 of file stm8s.h.

__IO uint8_t TIM3_struct::CNTRL

counter low

Definition at line 947 of file stm8s.h.

__IO uint8_t TIM3_struct::CR1

control register 1

Definition at line 938 of file stm8s.h.

__IO uint8_t TIM3_struct::EGR

event generation register

Definition at line 942 of file stm8s.h.

__IO uint8_t TIM3_struct::IER

interrupt enable register

Definition at line 939 of file stm8s.h.

__IO uint8_t TIM3_struct::PSCR

prescaler register

Definition at line 948 of file stm8s.h.

__IO uint8_t TIM3_struct::SR1

status register 1

Definition at line 940 of file stm8s.h.

__IO uint8_t TIM3_struct::SR2

status register 2

Definition at line 941 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM4_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM4_struct Struct Reference

8-bit system timer (TIM4) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARR
__IO uint8_t | CNTR
__IO uint8_t | CR1
__IO uint8_t | EGR
__IO uint8_t | IER
__IO uint8_t | PSCR
__IO uint8_t | SR1

Detailed Description

8-bit system timer (TIM4)

Definition at line 1042 of file stm8s.h.

Field Documentation

__IO uint8_t TIM4_struct::ARR

auto-reload register

Definition at line 1054 of file stm8s.h.

__IO uint8_t TIM4_struct::CNTR

counter register

Definition at line 1052 of file stm8s.h.

__IO uint8_t TIM4_struct::CR1

control register 1

Definition at line 1044 of file stm8s.h.

__IO uint8_t TIM4_struct::EGR

event generation register

Definition at line 1051 of file stm8s.h.

__IO uint8_t TIM4_struct::IER

interrupt enable register

Definition at line 1049 of file stm8s.h.

__IO uint8_t TIM4_struct::PSCR

prescaler register

Definition at line 1053 of file stm8s.h.

__IO uint8_t TIM4_struct::SR1

status register 1

Definition at line 1050 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM5_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM5_struct Struct Reference

16-bit timer with synchro module (TIM5) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARRH
__IO uint8_t | ARRL
__IO uint8_t | CCER1
__IO uint8_t | CCER2
__IO uint8_t | CCMR1
__IO uint8_t | CCMR2
__IO uint8_t | CCMR3
__IO uint8_t | CCR1H
__IO uint8_t | CCR1L
__IO uint8_t | CCR2H
__IO uint8_t | CCR2L
__IO uint8_t | CCR3H
__IO uint8_t | CCR3L
__IO uint8_t | CNTRH
__IO uint8_t | CNTRL
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | EGR
__IO uint8_t | IER
__IO uint8_t | PSCR
__IO uint8_t | SMCR
__IO uint8_t | SR1
__IO uint8_t | SR2

Detailed Description

16-bit timer with synchro module (TIM5)

Definition at line 1105 of file stm8s.h.

Field Documentation

__IO uint8_t TIM5_struct::ARRH

TIM5 Auto-Reload Register High

Definition at line 1122 of file stm8s.h.

__IO uint8_t TIM5_struct::ARRL

TIM5 Auto-Reload Register Low

Definition at line 1123 of file stm8s.h.

__IO uint8_t TIM5_struct::CCER1

TIM5 Capture/Compare Enable Register 1

Definition at line 1117 of file stm8s.h.

__IO uint8_t TIM5_struct::CCER2

TIM5 Capture/Compare Enable Register 2

Definition at line 1118 of file stm8s.h.

__IO uint8_t TIM5_struct::CCMR1

TIM5 Capture/Compare Mode Register 1

Definition at line 1114 of file stm8s.h.

__IO uint8_t TIM5_struct::CCMR2

TIM5 Capture/Compare Mode Register 2

Definition at line 1115 of file stm8s.h.

__IO uint8_t TIM5_struct::CCMR3

TIM5 Capture/Compare Mode Register 3

Definition at line 1116 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR1H

TIM5 Capture/Compare Register 1 High

Definition at line 1124 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR1L

TIM5 Capture/Compare Register 1 Low

Definition at line 1125 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR2H

TIM5 Capture/Compare Register 2 High

Definition at line 1126 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR2L

TIM5 Capture/Compare Register 2 Low

Definition at line 1127 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR3H

TIM5 Capture/Compare Register 3 High

Definition at line 1128 of file stm8s.h.

__IO uint8_t TIM5_struct::CCR3L

TIM5 Capture/Compare Register 3 Low

Definition at line 1129 of file stm8s.h.

__IO uint8_t TIM5_struct::CNTRH

TIM5 Counter High

Definition at line 1119 of file stm8s.h.

__IO uint8_t TIM5_struct::CNTRL

TIM5 Counter Low

Definition at line 1120 of file stm8s.h.

__IO uint8_t TIM5_struct::CR1

TIM5 Control Register 1

Definition at line 1107 of file stm8s.h.

__IO uint8_t TIM5_struct::CR2

TIM5 Control Register 2

Definition at line 1108 of file stm8s.h.

__IO uint8_t TIM5_struct::EGR

TIM5 Event Generation Register

Definition at line 1113 of file stm8s.h.

__IO uint8_t TIM5_struct::IER

TIM5 Interrupt Enable Register

Definition at line 1110 of file stm8s.h.

__IO uint8_t TIM5_struct::PSCR

TIM5 Prescaler Register

Definition at line 1121 of file stm8s.h.

__IO uint8_t TIM5_struct::SMCR

TIM5 Slave Mode Control Register

Definition at line 1109 of file stm8s.h.

__IO uint8_t TIM5_struct::SR1

TIM5 Status Register 1

Definition at line 1111 of file stm8s.h.

__IO uint8_t TIM5_struct::SR2

TIM5 Status Register 2

Definition at line 1112 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: TIM6_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM6_struct Struct Reference

8-bit system timer with synchro module(TIM6) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | ARR
__IO uint8_t | CNTR
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | EGR
__IO uint8_t | IER
__IO uint8_t | PSCR
__IO uint8_t | SMCR
__IO uint8_t | SR1

Detailed Description

8-bit system timer with synchro module(TIM6)

Definition at line 1244 of file stm8s.h.

Field Documentation

__IO uint8_t TIM6_struct::ARR

auto-reload register

Definition at line 1254 of file stm8s.h.

__IO uint8_t TIM6_struct::CNTR

counter register

Definition at line 1252 of file stm8s.h.

__IO uint8_t TIM6_struct::CR1

control register 1

Definition at line 1246 of file stm8s.h.

__IO uint8_t TIM6_struct::CR2

control register 2

Definition at line 1247 of file stm8s.h.

__IO uint8_t TIM6_struct::EGR

event generation register

Definition at line 1251 of file stm8s.h.

__IO uint8_t TIM6_struct::IER

interrupt enable register

Definition at line 1249 of file stm8s.h.

__IO uint8_t TIM6_struct::PSCR

prescaler register

Definition at line 1253 of file stm8s.h.

__IO uint8_t TIM6_struct::SMCR

Synchro mode control register

Definition at line 1248 of file stm8s.h.

__IO uint8_t TIM6_struct::SR1

status register 1

Definition at line 1250 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: UART1_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

UART1_struct Struct Reference

Universal Synchronous Asynchronous Receiver Transmitter (UART1) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | BRR1
__IO uint8_t | BRR2
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | CR3
__IO uint8_t | CR4
__IO uint8_t | CR5
__IO uint8_t | DR
__IO uint8_t | GTR
__IO uint8_t | PSCR
__IO uint8_t | SR

Detailed Description

Universal Synchronous Asynchronous Receiver Transmitter (UART1)

Definition at line 1751 of file stm8s.h.

Field Documentation

__IO uint8_t UART1_struct::BRR1

UART1 baud rate register

Definition at line 1755 of file stm8s.h.

__IO uint8_t UART1_struct::BRR2

UART1 DIV mantissa[11:8] SCIDIV fraction

Definition at line 1756 of file stm8s.h.

__IO uint8_t UART1_struct::CR1

UART1 control register 1

Definition at line 1757 of file stm8s.h.

__IO uint8_t UART1_struct::CR2

UART1 control register 2

Definition at line 1758 of file stm8s.h.

__IO uint8_t UART1_struct::CR3

UART1 control register 3

Definition at line 1759 of file stm8s.h.

__IO uint8_t UART1_struct::CR4

UART1 control register 4

Definition at line 1760 of file stm8s.h.

__IO uint8_t UART1_struct::CR5

UART1 control register 5

Definition at line 1761 of file stm8s.h.

__IO uint8_t UART1_struct::DR

UART1 data register

Definition at line 1754 of file stm8s.h.

__IO uint8_t UART1_struct::GTR

UART1 guard time register

Definition at line 1762 of file stm8s.h.

__IO uint8_t UART1_struct::PSCR

UART1 prescaler register

Definition at line 1763 of file stm8s.h.

__IO uint8_t UART1_struct::SR

UART1 status register

Definition at line 1753 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: UART2_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

UART2_struct Struct Reference

Universal Synchronous Asynchronous Receiver Transmitter (UART2) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | BRR1
__IO uint8_t | BRR2
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | CR3
__IO uint8_t | CR4
__IO uint8_t | CR5
__IO uint8_t | CR6
__IO uint8_t | DR
__IO uint8_t | GTR
__IO uint8_t | PSCR
__IO uint8_t | SR

Detailed Description

Universal Synchronous Asynchronous Receiver Transmitter (UART2)

Definition at line 1849 of file stm8s.h.

Field Documentation

__IO uint8_t UART2_struct::BRR1

UART1 baud rate register

Definition at line 1853 of file stm8s.h.

__IO uint8_t UART2_struct::BRR2

UART1 DIV mantissa[11:8] SCIDIV fraction

Definition at line 1854 of file stm8s.h.

__IO uint8_t UART2_struct::CR1

UART1 control register 1

Definition at line 1855 of file stm8s.h.

__IO uint8_t UART2_struct::CR2

UART1 control register 2

Definition at line 1856 of file stm8s.h.

__IO uint8_t UART2_struct::CR3

UART1 control register 3

Definition at line 1857 of file stm8s.h.

__IO uint8_t UART2_struct::CR4

UART1 control register 4

Definition at line 1858 of file stm8s.h.

__IO uint8_t UART2_struct::CR5

UART1 control register 5

Definition at line 1859 of file stm8s.h.

__IO uint8_t UART2_struct::CR6

UART1 control register 6

Definition at line 1860 of file stm8s.h.

__IO uint8_t UART2_struct::DR

UART1 data register

Definition at line 1852 of file stm8s.h.

__IO uint8_t UART2_struct::GTR

UART1 guard time register

Definition at line 1861 of file stm8s.h.

__IO uint8_t UART2_struct::PSCR

UART1 prescaler register

Definition at line 1862 of file stm8s.h.

__IO uint8_t UART2_struct::SR

UART1 status register

Definition at line 1851 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: UART3_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

UART3_struct Struct Reference

LIN Universal Asynchronous Receiver Transmitter (UART3) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | BRR1
__IO uint8_t | BRR2
__IO uint8_t | CR1
__IO uint8_t | CR2
__IO uint8_t | CR3
__IO uint8_t | CR4
__IO uint8_t | CR6
__IO uint8_t | DR
uint8_t RESERVED
__IO uint8_t | SR

Detailed Description

LIN Universal Asynchronous Receiver Transmitter (UART3)

Definition at line 1957 of file stm8s.h.

Field Documentation

__IO uint8_t UART3_struct::BRR1

baud rate register

Definition at line 1961 of file stm8s.h.

__IO uint8_t UART3_struct::BRR2

DIV mantissa[11:8] SCIDIV fraction

Definition at line 1962 of file stm8s.h.

__IO uint8_t UART3_struct::CR1

control register 1

Definition at line 1963 of file stm8s.h.

__IO uint8_t UART3_struct::CR2

control register 2

Definition at line 1964 of file stm8s.h.

__IO uint8_t UART3_struct::CR3

control register 3

Definition at line 1965 of file stm8s.h.

__IO uint8_t UART3_struct::CR4

control register 4

Definition at line 1966 of file stm8s.h.

__IO uint8_t UART3_struct::CR6

control register 5

Definition at line 1968 of file stm8s.h.

__IO uint8_t UART3_struct::DR

data register

Definition at line 1960 of file stm8s.h.

uint8_t UART3_struct::RESERVED

Reserved byte

Definition at line 1967 of file stm8s.h.

__IO uint8_t UART3_struct::SR

status register

Definition at line 1959 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: WWDG_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

WWDG_struct Struct Reference

Window Watchdog (WWDG) More...

#include <stm8s.h>

Data Fields

__IO uint8_t | CR
__IO uint8_t | WR

Detailed Description

Window Watchdog (WWDG)

Definition at line 1617 of file stm8s.h.

Field Documentation

__IO uint8_t WWDG_struct::CR

Control Register

Definition at line 1619 of file stm8s.h.

__IO uint8_t WWDG_struct::WR

Window Register

Definition at line 1620 of file stm8s.h.

The documentation for this struct was generated from the following file:
  • stm8s.h


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • m
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  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • APR : AWU_struct
  • ARR : TIM4_struct , TIM6_struct
  • ARRH : TIM1_struct , TIM2_struct , TIM5_struct , TIM3_struct
  • ARRL : TIM2_struct , TIM5_struct , TIM3_struct , TIM1_struct


STM8S/A Standard Peripherals Drivers: stm8s.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Data Structures | Defines | Typedefs | Enumerations

stm8s.h File Reference

This file contains all HW registers definitions and memory mapping. More...

#include "stm8s_conf.h"
#include <intrinsics.h>

Go to the source code of this file.

Data Structures

struct | AWU_struct
Auto Wake Up (AWU) peripheral registers. More...
struct | BEEP_struct
Beeper (BEEP) peripheral registers. More...
struct | CAN_TypeDef
Controller Area Network (CAN) More...
struct | CFG_struct
Configuration Registers (CFG) More...
struct | CLK_struct
Clock Controller (CLK) More...
struct | EXTI_struct
External Interrupt Controller (EXTI) More...
struct | FLASH_struct
FLASH program and Data memory (FLASH) More...
struct | GPIO_struct
General Purpose I/Os (GPIO) More...
struct | I2C_struct
Inter-Integrated Circuit (I2C) More...
struct | ITC_struct
Interrupt Controller (ITC) More...
struct | IWDG_struct
Independent Watchdog (IWDG) More...
struct | OPT_struct
Option Bytes (OPT) More...
struct | RST_struct
Reset Controller (RST) More...
struct | SPI_struct
Serial Peripheral Interface (SPI) More...
struct | TIM1_struct
16-bit timer with complementary PWM outputs (TIM1) More...
struct | TIM2_struct
16-bit timer (TIM2) More...
struct | TIM3_struct
16-bit timer (TIM3) More...
struct | TIM4_struct
8-bit system timer (TIM4) More...
struct | TIM5_struct
16-bit timer with synchro module (TIM5) More...
struct | TIM6_struct
8-bit system timer with synchro module(TIM6) More...
struct | UART1_struct
Universal Synchronous Asynchronous Receiver Transmitter (UART1) More...
struct | UART2_struct
Universal Synchronous Asynchronous Receiver Transmitter (UART2) More...
struct | UART3_struct
LIN Universal Asynchronous Receiver Transmitter (UART3) More...
struct | WWDG_struct
Window Watchdog (WWDG) More...

Defines

#define | __I volatile const
IO definitions.
#define | __IO volatile
#define | __O volatile
#define | __STM8S_STDPERIPH_VERSION
#define | __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02)
#define | __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00)
#define | __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x01)
#define | __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00)
#define | ADC1_BaseAddress 0x53E0
#define | ADC2_BaseAddress 0x5400
#define | AffBit(VAR, Place, Value)
#define | AREA 0x00
#define | AWU ((AWU_TypeDef *) AWU_BaseAddress)
#define | AWU_APR_APR ((uint8_t)0x3F)
#define | AWU_APR_RESET_VALUE ((uint8_t)0x3F)
#define | AWU_BaseAddress 0x50F0
#define | AWU_CSR_AWUEN ((uint8_t)0x10)
#define | AWU_CSR_AWUF ((uint8_t)0x20)
#define | AWU_CSR_MSR ((uint8_t)0x01)
#define | AWU_CSR_RESET_VALUE ((uint8_t)0x00)
#define | AWU_TBR_AWUTB ((uint8_t)0x0F)
#define | AWU_TBR_RESET_VALUE ((uint8_t)0x00)
#define | BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
#define | BEEP_BaseAddress 0x50F3
#define | BEEP_CSR_BEEPDIV ((uint8_t)0x1F)
#define | BEEP_CSR_BEEPEN ((uint8_t)0x20)
#define | BEEP_CSR_BEEPSEL ((uint8_t)0xC0)
#define | BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)
#define | BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
#define | BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
#define | BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
#define | BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF))
#define | BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))
#define | BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16)))
#define | BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24)))
#define | CAN_BaseAddress 0x5420
#define | CAN_BTR1_RESET_VALUE ((uint8_t)0x40)
#define | CAN_BTR2_RESET_VALUE ((uint8_t)0x23)
#define | CAN_DGR_LBKM ((uint8_t)0x01)
#define | CAN_DGR_RESET_VALUE ((uint8_t)0x0C)
#define | CAN_DGR_RX ((uint8_t)0x08)
#define | CAN_DGR_SAMP ((uint8_t)0x04)
#define | CAN_DGR_SLIM ((uint8_t)0x02)
#define | CAN_DGR_TXM2E ((uint8_t)0x10)
#define | CAN_EIER_BOFIE ((uint8_t)0x04)
#define | CAN_EIER_EPVIE ((uint8_t)0x02)
#define | CAN_EIER_ERRIE ((uint8_t)0x80)
#define | CAN_EIER_EWGIE ((uint8_t)0x01)
#define | CAN_EIER_LECIE ((uint8_t)0x10)
#define | CAN_EIER_RESET_VALUE ((uint8_t)0x00)
#define | CAN_ESR_BOFF ((uint8_t)0x04)
#define | CAN_ESR_EPVF ((uint8_t)0x02)
#define | CAN_ESR_EWGF ((uint8_t)0x01)
#define | CAN_ESR_LEC ((uint8_t)0x70)
#define | CAN_ESR_LEC0 ((uint8_t)0x10)
#define | CAN_ESR_LEC1 ((uint8_t)0x20)
#define | CAN_ESR_LEC2 ((uint8_t)0x40)
#define | CAN_ESR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FCR1_FACT0 ((uint8_t)0x01)
#define | CAN_FCR1_FACT1 ((uint8_t)0x10)
#define | CAN_FCR1_FSC00 ((uint8_t)0x02)
#define | CAN_FCR1_FSC01 ((uint8_t)0x04)
#define | CAN_FCR1_FSC10 ((uint8_t)0x20)
#define | CAN_FCR1_FSC11 ((uint8_t)0x40)
#define | CAN_FCR2_FACT2 ((uint8_t)0x01)
#define | CAN_FCR2_FACT3 ((uint8_t)0x10)
#define | CAN_FCR2_FSC20 ((uint8_t)0x02)
#define | CAN_FCR2_FSC21 ((uint8_t)0x04)
#define | CAN_FCR2_FSC30 ((uint8_t)0x20)
#define | CAN_FCR2_FSC31 ((uint8_t)0x40)
#define | CAN_FCR3_FACT4 ((uint8_t)0x01)
#define | CAN_FCR3_FACT5 ((uint8_t)0x10)
#define | CAN_FCR3_FSC40 ((uint8_t)0x02)
#define | CAN_FCR3_FSC41 ((uint8_t)0x04)
#define | CAN_FCR3_FSC50 ((uint8_t)0x20)
#define | CAN_FCR3_FSC51 ((uint8_t)0x40)
#define | CAN_FCR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FMR1_FMH0 ((uint8_t)0x02)
#define | CAN_FMR1_FMH1 ((uint8_t)0x08)
#define | CAN_FMR1_FMH2 ((uint8_t)0x20)
#define | CAN_FMR1_FMH3 ((uint8_t)0x80)
#define | CAN_FMR1_FML0 ((uint8_t)0x01)
#define | CAN_FMR1_FML1 ((uint8_t)0x04)
#define | CAN_FMR1_FML2 ((uint8_t)0x10)
#define | CAN_FMR1_FML3 ((uint8_t)0x40)
#define | CAN_FMR1_RESET_VALUE ((uint8_t)0x00)
#define | CAN_FMR2_FMH4 ((uint8_t)0x02)
#define | CAN_FMR2_FMH5 ((uint8_t)0x08)
#define | CAN_FMR2_FML4 ((uint8_t)0x01)
#define | CAN_FMR2_FML5 ((uint8_t)0x04)
#define | CAN_FMR2_RESET_VALUE ((uint8_t)0x00)
#define | CAN_IER_FFIE ((uint8_t)0x04)
#define | CAN_IER_FMPIE ((uint8_t)0x02)
#define | CAN_IER_FOVIE ((uint8_t)0x08)
#define | CAN_IER_RESET_VALUE ((uint8_t)0x00)
#define | CAN_IER_TMEIE ((uint8_t)0x01)
#define | CAN_IER_WKUIE ((uint8_t)0x80)
#define | CAN_MCR_ABOM ((uint8_t)0x40)
#define | CAN_MCR_AWUM ((uint8_t)0x20)
#define | CAN_MCR_INRQ ((uint8_t)0x01)
#define | CAN_MCR_NART ((uint8_t)0x10)
#define | CAN_MCR_RESET_VALUE ((uint8_t)0x02)
#define | CAN_MCR_RFLM ((uint8_t)0x08)
#define | CAN_MCR_SLEEP ((uint8_t)0x02)
#define | CAN_MCR_TTCM ((uint8_t)0x80)
#define | CAN_MCR_TXFP ((uint8_t)0x04)
#define | CAN_MCSR_ABRQ ((uint8_t)0x02)
#define | CAN_MCSR_ALST ((uint8_t)0x10)
#define | CAN_MCSR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MCSR_RQCP ((uint8_t)0x04)
#define | CAN_MCSR_TERR ((uint8_t)0x20)
#define | CAN_MCSR_TXOK ((uint8_t)0x08)
#define | CAN_MCSR_TXRQ ((uint8_t)0x01)
#define | CAN_MDLC_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MDLCR_DLC ((uint8_t)0x0F)
#define | CAN_MDLCR_TGT ((uint8_t)0x80)
#define | CAN_MFMI_RESET_VALUE ((uint8_t)0x00)
#define | CAN_MIDR1_IDE ((uint8_t)0x40)
#define | CAN_MIDR1_RTR ((uint8_t)0x20)
#define | CAN_MSR_ERRI ((uint8_t)0x04)
#define | CAN_MSR_INAK ((uint8_t)0x01)
#define | CAN_MSR_RESET_VALUE ((uint8_t)0x02)
#define | CAN_MSR_RX ((uint8_t)0x20)
#define | CAN_MSR_SLAK ((uint8_t)0x02)
#define | CAN_MSR_TX ((uint8_t)0x10)
#define | CAN_MSR_WKUI ((uint8_t)0x08)
#define | CAN_PSR_PS0 ((uint8_t)0x01)
#define | CAN_PSR_PS1 ((uint8_t)0x02)
#define | CAN_PSR_PS2 ((uint8_t)0x04)
#define | CAN_PSR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_RECR_REC0 ((uint8_t)0x01)
#define | CAN_RECR_REC1 ((uint8_t)0x02)
#define | CAN_RECR_REC2 ((uint8_t)0x04)
#define | CAN_RECR_REC3 ((uint8_t)0x08)
#define | CAN_RECR_REC4 ((uint8_t)0x10)
#define | CAN_RECR_REC5 ((uint8_t)0x20)
#define | CAN_RECR_REC6 ((uint8_t)0x40)
#define | CAN_RECR_REC7 ((uint8_t)0x80)
#define | CAN_RECR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_RFR_FMP01 ((uint8_t)0x03)
#define | CAN_RFR_FOVR ((uint8_t)0x10)
#define | CAN_RFR_FULL ((uint8_t)0x08)
#define | CAN_RFR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_RFR_RFOM ((uint8_t)0x20)
#define | CAN_TECR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_TECR_TEC0 ((uint8_t)0x01)
#define | CAN_TECR_TEC1 ((uint8_t)0x02)
#define | CAN_TECR_TEC2 ((uint8_t)0x04)
#define | CAN_TECR_TEC3 ((uint8_t)0x08)
#define | CAN_TECR_TEC4 ((uint8_t)0x10)
#define | CAN_TECR_TEC5 ((uint8_t)0x20)
#define | CAN_TECR_TEC6 ((uint8_t)0x40)
#define | CAN_TECR_TEC7 ((uint8_t)0x80)
#define | CAN_TPR_CODE0 ((uint8_t)0x01)
#define | CAN_TPR_LOW0 ((uint8_t)0x20)
#define | CAN_TPR_LOW1 ((uint8_t)0x40)
#define | CAN_TPR_LOW2 ((uint8_t)0x80)
#define | CAN_TPR_RESET_VALUE ((uint8_t)0x0C)
#define | CAN_TPR_TME0 ((uint8_t)0x04)
#define | CAN_TPR_TME1 ((uint8_t)0x08)
#define | CAN_TPR_TME2 ((uint8_t)0x10)
#define | CAN_TSR_RESET_VALUE ((uint8_t)0x00)
#define | CAN_TSR_RQCP0 ((uint8_t)0x01)
#define | CAN_TSR_RQCP012 ((uint8_t)0x07)
#define | CAN_TSR_RQCP1 ((uint8_t)0x02)
#define | CAN_TSR_RQCP2 ((uint8_t)0x04)
#define | CAN_TSR_TXOK0 ((uint8_t)0x10)
#define | CAN_TSR_TXOK1 ((uint8_t)0x20)
#define | CAN_TSR_TXOK2 ((uint8_t)0x40)
#define | CCMR_TIxDirect_Set ((uint8_t)0x01)
#define | CFG ((CFG_TypeDef *) CFG_BaseAddress)
#define | CFG_BaseAddress 0x7F60
#define | CFG_GCR_AL ((uint8_t)0x02)
#define | CFG_GCR_RESET_VALUE ((uint8_t)0x00)
#define | CFG_GCR_SWD ((uint8_t)0x01)
#define | ChgBit(VAR, Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
#define | CLK ((CLK_TypeDef *) CLK_BaseAddress)
#define | CLK_BaseAddress 0x50C0
#define | CLK_CCOR_CCOBSY ((uint8_t)0x40)
#define | CLK_CCOR_CCOEN ((uint8_t)0x01)
#define | CLK_CCOR_CCORDY ((uint8_t)0x20)
#define | CLK_CCOR_CCOSEL ((uint8_t)0x1E)
#define | CLK_CCOR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_CKDIVR_CPUDIV ((uint8_t)0x07)
#define | CLK_CKDIVR_HSIDIV ((uint8_t)0x18)
#define | CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)
#define | CLK_CMSR_CKM ((uint8_t)0xFF)
#define | CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)
#define | CLK_CSSR_AUX ((uint8_t)0x02)
#define | CLK_CSSR_CSSD ((uint8_t)0x08)
#define | CLK_CSSR_CSSDIE ((uint8_t)0x04)
#define | CLK_CSSR_CSSEN ((uint8_t)0x01)
#define | CLK_CSSR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_ECKR_HSEEN ((uint8_t)0x01)
#define | CLK_ECKR_HSERDY ((uint8_t)0x02)
#define | CLK_ECKR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_HSITRIMR_HSITRIM ((uint8_t)0x07)
#define | CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_ICKR_FHWU ((uint8_t)0x04)
#define | CLK_ICKR_HSIEN ((uint8_t)0x01)
#define | CLK_ICKR_HSIRDY ((uint8_t)0x02)
#define | CLK_ICKR_LSIEN ((uint8_t)0x08)
#define | CLK_ICKR_LSIRDY ((uint8_t)0x10)
#define | CLK_ICKR_RESET_VALUE ((uint8_t)0x01)
#define | CLK_ICKR_SWUAH ((uint8_t)0x20)
#define | CLK_PCKENR1_I2C ((uint8_t)0x01)
#define | CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)
#define | CLK_PCKENR1_SPI ((uint8_t)0x02)
#define | CLK_PCKENR1_TIM1 ((uint8_t)0x80)
#define | CLK_PCKENR1_TIM2 ((uint8_t)0x20)
#define | CLK_PCKENR1_TIM3 ((uint8_t)0x40)
#define | CLK_PCKENR1_TIM4 ((uint8_t)0x10)
#define | CLK_PCKENR1_TIM5 ((uint8_t)0x20)
#define | CLK_PCKENR1_TIM6 ((uint8_t)0x10)
#define | CLK_PCKENR1_UART1 ((uint8_t)0x04)
#define | CLK_PCKENR1_UART2 ((uint8_t)0x08)
#define | CLK_PCKENR1_UART3 ((uint8_t)0x08)
#define | CLK_PCKENR2_ADC ((uint8_t)0x08)
#define | CLK_PCKENR2_AWU ((uint8_t)0x04)
#define | CLK_PCKENR2_CAN ((uint8_t)0x80)
#define | CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)
#define | CLK_SWCR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_SWCR_SWBSY ((uint8_t)0x01)
#define | CLK_SWCR_SWEN ((uint8_t)0x02)
#define | CLK_SWCR_SWIEN ((uint8_t)0x04)
#define | CLK_SWCR_SWIF ((uint8_t)0x08)
#define | CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)
#define | CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01)
#define | CLK_SWR_RESET_VALUE ((uint8_t)0xE1)
#define | CLK_SWR_SWI ((uint8_t)0xFF)
#define | ClrBit(VAR, Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
#define | CONST const
#define | CPU_CC_I1I0 ((uint8_t)0x28)
#define | disableInterrupts() __disable_interrupt()
#define | DM ((DM_TypeDef *) DM_BaseAddress)
#define | DM_BaseAddress 0x7F90
#define | EEPROM __eeprom
#define | enableInterrupts() __enable_interrupt()
#define | EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)
#define | EXTI_BaseAddress 0x50A0
#define | EXTI_CR1_PAIS ((uint8_t)0x03)
#define | EXTI_CR1_PBIS ((uint8_t)0x0C)
#define | EXTI_CR1_PCIS ((uint8_t)0x30)
#define | EXTI_CR1_PDIS ((uint8_t)0xC0)
#define | EXTI_CR1_RESET_VALUE ((uint8_t)0x00)
#define | EXTI_CR2_PEIS ((uint8_t)0x03)
#define | EXTI_CR2_RESET_VALUE ((uint8_t)0x00)
#define | EXTI_CR2_TLIS ((uint8_t)0x04)
#define | FAR __far
#define | FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
#define | FLASH_BaseAddress 0x505A
#define | FLASH_CR1_AHALT ((uint8_t)0x04)
#define | FLASH_CR1_FIX ((uint8_t)0x01)
#define | FLASH_CR1_HALT ((uint8_t)0x08)
#define | FLASH_CR1_IE ((uint8_t)0x02)
#define | FLASH_CR1_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_CR2_ERASE ((uint8_t)0x20)
#define | FLASH_CR2_FPRG ((uint8_t)0x10)
#define | FLASH_CR2_OPT ((uint8_t)0x80)
#define | FLASH_CR2_PRG ((uint8_t)0x01)
#define | FLASH_CR2_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_CR2_WPRG ((uint8_t)0x40)
#define | FLASH_DUKR_DUK ((uint8_t)0xFF)
#define | FLASH_DUKR_RESET_VALUE ((uint8_t)0x00)
#define | FLASH_IAPSR_DUL ((uint8_t)0x08)
#define | FLASH_IAPSR_EOP ((uint8_t)0x04)
#define | FLASH_IAPSR_HVOFF ((uint8_t)0x40)
#define | FLASH_IAPSR_PUL ((uint8_t)0x02)
#define | FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)
#define | FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01)
#define | FLASH_NCR2_NERASE ((uint8_t)0x20)
#define | FLASH_NCR2_NFPRG ((uint8_t)0x10)
#define | FLASH_NCR2_NOPT ((uint8_t)0x80)
#define | FLASH_NCR2_NPRG ((uint8_t)0x01)
#define | FLASH_NCR2_NWPRG ((uint8_t)0x40)
#define | FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF)
#define | FLASH_PUKR_PUK ((uint8_t)0xFF)
#define | FLASH_PUKR_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
#define | GPIO_ODR_RESET_VALUE ((uint8_t)0x00)
#define | GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
#define | GPIOA_BaseAddress 0x5000
#define | GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
#define | GPIOB_BaseAddress 0x5005
#define | GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
#define | GPIOC_BaseAddress 0x500A
#define | GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
#define | GPIOD_BaseAddress 0x500F
#define | GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
#define | GPIOE_BaseAddress 0x5014
#define | GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
#define | GPIOF_BaseAddress 0x5019
#define | GPIOG_BaseAddress 0x501E
#define | GPIOH_BaseAddress 0x5023
#define | GPIOI_BaseAddress 0x5028
#define | halt() __halt()
#define | HSE_VALUE ((u32)16000000)
In the following line adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSI_VALUE ((uint32_t)16000000)
Definition of Device on-chip RC oscillator frequencies.
#define | I2C ((I2C_TypeDef *) I2C_BaseAddress)
#define | I2C_BaseAddress 0x5210
#define | I2C_CCRH_CCR ((uint8_t)0x0F)
#define | I2C_CCRH_DUTY ((uint8_t)0x40)
#define | I2C_CCRH_FS ((uint8_t)0x80)
#define | I2C_CCRH_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CCRL_CCR ((uint8_t)0xFF)
#define | I2C_CCRL_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CR1_ENGC ((uint8_t)0x40)
#define | I2C_CR1_NOSTRETCH ((uint8_t)0x80)
#define | I2C_CR1_PE ((uint8_t)0x01)
#define | I2C_CR1_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CR2_ACK ((uint8_t)0x04)
#define | I2C_CR2_POS ((uint8_t)0x08)
#define | I2C_CR2_RESET_VALUE ((uint8_t)0x00)
#define | I2C_CR2_START ((uint8_t)0x01)
#define | I2C_CR2_STOP ((uint8_t)0x02)
#define | I2C_CR2_SWRST ((uint8_t)0x80)
#define | I2C_DR_DR ((uint8_t)0xFF)
#define | I2C_DR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_FREQR_FREQ ((uint8_t)0x3F)
#define | I2C_FREQR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_ITR_ITBUFEN ((uint8_t)0x04)
#define | I2C_ITR_ITERREN ((uint8_t)0x01)
#define | I2C_ITR_ITEVTEN ((uint8_t)0x02)
#define | I2C_ITR_RESET_VALUE ((uint8_t)0x00)
#define | I2C_OARH_ADD ((uint8_t)0x06)
#define | I2C_OARH_ADDCONF ((uint8_t)0x40)
#define | I2C_OARH_ADDMODE ((uint8_t)0x80)
#define | I2C_OARH_RESET_VALUE ((uint8_t)0x00)
#define | I2C_OARL_ADD ((uint8_t)0xFE)
#define | I2C_OARL_ADD0 ((uint8_t)0x01)
#define | I2C_OARL_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR1_ADD10 ((uint8_t)0x08)
#define | I2C_SR1_ADDR ((uint8_t)0x02)
#define | I2C_SR1_BTF ((uint8_t)0x04)
#define | I2C_SR1_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR1_RXNE ((uint8_t)0x40)
#define | I2C_SR1_SB ((uint8_t)0x01)
#define | I2C_SR1_STOPF ((uint8_t)0x10)
#define | I2C_SR1_TXE ((uint8_t)0x80)
#define | I2C_SR2_AF ((uint8_t)0x04)
#define | I2C_SR2_ARLO ((uint8_t)0x02)
#define | I2C_SR2_BERR ((uint8_t)0x01)
#define | I2C_SR2_OVR ((uint8_t)0x08)
#define | I2C_SR2_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR2_WUFH ((uint8_t)0x20)
#define | I2C_SR3_BUSY ((uint8_t)0x02)
#define | I2C_SR3_GENCALL ((uint8_t)0x10)
#define | I2C_SR3_MSL ((uint8_t)0x01)
#define | I2C_SR3_RESET_VALUE ((uint8_t)0x00)
#define | I2C_SR3_TRA ((uint8_t)0x04)
#define | I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
#define | I2C_TRISER_TRISE ((uint8_t)0x3F)
#define | IN_RAM(a) a
#define | IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define | IS_STATE_VALUE_OK(SensitivityValue)
#define | ITC ((ITC_TypeDef *) ITC_BaseAddress)
#define | ITC_BaseAddress 0x7F70
#define | ITC_SPRX_RESET_VALUE ((uint8_t)0xFF)
#define | IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
#define | IWDG_BaseAddress 0x50E0
#define | IWDG_PR_RESET_VALUE ((uint8_t)0x00)
#define | IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)
#define | LSI_VALUE ((uint32_t)128000)
#define | MskBit(Dest, Msk, Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )
#define | NEAR __near
#define | nop() __no_operation()
#define | OPT ((OPT_TypeDef *) OPT_BaseAddress)
#define | OPT_BaseAddress 0x4800
#define | PointerAttr FAR
#define | rim() __enable_interrupt()
#define | RST ((RST_TypeDef *) RST_BaseAddress)
#define | RST_BaseAddress 0x50B3
#define | RST_SR_EMCF ((uint8_t)0x10)
#define | RST_SR_ILLOPF ((uint8_t)0x04)
#define | RST_SR_IWDGF ((uint8_t)0x02)
#define | RST_SR_SWIMF ((uint8_t)0x08)
#define | RST_SR_WWDGF ((uint8_t)0x01)
#define | S16_MAX (32767)
#define | S16_MIN (-32768)
#define | S32_MAX (2147483647)
#define | S32_MIN (-2147483648uL)
#define | S8_MAX (127)
#define | S8_MIN (-128)
#define | SetBit(VAR, Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
#define | sim() __disable_interrupt()
#define | SPI ((SPI_TypeDef *) SPI_BaseAddress)
#define | SPI_BaseAddress 0x5200
#define | SPI_CR1_BR ((uint8_t)0x38)
#define | SPI_CR1_CPHA ((uint8_t)0x01)
#define | SPI_CR1_CPOL ((uint8_t)0x02)
#define | SPI_CR1_LSBFIRST ((uint8_t)0x80)
#define | SPI_CR1_MSTR ((uint8_t)0x04)
#define | SPI_CR1_RESET_VALUE ((uint8_t)0x00)
#define | SPI_CR1_SPE ((uint8_t)0x40)
#define | SPI_CR2_BDM ((uint8_t)0x80)
#define | SPI_CR2_BDOE ((uint8_t)0x40)
#define | SPI_CR2_CRCEN ((uint8_t)0x20)
#define | SPI_CR2_CRCNEXT ((uint8_t)0x10)
#define | SPI_CR2_RESET_VALUE ((uint8_t)0x00)
#define | SPI_CR2_RXONLY ((uint8_t)0x04)
#define | SPI_CR2_SSI ((uint8_t)0x01)
#define | SPI_CR2_SSM ((uint8_t)0x02)
#define | SPI_CRCPR_RESET_VALUE ((uint8_t)0x07)
#define | SPI_DR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_ICR_ERRIE ((uint8_t)0x20)
#define | SPI_ICR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_ICR_RXEI ((uint8_t)0x40)
#define | SPI_ICR_TXEI ((uint8_t)0x80)
#define | SPI_ICR_WKIE ((uint8_t)0x10)
#define | SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00)
#define | SPI_SR_BSY ((uint8_t)0x80)
#define | SPI_SR_CRCERR ((uint8_t)0x10)
#define | SPI_SR_MODF ((uint8_t)0x20)
#define | SPI_SR_OVR ((uint8_t)0x40)
#define | SPI_SR_RESET_VALUE ((uint8_t)0x02)
#define | SPI_SR_RXNE ((uint8_t)0x01)
#define | SPI_SR_TXE ((uint8_t)0x02)
#define | SPI_SR_WKUP ((uint8_t)0x08)
#define | SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
#define | TIM1_ARRH_ARR ((uint8_t)0xFF)
#define | TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM1_ARRL_ARR ((uint8_t)0xFF)
#define | TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM1_BaseAddress 0x5250
#define | TIM1_BKR_AOE ((uint8_t)0x40)
#define | TIM1_BKR_BKE ((uint8_t)0x10)
#define | TIM1_BKR_BKP ((uint8_t)0x20)
#define | TIM1_BKR_LOCK ((uint8_t)0x03)
#define | TIM1_BKR_MOE ((uint8_t)0x80)
#define | TIM1_BKR_OSSI ((uint8_t)0x04)
#define | TIM1_BKR_OSSR ((uint8_t)0x08)
#define | TIM1_BKR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCER1_CC1E ((uint8_t)0x01)
#define | TIM1_CCER1_CC1NE ((uint8_t)0x04)
#define | TIM1_CCER1_CC1NP ((uint8_t)0x08)
#define | TIM1_CCER1_CC1P ((uint8_t)0x02)
#define | TIM1_CCER1_CC2E ((uint8_t)0x10)
#define | TIM1_CCER1_CC2NE ((uint8_t)0x40)
#define | TIM1_CCER1_CC2NP ((uint8_t)0x80)
#define | TIM1_CCER1_CC2P ((uint8_t)0x20)
#define | TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCER2_CC3E ((uint8_t)0x01)
#define | TIM1_CCER2_CC3NE ((uint8_t)0x04)
#define | TIM1_CCER2_CC3NP ((uint8_t)0x08)
#define | TIM1_CCER2_CC3P ((uint8_t)0x02)
#define | TIM1_CCER2_CC4E ((uint8_t)0x10)
#define | TIM1_CCER2_CC4P ((uint8_t)0x20)
#define | TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCMR_CCxS ((uint8_t)0x03)
#define | TIM1_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM1_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM1_CCMR_OCM ((uint8_t)0x70)
#define | TIM1_CCMR_OCxFE ((uint8_t)0x04)
#define | TIM1_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM1_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR4H_CCR4 ((uint8_t)0xFF)
#define | TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CCR4L_CCR4 ((uint8_t)0xFF)
#define | TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CR1_ARPE ((uint8_t)0x80)
#define | TIM1_CR1_CEN ((uint8_t)0x01)
#define | TIM1_CR1_CMS ((uint8_t)0x60)
#define | TIM1_CR1_DIR ((uint8_t)0x10)
#define | TIM1_CR1_OPM ((uint8_t)0x08)
#define | TIM1_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CR1_UDIS ((uint8_t)0x02)
#define | TIM1_CR1_URS ((uint8_t)0x04)
#define | TIM1_CR2_CCPC ((uint8_t)0x01)
#define | TIM1_CR2_COMS ((uint8_t)0x04)
#define | TIM1_CR2_MMS ((uint8_t)0x70)
#define | TIM1_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_CR2_TI1S ((uint8_t)0x80)
#define | TIM1_DTR_DTG ((uint8_t)0xFF)
#define | TIM1_DTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_EGR_BG ((uint8_t)0x80)
#define | TIM1_EGR_CC1G ((uint8_t)0x02)
#define | TIM1_EGR_CC2G ((uint8_t)0x04)
#define | TIM1_EGR_CC3G ((uint8_t)0x08)
#define | TIM1_EGR_CC4G ((uint8_t)0x10)
#define | TIM1_EGR_COMG ((uint8_t)0x20)
#define | TIM1_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_EGR_TG ((uint8_t)0x40)
#define | TIM1_EGR_UG ((uint8_t)0x01)
#define | TIM1_ETR_ECE ((uint8_t)0x40)
#define | TIM1_ETR_ETF ((uint8_t)0x0F)
#define | TIM1_ETR_ETP ((uint8_t)0x80)
#define | TIM1_ETR_ETPS ((uint8_t)0x30)
#define | TIM1_ETR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_IER_BIE ((uint8_t)0x80)
#define | TIM1_IER_CC1IE ((uint8_t)0x02)
#define | TIM1_IER_CC2IE ((uint8_t)0x04)
#define | TIM1_IER_CC3IE ((uint8_t)0x08)
#define | TIM1_IER_CC4IE ((uint8_t)0x10)
#define | TIM1_IER_COMIE ((uint8_t)0x20)
#define | TIM1_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_IER_TIE ((uint8_t)0x40)
#define | TIM1_IER_UIE ((uint8_t)0x01)
#define | TIM1_OISR_OIS1 ((uint8_t)0x01)
#define | TIM1_OISR_OIS1N ((uint8_t)0x02)
#define | TIM1_OISR_OIS2 ((uint8_t)0x04)
#define | TIM1_OISR_OIS2N ((uint8_t)0x08)
#define | TIM1_OISR_OIS3 ((uint8_t)0x10)
#define | TIM1_OISR_OIS3N ((uint8_t)0x20)
#define | TIM1_OISR_OIS4 ((uint8_t)0x40)
#define | TIM1_OISR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_PSCH_PSC ((uint8_t)0xFF)
#define | TIM1_PSCL_PSC ((uint8_t)0xFF)
#define | TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_RCR_REP ((uint8_t)0xFF)
#define | TIM1_RCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SMCR_MSM ((uint8_t)0x80)
#define | TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SMCR_SMS ((uint8_t)0x07)
#define | TIM1_SMCR_TS ((uint8_t)0x70)
#define | TIM1_SR1_BIF ((uint8_t)0x80)
#define | TIM1_SR1_CC1IF ((uint8_t)0x02)
#define | TIM1_SR1_CC2IF ((uint8_t)0x04)
#define | TIM1_SR1_CC3IF ((uint8_t)0x08)
#define | TIM1_SR1_CC4IF ((uint8_t)0x10)
#define | TIM1_SR1_COMIF ((uint8_t)0x20)
#define | TIM1_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM1_SR1_TIF ((uint8_t)0x40)
#define | TIM1_SR1_UIF ((uint8_t)0x01)
#define | TIM1_SR2_CC1OF ((uint8_t)0x02)
#define | TIM1_SR2_CC2OF ((uint8_t)0x04)
#define | TIM1_SR2_CC3OF ((uint8_t)0x08)
#define | TIM1_SR2_CC4OF ((uint8_t)0x10)
#define | TIM1_SR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_ARRH_ARR ((uint8_t)0xFF)
#define | TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM2_ARRL_ARR ((uint8_t)0xFF)
#define | TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM2_BaseAddress 0x5300
#define | TIM2_CCER1_CC1E ((uint8_t)0x01)
#define | TIM2_CCER1_CC1P ((uint8_t)0x02)
#define | TIM2_CCER1_CC2E ((uint8_t)0x10)
#define | TIM2_CCER1_CC2P ((uint8_t)0x20)
#define | TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCER2_CC3E ((uint8_t)0x01)
#define | TIM2_CCER2_CC3P ((uint8_t)0x02)
#define | TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCMR_CCxS ((uint8_t)0x03)
#define | TIM2_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM2_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM2_CCMR_OCM ((uint8_t)0x70)
#define | TIM2_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM2_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CR1_ARPE ((uint8_t)0x80)
#define | TIM2_CR1_CEN ((uint8_t)0x01)
#define | TIM2_CR1_OPM ((uint8_t)0x08)
#define | TIM2_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_CR1_UDIS ((uint8_t)0x02)
#define | TIM2_CR1_URS ((uint8_t)0x04)
#define | TIM2_EGR_CC1G ((uint8_t)0x02)
#define | TIM2_EGR_CC2G ((uint8_t)0x04)
#define | TIM2_EGR_CC3G ((uint8_t)0x08)
#define | TIM2_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_EGR_UG ((uint8_t)0x01)
#define | TIM2_IER_CC1IE ((uint8_t)0x02)
#define | TIM2_IER_CC2IE ((uint8_t)0x04)
#define | TIM2_IER_CC3IE ((uint8_t)0x08)
#define | TIM2_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_IER_UIE ((uint8_t)0x01)
#define | TIM2_PSCR_PSC ((uint8_t)0xFF)
#define | TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_SR1_CC1IF ((uint8_t)0x02)
#define | TIM2_SR1_CC2IF ((uint8_t)0x04)
#define | TIM2_SR1_CC3IF ((uint8_t)0x08)
#define | TIM2_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM2_SR1_UIF ((uint8_t)0x01)
#define | TIM2_SR2_CC1OF ((uint8_t)0x02)
#define | TIM2_SR2_CC2OF ((uint8_t)0x04)
#define | TIM2_SR2_CC3OF ((uint8_t)0x08)
#define | TIM2_SR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_ARRH_ARR ((uint8_t)0xFF)
#define | TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM3_ARRL_ARR ((uint8_t)0xFF)
#define | TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM3_BaseAddress 0x5320
#define | TIM3_CCER1_CC1E ((uint8_t)0x01)
#define | TIM3_CCER1_CC1P ((uint8_t)0x02)
#define | TIM3_CCER1_CC2E ((uint8_t)0x10)
#define | TIM3_CCER1_CC2P ((uint8_t)0x20)
#define | TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCMR_CCxS ((uint8_t)0x03)
#define | TIM3_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM3_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM3_CCMR_OCM ((uint8_t)0x70)
#define | TIM3_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM3_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CR1_ARPE ((uint8_t)0x80)
#define | TIM3_CR1_CEN ((uint8_t)0x01)
#define | TIM3_CR1_OPM ((uint8_t)0x08)
#define | TIM3_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_CR1_UDIS ((uint8_t)0x02)
#define | TIM3_CR1_URS ((uint8_t)0x04)
#define | TIM3_EGR_CC1G ((uint8_t)0x02)
#define | TIM3_EGR_CC2G ((uint8_t)0x04)
#define | TIM3_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_EGR_UG ((uint8_t)0x01)
#define | TIM3_IER_CC1IE ((uint8_t)0x02)
#define | TIM3_IER_CC2IE ((uint8_t)0x04)
#define | TIM3_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_IER_UIE ((uint8_t)0x01)
#define | TIM3_PSCR_PSC ((uint8_t)0xFF)
#define | TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_SR1_CC1IF ((uint8_t)0x02)
#define | TIM3_SR1_CC2IF ((uint8_t)0x04)
#define | TIM3_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM3_SR1_UIF ((uint8_t)0x01)
#define | TIM3_SR2_CC1OF ((uint8_t)0x02)
#define | TIM3_SR2_CC2OF ((uint8_t)0x04)
#define | TIM3_SR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_ARR_ARR ((uint8_t)0xFF)
#define | TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)
#define | TIM4_BaseAddress 0x5340
#define | TIM4_CNTR_CNT ((uint8_t)0xFF)
#define | TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_CR1_ARPE ((uint8_t)0x80)
#define | TIM4_CR1_CEN ((uint8_t)0x01)
#define | TIM4_CR1_OPM ((uint8_t)0x08)
#define | TIM4_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_CR1_UDIS ((uint8_t)0x02)
#define | TIM4_CR1_URS ((uint8_t)0x04)
#define | TIM4_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_EGR_UG ((uint8_t)0x01)
#define | TIM4_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_IER_UIE ((uint8_t)0x01)
#define | TIM4_PSCR_PSC ((uint8_t)0x07)
#define | TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM4_SR1_UIF ((uint8_t)0x01)
#define | TIM5_ARRH_ARR ((uint8_t)0xFF)
#define | TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define | TIM5_ARRL_ARR ((uint8_t)0xFF)
#define | TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define | TIM5_BaseAddress 0x5300
#define | TIM5_CCER1_CC1E ((uint8_t)0x01)
#define | TIM5_CCER1_CC1P ((uint8_t)0x02)
#define | TIM5_CCER1_CC2E ((uint8_t)0x10)
#define | TIM5_CCER1_CC2P ((uint8_t)0x20)
#define | TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCER2_CC3E ((uint8_t)0x01)
#define | TIM5_CCER2_CC3P ((uint8_t)0x02)
#define | TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCMR_CCxS ((uint8_t)0x03)
#define | TIM5_CCMR_ICxF ((uint8_t)0xF0)
#define | TIM5_CCMR_ICxPSC ((uint8_t)0x0C)
#define | TIM5_CCMR_OCM ((uint8_t)0x70)
#define | TIM5_CCMR_OCxPE ((uint8_t)0x08)
#define | TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)
#define | TIM5_CCR1H_CCR1 ((uint8_t)0xFF)
#define | TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR1L_CCR1 ((uint8_t)0xFF)
#define | TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR2H_CCR2 ((uint8_t)0xFF)
#define | TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR2L_CCR2 ((uint8_t)0xFF)
#define | TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR3H_CCR3 ((uint8_t)0xFF)
#define | TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CCR3L_CCR3 ((uint8_t)0xFF)
#define | TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CNTRH_CNT ((uint8_t)0xFF)
#define | TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CNTRL_CNT ((uint8_t)0xFF)
#define | TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CR1_ARPE ((uint8_t)0x80)
#define | TIM5_CR1_CEN ((uint8_t)0x01)
#define | TIM5_CR1_OPM ((uint8_t)0x08)
#define | TIM5_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CR1_UDIS ((uint8_t)0x02)
#define | TIM5_CR1_URS ((uint8_t)0x04)
#define | TIM5_CR2_MMS ((uint8_t)0x70)
#define | TIM5_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_CR2_TI1S ((uint8_t)0x80)
#define | TIM5_EGR_CC1G ((uint8_t)0x02)
#define | TIM5_EGR_CC2G ((uint8_t)0x04)
#define | TIM5_EGR_CC3G ((uint8_t)0x08)
#define | TIM5_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_EGR_TG ((uint8_t)0x40)
#define | TIM5_EGR_UG ((uint8_t)0x01)
#define | TIM5_IER_CC1IE ((uint8_t)0x02)
#define | TIM5_IER_CC2IE ((uint8_t)0x04)
#define | TIM5_IER_CC3IE ((uint8_t)0x08)
#define | TIM5_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_IER_TIE ((uint8_t)0x40)
#define | TIM5_IER_UIE ((uint8_t)0x01)
#define | TIM5_PSCR_PSC ((uint8_t)0xFF)
#define | TIM5_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SMCR_MSM ((uint8_t)0x80)
#define | TIM5_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SMCR_SMS ((uint8_t)0x07)
#define | TIM5_SMCR_TS ((uint8_t)0x70)
#define | TIM5_SR1_CC1IF ((uint8_t)0x02)
#define | TIM5_SR1_CC2IF ((uint8_t)0x04)
#define | TIM5_SR1_CC3IF ((uint8_t)0x08)
#define | TIM5_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM5_SR1_TIF ((uint8_t)0x40)
#define | TIM5_SR1_UIF ((uint8_t)0x01)
#define | TIM5_SR2_CC1OF ((uint8_t)0x02)
#define | TIM5_SR2_CC2OF ((uint8_t)0x04)
#define | TIM5_SR2_CC3OF ((uint8_t)0x08)
#define | TIM5_SR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_ARR_ARR ((uint8_t)0xFF)
#define | TIM6_ARR_RESET_VALUE ((uint8_t)0xFF)
#define | TIM6_BaseAddress 0x5340
#define | TIM6_CNTR_CNT ((uint8_t)0xFF)
#define | TIM6_CNTR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_CR1_ARPE ((uint8_t)0x80)
#define | TIM6_CR1_CEN ((uint8_t)0x01)
#define | TIM6_CR1_OPM ((uint8_t)0x08)
#define | TIM6_CR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_CR1_UDIS ((uint8_t)0x02)
#define | TIM6_CR1_URS ((uint8_t)0x04)
#define | TIM6_CR2_MMS ((uint8_t)0x70)
#define | TIM6_CR2_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_EGR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_EGR_TG ((uint8_t)0x40)
#define | TIM6_EGR_UG ((uint8_t)0x01)
#define | TIM6_IER_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_IER_TIE ((uint8_t)0x40)
#define | TIM6_IER_UIE ((uint8_t)0x01)
#define | TIM6_PSCR_PSC ((uint8_t)0x07)
#define | TIM6_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_SMCR_MSM ((uint8_t)0x80)
#define | TIM6_SMCR_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_SMCR_SMS ((uint8_t)0x07)
#define | TIM6_SMCR_TS ((uint8_t)0x70)
#define | TIM6_SR1_RESET_VALUE ((uint8_t)0x00)
#define | TIM6_SR1_TIF ((uint8_t)0x40)
#define | TIM6_SR1_UIF ((uint8_t)0x01)
#define | TINY __tiny
#define | trap() __trap()
#define | U16_MAX (65535u)
#define | U32_MAX (4294967295uL)
#define | U8_MAX (255)
#define | UART1_BaseAddress 0x5230
#define | UART1_BRR1_DIVM ((uint8_t)0xFF)
#define | UART1_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART1_BRR2_DIVF ((uint8_t)0x0F)
#define | UART1_BRR2_DIVM ((uint8_t)0xF0)
#define | UART1_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR1_M ((uint8_t)0x10)
#define | UART1_CR1_PCEN ((uint8_t)0x04)
#define | UART1_CR1_PIEN ((uint8_t)0x01)
#define | UART1_CR1_PS ((uint8_t)0x02)
#define | UART1_CR1_R8 ((uint8_t)0x80)
#define | UART1_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR1_T8 ((uint8_t)0x40)
#define | UART1_CR1_UARTD ((uint8_t)0x20)
#define | UART1_CR1_WAKE ((uint8_t)0x08)
#define | UART1_CR2_ILIEN ((uint8_t)0x10)
#define | UART1_CR2_REN ((uint8_t)0x04)
#define | UART1_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR2_RIEN ((uint8_t)0x20)
#define | UART1_CR2_RWU ((uint8_t)0x02)
#define | UART1_CR2_SBK ((uint8_t)0x01)
#define | UART1_CR2_TCIEN ((uint8_t)0x40)
#define | UART1_CR2_TEN ((uint8_t)0x08)
#define | UART1_CR2_TIEN ((uint8_t)0x80)
#define | UART1_CR3_CKEN ((uint8_t)0x08)
#define | UART1_CR3_CPHA ((uint8_t)0x02)
#define | UART1_CR3_CPOL ((uint8_t)0x04)
#define | UART1_CR3_LBCL ((uint8_t)0x01)
#define | UART1_CR3_LINEN ((uint8_t)0x40)
#define | UART1_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR3_STOP ((uint8_t)0x30)
#define | UART1_CR4_ADD ((uint8_t)0x0F)
#define | UART1_CR4_LBDF ((uint8_t)0x10)
#define | UART1_CR4_LBDIEN ((uint8_t)0x40)
#define | UART1_CR4_LBDL ((uint8_t)0x20)
#define | UART1_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR5_HDSEL ((uint8_t)0x08)
#define | UART1_CR5_IREN ((uint8_t)0x02)
#define | UART1_CR5_IRLP ((uint8_t)0x04)
#define | UART1_CR5_NACK ((uint8_t)0x10)
#define | UART1_CR5_RESET_VALUE ((uint8_t)0x00)
#define | UART1_CR5_SCEN ((uint8_t)0x20)
#define | UART1_GTR_RESET_VALUE ((uint8_t)0x00)
#define | UART1_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | UART1_SR_FE ((uint8_t)0x02)
#define | UART1_SR_IDLE ((uint8_t)0x10)
#define | UART1_SR_NF ((uint8_t)0x04)
#define | UART1_SR_OR ((uint8_t)0x08)
#define | UART1_SR_PE ((uint8_t)0x01)
#define | UART1_SR_RESET_VALUE ((uint8_t)0xC0)
#define | UART1_SR_RXNE ((uint8_t)0x20)
#define | UART1_SR_TC ((uint8_t)0x40)
#define | UART1_SR_TXE ((uint8_t)0x80)
#define | UART2_BaseAddress 0x5240
#define | UART2_BRR1_DIVM ((uint8_t)0xFF)
#define | UART2_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART2_BRR2_DIVF ((uint8_t)0x0F)
#define | UART2_BRR2_DIVM ((uint8_t)0xF0)
#define | UART2_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR1_M ((uint8_t)0x10)
#define | UART2_CR1_PCEN ((uint8_t)0x04)
#define | UART2_CR1_PIEN ((uint8_t)0x01)
#define | UART2_CR1_PS ((uint8_t)0x02)
#define | UART2_CR1_R8 ((uint8_t)0x80)
#define | UART2_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR1_T8 ((uint8_t)0x40)
#define | UART2_CR1_UARTD ((uint8_t)0x20)
#define | UART2_CR1_WAKE ((uint8_t)0x08)
#define | UART2_CR2_ILIEN ((uint8_t)0x10)
#define | UART2_CR2_REN ((uint8_t)0x04)
#define | UART2_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR2_RIEN ((uint8_t)0x20)
#define | UART2_CR2_RWU ((uint8_t)0x02)
#define | UART2_CR2_SBK ((uint8_t)0x01)
#define | UART2_CR2_TCIEN ((uint8_t)0x40)
#define | UART2_CR2_TEN ((uint8_t)0x08)
#define | UART2_CR2_TIEN ((uint8_t)0x80)
#define | UART2_CR3_CKEN ((uint8_t)0x08)
#define | UART2_CR3_CPHA ((uint8_t)0x02)
#define | UART2_CR3_CPOL ((uint8_t)0x04)
#define | UART2_CR3_LBCL ((uint8_t)0x01)
#define | UART2_CR3_LINEN ((uint8_t)0x40)
#define | UART2_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR3_STOP ((uint8_t)0x30)
#define | UART2_CR4_ADD ((uint8_t)0x0F)
#define | UART2_CR4_LBDF ((uint8_t)0x10)
#define | UART2_CR4_LBDIEN ((uint8_t)0x40)
#define | UART2_CR4_LBDL ((uint8_t)0x20)
#define | UART2_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR5_HDSEL ((uint8_t)0x08)
#define | UART2_CR5_IREN ((uint8_t)0x02)
#define | UART2_CR5_IRLP ((uint8_t)0x04)
#define | UART2_CR5_NACK ((uint8_t)0x10)
#define | UART2_CR5_RESET_VALUE ((uint8_t)0x00)
#define | UART2_CR5_SCEN ((uint8_t)0x20)
#define | UART2_CR6_LASE ((uint8_t)0x10)
#define | UART2_CR6_LDUM ((uint8_t)0x80)
#define | UART2_CR6_LHDF ((uint8_t)0x02)
#define | UART2_CR6_LHDIEN ((uint8_t)0x04)
#define | UART2_CR6_LSF ((uint8_t)0x01)
#define | UART2_CR6_LSLV ((uint8_t)0x20)
#define | UART2_CR6_RESET_VALUE ((uint8_t)0x00)
#define | UART2_GTR_RESET_VALUE ((uint8_t)0x00)
#define | UART2_PSCR_RESET_VALUE ((uint8_t)0x00)
#define | UART2_SR_FE ((uint8_t)0x02)
#define | UART2_SR_IDLE ((uint8_t)0x10)
#define | UART2_SR_NF ((uint8_t)0x04)
#define | UART2_SR_OR ((uint8_t)0x08)
#define | UART2_SR_PE ((uint8_t)0x01)
#define | UART2_SR_RESET_VALUE ((uint8_t)0xC0)
#define | UART2_SR_RXNE ((uint8_t)0x20)
#define | UART2_SR_TC ((uint8_t)0x40)
#define | UART2_SR_TXE ((uint8_t)0x80)
#define | UART3_BaseAddress 0x5240
#define | UART3_BRR1_DIVM ((uint8_t)0xFF)
#define | UART3_BRR1_RESET_VALUE ((uint8_t)0x00)
#define | UART3_BRR2_DIVF ((uint8_t)0x0F)
#define | UART3_BRR2_DIVM ((uint8_t)0xF0)
#define | UART3_BRR2_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR1_M ((uint8_t)0x10)
#define | UART3_CR1_PCEN ((uint8_t)0x04)
#define | UART3_CR1_PIEN ((uint8_t)0x01)
#define | UART3_CR1_PS ((uint8_t)0x02)
#define | UART3_CR1_R8 ((uint8_t)0x80)
#define | UART3_CR1_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR1_T8 ((uint8_t)0x40)
#define | UART3_CR1_UARTD ((uint8_t)0x20)
#define | UART3_CR1_WAKE ((uint8_t)0x08)
#define | UART3_CR2_ILIEN ((uint8_t)0x10)
#define | UART3_CR2_REN ((uint8_t)0x04)
#define | UART3_CR2_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR2_RIEN ((uint8_t)0x20)
#define | UART3_CR2_RWU ((uint8_t)0x02)
#define | UART3_CR2_SBK ((uint8_t)0x01)
#define | UART3_CR2_TCIEN ((uint8_t)0x40)
#define | UART3_CR2_TEN ((uint8_t)0x08)
#define | UART3_CR2_TIEN ((uint8_t)0x80)
#define | UART3_CR3_LINEN ((uint8_t)0x40)
#define | UART3_CR3_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR3_STOP ((uint8_t)0x30)
#define | UART3_CR4_ADD ((uint8_t)0x0F)
#define | UART3_CR4_LBDF ((uint8_t)0x10)
#define | UART3_CR4_LBDIEN ((uint8_t)0x40)
#define | UART3_CR4_LBDL ((uint8_t)0x20)
#define | UART3_CR4_RESET_VALUE ((uint8_t)0x00)
#define | UART3_CR6_LASE ((uint8_t)0x10)
#define | UART3_CR6_LDUM ((uint8_t)0x80)
#define | UART3_CR6_LHDF ((uint8_t)0x02)
#define | UART3_CR6_LHDIEN ((uint8_t)0x04)
#define | UART3_CR6_LSF ((uint8_t)0x01)
#define | UART3_CR6_LSLV ((uint8_t)0x20)
#define | UART3_CR6_RESET_VALUE ((uint8_t)0x00)
#define | UART3_SR_FE ((uint8_t)0x02)
#define | UART3_SR_IDLE ((uint8_t)0x10)
#define | UART3_SR_NF ((uint8_t)0x04)
#define | UART3_SR_OR ((uint8_t)0x08)
#define | UART3_SR_PE ((uint8_t)0x01)
#define | UART3_SR_RESET_VALUE ((uint8_t)0xC0)
#define | UART3_SR_RXNE ((uint8_t)0x20)
#define | UART3_SR_TC ((uint8_t)0x40)
#define | UART3_SR_TXE ((uint8_t)0x80)
#define | USE_STDPERIPH_DRIVER
#define | ValBit(VAR, Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))
#define | wfi() __wait_for_interrupt()
#define | WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
#define | WWDG_BaseAddress 0x50D1
#define | WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
#define | WWDG_CR_T ((uint8_t)0x7F)
#define | WWDG_CR_T6 ((uint8_t)0x40)
#define | WWDG_CR_WDGA ((uint8_t)0x80)
#define | WWDG_WR_MSB ((uint8_t)0x80)
#define | WWDG_WR_RESET_VALUE ((uint8_t)0x7F)
#define | WWDG_WR_W ((uint8_t)0x7F)

Typedefs

typedef struct AWU_struct | AWU_TypeDef
Auto Wake Up (AWU) peripheral registers.
typedef struct BEEP_struct | BEEP_TypeDef
Beeper (BEEP) peripheral registers.
typedef enum FlagStatus | BitAction
typedef enum FlagStatus | BitStatus
typedef struct CFG_struct | CFG_TypeDef
Configuration Registers (CFG)
typedef struct CLK_struct | CLK_TypeDef
Clock Controller (CLK)
typedef struct EXTI_struct | EXTI_TypeDef
External Interrupt Controller (EXTI)
typedef struct FLASH_struct | FLASH_TypeDef
FLASH program and Data memory (FLASH)
typedef struct GPIO_struct | GPIO_TypeDef
General Purpose I/Os (GPIO)
typedef struct I2C_struct | I2C_TypeDef
Inter-Integrated Circuit (I2C)
typedef signed short | int16_t
typedef signed long | int32_t
typedef signed char | int8_t
typedef struct ITC_struct | ITC_TypeDef
Interrupt Controller (ITC)
typedef enum FlagStatus | ITStatus
typedef struct IWDG_struct | IWDG_TypeDef
Independent Watchdog (IWDG)
typedef struct OPT_struct | OPT_TypeDef
Option Bytes (OPT)
typedef struct RST_struct | RST_TypeDef
Reset Controller (RST)
typedef int16_t | s16
typedef int32_t | s32
typedef int8_t | s8
typedef struct SPI_struct | SPI_TypeDef
Serial Peripheral Interface (SPI)
typedef struct TIM1_struct | TIM1_TypeDef
16-bit timer with complementary PWM outputs (TIM1)
typedef struct TIM2_struct | TIM2_TypeDef
16-bit timer (TIM2)
typedef struct TIM3_struct | TIM3_TypeDef
16-bit timer (TIM3)
typedef struct TIM4_struct | TIM4_TypeDef
8-bit system timer (TIM4)
typedef struct TIM5_struct | TIM5_TypeDef
16-bit timer with synchro module (TIM5)
typedef struct TIM6_struct | TIM6_TypeDef
8-bit system timer with synchro module(TIM6)
typedef uint16_t | u16
typedef uint32_t | u32
typedef uint8_t | u8
typedef struct UART1_struct | UART1_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter (UART1)
typedef struct UART2_struct | UART2_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter (UART2)
typedef struct UART3_struct | UART3_TypeDef
LIN Universal Asynchronous Receiver Transmitter (UART3)
typedef unsigned short | uint16_t
typedef unsigned long | uint32_t
typedef unsigned char | uint8_t
typedef struct WWDG_struct | WWDG_TypeDef
Window Watchdog (WWDG)

Enumerations

enum | bool { FALSE = 0, TRUE = !FALSE }
enum | ErrorStatus { ERROR = 0, SUCCESS = !ERROR }
enum | FlagStatus { RESET = 0, SET = !RESET }
enum | FunctionalState { DISABLE = 0, ENABLE = !DISABLE }

Detailed Description

This file contains all HW registers definitions and memory mapping.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s.h.

Define Documentation

#define AffBit | ( | VAR,
 |  | Place,
 |  | Value
 | ) |
Value:
((Value) ? \
                                   ((VAR) |= ((uint8_t)1<<(Place))) : \
                                   ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))

Definition at line 2678 of file stm8s.h.

#define AREA 0x00

Definition at line 2704 of file stm8s.h.

#define AWU ((AWU_TypeDef *) AWU_BaseAddress)

Definition at line 2500 of file stm8s.h.

Referenced by AWU_Cmd(), AWU_DeInit(), AWU_GetFlagStatus(), AWU_IdleModeEnable(), AWU_Init(), and AWU_LSICalibrationConfig().

#define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)

Definition at line 2502 of file stm8s.h.

Referenced by BEEP_Cmd(), BEEP_DeInit(), BEEP_Init(), and BEEP_LSICalibrationConfig().

#define BitClr ( BIT ) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )

Definition at line 2706 of file stm8s.h.

#define BitSet ( BIT ) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )

Definition at line 2707 of file stm8s.h.

#define BitVal ( BIT ) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )

Definition at line 2708 of file stm8s.h.

#define BYTE_0 ( n ) ((uint8_t)((n) & (uint8_t)0xFF))

Returns the low byte of the 32-bit value

Definition at line 2685 of file stm8s.h.

#define BYTE_1 ( n ) ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))

Returns the second byte of the 32-bit value

Definition at line 2686 of file stm8s.h.

#define BYTE_2 ( n ) ((uint8_t)(BYTE_0((n) >> (uint8_t)16)))

Returns the third byte of the 32-bit value

Definition at line 2687 of file stm8s.h.

#define BYTE_3 ( n ) ((uint8_t)(BYTE_0((n) >> (uint8_t)24)))

Returns the high byte of the 32-bit value

Definition at line 2688 of file stm8s.h.

#define CFG ((CFG_TypeDef *) CFG_BaseAddress)

Definition at line 2587 of file stm8s.h.

#define ChgBit | ( | VAR,
 |  | Place
 | ) | ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )

Definition at line 2677 of file stm8s.h.

#define CLK ((CLK_TypeDef *) CLK_BaseAddress)

Definition at line 2508 of file stm8s.h.

Referenced by CLK_AdjustHSICalibrationValue(), CLK_CCOCmd(), CLK_CCOConfig(), CLK_ClearITPendingBit(), CLK_ClockSecuritySystemEnable(), CLK_ClockSwitchCmd(), CLK_ClockSwitchConfig(), CLK_DeInit(), CLK_FastHaltWakeUpCmd(), CLK_GetClockFreq(), CLK_GetFlagStatus(), CLK_GetITStatus(), CLK_GetSYSCLKSource(), CLK_HSECmd(), CLK_HSICmd(), CLK_HSIPrescalerConfig(), CLK_ITConfig(), CLK_LSICmd(), CLK_PeripheralClockConfig(), CLK_SlowActiveHaltWakeUpCmd(), CLK_SWIMConfig(), CLK_SYSCLKConfig(), and CLK_SYSCLKEmergencyClear().

#define ClrBit | ( | VAR,
 |  | Place
 | ) | ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )

Definition at line 2675 of file stm8s.h.

#define disableInterrupts ( ) __disable_interrupt()

Definition at line 2621 of file stm8s.h.

#define DM ((DM_TypeDef *) DM_BaseAddress)

Definition at line 2589 of file stm8s.h.

#define enableInterrupts ( ) __enable_interrupt()

Definition at line 2620 of file stm8s.h.

#define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)

Definition at line 2510 of file stm8s.h.

Referenced by EXTI_DeInit(), EXTI_GetExtIntSensitivity(), EXTI_GetTLISensitivity(), EXTI_SetExtIntSensitivity(), and EXTI_SetTLISensitivity().

#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)

Definition at line 2512 of file stm8s.h.

Referenced by FLASH_DeInit(), FLASH_EraseOptionByte(), FLASH_GetBootSize(), FLASH_GetFlagStatus(), FLASH_GetLowPowerMode(), FLASH_GetProgrammingTime(), FLASH_ITConfig(), FLASH_Lock(), FLASH_ProgramOptionByte(), FLASH_ProgramWord(), FLASH_SetLowPowerMode(), FLASH_SetProgrammingTime(), and FLASH_Unlock().

#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)

Definition at line 2516 of file stm8s.h.

#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)

Definition at line 2518 of file stm8s.h.

#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)

Definition at line 2520 of file stm8s.h.

#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)

Definition at line 2522 of file stm8s.h.

#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)

Definition at line 2524 of file stm8s.h.

#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)

Definition at line 2526 of file stm8s.h.

#define halt ( ) __halt()

Definition at line 2627 of file stm8s.h.

#define I2C ((I2C_TypeDef *) I2C_BaseAddress)

Definition at line 2545 of file stm8s.h.

Referenced by I2C_AcknowledgeConfig(), I2C_CheckEvent(), I2C_ClearFlag(), I2C_ClearITPendingBit(), I2C_Cmd(), I2C_DeInit(), I2C_FastModeDutyCycleConfig(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_GetITStatus(), I2C_GetLastEvent(), I2C_Init(), I2C_ITConfig(), I2C_ReceiveData(), I2C_Send7bitAddress(), I2C_SendData(), I2C_SoftwareResetCmd(), and I2C_StretchClockCmd().

#define IS_STATE_VALUE_OK ( SensitivityValue )
Value:
(((SensitivityValue) == ENABLE) || \
   ((SensitivityValue) == DISABLE))

Definition at line 2691 of file stm8s.h.

#define ITC ((ITC_TypeDef *) ITC_BaseAddress)

Definition at line 2585 of file stm8s.h.

Referenced by ITC_DeInit(), ITC_GetSoftwarePriority(), and ITC_SetSoftwarePriority().

#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)

Definition at line 2542 of file stm8s.h.

Referenced by IWDG_Enable(), IWDG_ReloadCounter(), IWDG_SetPrescaler(), IWDG_SetReload(), and IWDG_WriteAccessCmd().

#define MskBit | ( | Dest,
 |  | Msk,
 |  | Src
 | ) | ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )

Definition at line 2681 of file stm8s.h.

#define nop ( ) __no_operation()

Definition at line 2624 of file stm8s.h.

#define OPT ((OPT_TypeDef *) OPT_BaseAddress)

Definition at line 2514 of file stm8s.h.

#define rim ( ) __enable_interrupt()

Definition at line 2622 of file stm8s.h.

#define RST ((RST_TypeDef *) RST_BaseAddress)

Definition at line 2539 of file stm8s.h.

Referenced by RST_ClearFlag(), and RST_GetFlagStatus().

#define SetBit | ( | VAR,
 |  | Place
 | ) | ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )

Definition at line 2674 of file stm8s.h.

#define sim ( ) __disable_interrupt()

Definition at line 2623 of file stm8s.h.

#define SPI ((SPI_TypeDef *) SPI_BaseAddress)

Definition at line 2544 of file stm8s.h.

Referenced by SPI_BiDirectionalLineConfig(), SPI_CalculateCRCCmd(), SPI_ClearFlag(), SPI_ClearITPendingBit(), SPI_Cmd(), SPI_DeInit(), SPI_GetCRC(), SPI_GetCRCPolynomial(), SPI_GetFlagStatus(), SPI_GetITStatus(), SPI_Init(), SPI_ITConfig(), SPI_NSSInternalSoftwareCmd(), SPI_ReceiveData(), SPI_SendData(), and SPI_TransmitCRC().

#define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)

Definition at line 2561 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM1_ARRPreloadConfig(), TIM1_BDTRConfig(), TIM1_CCPreloadControl(), TIM1_CCxCmd(), TIM1_CCxNCmd(), TIM1_ClearFlag(), TIM1_ClearITPendingBit(), TIM1_Cmd(), TIM1_CounterModeConfig(), TIM1_CtrlPWMOutputs(), TIM1_DeInit(), TIM1_EncoderInterfaceConfig(), TIM1_ETRClockMode1Config(), TIM1_ETRClockMode2Config(), TIM1_ETRConfig(), TIM1_ForcedOC1Config(), TIM1_ForcedOC2Config(), TIM1_ForcedOC3Config(), TIM1_ForcedOC4Config(), TIM1_GenerateEvent(), TIM1_GetCapture1(), TIM1_GetCapture2(), TIM1_GetCapture3(), TIM1_GetCapture4(), TIM1_GetCounter(), TIM1_GetFlagStatus(), TIM1_GetITStatus(), TIM1_GetPrescaler(), TIM1_InternalClockConfig(), TIM1_ITConfig(), TIM1_OC1FastConfig(), TIM1_OC1Init(), TIM1_OC1NPolarityConfig(), TIM1_OC1PolarityConfig(), TIM1_OC1PreloadConfig(), TIM1_OC2FastConfig(), TIM1_OC2Init(), TIM1_OC2NPolarityConfig(), TIM1_OC2PolarityConfig(), TIM1_OC2PreloadConfig(), TIM1_OC3FastConfig(), TIM1_OC3Init(), TIM1_OC3NPolarityConfig(), TIM1_OC3PolarityConfig(), TIM1_OC3PreloadConfig(), TIM1_OC4FastConfig(), TIM1_OC4Init(), TIM1_OC4PolarityConfig(), TIM1_OC4PreloadConfig(), TIM1_PrescalerConfig(), TIM1_SelectCOM(), TIM1_SelectHallSensor(), TIM1_SelectInputTrigger(), TIM1_SelectMasterSlaveMode(), TIM1_SelectOCxM(), TIM1_SelectOnePulseMode(), TIM1_SelectOutputTrigger(), TIM1_SelectSlaveMode(), TIM1_SetAutoreload(), TIM1_SetCompare1(), TIM1_SetCompare2(), TIM1_SetCompare3(), TIM1_SetCompare4(), TIM1_SetCounter(), TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), TIM1_SetIC4Prescaler(), TIM1_TimeBaseInit(), TIM1_TIxExternalClockConfig(), TIM1_UpdateDisableConfig(), and TIM1_UpdateRequestConfig().

#define trap ( ) __trap()

Definition at line 2625 of file stm8s.h.

#define ValBit | ( | VAR,
 |  | Place
 | ) | ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))

Definition at line 2683 of file stm8s.h.

#define wfi ( ) __wait_for_interrupt()

Definition at line 2626 of file stm8s.h.

#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)

Definition at line 2541 of file stm8s.h.

Referenced by WWDG_GetCounter(), WWDG_Init(), WWDG_SetCounter(), WWDG_SetWindowValue(), and WWDG_SWReset().

Typedef Documentation

typedef struct AWU_struct AWU_TypeDef

Auto Wake Up (AWU) peripheral registers.

typedef struct BEEP_struct BEEP_TypeDef

Beeper (BEEP) peripheral registers.

typedef struct CFG_struct CFG_TypeDef

Configuration Registers (CFG)

typedef struct CLK_struct CLK_TypeDef

Clock Controller (CLK)

typedef struct EXTI_struct EXTI_TypeDef

External Interrupt Controller (EXTI)

typedef struct FLASH_struct FLASH_TypeDef

FLASH program and Data memory (FLASH)

typedef struct I2C_struct I2C_TypeDef

Inter-Integrated Circuit (I2C)

typedef struct ITC_struct ITC_TypeDef

Interrupt Controller (ITC)

typedef struct IWDG_struct IWDG_TypeDef

Independent Watchdog (IWDG)

typedef struct OPT_struct OPT_TypeDef

Option Bytes (OPT)

typedef struct RST_struct RST_TypeDef

Reset Controller (RST)

typedef struct SPI_struct SPI_TypeDef

Serial Peripheral Interface (SPI)

typedef struct TIM1_struct TIM1_TypeDef

16-bit timer with complementary PWM outputs (TIM1)

typedef struct TIM2_struct TIM2_TypeDef

16-bit timer (TIM2)

typedef struct TIM3_struct TIM3_TypeDef

16-bit timer (TIM3)

typedef struct TIM4_struct TIM4_TypeDef

8-bit system timer (TIM4)

typedef struct TIM5_struct TIM5_TypeDef

16-bit timer with synchro module (TIM5)

typedef struct TIM6_struct TIM6_TypeDef

8-bit system timer with synchro module(TIM6)

typedef struct UART1_struct UART1_TypeDef

Universal Synchronous Asynchronous Receiver Transmitter (UART1)

typedef struct UART2_struct UART2_TypeDef

Universal Synchronous Asynchronous Receiver Transmitter (UART2)

typedef struct UART3_struct UART3_TypeDef

LIN Universal Asynchronous Receiver Transmitter (UART3)

typedef struct WWDG_struct WWDG_TypeDef

Window Watchdog (WWDG)


STM8S/A Standard Peripherals Drivers: stm8s_adc1.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_adc1.c File Reference

This file contains all the functions/macros for the ADC1 peripheral. More...

#include "stm8s_adc1.h"

Go to the source code of this file.

Functions

void | ADC1_AWDChannelConfig (ADC1_Channel_TypeDef Channel, FunctionalState NewState)
Enables or disables the analog watchdog for the given channel.
void | ADC1_ClearFlag (ADC1_Flag_TypeDef Flag)
Clear the specified ADC1 Flag.
void | ADC1_ClearITPendingBit (ADC1_IT_TypeDef ITPendingBit)
Clear the ADC1 End of Conversion pending bit.
void | ADC1_Cmd (FunctionalState NewState)
Enables or Disables the ADC1 peripheral.
void | ADC1_ConversionConfig (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)
Configure the ADC1 conversion on selected channel.
void | ADC1_DataBufferCmd (FunctionalState NewState)
Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.
void | ADC1_DeInit (void)
Deinitializes the ADC1 peripheral registers to their default reset values.
void | ADC1_ExternalTriggerConfig (ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
Configure the ADC1 conversion on external trigger event.
FlagStatus | ADC1_GetAWDChannelStatus (ADC1_Channel_TypeDef Channel)
Checks the specified analog watchdog channel status.
uint16_t | ADC1_GetBufferValue (uint8_t Buffer)
Get one sample of measured signal.
uint16_t | ADC1_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC1_GetFlagStatus (ADC1_Flag_TypeDef Flag)
Checks the specified ADC1 flag status.
ITStatus | ADC1_GetITStatus (ADC1_IT_TypeDef ITPendingBit)
Returns the specified pending bit status.
void | ADC1_Init (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)
Initializes the ADC1 peripheral according to the specified parameters.
void | ADC1_ITConfig (ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)
Enables or disables the ADC1 interrupt.
void | ADC1_PrescalerConfig (ADC1_PresSel_TypeDef ADC1_Prescaler)
Configure the ADC1 prescaler division factor.
void | ADC1_ScanModeCmd (FunctionalState NewState)
Enables or Disables the ADC1 scan mode.
void | ADC1_SchmittTriggerConfig (ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC1 Schmitt Trigger on a selected channel.
void | ADC1_SetHighThreshold (uint16_t Threshold)
Sets the high threshold of the analog watchdog.
void | ADC1_SetLowThreshold (uint16_t Threshold)
Sets the low threshold of the analog watchdog.
void | ADC1_StartConversion (void)
Start ADC1 conversion.

Detailed Description

This file contains all the functions/macros for the ADC1 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_adc1.c.


STM8S/A Standard Peripherals Drivers: stm8s_adc1.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_adc1.h File Reference

This file contains all the prototypes/macros for the ADC1 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_ADC1_ALIGN_OK(ALIGN)
Macro used by the assert function to check the different alignment modes.
#define | IS_ADC1_BUFFER_OK(BUFFER) ((BUFFER) <= (uint8_t)0x09)
Macro used by the assert function to check the possible buffer values.
#define | IS_ADC1_CHANNEL_OK(CHANNEL)
Macro used by the assert function to check the different channels values.
#define | IS_ADC1_CONVERSIONMODE_OK(MODE)
Macro used by the assert function to check the different conversion modes.
#define | IS_ADC1_EXTTRIG_OK(EXTRIG)
Macro used by the assert function to check the different external trigger values.
#define | IS_ADC1_FLAG_OK(FLAG)
Macro used by the assert function to check the ADC1 Flag.
#define | IS_ADC1_IT_OK(IT)
Macro used by the assert function to check the Interrupt source.
#define | IS_ADC1_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the ADC1 pending bits.
#define | IS_ADC1_PRESSEL_OK(PRESCALER)
Macro used by the assert function to check the different prescaler's values.
#define | IS_ADC1_SCHMITTTRIG_OK(SCHMITTTRIG)
Macro used by the assert function to check the different schmitt trigger values.

Enumerations

enum | ADC1_Align_TypeDef { ADC1_ALIGN_LEFT = (uint8_t)0x00, ADC1_ALIGN_RIGHT = (uint8_t)0x08 }

ADC1 data alignment.

More...
enum ADC1_Channel_TypeDef {
ADC1_CHANNEL_0 = (uint8_t)0x00, ADC1_CHANNEL_1 = (uint8_t)0x01, ADC1_CHANNEL_2 = (uint8_t)0x02, ADC1_CHANNEL_3 = (uint8_t)0x03,
ADC1_CHANNEL_4 = (uint8_t)0x04, ADC1_CHANNEL_5 = (uint8_t)0x05, ADC1_CHANNEL_6 = (uint8_t)0x06, ADC1_CHANNEL_7 = (uint8_t)0x07,
ADC1_CHANNEL_8 = (uint8_t)0x08, ADC1_CHANNEL_9 = (uint8_t)0x09, ADC1_CHANNEL_12 = (uint8_t)0x0C
}

ADC1 analog channel selection.

More...
enum | ADC1_ConvMode_TypeDef { ADC1_CONVERSIONMODE_SINGLE = (uint8_t)0x00, ADC1_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 }

ADC1 conversion mode selection.

More...
enum | ADC1_ExtTrig_TypeDef { ADC1_EXTTRIG_TIM = (uint8_t)0x00, ADC1_EXTTRIG_GPIO = (uint8_t)0x10 }

ADC1 External conversion trigger event selection.

More...
enum ADC1_Flag_TypeDef {
ADC1_FLAG_OVR = (uint8_t)0x41, ADC1_FLAG_AWD = (uint8_t)0x40, ADC1_FLAG_AWS0 = (uint8_t)0x10, ADC1_FLAG_AWS1 = (uint8_t)0x11,
ADC1_FLAG_AWS2 = (uint8_t)0x12, ADC1_FLAG_AWS3 = (uint8_t)0x13, ADC1_FLAG_AWS4 = (uint8_t)0x14, ADC1_FLAG_AWS5 = (uint8_t)0x15,
ADC1_FLAG_AWS6 = (uint8_t)0x16, ADC1_FLAG_AWS7 = (uint8_t)0x17, ADC1_FLAG_AWS8 = (uint8_t)0x18, ADC1_FLAG_AWS9 = (uint8_t)0x19,
ADC1_FLAG_AWS12 = (uint8_t)0x1C, ADC1_FLAG_EOC = (uint8_t)0x80
}

ADC1 Flags.

More...
enum ADC1_IT_TypeDef {
ADC1_IT_AWDIE = (uint16_t)0x010, ADC1_IT_EOCIE = (uint16_t)0x020, ADC1_IT_AWD = (uint16_t)0x140, ADC1_IT_AWS0 = (uint16_t)0x110,
ADC1_IT_AWS1 = (uint16_t)0x111, ADC1_IT_AWS2 = (uint16_t)0x112, ADC1_IT_AWS3 = (uint16_t)0x113, ADC1_IT_AWS4 = (uint16_t)0x114,
ADC1_IT_AWS5 = (uint16_t)0x115, ADC1_IT_AWS6 = (uint16_t)0x116, ADC1_IT_AWS7 = (uint16_t)0x117, ADC1_IT_AWS8 = (uint16_t)0x118,
ADC1_IT_AWS9 = (uint16_t)0x119, ADC1_IT_AWS12 = (uint16_t)0x11C, ADC1_IT_EOC = (uint16_t)0x080
}

ADC1 Interrupt source.

More...
enum ADC1_PresSel_TypeDef {
ADC1_PRESSEL_FCPU_D2 = (uint8_t)0x00, ADC1_PRESSEL_FCPU_D3 = (uint8_t)0x10, ADC1_PRESSEL_FCPU_D4 = (uint8_t)0x20, ADC1_PRESSEL_FCPU_D6 = (uint8_t)0x30,
ADC1_PRESSEL_FCPU_D8 = (uint8_t)0x40, ADC1_PRESSEL_FCPU_D10 = (uint8_t)0x50, ADC1_PRESSEL_FCPU_D12 = (uint8_t)0x60, ADC1_PRESSEL_FCPU_D18 = (uint8_t)0x70
}

ADC1 clock prescaler selection.

More...
enum ADC1_SchmittTrigg_TypeDef {
ADC1_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, ADC1_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, ADC1_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, ADC1_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03,
ADC1_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, ADC1_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, ADC1_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, ADC1_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07,
ADC1_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, ADC1_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, ADC1_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, ADC1_SCHMITTTRIG_ALL = (uint8_t)0xFF
}

ADC1 schmitt Trigger.

More...

Functions

void | ADC1_AWDChannelConfig (ADC1_Channel_TypeDef Channel, FunctionalState NewState)
Enables or disables the analog watchdog for the given channel.
void | ADC1_ClearFlag (ADC1_Flag_TypeDef Flag)
Clear the specified ADC1 Flag.
void | ADC1_ClearITPendingBit (ADC1_IT_TypeDef ITPendingBit)
Clear the ADC1 End of Conversion pending bit.
void | ADC1_Cmd (FunctionalState NewState)
Enables or Disables the ADC1 peripheral.
void | ADC1_ConversionConfig (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)
Configure the ADC1 conversion on selected channel.
void | ADC1_DataBufferCmd (FunctionalState NewState)
Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register.
void | ADC1_DeInit (void)
Deinitializes the ADC1 peripheral registers to their default reset values.
void | ADC1_ExternalTriggerConfig (ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
Configure the ADC1 conversion on external trigger event.
FlagStatus | ADC1_GetAWDChannelStatus (ADC1_Channel_TypeDef Channel)
Checks the specified analog watchdog channel status.
uint16_t | ADC1_GetBufferValue (uint8_t Buffer)
Get one sample of measured signal.
uint16_t | ADC1_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC1_GetFlagStatus (ADC1_Flag_TypeDef Flag)
Checks the specified ADC1 flag status.
ITStatus | ADC1_GetITStatus (ADC1_IT_TypeDef ITPendingBit)
Returns the specified pending bit status.
void | ADC1_Init (ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)
Initializes the ADC1 peripheral according to the specified parameters.
void | ADC1_ITConfig (ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)
Enables or disables the ADC1 interrupt.
void | ADC1_PrescalerConfig (ADC1_PresSel_TypeDef ADC1_Prescaler)
Configure the ADC1 prescaler division factor.
void | ADC1_ScanModeCmd (FunctionalState NewState)
Enables or Disables the ADC1 scan mode.
void | ADC1_SchmittTriggerConfig (ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC1 Schmitt Trigger on a selected channel.
void | ADC1_SetHighThreshold (uint16_t Threshold)
Sets the high threshold of the analog watchdog.
void | ADC1_SetLowThreshold (uint16_t Threshold)
Sets the low threshold of the analog watchdog.
void | ADC1_StartConversion (void)
Start ADC1 conversion.

Detailed Description

This file contains all the prototypes/macros for the ADC1 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_adc1.h.


STM8S/A Standard Peripherals Drivers: stm8s_adc2.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_adc2.c File Reference

This file contains all the functions/macros for the ADC2 peripheral. More...

#include "stm8s_adc2.h"

Go to the source code of this file.

Functions

void | ADC2_ClearFlag (void)
Clear the ADC2 EOC Flag.
void | ADC2_ClearITPendingBit (void)
Clear the ADC2 End of Conversion pending bit.
void | ADC2_Cmd (FunctionalState NewState)
Enables or Disables the ADC2 peripheral.
void | ADC2_ConversionConfig (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)
Configure the ADC2 conversion on selected channel.
void | ADC2_DeInit (void)
Deinitializes the ADC2 peripheral registers to their default reset values.
void | ADC2_ExternalTriggerConfig (ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)
Configure the ADC2 conversion on external trigger event.
uint16_t | ADC2_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC2_GetFlagStatus (void)
Checks the ADC2 EOC flag status.
ITStatus | ADC2_GetITStatus (void)
Returns the EOC pending bit status.
void | ADC2_Init (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)
Initializes the ADC2 peripheral according to the specified parameters.
void | ADC2_ITConfig (FunctionalState NewState)
Enables or disables the ADC2 interrupt.
void | ADC2_PrescalerConfig (ADC2_PresSel_TypeDef ADC2_Prescaler)
Configure the ADC2 prescaler division factor.
void | ADC2_SchmittTriggerConfig (ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC2 Schmitt Trigger on a selected channel.
void | ADC2_StartConversion (void)
Start ADC2 conversion.

Detailed Description

This file contains all the functions/macros for the ADC2 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_adc2.c.


STM8S/A Standard Peripherals Drivers: stm8s_adc2.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_adc2.h File Reference

This file contains all the prototypes/macros for the ADC2 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_ADC2_ALIGN_OK(ALIGN)
Macro used by the assert function to check the different alignement modes.
#define | IS_ADC2_CHANNEL_OK(CHANNEL)
Macro used by the assert function to check the different channels values.
#define | IS_ADC2_CONVERSIONMODE_OK(MODE)
Macro used by the assert function to check the different conversion modes.
#define | IS_ADC2_EXTTRIG_OK(EXTRIG)
Macro used by the assert function to check the different external trigger values.
#define | IS_ADC2_PRESSEL_OK(PRESCALER)
Macro used by the assert function to check the different prescaler's values.
#define | IS_ADC2_SCHMITTTRIG_OK(SCHMITTTRIG)
Macro used by the assert function to check the different schmitt trigger values.

Enumerations

enum | ADC2_Align_TypeDef { ADC2_ALIGN_LEFT = (uint8_t)0x00, ADC2_ALIGN_RIGHT = (uint8_t)0x08 }

ADC2 data alignment.

More...
enum ADC2_Channel_TypeDef {
ADC2_CHANNEL_0 = (uint8_t)0x00, ADC2_CHANNEL_1 = (uint8_t)0x01, ADC2_CHANNEL_2 = (uint8_t)0x02, ADC2_CHANNEL_3 = (uint8_t)0x03,
ADC2_CHANNEL_4 = (uint8_t)0x04, ADC2_CHANNEL_5 = (uint8_t)0x05, ADC2_CHANNEL_6 = (uint8_t)0x06, ADC2_CHANNEL_7 = (uint8_t)0x07,
ADC2_CHANNEL_8 = (uint8_t)0x08, ADC2_CHANNEL_9 = (uint8_t)0x09, ADC2_CHANNEL_10 = (uint8_t)0x0A, ADC2_CHANNEL_11 = (uint8_t)0x0B,
ADC2_CHANNEL_12 = (uint8_t)0x0C, ADC2_CHANNEL_13 = (uint8_t)0x0D, ADC2_CHANNEL_14 = (uint8_t)0x0E, ADC2_CHANNEL_15 = (uint8_t)0x0F
}

ADC2 analog channel selection.

More...
enum | ADC2_ConvMode_TypeDef { ADC2_CONVERSIONMODE_SINGLE = (uint8_t)0x00, ADC2_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 }

ADC2 conversion mode selection.

More...
enum | ADC2_ExtTrig_TypeDef { ADC2_EXTTRIG_TIM = (uint8_t)0x00, ADC2_EXTTRIG_GPIO = (uint8_t)0x01 }

ADC2 External conversion trigger event selection.

More...
enum ADC2_PresSel_TypeDef {
ADC2_PRESSEL_FCPU_D2 = (uint8_t)0x00, ADC2_PRESSEL_FCPU_D3 = (uint8_t)0x10, ADC2_PRESSEL_FCPU_D4 = (uint8_t)0x20, ADC2_PRESSEL_FCPU_D6 = (uint8_t)0x30,
ADC2_PRESSEL_FCPU_D8 = (uint8_t)0x40, ADC2_PRESSEL_FCPU_D10 = (uint8_t)0x50, ADC2_PRESSEL_FCPU_D12 = (uint8_t)0x60, ADC2_PRESSEL_FCPU_D18 = (uint8_t)0x70
}

ADC2 clock prescaler selection.

More...
enum ADC2_SchmittTrigg_TypeDef {
ADC2_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, ADC2_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, ADC2_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, ADC2_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03,
ADC2_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, ADC2_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, ADC2_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, ADC2_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07,
ADC2_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, ADC2_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, ADC2_SCHMITTTRIG_CHANNEL10 = (uint8_t)0x0A, ADC2_SCHMITTTRIG_CHANNEL11 = (uint8_t)0x0B,
ADC2_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, ADC2_SCHMITTTRIG_CHANNEL13 = (uint8_t)0x0D, ADC2_SCHMITTTRIG_CHANNEL14 = (uint8_t)0x0E, ADC2_SCHMITTTRIG_CHANNEL15 = (uint8_t)0x0F,
ADC2_SCHMITTTRIG_ALL = (uint8_t)0x1F
}

ADC2 schmitt Trigger.

More...

Functions

void | ADC2_ClearFlag (void)
Clear the ADC2 EOC Flag.
void | ADC2_ClearITPendingBit (void)
Clear the ADC2 End of Conversion pending bit.
void | ADC2_Cmd (FunctionalState NewState)
Enables or Disables the ADC2 peripheral.
void | ADC2_ConversionConfig (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)
Configure the ADC2 conversion on selected channel.
void | ADC2_DeInit (void)
Deinitializes the ADC2 peripheral registers to their default reset values.
void | ADC2_ExternalTriggerConfig (ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)
Configure the ADC2 conversion on external trigger event.
uint16_t | ADC2_GetConversionValue (void)
Get one sample of measured signal.
FlagStatus | ADC2_GetFlagStatus (void)
Checks the ADC2 EOC flag status.
ITStatus | ADC2_GetITStatus (void)
Returns the EOC pending bit status.
void | ADC2_Init (ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)
Initializes the ADC2 peripheral according to the specified parameters.
void | ADC2_ITConfig (FunctionalState NewState)
Enables or disables the ADC2 interrupt.
void | ADC2_PrescalerConfig (ADC2_PresSel_TypeDef ADC2_Prescaler)
Configure the ADC2 prescaler division factor.
void | ADC2_SchmittTriggerConfig (ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)
Enables or disables the ADC2 Schmitt Trigger on a selected channel.
void | ADC2_StartConversion (void)
Start ADC2 conversion.

Detailed Description

This file contains all the prototypes/macros for the ADC2 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_adc2.h.


STM8S/A Standard Peripherals Drivers: stm8s_awu.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions | Variables

stm8s_awu.c File Reference

This file contains all the functions for the AWU peripheral. More...

#include "stm8s_awu.h"

Go to the source code of this file.

Functions

void | AWU_Cmd (FunctionalState NewState)
Enable or disable the AWU peripheral.
void | AWU_DeInit (void)
Deinitializes the AWU peripheral registers to their default reset values.
FlagStatus | AWU_GetFlagStatus (void)
Returns status of the AWU peripheral flag.
void | AWU_IdleModeEnable (void)
Configures AWU in Idle mode to reduce power consumption.
void | AWU_Init (AWU_Timebase_TypeDef AWU_TimeBase)
Initializes the AWU peripheral according to the specified parameters.
void | AWU_LSICalibrationConfig (uint32_t LSIFreqHz)
Update APR register with the measured LSI frequency.

Variables

CONST uint8_t | APR_Array [17]
Contains the different values to write in the APR register (used by AWU_Init function)
CONST uint8_t | TBR_Array [17]
Contains the different values to write in the TBR register (used by AWU_Init function)

Detailed Description

This file contains all the functions for the AWU peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_awu.c.


STM8S/A Standard Peripherals Drivers: stm8s_awu.h File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_awu.h File Reference

This file contains all functions prototype and macros for the AWU peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_AWU_TIMEBASE_OK(TB)
Macro used by the assert function to check the different functions parameters.
#define | IS_LSI_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the LSI frequency (in Hz)
#define | LSI_FREQUENCY_MAX ((uint32_t)150000)
#define | LSI_FREQUENCY_MIN ((uint32_t)110000)

Enumerations

enum AWU_Timebase_TypeDef {
AWU_TIMEBASE_NO_IT = (uint8_t)0, AWU_TIMEBASE_250US = (uint8_t)1, AWU_TIMEBASE_500US = (uint8_t)2, AWU_TIMEBASE_1MS = (uint8_t)3,
AWU_TIMEBASE_2MS = (uint8_t)4, AWU_TIMEBASE_4MS = (uint8_t)5, AWU_TIMEBASE_8MS = (uint8_t)6, AWU_TIMEBASE_16MS = (uint8_t)7,
AWU_TIMEBASE_32MS = (uint8_t)8, AWU_TIMEBASE_64MS = (uint8_t)9, AWU_TIMEBASE_128MS = (uint8_t)10, AWU_TIMEBASE_256MS = (uint8_t)11,
AWU_TIMEBASE_512MS = (uint8_t)12, AWU_TIMEBASE_1S = (uint8_t)13, AWU_TIMEBASE_2S = (uint8_t)14, AWU_TIMEBASE_12S = (uint8_t)15,
AWU_TIMEBASE_30S = (uint8_t)16
}

AWU TimeBase selection.

More...

Functions

void | AWU_Cmd (FunctionalState NewState)
Enable or disable the AWU peripheral.
void | AWU_DeInit (void)
Deinitializes the AWU peripheral registers to their default reset values.
FlagStatus | AWU_GetFlagStatus (void)
Returns status of the AWU peripheral flag.
void | AWU_IdleModeEnable (void)
Configures AWU in Idle mode to reduce power consumption.
void | AWU_Init (AWU_Timebase_TypeDef AWU_TimeBase)
Initializes the AWU peripheral according to the specified parameters.
void | AWU_LSICalibrationConfig (uint32_t LSIFreqHz)
Update APR register with the measured LSI frequency.

Detailed Description

This file contains all functions prototype and macros for the AWU peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_awu.h.


STM8S/A Standard Peripherals Drivers: stm8s_beep.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_beep.c File Reference

This file contains all the functions for the BEEP peripheral. More...

#include "stm8s_beep.h"

Go to the source code of this file.

Functions

void | BEEP_Cmd (FunctionalState NewState)
Enable or disable the BEEP function.
void | BEEP_DeInit (void)
Deinitializes the BEEP peripheral registers to their default reset values.
void | BEEP_Init (BEEP_Frequency_TypeDef BEEP_Frequency)
Initializes the BEEP function according to the specified parameters.
void | BEEP_LSICalibrationConfig (uint32_t LSIFreqHz)
Update CSR register with the measured LSI frequency.

Detailed Description

This file contains all the functions for the BEEP peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_beep.c.


STM8S/A Standard Peripherals Drivers: stm8s_beep.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_beep.h File Reference

This file contains all functions prototype and macros for the BEEP peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | BEEP_CALIBRATION_DEFAULT ((uint8_t)0x0B)
#define | IS_BEEP_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the different functions parameters.
#define | IS_LSI_FREQUENCY_OK(FREQ)
Macro used by the assert function to check the LSI frequency (in Hz).
#define | LSI_FREQUENCY_MAX ((uint32_t)150000)
#define | LSI_FREQUENCY_MIN ((uint32_t)110000)

Enumerations

enum | BEEP_Frequency_TypeDef { BEEP_FREQUENCY_1KHZ = (uint8_t)0x00, BEEP_FREQUENCY_2KHZ = (uint8_t)0x40, BEEP_FREQUENCY_4KHZ = (uint8_t)0x80 }

BEEP Frequency selection.

More...

Functions

void | BEEP_Cmd (FunctionalState NewState)
Enable or disable the BEEP function.
void | BEEP_DeInit (void)
Deinitializes the BEEP peripheral registers to their default reset values.
void | BEEP_Init (BEEP_Frequency_TypeDef BEEP_Frequency)
Initializes the BEEP function according to the specified parameters.
void | BEEP_LSICalibrationConfig (uint32_t LSIFreqHz)
Update CSR register with the measured LSI frequency.

Detailed Description

This file contains all functions prototype and macros for the BEEP peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_beep.h.


STM8S/A Standard Peripherals Drivers: stm8s_can.c File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • src
Defines | Functions | Variables

stm8s_can.c File Reference

This file contains all the functions for the CAN peripheral. More...

#include "stm8s_can.h"

Go to the source code of this file.

Defines

#define | CAN_ACKNOWLEDGE_TIMEOUT ((uint16_t)0xFFFF)
#define | CAN_IDLIST_IDMASK_MASK ((uint8_t) 0x55)
#define | CAN_IDMASK_IDLIST_MASK ((uint8_t) 0xAA)
#define | CAN_MODE_MASK ((uint8_t) 0x03)

Functions

void | CAN_CancelTransmit (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_FLAG_TypeDef CAN_Flag)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_IT_TypeDef CAN_IT)
Clears the CAN’s interrupt pending bits.
void | CAN_DeInit (void)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (void)
Releases the CAN FIFO.
void | CAN_FilterInit (CAN_FilterNumber_TypeDef CAN_FilterNumber, FunctionalState CAN_FilterActivation, CAN_FilterMode_TypeDef CAN_FilterMode, CAN_FilterScale_TypeDef CAN_FilterScale, uint8_t CAN_FilterID1, uint8_t CAN_FilterID2, uint8_t CAN_FilterID3, uint8_t CAN_FilterID4, uint8_t CAN_FilterIDMask1, uint8_t CAN_FilterIDMask2, uint8_t CAN_FilterIDMask3, uint8_t CAN_FilterIDMask4)
Initializes the CAN peripheral Filter according to the specified parameters.
FlagStatus | CAN_GetFlagStatus (CAN_FLAG_TypeDef CAN_Flag)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_IT_TypeDef CAN_IT)
Checks whether the specified CAN interrupt has occurred or not.
CAN_ErrorCode_TypeDef | CAN_GetLastErrorCode (void)
Gets the Last Error Code.
uint16_t | CAN_GetMessageTimeStamp (void)
Returns the Received time stamp.
uint8_t | CAN_GetReceivedData (uint8_t CAN_DataIndex)
Gets the CAN Data of the received message.
uint8_t | CAN_GetReceivedDLC (void)
Gets the CAN DLC of the received message.
uint8_t | CAN_GetReceivedFMI (void)
Gets the CAN FMI of the received message.
uint32_t | CAN_GetReceivedId (void)
Gets the CAN Id of the received message.
CAN_Id_TypeDef | CAN_GetReceivedIDE (void)
Gets the CAN IDE of the received message.
CAN_RTR_TypeDef | CAN_GetReceivedRTR (void)
Gets the CAN RTR of the received message.
CAN_Page_TypeDef | CAN_GetSelectedPage (void)
Gets the selected registers page.
CAN_InitStatus_TypeDef | CAN_Init (CAN_MasterCtrl_TypeDef CAN_MasterCtrl, CAN_Mode_TypeDef CAN_Mode, CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth, CAN_BitSeg1_TypeDef CAN_BitSeg1, CAN_BitSeg2_TypeDef CAN_BitSeg2, uint8_t CAN_Prescaler)
Initializes the CAN peripheral according to the specified parameters.
void | CAN_ITConfig (CAN_IT_TypeDef CAN_IT, FunctionalState NewState)
Enables or disables the specified CAN interrupts.
CAN_NbrPendingMessage_TypeDef | CAN_MessagePending (void)
Returns the number of pending messages.
CAN_ModeStatus_TypeDef | CAN_OperatingModeRequest (CAN_OperatingMode_TypeDef CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (void)
Receives a message which contains CAN Id, IDE, RTR DLC, datas and FMI number.
void | CAN_SelectPage (CAN_Page_TypeDef CAN_Page)
Sets the registers page to be selected.
CAN_Sleep_TypeDef | CAN_Sleep (void)
Enters the Sleep low power mode.
void | CAN_ST7CompatibilityCmd (CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)
Enables or Disables the ST7 CAN Compatibility.
CAN_TxStatus_TypeDef | CAN_Transmit (uint32_t CAN_Id, CAN_Id_TypeDef CAN_IDE, CAN_RTR_TypeDef CAN_RTR, uint8_t CAN_DLC, uint8_t *CAN_Data)
Initiates the transmission of a message.
CAN_TxStatus_TypeDef | CAN_TransmitStatus (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
CAN_WakeUp_TypeDef | CAN_WakeUp (void)
Wakes the CAN up.
static ITStatus | CheckITStatus (uint8_t CAN_Reg, uint8_t It_Bit)
Checks whether the CAN interrupt has occurred or not.

Variables

__IO uint8_t | _Data [8] = {0}
__IO uint8_t | _DLC = 0
__IO uint8_t | _FMI = 0
__IO uint32_t | _Id = 0
__IO uint8_t | _IDE = 0
__IO uint8_t | _RTR = 0

Detailed Description

This file contains all the functions for the CAN peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_can.c.


STM8S/A Standard Peripherals Drivers: stm8s_can.h File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_can.h File Reference

This file contains all the functions for the CAN peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | CAN_DLC_MAX ((uint8_t)0x08)
#define | CAN_EXTID_SIZE ((uint32_t)0x1FFFFFFF)
#define | CAN_IT_CONFIG_MASK ~(uint16_t)(CAN_IT_TME|CAN_IT_FMP|CAN_IT_FF|CAN_IT_FOV|CAN_IT_WKU|CAN_IT_EWG|CAN_IT_EPV|CAN_IT_BOF|CAN_IT_LEC|CAN_IT_ERR)
Macro used by the assert function in order to check the CAN Configuration interrupts.
#define | CAN_STDID_SIZE ((uint16_t)0x07FF)
#define | IS_CAN_BITSEG1_OK(BS1) ((BS1) <= CAN_BitSeg1_16TimeQuantum)
Macro used by the assert function in order to check time quantum in bit segment 1 .
#define | IS_CAN_BITSEG2_OK(BS2) ((((BS2) >= CAN_BitSeg2_2TimeQuantum) && ((BS2) <= CAN_BitSeg2_8TimeQuantum))|| ((BS2) == CAN_BitSeg2_1TimeQuantum))
Macro used by the assert function in order to check time quantum in bit segment 2.
#define | IS_CAN_DLC_OK(DLC) ((DLC) <= CAN_DLC_MAX)
Macro used by the assert function in order to check the DLC to be sent.
#define | IS_CAN_EXTID_OK(EXTID) ((EXTID) <= ((uint32_t)CAN_EXTID_SIZE))
Macro used by the assert function in order to check the Extended ID to be sent.
#define | IS_CAN_FILTER_MODE_OK(MODE)
Macro used by the assert function in order to check CAN filter mode.
#define | IS_CAN_FILTER_NUMBER_OK(NUMBER)
Macro used by the assert function in order to check CAN filter number.
#define | IS_CAN_FILTER_SCALE_OK(SCALE)
Macro used by the assert function in order to check CAN filter scale.
#define | IS_CAN_FLAG_CLEAR_OK(FLAG)
Macro used by the assert function in order to check CAN flags which can be cleared by CAN_ClearFlag.
#define | IS_CAN_FLAG_STATUS_OK(FLAG)
Macro used by the assert function in order to check CAN flags which can be got by CAN_GetFlagStatus.
#define | IS_CAN_IDTYPE_OK(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended))
Macro used by the assert function in order to check the type of the ID to be sent.
#define | IS_CAN_IT_CONFIG_OK(IT) (((IT) != 0x0000) && ((uint16_t)((uint16_t)(IT) & (uint16_t)CAN_IT_CONFIG_MASK) == 0x0000))
#define | IS_CAN_IT_PENDING_BIT_OK(IT)
Macro used by the assert function in order to check the CAN Pending bit interrupts.
#define | IS_CAN_IT_STATUS_OK(IT)
Macro used by the assert function in order to check the CAN status interrupts.
#define | IS_CAN_LAST_ERROR_CODE_OK(CODE) (((CODE) & 0x8F) == 0x00)
Macro used by the assert function in order to check the Last Error Code.
#define | IS_CAN_MASTERCTRL_OK(MODE)
Macro used by the assert function in order to check CAN Time Triggered Communication mode.
#define | IS_CAN_MODE_OK(MODE)
Macro used by the assert function in order to check CAN mode options .
#define | IS_CAN_OPERATINGMODE_OK(MODE)
Macro used by the assert function in order to check CAN operating mode.
#define | IS_CAN_PRESCALER_OK(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 64))
Macro used by the assert function in order to check CAN clock prescaler.
#define | IS_CAN_RTR_OK(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
Macro used by the assert function in order to check CAN transmission Frame Type.
#define | IS_CAN_ST7_COMPATIBILITY_OK(STATE) (((STATE) == CAN_ST7Compatibility_Enable) || ((STATE) == CAN_ST7Compatibility_Disable))
Macro used by the assert function in order to check the CAN ST7 Compatibility parameters.
#define | IS_CAN_STDID_OK(STDID) ((STDID) <= ((uint16_t)CAN_STDID_SIZE))
Macro used by the assert function in order to check the Standard ID to be sent.
#define | IS_CAN_SYNJUMPWIDTH_OK(SJW)
Macro used by the assert function in order to check the CAN synchronisation jump width (SJW).
#define | IS_CAN_TRANSMITMAILBOX_OK(TRANSMITMAILBOX)
Macro used by the assert function in order to check CAN Tx mailboxes.

Enumerations

enum CAN_BitSeg1_TypeDef {
CAN_BitSeg1_1TimeQuantum = ((uint8_t)0x00), CAN_BitSeg1_2TimeQuantum = ((uint8_t)0x01), CAN_BitSeg1_3TimeQuantum = ((uint8_t)0x02), CAN_BitSeg1_4TimeQuantum = ((uint8_t)0x03),
CAN_BitSeg1_5TimeQuantum = ((uint8_t)0x04), CAN_BitSeg1_6TimeQuantum = ((uint8_t)0x05), CAN_BitSeg1_7TimeQuantum = ((uint8_t)0x06), CAN_BitSeg1_8TimeQuantum = ((uint8_t)0x07),
CAN_BitSeg1_9TimeQuantum = ((uint8_t)0x08), CAN_BitSeg1_10TimeQuantum = ((uint8_t)0x09), CAN_BitSeg1_11TimeQuantum = ((uint8_t)0x0A), CAN_BitSeg1_12TimeQuantum = ((uint8_t)0x0B),
CAN_BitSeg1_13TimeQuantum = ((uint8_t)0x0C), CAN_BitSeg1_14TimeQuantum = ((uint8_t)0x0D), CAN_BitSeg1_15TimeQuantum = ((uint8_t)0x0E), CAN_BitSeg1_16TimeQuantum = ((uint8_t)0x0F)
}

time quantum in bit segment 1

More...
enum CAN_BitSeg2_TypeDef {
CAN_BitSeg2_1TimeQuantum = ((uint8_t)0x00), CAN_BitSeg2_2TimeQuantum = ((uint8_t)0x10), CAN_BitSeg2_3TimeQuantum = ((uint8_t)0x20), CAN_BitSeg2_4TimeQuantum = ((uint8_t)0x30),
CAN_BitSeg2_5TimeQuantum = ((uint8_t)0x40), CAN_BitSeg2_6TimeQuantum = ((uint8_t)0x50), CAN_BitSeg2_7TimeQuantum = ((uint8_t)0x60), CAN_BitSeg2_8TimeQuantum = ((uint8_t)0x70)
}

time quantum in bit segment 2

More...
enum CAN_ErrorCode_TypeDef {
CAN_ErrorCode_NoErr = ((uint8_t)0x00), CAN_ErrorCode_StuffErr = ((uint8_t)0x10), CAN_ErrorCode_FormErr = ((uint8_t)0x20), CAN_ErrorCode_ACKErr = ((uint8_t)0x30),
CAN_ErrorCode_BitRecessiveErr = ((uint8_t)0x40), CAN_ErrorCode_BitDominantErr = ((uint8_t)0x50), CAN_ErrorCode_CRCErr = ((uint8_t)0x60), CAN_ErrorCode_SoftwareSetErr = ((uint8_t)0x70)
}

CAN Error Code description.

More...
enum | CAN_FilterMode_TypeDef { CAN_FilterMode_IdMask = ((uint8_t)0x00), CAN_FilterMode_IdMask_IdList = ((uint8_t)0x10), CAN_FilterMode_IdList_IdMask = ((uint8_t)0x11), CAN_FilterMode_IdList = ((uint8_t)0x01) }

CAN filter mode.

More...
enum CAN_FilterNumber_TypeDef {
CAN_FilterNumber_0 = ((uint8_t)0x00), CAN_FilterNumber_1 = ((uint8_t)0x01), CAN_FilterNumber_2 = ((uint8_t)0x02), CAN_FilterNumber_3 = ((uint8_t)0x03),
CAN_FilterNumber_4 = ((uint8_t)0x04), CAN_FilterNumber_5 = ((uint8_t)0x05)
}

CAN filter number.

More...
enum | CAN_FilterScale_TypeDef { CAN_FilterScale_8Bit = ((uint8_t)0x00), CAN_FilterScale_16_8Bit = ((uint8_t)0x02), CAN_FilterScale_16Bit = ((uint8_t)0x04), CAN_FilterScale_32Bit = ((uint8_t)0x06) }

CAN filter scale.

More...
enum CAN_FLAG_TypeDef {
CAN_FLAG_RQCP0 = ((uint16_t)0x3401), CAN_FLAG_RQCP1 = ((uint16_t)0x3402), CAN_FLAG_RQCP2 = ((uint16_t)0x3404), CAN_FLAG_FMP = ((uint16_t)0x1203),
CAN_FLAG_FF = ((uint16_t)0x3208), CAN_FLAG_FOV = ((uint16_t)0x3210), CAN_FLAG_WKU = ((uint16_t)0x3108), CAN_FLAG_EWG = ((uint16_t)0x1001),
CAN_FLAG_EPV = ((uint16_t)0x1002), CAN_FLAG_BOF = ((uint16_t)0x1004), CAN_FLAG_LEC = ((uint16_t)0x3070)
}

CAN flags.

More...
enum | CAN_Id_TypeDef { CAN_Id_Standard = ((uint8_t)0x00), CAN_Id_Extended = ((uint8_t)0x40) }

CAN identifier type.

More...
enum | CAN_InitStatus_TypeDef { CAN_InitStatus_Failed = 0, CAN_InitStatus_Success = ! CAN_InitStatus_Failed }

CAN sleep constants.

More...
enum CAN_IT_TypeDef {
CAN_IT_TME = ((uint16_t)0x0001), CAN_IT_FMP = ((uint16_t)0x0002), CAN_IT_FF = ((uint16_t)0x0004), CAN_IT_FOV = ((uint16_t)0x0008),
CAN_IT_WKU = ((uint16_t)0x0080), CAN_IT_ERR = ((uint16_t)0x4000), CAN_IT_EWG = ((uint16_t)0x0100), CAN_IT_EPV = ((uint16_t)0x0200),
CAN_IT_BOF = ((uint16_t)0x0400), CAN_IT_LEC = ((uint16_t)0x0800)
}

CAN interrupts.

More...
enum CAN_MasterCtrl_TypeDef {
CAN_MasterCtrl_AllDisabled = ((uint8_t)0x00), CAN_MasterCtrl_AllEnabled = ((uint8_t)0xFC), CAN_MasterCtrl_TimeTriggerCOMMode = ((uint8_t)0x80), CAN_MasterCtrl_AutoBusOffManagement = ((uint8_t)0x40),
CAN_MasterCtrl_AutoWakeUpMode = ((uint8_t)0x20), CAN_MasterCtrl_NoAutoReTx = ((uint8_t)0x10), CAN_MasterCtrl_RxFifoLockedMode = ((uint8_t)0x08), CAN_MasterCtrl_TxFifoPriority = ((uint8_t)0x04)
}

CAN Time Triggered Communication mode.

More...
enum | CAN_Mode_TypeDef { CAN_Mode_Normal = ((uint8_t)0x00), CAN_Mode_LoopBack = ((uint8_t)0x01), CAN_Mode_Silent = ((uint8_t)0x02), CAN_Mode_Silent_LoopBack = ((uint8_t)0x03) }

CAN mode options.

More...
enum | CAN_ModeStatus_TypeDef { CAN_ModeStatus_Failed = ((uint8_t)0x00), CAN_ModeStatus_Success = ! CAN_ModeStatus_Failed }

CAN operating mode status.

More...
enum | CAN_NbrPendingMessage_TypeDef { CAN_NbrPendingMessage_0 = ((uint8_t)0x00), CAN_NbrPendingMessage_1 = ((uint8_t)0x01), CAN_NbrPendingMessage_2 = ((uint8_t)0x02), CAN_NbrPendingMessage_3 = ((uint8_t)0x03) }

CAN Pending Messages number.

More...
enum | CAN_OperatingMode_TypeDef { CAN_OperatingMode_Initialization = ((uint8_t)0x00), CAN_OperatingMode_Normal = ((uint8_t)0x01), CAN_OperatingMode_Sleep = ((uint8_t)0x02) }

CAN operating mode.

More...
enum CAN_Page_TypeDef {
CAN_Page_TxMailBox0 = ((uint8_t) 0), CAN_Page_TxMailBox1 = ((uint8_t) 1), CAN_Page_TxMailBox2 = ((uint8_t) 5), CAN_Page_Filter01 = ((uint8_t) 2),
CAN_Page_Filter23 = ((uint8_t) 3), CAN_Page_Filter45 = ((uint8_t) 4), CAN_Page_Config = ((uint8_t) 6), CAN_Page_RxFifo = ((uint8_t) 7)
}

CAN Page Mapping.

More...
enum | CAN_RTR_TypeDef { CAN_RTR_Data = ((uint8_t)0x00), CAN_RTR_Remote = ((uint8_t)0x20) }

CAN remote transmission request.

More...
enum | CAN_Sleep_TypeDef { CAN_Sleep_Failed = ((uint8_t)0x00), CAN_Sleep_Ok = ((uint8_t)0x01) }

CAN sleep Status.

More...
enum | CAN_ST7Compatibility_TypeDef { CAN_ST7Compatibility_Enable = ((uint8_t)0x00), CAN_ST7Compatibility_Disable = ((uint8_t)0x10) }

CAN ST7 Compatibility.

More...
enum | CAN_SynJumpWidth_TypeDef { CAN_SynJumpWidth_1TimeQuantum = ((uint8_t)0x00), CAN_SynJumpWidth_2TimeQuantum = ((uint8_t)0x40), CAN_SynJumpWidth_3TimeQuantum = ((uint8_t)0x80), CAN_SynJumpWidth_4TimeQuantum = ((uint8_t)0xC0) }

CAN synchronisation jump width (SJW)

More...
enum | CAN_TransmitMailBox_TypeDef { CAN_TransmitMailBox_0 = ((uint8_t) 0x00), CAN_TransmitMailBox_1 = ((uint8_t) 0x01), CAN_TransmitMailBox_2 = ((uint8_t) 0x05) }

CAN Tx mailboxes.

More...
enum CAN_TxStatus_TypeDef {
CAN_TxStatus_Failed = ((uint8_t)0xF0), CAN_TxStatus_Ok = ((uint8_t)0xF1), CAN_TxStatus_Pending = ((uint8_t)0xF2), CAN_TxStatus_NoMailBox = ((uint8_t)0xF4),
CAN_TxStatus_MailBoxEmpty = ((uint8_t)0xF5), CAN_TxStatus_MailBox0Ok = ((uint8_t)0x00), CAN_TxStatus_MailBox1Ok = ((uint8_t)0x01), CAN_TxStatus_MailBox2Ok = ((uint8_t)0x05)
}

CAN transmit Status.

More...
enum | CAN_WakeUp_TypeDef { CAN_WakeUp_Failed = ((uint8_t)0x00), CAN_WakeUp_Ok = ((uint8_t)0x01) }

CAN wake up status.

More...

Functions

void | CAN_CancelTransmit (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_FLAG_TypeDef CAN_Flag)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_IT_TypeDef CAN_IT)
Clears the CAN’s interrupt pending bits.
void | CAN_DeInit (void)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (void)
Releases the CAN FIFO.
void | CAN_FilterInit (CAN_FilterNumber_TypeDef CAN_FilterNumber, FunctionalState CAN_FilterActivation, CAN_FilterMode_TypeDef CAN_FilterMode, CAN_FilterScale_TypeDef CAN_FilterScale, uint8_t CAN_FilterID1, uint8_t CAN_FilterID2, uint8_t CAN_FilterID3, uint8_t CAN_FilterID4, uint8_t CAN_FilterIDMask1, uint8_t CAN_FilterIDMask2, uint8_t CAN_FilterIDMask3, uint8_t CAN_FilterIDMask4)
Initializes the CAN peripheral Filter according to the specified parameters.
FlagStatus | CAN_GetFlagStatus (CAN_FLAG_TypeDef CAN_Flag)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_IT_TypeDef CAN_IT)
Checks whether the specified CAN interrupt has occurred or not.
CAN_ErrorCode_TypeDef | CAN_GetLastErrorCode (void)
Gets the Last Error Code.
uint16_t | CAN_GetMessageTimeStamp (void)
Returns the Received time stamp.
uint8_t | CAN_GetReceivedData (uint8_t CAN_DataIndex)
Gets the CAN Data of the received message.
uint8_t | CAN_GetReceivedDLC (void)
Gets the CAN DLC of the received message.
uint8_t | CAN_GetReceivedFMI (void)
Gets the CAN FMI of the received message.
uint32_t | CAN_GetReceivedId (void)
Gets the CAN Id of the received message.
CAN_Id_TypeDef | CAN_GetReceivedIDE (void)
Gets the CAN IDE of the received message.
CAN_RTR_TypeDef | CAN_GetReceivedRTR (void)
Gets the CAN RTR of the received message.
CAN_Page_TypeDef | CAN_GetSelectedPage (void)
Gets the selected registers page.
CAN_InitStatus_TypeDef | CAN_Init (CAN_MasterCtrl_TypeDef CAN_MasterCtrl, CAN_Mode_TypeDef CAN_Mode, CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth, CAN_BitSeg1_TypeDef CAN_BitSeg1, CAN_BitSeg2_TypeDef CAN_BitSeg2, uint8_t CAN_Prescaler)
Initializes the CAN peripheral according to the specified parameters.
void | CAN_ITConfig (CAN_IT_TypeDef CAN_IT, FunctionalState NewState)
Enables or disables the specified CAN interrupts.
CAN_NbrPendingMessage_TypeDef | CAN_MessagePending (void)
Returns the number of pending messages.
CAN_ModeStatus_TypeDef | CAN_OperatingModeRequest (CAN_OperatingMode_TypeDef CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (void)
Receives a message which contains CAN Id, IDE, RTR DLC, datas and FMI number.
void | CAN_SelectPage (CAN_Page_TypeDef CAN_Page)
Sets the registers page to be selected.
CAN_Sleep_TypeDef | CAN_Sleep (void)
Enters the Sleep low power mode.
void | CAN_ST7CompatibilityCmd (CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)
Enables or Disables the ST7 CAN Compatibility.
CAN_TxStatus_TypeDef | CAN_Transmit (uint32_t CAN_Id, CAN_Id_TypeDef CAN_IDE, CAN_RTR_TypeDef CAN_RTR, uint8_t CAN_DLC, uint8_t *CAN_Data)
Initiates the transmission of a message.
CAN_TxStatus_TypeDef | CAN_TransmitStatus (CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
CAN_WakeUp_TypeDef | CAN_WakeUp (void)
Wakes the CAN up.

Detailed Description

This file contains all the functions for the CAN peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_can.h.

Define Documentation

#define CAN_DLC_MAX ((uint8_t)0x08)

Definition at line 32 of file stm8s_can.h.

#define CAN_EXTID_SIZE ((uint32_t)0x1FFFFFFF)

Definition at line 31 of file stm8s_can.h.

Referenced by CAN_Receive(), and CAN_Transmit().

#define CAN_STDID_SIZE ((uint16_t)0x07FF)

Definition at line 30 of file stm8s_can.h.

Referenced by CAN_Receive(), and CAN_Transmit().


STM8S/A Standard Peripherals Drivers: stm8s_clk.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions | Variables

stm8s_clk.c File Reference

This file contains all the functions for the CLK peripheral. More...

#include "stm8s_clk.h"

Go to the source code of this file.

Functions

void | CLK_AdjustHSICalibrationValue (CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | CLK_CCOCmd (FunctionalState NewState)
Enables or disablle the Configurable Clock Output (CCO).
void | CLK_CCOConfig (CLK_Output_TypeDef CLK_CCO)
Output the selected clock on a dedicated I/O pin.
void | CLK_ClearITPendingBit (CLK_IT_TypeDef CLK_IT)
Clears the CLK’s interrupt pending bits.
void | CLK_ClockSecuritySystemEnable (void)
Enables the Clock Security System.
void | CLK_ClockSwitchCmd (FunctionalState NewState)
Starts or Stops manually the clock switch execution.
ErrorStatus | CLK_ClockSwitchConfig (CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
configures the Switch from one clock to another
void | CLK_DeInit (void)
Deinitializes the CLK peripheral registers to their default reset values.
void | CLK_FastHaltWakeUpCmd (FunctionalState NewState)
Configures the High Speed Internal oscillator (HSI).
uint32_t | CLK_GetClockFreq (void)
This function returns the frequencies of different on chip clocks.
FlagStatus | CLK_GetFlagStatus (CLK_Flag_TypeDef CLK_FLAG)
Checks whether the specified CLK flag is set or not.
ITStatus | CLK_GetITStatus (CLK_IT_TypeDef CLK_IT)
Checks whether the specified CLK interrupt has is enabled or not.
CLK_Source_TypeDef | CLK_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | CLK_HSECmd (FunctionalState NewState)
Enable or Disable the External High Speed oscillator (HSE).
void | CLK_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | CLK_HSIPrescalerConfig (CLK_Prescaler_TypeDef HSIPrescaler)
Configures the HSI clock dividers.
void | CLK_ITConfig (CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
Enables or disables the specified CLK interrupts.
void | CLK_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | CLK_PeripheralClockConfig (CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
Enables or disables the specified peripheral CLK.
void | CLK_SlowActiveHaltWakeUpCmd (FunctionalState NewState)
Configures the slow active halt wake up.
void | CLK_SWIMConfig (CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
Configures the SWIM clock frequency on the fly.
void | CLK_SYSCLKConfig (CLK_Prescaler_TypeDef CLK_Prescaler)
Configures the HSI and CPU clock dividers.
void | CLK_SYSCLKEmergencyClear (void)
Reset the SWBSY flag (SWICR Reister)

Variables

CONST uint8_t | CLKPrescTable [8] = {1, 2, 4, 8, 10, 16, 20, 40}
CONST uint8_t | HSIDivFactor [4] = {1, 2, 4, 8}

Detailed Description

This file contains all the functions for the CLK peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_clk.c.


STM8S/A Standard Peripherals Drivers: stm8s_clk.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_clk.h File Reference

This file contains all functions prototype and macros for the CLK peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | CLK_TIMEOUT ((uint16_t)0x491)
#define | IS_CLK_CSSCONFIG_OK(CSSVALUE)
Macros used by the assert function in order to check the CSS configuration.
#define | IS_CLK_CURRENTCLOCKSTATE_OK(STATE)
Macros used by the assert function in order to check the current clock state.
#define | IS_CLK_FLAG_OK(FLAG)
Macros used by the assert function in order to check the different clock flags.
#define | IS_CLK_HSIPRESCALER_OK(PRESCALER)
Macros used by the assert function in order to check the different HSI prescaler values.
#define | IS_CLK_HSITRIMVALUE_OK(TRIMVALUE)
Macros used by the assert function in order to check the different HSI trimming values.
#define | IS_CLK_IT_OK(IT) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF))
Macros used by the assert function in order to check the different clock IT pending bits.
#define | IS_CLK_OUTPUT_OK(OUTPUT)
Macros used by the assert function in order to check the different clocks to output.
#define | IS_CLK_PERIPHERAL_OK(PERIPHERAL)
Macros used by the assert function in order to check the different peripheral's clock.
#define | IS_CLK_PRESCALER_OK(PRESCALER)
Macros used by the assert function in order to check the different clock prescaler values.
#define | IS_CLK_SOURCE_OK(SOURCE)
Macros used by the assert function in order to check the different clock sources.
#define | IS_CLK_SWIMDIVIDER_OK(SWIMDIVIDER) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER))
Macros used by the assert function in order to check the different SWIM dividers values.
#define | IS_CLK_SWITCHMODE_OK(MODE) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO))
Macros used by the assert function in order to check the different functions parameters.

Enumerations

enum | CLK_CSSConfig_TypeDef { CLK_CSSCONFIG_ENABLEWITHIT = (uint8_t)0x05, CLK_CSSCONFIG_ENABLE = (uint8_t)0x01, CLK_CSSCONFIG_DISABLE = (uint8_t)0x00 }

Clock security system configuration.

More...
enum | CLK_CurrentClockState_TypeDef { CLK_CURRENTCLOCKSTATE_DISABLE = (uint8_t)0x00, CLK_CURRENTCLOCKSTATE_ENABLE = (uint8_t)0x01 }

Current Clock State.

More...
enum CLK_Flag_TypeDef {
CLK_FLAG_LSIRDY = (uint16_t)0x0110, CLK_FLAG_HSIRDY = (uint16_t)0x0102, CLK_FLAG_HSERDY = (uint16_t)0x0202, CLK_FLAG_SWIF = (uint16_t)0x0308,
CLK_FLAG_SWBSY = (uint16_t)0x0301, CLK_FLAG_CSSD = (uint16_t)0x0408, CLK_FLAG_AUX = (uint16_t)0x0402, CLK_FLAG_CCOBSY = (uint16_t)0x0504,
CLK_FLAG_CCORDY = (uint16_t)0x0502
}

CLK Flags.

More...
enum CLK_HSITrimValue_TypeDef {
CLK_HSITRIMVALUE_0 = (uint8_t)0x00, CLK_HSITRIMVALUE_1 = (uint8_t)0x01, CLK_HSITRIMVALUE_2 = (uint8_t)0x02, CLK_HSITRIMVALUE_3 = (uint8_t)0x03,
CLK_HSITRIMVALUE_4 = (uint8_t)0x04, CLK_HSITRIMVALUE_5 = (uint8_t)0x05, CLK_HSITRIMVALUE_6 = (uint8_t)0x06, CLK_HSITRIMVALUE_7 = (uint8_t)0x07
}

CLK HSI Calibration Value.

More...
enum | CLK_IT_TypeDef { CLK_IT_CSSD = (uint8_t)0x0C, CLK_IT_SWIF = (uint8_t)0x1C }

CLK interrupt configuration and Flags cleared by software.

More...
enum CLK_Output_TypeDef {
CLK_OUTPUT_HSI = (uint8_t)0x00, CLK_OUTPUT_LSI = (uint8_t)0x02, CLK_OUTPUT_HSE = (uint8_t)0x04, CLK_OUTPUT_CPU = (uint8_t)0x08,
CLK_OUTPUT_CPUDIV2 = (uint8_t)0x0A, CLK_OUTPUT_CPUDIV4 = (uint8_t)0x0C, CLK_OUTPUT_CPUDIV8 = (uint8_t)0x0E, CLK_OUTPUT_CPUDIV16 = (uint8_t)0x10,
CLK_OUTPUT_CPUDIV32 = (uint8_t)0x12, CLK_OUTPUT_CPUDIV64 = (uint8_t)0x14, CLK_OUTPUT_HSIRC = (uint8_t)0x16, CLK_OUTPUT_MASTER = (uint8_t)0x18,
CLK_OUTPUT_OTHERS = (uint8_t)0x1A
}

CLK Clock Output.

More...
enum CLK_Peripheral_TypeDef {
CLK_PERIPHERAL_I2C = (uint8_t)0x00, CLK_PERIPHERAL_SPI = (uint8_t)0x01, CLK_PERIPHERAL_UART1 = (uint8_t)0x03, CLK_PERIPHERAL_UART2 = (uint8_t)0x03,
CLK_PERIPHERAL_UART3 = (uint8_t)0x03, CLK_PERIPHERAL_TIMER6 = (uint8_t)0x04, CLK_PERIPHERAL_TIMER4 = (uint8_t)0x04, CLK_PERIPHERAL_TIMER5 = (uint8_t)0x05,
CLK_PERIPHERAL_TIMER2 = (uint8_t)0x05, CLK_PERIPHERAL_TIMER3 = (uint8_t)0x06, CLK_PERIPHERAL_TIMER1 = (uint8_t)0x07, CLK_PERIPHERAL_AWU = (uint8_t)0x12,
CLK_PERIPHERAL_ADC = (uint8_t)0x13, CLK_PERIPHERAL_CAN = (uint8_t)0x17
}

CLK Enable peripheral.

More...
enum CLK_Prescaler_TypeDef {
CLK_PRESCALER_HSIDIV1 = (uint8_t)0x00, CLK_PRESCALER_HSIDIV2 = (uint8_t)0x08, CLK_PRESCALER_HSIDIV4 = (uint8_t)0x10, CLK_PRESCALER_HSIDIV8 = (uint8_t)0x18,
CLK_PRESCALER_CPUDIV1 = (uint8_t)0x80, CLK_PRESCALER_CPUDIV2 = (uint8_t)0x81, CLK_PRESCALER_CPUDIV4 = (uint8_t)0x82, CLK_PRESCALER_CPUDIV8 = (uint8_t)0x83,
CLK_PRESCALER_CPUDIV16 = (uint8_t)0x84, CLK_PRESCALER_CPUDIV32 = (uint8_t)0x85, CLK_PRESCALER_CPUDIV64 = (uint8_t)0x86, CLK_PRESCALER_CPUDIV128 = (uint8_t)0x87
}

CLK Clock Divisor.

More...
enum | CLK_Source_TypeDef { CLK_SOURCE_HSI = (uint8_t)0xE1, CLK_SOURCE_LSI = (uint8_t)0xD2, CLK_SOURCE_HSE = (uint8_t)0xB4 }

CLK Clock Source.

More...
enum | CLK_SWIMDivider_TypeDef { CLK_SWIMDIVIDER_2 = (uint8_t)0x00, CLK_SWIMDIVIDER_OTHER = (uint8_t)0x01 }

SWIM Clock divider.

More...
enum | CLK_SwitchMode_TypeDef { CLK_SWITCHMODE_MANUAL = (uint8_t)0x00, CLK_SWITCHMODE_AUTO = (uint8_t)0x01 }

Switch Mode Auto, Manual.

More...

Functions

void | CLK_AdjustHSICalibrationValue (CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | CLK_CCOCmd (FunctionalState NewState)
Enables or disablle the Configurable Clock Output (CCO).
void | CLK_CCOConfig (CLK_Output_TypeDef CLK_CCO)
Output the selected clock on a dedicated I/O pin.
void | CLK_ClearITPendingBit (CLK_IT_TypeDef CLK_IT)
Clears the CLK’s interrupt pending bits.
void | CLK_ClockSecuritySystemEnable (void)
Enables the Clock Security System.
void | CLK_ClockSwitchCmd (FunctionalState NewState)
Starts or Stops manually the clock switch execution.
ErrorStatus | CLK_ClockSwitchConfig (CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
configures the Switch from one clock to another
void | CLK_DeInit (void)
Deinitializes the CLK peripheral registers to their default reset values.
void | CLK_FastHaltWakeUpCmd (FunctionalState NewState)
Configures the High Speed Internal oscillator (HSI).
uint32_t | CLK_GetClockFreq (void)
This function returns the frequencies of different on chip clocks.
FlagStatus | CLK_GetFlagStatus (CLK_Flag_TypeDef CLK_FLAG)
Checks whether the specified CLK flag is set or not.
ITStatus | CLK_GetITStatus (CLK_IT_TypeDef CLK_IT)
Checks whether the specified CLK interrupt has is enabled or not.
CLK_Source_TypeDef | CLK_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | CLK_HSECmd (FunctionalState NewState)
Enable or Disable the External High Speed oscillator (HSE).
void | CLK_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | CLK_HSIPrescalerConfig (CLK_Prescaler_TypeDef HSIPrescaler)
Configures the HSI clock dividers.
void | CLK_ITConfig (CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
Enables or disables the specified CLK interrupts.
void | CLK_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | CLK_PeripheralClockConfig (CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
Enables or disables the specified peripheral CLK.
void | CLK_SlowActiveHaltWakeUpCmd (FunctionalState NewState)
Configures the slow active halt wake up.
void | CLK_SWIMConfig (CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
Configures the SWIM clock frequency on the fly.
void | CLK_SYSCLKConfig (CLK_Prescaler_TypeDef CLK_Prescaler)
Configures the HSI and CPU clock dividers.
void | CLK_SYSCLKEmergencyClear (void)
Reset the SWBSY flag (SWICR Reister)

Detailed Description

This file contains all functions prototype and macros for the CLK peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_clk.h.


STM8S/A Standard Peripherals Drivers: stm8s_exti.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_exti.c File Reference

This file contains all the functions for the EXTI peripheral. More...

#include "stm8s_exti.h"

Go to the source code of this file.

Functions

void | EXTI_DeInit (void)
Deinitializes the external interrupt control registers to their default reset value.
EXTI_Sensitivity_TypeDef | EXTI_GetExtIntSensitivity (EXTI_Port_TypeDef Port)
Get the external interrupt sensitivity of the selected port.
EXTI_TLISensitivity_TypeDef | EXTI_GetTLISensitivity (void)
Get the TLI interrupt sensitivity.
void | EXTI_SetExtIntSensitivity (EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)
Set the external interrupt sensitivity of the selected port.
void | EXTI_SetTLISensitivity (EXTI_TLISensitivity_TypeDef SensitivityValue)
Set the TLI interrupt sensitivity.

Detailed Description

This file contains all the functions for the EXTI peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_exti.c.


STM8S/A Standard Peripherals Drivers: stm8s_exti.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_exti.h File Reference

This file contains all functions prototype and macros for the EXTI peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_EXTI_PINMASK_OK(PinMask) ((((PinMask) & (uint8_t)0x00) == (uint8_t)0x00) && ((PinMask) != (uint8_t)0x00))
Macro used by the assert function in order to check the different values of the EXTI PinMask.
#define | IS_EXTI_PORT_OK(PORT)
Macro used by the assert function in order to check the different Port values.
#define | IS_EXTI_SENSITIVITY_OK(SensitivityValue)
Macro used by the assert function in order to check the different sensitivity values for PORTA to PORTE.
#define | IS_EXTI_TLISENSITIVITY_OK(SensitivityValue)
Macro used by the assert function in order to check the different sensitivity values for TLI.

Enumerations

enum EXTI_Port_TypeDef {
EXTI_PORT_GPIOA = (uint8_t)0x00, EXTI_PORT_GPIOB = (uint8_t)0x01, EXTI_PORT_GPIOC = (uint8_t)0x02, EXTI_PORT_GPIOD = (uint8_t)0x03,
EXTI_PORT_GPIOE = (uint8_t)0x04
}

EXTI PortNum possible values.

More...
enum | EXTI_Sensitivity_TypeDef { EXTI_SENSITIVITY_FALL_LOW = (uint8_t)0x00, EXTI_SENSITIVITY_RISE_ONLY = (uint8_t)0x01, EXTI_SENSITIVITY_FALL_ONLY = (uint8_t)0x02, EXTI_SENSITIVITY_RISE_FALL = (uint8_t)0x03 }

EXTI Sensitivity values for PORTA to PORTE.

More...
enum | EXTI_TLISensitivity_TypeDef { EXTI_TLISENSITIVITY_FALL_ONLY = (uint8_t)0x00, EXTI_TLISENSITIVITY_RISE_ONLY = (uint8_t)0x04 }

EXTI Sensitivity values for TLI.

More...

Functions

void | EXTI_DeInit (void)
Deinitializes the external interrupt control registers to their default reset value.
EXTI_Sensitivity_TypeDef | EXTI_GetExtIntSensitivity (EXTI_Port_TypeDef Port)
Get the external interrupt sensitivity of the selected port.
EXTI_TLISensitivity_TypeDef | EXTI_GetTLISensitivity (void)
Get the TLI interrupt sensitivity.
void | EXTI_SetExtIntSensitivity (EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)
Set the external interrupt sensitivity of the selected port.
void | EXTI_SetTLISensitivity (EXTI_TLISensitivity_TypeDef SensitivityValue)
Set the TLI interrupt sensitivity.

Detailed Description

This file contains all functions prototype and macros for the EXTI peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_exti.h.


STM8S/A Standard Peripherals Drivers: stm8s_flash.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Defines | Functions

stm8s_flash.c File Reference

This file contains all the functions for the FLASH peripheral. More...

#include "stm8s_flash.h"

Go to the source code of this file.

Defines

#define | FLASH_CLEAR_BYTE ((uint8_t)0x00)
#define | FLASH_SET_BYTE ((uint8_t)0xFF)
#define | OPERATION_TIMEOUT ((uint32_t)0xFFFFF)

Functions

void | FLASH_DeInit (void)
Deinitializes the FLASH registers to their default reset values.
void | FLASH_EraseByte (uint32_t Address)
Erases one byte in the program or data EEPROM memory.
void | FLASH_EraseOptionByte (uint16_t Address)
Erases option byte.
uint32_t | FLASH_GetBootSize (void)
Returns the Boot memory size in bytes.
FlagStatus | FLASH_GetFlagStatus (FLASH_Flag_TypeDef FLASH_FLAG)
Checks whether the specified SPI flag is set or not.
FLASH_LPMode_TypeDef | FLASH_GetLowPowerMode (void)
Returns the Flash behaviour type in low power mode.
FLASH_ProgramTime_TypeDef | FLASH_GetProgrammingTime (void)
Returns the fixed programming time.
void | FLASH_ITConfig (FunctionalState NewState)
Enables or Disables the Flash interrupt mode.
void | FLASH_Lock (FLASH_MemType_TypeDef FLASH_MemType)
Locks the program or data EEPROM memory.
void | FLASH_ProgramByte (uint32_t Address, uint8_t Data)
Programs one byte in program or data EEPROM memory.
void | FLASH_ProgramOptionByte (uint16_t Address, uint8_t Data)
Programs option byte.
void | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs one word (4 bytes) in program or data EEPROM memory.
uint8_t | FLASH_ReadByte (uint32_t Address)
Reads any byte from flash memory.
uint16_t | FLASH_ReadOptionByte (uint16_t Address)
Reads one option byte.
void | FLASH_SetLowPowerMode (FLASH_LPMode_TypeDef FLASH_LPMode)
Select the Flash behaviour in low power mode.
void | FLASH_SetProgrammingTime (FLASH_ProgramTime_TypeDef FLASH_ProgTime)
Sets the fixed programming time.
void | FLASH_Unlock (FLASH_MemType_TypeDef FLASH_MemType)
Unlocks the program or data EEPROM memory.

Detailed Description

This file contains all the functions for the FLASH peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_flash.c.


STM8S/A Standard Peripherals Drivers: stm8s_flash.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_flash.h File Reference

This file contains all functions prototype and macros for the FLASH peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | FLASH_OPTIONBYTE_ERROR ((uint16_t)0x5555)
#define | FLASH_PROG_START_PHYSICAL_ADDRESS ((uint32_t)0x008000)
#define | FLASH_RASS_KEY1 ((uint8_t)0x56)
#define | FLASH_RASS_KEY2 ((uint8_t)0xAE)
#define | IS_FLASH_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom and flash program Address.
#define | IS_FLASH_DATA_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom Address.
#define | IS_FLASH_DATA_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_DATA_BLOCKS_NUMBER)
Macro used by the assert function in order to check the different sensitivity values for the data eeprom Block number.
#define | IS_FLASH_FLAGS_OK(FLAG)
Macro used by the assert function in order to check the different flags values.
#define | IS_FLASH_LOW_POWER_MODE_OK(LPMODE)
Macro used by the assert function in order to check the different sensitivity values for the low power mode.
#define | IS_FLASH_PROG_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the flash program Address.
#define | IS_FLASH_PROG_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_PROG_BLOCKS_NUMBER)
Macro used by the assert function in order to check the different sensitivity values for the flash program Block number.
#define | IS_FLASH_PROGRAM_MODE_OK(MODE)
Macro used by the assert function in order to check the different sensitivity values for the flash program mode.
#define | IS_FLASH_PROGRAM_TIME_OK(TIME)
Macro used by the assert function in order to check the program time mode.
#define | IS_MEMORY_TYPE_OK(MEMTYPE)
Macro used by the assert function in order to check the different sensitivity values for the flash memory type.
#define | IS_OPTION_BYTE_ADDRESS_OK(ADDRESS)
Macro used by the assert function in order to check the different sensitivity values for the option bytes Address.
#define | OPTION_BYTE_END_PHYSICAL_ADDRESS ((uint16_t)0x487F)
#define | OPTION_BYTE_START_PHYSICAL_ADDRESS ((uint16_t)0x4800)

Enumerations

enum | FLASH_Flag_TypeDef { FLASH_FLAG_DUL = (uint8_t)0x08, FLASH_FLAG_EOP = (uint8_t)0x04, FLASH_FLAG_PUL = (uint8_t)0x02, FLASH_FLAG_WR_PG_DIS = (uint8_t)0x01 }

FLASH flags definition

  • Warning : FLAG value = mapping position register.
More...
enum | FLASH_LPMode_TypeDef { FLASH_LPMODE_POWERDOWN = (uint8_t)0x04, FLASH_LPMODE_STANDBY = (uint8_t)0x08, FLASH_LPMODE_POWERDOWN_STANDBY = (uint8_t)0x00, FLASH_LPMODE_STANDBY_POWERDOWN = (uint8_t)0x0C }

FLASH Low Power mode select.

More...
enum | FLASH_MemType_TypeDef { FLASH_MEMTYPE_PROG = (uint8_t)0xFD, FLASH_MEMTYPE_DATA = (uint8_t)0xF7 }

FLASH Memory types.

More...
enum | FLASH_ProgramMode_TypeDef { FLASH_PROGRAMMODE_STANDARD = (uint8_t)0x00, FLASH_PROGRAMMODE_FAST = (uint8_t)0x10 }

FLASH programming modes.

More...
enum | FLASH_ProgramTime_TypeDef { FLASH_PROGRAMTIME_STANDARD = (uint8_t)0x00, FLASH_PROGRAMTIME_TPROG = (uint8_t)0x01 }

FLASH fixed programming time.

More...
enum | FLASH_Status_TypeDef { FLASH_STATUS_SUCCESSFUL_OPERATION = (uint8_t)0x04, FLASH_STATUS_TIMEOUT = (uint8_t)0x02, FLASH_STATUS_WRITE_PROTECTION_ERROR = (uint8_t)0x01 }

FLASH status of the last operation.

More...

Functions

void | FLASH_DeInit (void)
Deinitializes the FLASH registers to their default reset values.
void | FLASH_EraseByte (uint32_t Address)
Erases one byte in the program or data EEPROM memory.
void | FLASH_EraseOptionByte (uint16_t Address)
Erases option byte.
uint32_t | FLASH_GetBootSize (void)
Returns the Boot memory size in bytes.
FlagStatus | FLASH_GetFlagStatus (FLASH_Flag_TypeDef FLASH_FLAG)
Checks whether the specified SPI flag is set or not.
FLASH_LPMode_TypeDef | FLASH_GetLowPowerMode (void)
Returns the Flash behaviour type in low power mode.
FLASH_ProgramTime_TypeDef | FLASH_GetProgrammingTime (void)
Returns the fixed programming time.
void | FLASH_ITConfig (FunctionalState NewState)
Enables or Disables the Flash interrupt mode.
void | FLASH_Lock (FLASH_MemType_TypeDef FLASH_MemType)
Locks the program or data EEPROM memory.
void | FLASH_ProgramByte (uint32_t Address, uint8_t Data)
Programs one byte in program or data EEPROM memory.
void | FLASH_ProgramOptionByte (uint16_t Address, uint8_t Data)
Programs option byte.
void | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs one word (4 bytes) in program or data EEPROM memory.
uint8_t | FLASH_ReadByte (uint32_t Address)
Reads any byte from flash memory.
uint16_t | FLASH_ReadOptionByte (uint16_t Address)
Reads one option byte.
void | FLASH_SetLowPowerMode (FLASH_LPMode_TypeDef FLASH_LPMode)
Select the Flash behaviour in low power mode.
void | FLASH_SetProgrammingTime (FLASH_ProgramTime_TypeDef FLASH_ProgTime)
Sets the fixed programming time.
void | FLASH_Unlock (FLASH_MemType_TypeDef FLASH_MemType)
Unlocks the program or data EEPROM memory.
IN_RAM (void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType, FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer))
IN_RAM (FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType))
IN_RAM (void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType))

Detailed Description

This file contains all functions prototype and macros for the FLASH peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_flash.h.


STM8S/A Standard Peripherals Drivers: stm8s_gpio.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_gpio.c File Reference

This file contains all the functions for the GPIO peripheral. More...

#include "stm8s_gpio.h"

Go to the source code of this file.

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ExternalPullUpConfig (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
Configures the external pull-up on GPIOx pins.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
Initializes the GPIOx according to the specified parameters.
uint8_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
BitStatus | GPIO_ReadInputPin (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
Reads the specified GPIO input data pin.
uint8_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint8_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteHigh (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes high level to the specified GPIO pins.
void | GPIO_WriteLow (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes low level to the specified GPIO pins.
void | GPIO_WriteReverse (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes reverse level to the specified GPIO pins.

Detailed Description

This file contains all the functions for the GPIO peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_gpio.c.


STM8S/A Standard Peripherals Drivers: stm8s_gpio.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_gpio.h File Reference

This file contains all functions prototype and macros for the GPIO peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_GPIO_MODE_OK(MODE)
Macro used by the assert function to check the different functions parameters.
#define | IS_GPIO_PIN_OK(PIN) ((PIN) != (uint8_t)0x00)
Macro used by the assert function in order to check the different values of GPIO_Pins.

Enumerations

enum GPIO_Mode_TypeDef {
GPIO_MODE_IN_FL_NO_IT = (uint8_t)0x00, GPIO_MODE_IN_PU_NO_IT = (uint8_t)0x40, GPIO_MODE_IN_FL_IT = (uint8_t)0x20, GPIO_MODE_IN_PU_IT = (uint8_t)0x60,
GPIO_MODE_OUT_OD_LOW_FAST = (uint8_t)0xA0, GPIO_MODE_OUT_PP_LOW_FAST = (uint8_t)0xE0, GPIO_MODE_OUT_OD_LOW_SLOW = (uint8_t)0x80, GPIO_MODE_OUT_PP_LOW_SLOW = (uint8_t)0xC0,
GPIO_MODE_OUT_OD_HIZ_FAST = (uint8_t)0xB0, GPIO_MODE_OUT_PP_HIGH_FAST = (uint8_t)0xF0, GPIO_MODE_OUT_OD_HIZ_SLOW = (uint8_t)0x90, GPIO_MODE_OUT_PP_HIGH_SLOW = (uint8_t)0xD0
}

GPIO modes.

More...
enum GPIO_Pin_TypeDef {
GPIO_PIN_0 = ((uint8_t)0x01), GPIO_PIN_1 = ((uint8_t)0x02), GPIO_PIN_2 = ((uint8_t)0x04), GPIO_PIN_3 = ((uint8_t)0x08),
GPIO_PIN_4 = ((uint8_t)0x10), GPIO_PIN_5 = ((uint8_t)0x20), GPIO_PIN_6 = ((uint8_t)0x40), GPIO_PIN_7 = ((uint8_t)0x80),
GPIO_PIN_LNIB = ((uint8_t)0x0F), GPIO_PIN_HNIB = ((uint8_t)0xF0), GPIO_PIN_ALL = ((uint8_t)0xFF)
}

Definition of the GPIO pins.

More...

Functions

void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ExternalPullUpConfig (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
Configures the external pull-up on GPIOx pins.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
Initializes the GPIOx according to the specified parameters.
uint8_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
BitStatus | GPIO_ReadInputPin (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
Reads the specified GPIO input data pin.
uint8_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint8_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteHigh (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes high level to the specified GPIO pins.
void | GPIO_WriteLow (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes low level to the specified GPIO pins.
void | GPIO_WriteReverse (GPIO_TypeDef *GPIOx, GPIO_Pin_TypeDef PortPins)
Writes reverse level to the specified GPIO pins.

Detailed Description

This file contains all functions prototype and macros for the GPIO peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_gpio.h.


STM8S/A Standard Peripherals Drivers: stm8s_i2c.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Defines | Functions

stm8s_i2c.c File Reference

This file contains all the functions for the I2C peripheral. More...

#include "stm8s_i2c.h"

Go to the source code of this file.

Defines

#define | FLAG_Mask ((uint16_t)0x00FF)
#define | ITEN_Mask ((uint16_t)0x0700)
#define | REGISTER_Mask ((uint16_t)0x3000)
#define | REGISTER_SR1_Index ((uint16_t)0x0100)
#define | REGISTER_SR2_Index ((uint16_t)0x0200)

Functions

void | I2C_AcknowledgeConfig (I2C_Ack_TypeDef Ack)
Enable or Disable the I2C acknowledge and position acknowledge feature.
ErrorStatus | I2C_CheckEvent (I2C_Event_TypeDef I2C_Event)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_Flag_TypeDef I2C_FLAG)
Clear flags.
void | I2C_ClearITPendingBit (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Clear IT pending bit.
void | I2C_Cmd (FunctionalState NewState)
Enables or disables the I2C peripheral.
void | I2C_DeInit (void)
Deinitializes the I2C peripheral registers to their default reset values.
void | I2C_FastModeDutyCycleConfig (I2C_DutyCycle_TypeDef I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (FunctionalState NewState)
Enables or disables the I2C General Call feature.
void | I2C_GenerateSTART (FunctionalState NewState)
Generates I2C communication START condition.
void | I2C_GenerateSTOP (FunctionalState NewState)
Generates I2C communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_Flag_TypeDef I2C_Flag)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Checks whether the specified I2C interrupt has occurred or not.
I2C_Event_TypeDef | I2C_GetLastEvent (void)
2) Advanced state monitoring
void | I2C_Init (uint32_t OutputClockFrequencyHz, uint16_t OwnAddress, I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack, I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz)
Initializes the I2C according to the specified parameters in standard or fast mode.
void | I2C_ITConfig (I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupt.
uint8_t | I2C_ReceiveData (void)
Returns the most recent received data.
void | I2C_Send7bitAddress (uint8_t Address, I2C_Direction_TypeDef Direction)
Transmits the 7-bit address (to select the) slave device.
void | I2C_SendData (uint8_t Data)
Send a byte by writing in the DR register.
void | I2C_SoftwareResetCmd (FunctionalState NewState)
Enables or disables I2C software reset.
void | I2C_StretchClockCmd (FunctionalState NewState)
Enables or disables the I2C clock stretching.

Detailed Description

This file contains all the functions for the I2C peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_i2c.c.


STM8S/A Standard Peripherals Drivers: stm8s_i2c.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_i2c.h File Reference

This file contains all functions prototype and macros for the I2C peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | I2C_MAX_FAST_FREQ ((uint32_t)400000)
#define | I2C_MAX_INPUT_FREQ ((uint8_t)16)
#define | I2C_MAX_STANDARD_FREQ ((uint32_t)100000)
#define | IS_I2C_ACK_OK(ACK)
Macro used by the assert function to check the different acknowledgement configuration.
#define | IS_I2C_ADDMODE_OK(ADDMODE)
Macro used by the assert function to check the different I2C addressing modes.
#define | IS_I2C_ADDRESS_OK(ADD) (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)
#define | IS_I2C_CLEAR_FLAG_OK(FLAG)
Macro used by the assert function to check the I2C flags to clear.
#define | IS_I2C_CLEAR_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the different I2C possible pending bits to clear by writing 0.
#define | IS_I2C_DIRECTION_OK(DIR)
Macro used by the assert function to check the different I2C communcation direction.
#define | IS_I2C_DUTYCYCLE_OK(DUTY)
Macro used by the assert function to check the different functions parameters.
#define | IS_I2C_EVENT_OK(EVENT)
Macro used by the assert function to check the different I2C possible events.
#define | IS_I2C_FLAG_OK(FLAG)
Macro used by the assert function to check the different I2C flags.
#define | IS_I2C_INPUT_CLOCK_FREQ_OK(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_INPUT_FREQ))
Macro used by the assert function to check that I2C Input clock frequency must be between 1MHz and 50MHz.
#define | IS_I2C_INTERRUPT_OK(IT)
Macro used by the assert function to check the different I2C interrupt types.
#define | IS_I2C_ITPENDINGBIT_OK(ITPENDINGBIT)
Macro used by the assert function to check the different I2C possible pending bits.
#define | IS_I2C_OUTPUT_CLOCK_FREQ_OK(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))
Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.
#define | IS_I2C_OWN_ADDRESS_OK(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
Macro used by the assert function to check the different I2C possible own address.

Enumerations

enum | I2C_Ack_TypeDef { I2C_ACK_NONE = (uint8_t)0x00, I2C_ACK_CURR = (uint8_t)0x01, I2C_ACK_NEXT = (uint8_t)0x02 }

I2C Acknowledgement configuration.

More...
enum | I2C_AddMode_TypeDef { I2C_ADDMODE_7BIT = (uint8_t)0x00, I2C_ADDMODE_10BIT = (uint8_t)0x80 }

I2C Addressing Mode (slave mode only)

More...
enum | I2C_Direction_TypeDef { I2C_DIRECTION_TX = (uint8_t)0x00, I2C_DIRECTION_RX = (uint8_t)0x01 }

I2C transfer direction Warning: the values correspond to the ADD0 bit position in the OARL register.

More...
enum | I2C_DutyCycle_TypeDef { I2C_DUTYCYCLE_2 = (uint8_t)0x00, I2C_DUTYCYCLE_16_9 = (uint8_t)0x40 }

I2C duty cycle (fast mode only)

More...
enum I2C_Event_TypeDef {
I2C_EVENT_MASTER_MODE_SELECT = (uint16_t)0x0301, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = (uint16_t)0x0302, I2C_EVENT_MASTER_MODE_ADDRESS10 = (uint16_t)0x0308,
I2C_EVENT_MASTER_BYTE_RECEIVED = (uint16_t)0x0340, I2C_EVENT_MASTER_BYTE_TRANSMITTING = (uint16_t)0x0780, I2C_EVENT_MASTER_BYTE_TRANSMITTED = (uint16_t)0x0784, I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = (uint16_t)0x0202,
I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682, I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = (uint16_t)0x1200, I2C_EVENT_SLAVE_BYTE_RECEIVED = (uint16_t)0x0240, I2C_EVENT_SLAVE_STOP_DETECTED = (uint16_t)0x0010,
I2C_EVENT_SLAVE_BYTE_TRANSMITTED = (uint16_t)0x0684, I2C_EVENT_SLAVE_BYTE_TRANSMITTING = (uint16_t)0x0680, I2C_EVENT_SLAVE_ACK_FAILURE = (uint16_t)0x0004
}

I2C possible events Values convention: 0xXXYY XX = Event SR3 corresponding value YY = Event SR1 corresponding value.

More...
enum I2C_Flag_TypeDef {
I2C_FLAG_TXEMPTY = (uint16_t)0x0180, I2C_FLAG_RXNOTEMPTY = (uint16_t)0x0140, I2C_FLAG_STOPDETECTION = (uint16_t)0x0110, I2C_FLAG_HEADERSENT = (uint16_t)0x0108,
I2C_FLAG_TRANSFERFINISHED = (uint16_t)0x0104, I2C_FLAG_ADDRESSSENTMATCHED = (uint16_t)0x0102, I2C_FLAG_STARTDETECTION = (uint16_t)0x0101, I2C_FLAG_WAKEUPFROMHALT = (uint16_t)0x0220,
I2C_FLAG_OVERRUNUNDERRUN = (uint16_t)0x0208, I2C_FLAG_ACKNOWLEDGEFAILURE = (uint16_t)0x0204, I2C_FLAG_ARBITRATIONLOSS = (uint16_t)0x0202, I2C_FLAG_BUSERROR = (uint16_t)0x0201,
I2C_FLAG_GENERALCALL = (uint16_t)0x0310, I2C_FLAG_TRANSMITTERRECEIVER = (uint16_t)0x0304, I2C_FLAG_BUSBUSY = (uint16_t)0x0302, I2C_FLAG_MASTERSLAVE = (uint16_t)0x0301
}

I2C Flags.

More...
enum | I2C_IT_TypeDef { I2C_IT_ERR = (uint8_t)0x01, I2C_IT_EVT = (uint8_t)0x02, I2C_IT_BUF = (uint8_t)0x04 }

I2C Interrupt sources Warning: the values correspond to the bit position in the ITR register.

More...
enum I2C_ITPendingBit_TypeDef {
I2C_ITPENDINGBIT_TXEMPTY = (uint16_t)0x1680, I2C_ITPENDINGBIT_RXNOTEMPTY = (uint16_t)0x1640, I2C_ITPENDINGBIT_STOPDETECTION = (uint16_t)0x1210, I2C_ITPENDINGBIT_HEADERSENT = (uint16_t)0x1208,
I2C_ITPENDINGBIT_TRANSFERFINISHED = (uint16_t)0x1204, I2C_ITPENDINGBIT_ADDRESSSENTMATCHED = (uint16_t)0x1202, I2C_ITPENDINGBIT_STARTDETECTION = (uint16_t)0x1201, I2C_ITPENDINGBIT_WAKEUPFROMHALT = (uint16_t)0x2220,
I2C_ITPENDINGBIT_OVERRUNUNDERRUN = (uint16_t)0x2108, I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE = (uint16_t)0x2104, I2C_ITPENDINGBIT_ARBITRATIONLOSS = (uint16_t)0x2102, I2C_ITPENDINGBIT_BUSERROR = (uint16_t)0x2101
}

I2C Pending bits Elements values convention: 0xXYZZ X = SRx registers index X = 1 : SR1 X = 2 : SR2 Y = Position of the corresponding Interrupt ZZ = flag mask in the dedicated register(X register)

More...

Functions

void | I2C_AcknowledgeConfig (I2C_Ack_TypeDef Ack)
Enable or Disable the I2C acknowledge and position acknowledge feature.
ErrorStatus | I2C_CheckEvent (I2C_Event_TypeDef I2C_Event)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_Flag_TypeDef I2C_FLAG)
Clear flags.
void | I2C_ClearITPendingBit (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Clear IT pending bit.
void | I2C_Cmd (FunctionalState NewState)
Enables or disables the I2C peripheral.
void | I2C_DeInit (void)
Deinitializes the I2C peripheral registers to their default reset values.
void | I2C_FastModeDutyCycleConfig (I2C_DutyCycle_TypeDef I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (FunctionalState NewState)
Enables or disables the I2C General Call feature.
void | I2C_GenerateSTART (FunctionalState NewState)
Generates I2C communication START condition.
void | I2C_GenerateSTOP (FunctionalState NewState)
Generates I2C communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_Flag_TypeDef I2C_Flag)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
Checks whether the specified I2C interrupt has occurred or not.
I2C_Event_TypeDef | I2C_GetLastEvent (void)
2) Advanced state monitoring
void | I2C_Init (uint32_t OutputClockFrequencyHz, uint16_t OwnAddress, I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack, I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz)
Initializes the I2C according to the specified parameters in standard or fast mode.
void | I2C_ITConfig (I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupt.
uint8_t | I2C_ReceiveData (void)
Returns the most recent received data.
void | I2C_Send7bitAddress (uint8_t Address, I2C_Direction_TypeDef Direction)
Transmits the 7-bit address (to select the) slave device.
void | I2C_SendData (uint8_t Data)
Send a byte by writing in the DR register.
void | I2C_SoftwareResetCmd (FunctionalState NewState)
Enables or disables I2C software reset.
void | I2C_StretchClockCmd (FunctionalState NewState)
Enables or disables the I2C clock stretching.

Detailed Description

This file contains all functions prototype and macros for the I2C peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_i2c.h.


STM8S/A Standard Peripherals Drivers: stm8s_itc.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_itc.c File Reference

This file contains all the functions for the ITC peripheral. More...

#include "stm8s_itc.h"

Go to the source code of this file.

Functions

void | ITC_DeInit (void)
Deinitializes the ITC registers to their default reset value.
uint8_t | ITC_GetCPUCC (void)
Utility function used to read CC register.
uint8_t | ITC_GetSoftIntStatus (void)
Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
ITC_PriorityLevel_TypeDef | ITC_GetSoftwarePriority (ITC_Irq_TypeDef IrqNum)
Gets the software priority of the specified interrupt source.
void | ITC_SetSoftwarePriority (ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
Sets the software priority of the specified interrupt source.

Detailed Description

This file contains all the functions for the ITC peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_itc.c.


STM8S/A Standard Peripherals Drivers: stm8s_itc.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_itc.h File Reference

This file contains all functions prototype and macros for the ITC peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | CPU_SOFT_INT_DISABLED ((uint8_t)0x28)
#define | IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)
#define | IS_ITC_IRQ_OK(IRQ) ((IRQ) <= (uint8_t)24)
#define | IS_ITC_PRIORITY_OK(PriorityValue)

Enumerations

enum ITC_Irq_TypeDef {
ITC_IRQ_TLI = (uint8_t)0, ITC_IRQ_AWU = (uint8_t)1, ITC_IRQ_CLK = (uint8_t)2, ITC_IRQ_PORTA = (uint8_t)3,
ITC_IRQ_PORTB = (uint8_t)4, ITC_IRQ_PORTC = (uint8_t)5, ITC_IRQ_PORTD = (uint8_t)6, ITC_IRQ_PORTE = (uint8_t)7,
ITC_IRQ_SPI = (uint8_t)10, ITC_IRQ_TIM1_OVF = (uint8_t)11, ITC_IRQ_TIM1_CAPCOM = (uint8_t)12, ITC_IRQ_TIM2_OVF = (uint8_t)13,
ITC_IRQ_TIM2_CAPCOM = (uint8_t)14, ITC_IRQ_TIM3_OVF = (uint8_t)15, ITC_IRQ_TIM3_CAPCOM = (uint8_t)16, ITC_IRQ_UART1_TX = (uint8_t)17,
ITC_IRQ_UART1_RX = (uint8_t)18, ITC_IRQ_I2C = (uint8_t)19, ITC_IRQ_TIM4_OVF = (uint8_t)23, ITC_IRQ_EEPROM_EEC = (uint8_t)24
}

ITC Interrupt Lines selection.

More...
enum | ITC_PriorityLevel_TypeDef { ITC_PRIORITYLEVEL_0 = (uint8_t)0x02, ITC_PRIORITYLEVEL_1 = (uint8_t)0x01, ITC_PRIORITYLEVEL_2 = (uint8_t)0x00, ITC_PRIORITYLEVEL_3 = (uint8_t)0x03 }

ITC Priority Levels selection.

More...

Functions

void | ITC_DeInit (void)
Deinitializes the ITC registers to their default reset value.
uint8_t | ITC_GetCPUCC (void)
Utility function used to read CC register.
uint8_t | ITC_GetSoftIntStatus (void)
Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
ITC_PriorityLevel_TypeDef | ITC_GetSoftwarePriority (ITC_Irq_TypeDef IrqNum)
Gets the software priority of the specified interrupt source.
void | ITC_SetSoftwarePriority (ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
Sets the software priority of the specified interrupt source.

Detailed Description

This file contains all functions prototype and macros for the ITC peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_itc.h.


STM8S/A Standard Peripherals Drivers: stm8s_iwdg.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_iwdg.c File Reference

This file contains all the functions for the IWDG peripheral. More...

#include "stm8s_iwdg.h"

Go to the source code of this file.

Functions

void | IWDG_Enable (void)
Enables IWDG.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter.
void | IWDG_SetPrescaler (IWDG_Prescaler_TypeDef IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint8_t IWDG_Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
Enables or disables write access to Prescaler and Reload registers.

Detailed Description

This file contains all the functions for the IWDG peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_iwdg.c.


STM8S/A Standard Peripherals Drivers: stm8s_iwdg.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_iwdg.h File Reference

This file contains all functions prototypes and macros for the IWDG peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_IWDG_PRESCALER_OK(VALUE)
Macro used by the assert function in order to check the different values of the prescaler.
#define | IS_IWDG_WRITEACCESS_MODE_OK(MODE) (((MODE) == IWDG_WriteAccess_Enable) || ((MODE) == IWDG_WriteAccess_Disable))
Macro used by the assert function in order to check the different values of the counter register.
#define | IWDG_KEY_ENABLE ((uint8_t)0xCC)
Define used to start the watchdog counter down.
#define | IWDG_KEY_REFRESH ((uint8_t)0xAA)
Define used to prevent watchdog reset.

Enumerations

enum IWDG_Prescaler_TypeDef {
IWDG_Prescaler_4 = (uint8_t)0x00, IWDG_Prescaler_8 = (uint8_t)0x01, IWDG_Prescaler_16 = (uint8_t)0x02, IWDG_Prescaler_32 = (uint8_t)0x03,
IWDG_Prescaler_64 = (uint8_t)0x04, IWDG_Prescaler_128 = (uint8_t)0x05, IWDG_Prescaler_256 = (uint8_t)0x06
}

IWDG prescaler enumaration.

More...
enum | IWDG_WriteAccess_TypeDef { IWDG_WriteAccess_Enable = (uint8_t)0x55, IWDG_WriteAccess_Disable = (uint8_t)0x00 }

IWDG write acces enumeration.

More...

Functions

void | IWDG_Enable (void)
Enables IWDG.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter.
void | IWDG_SetPrescaler (IWDG_Prescaler_TypeDef IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint8_t IWDG_Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
Enables or disables write access to Prescaler and Reload registers.

Detailed Description

This file contains all functions prototypes and macros for the IWDG peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_iwdg.h.


STM8S/A Standard Peripherals Drivers: stm8s_rst.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_rst.c File Reference

This file contains all the functions for the RST peripheral. More...

#include "stm8s_rst.h"

Go to the source code of this file.

Functions

void | RST_ClearFlag (RST_Flag_TypeDef RST_Flag)
Clears the specified RST flag.
FlagStatus | RST_GetFlagStatus (RST_Flag_TypeDef RST_Flag)
Checks whether the specified RST flag is set or not.

Detailed Description

This file contains all the functions for the RST peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_rst.c.


STM8S/A Standard Peripherals Drivers: stm8s_rst.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_rst.h File Reference

This file contains all functions prototype and macros for the RST peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_RST_FLAG_OK(FLAG)
Macro used by the assert function to check the different functions parameters.

Enumerations

enum RST_Flag_TypeDef {
RST_FLAG_EMCF = (uint8_t)0x10, RST_FLAG_SWIMF = (uint8_t)0x08, RST_FLAG_ILLOPF = (uint8_t)0x04, RST_FLAG_IWDGF = (uint8_t)0x02,
RST_FLAG_WWDGF = (uint8_t)0x01
}

Functions

void | RST_ClearFlag (RST_Flag_TypeDef RST_Flag)
Clears the specified RST flag.
FlagStatus | RST_GetFlagStatus (RST_Flag_TypeDef RST_Flag)
Checks whether the specified RST flag is set or not.

Detailed Description

This file contains all functions prototype and macros for the RST peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_rst.h.


STM8S/A Standard Peripherals Drivers: stm8s_spi.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_spi.c File Reference

This file contains all the functions for the SPI peripheral. More...

#include "stm8s_spi.h"

Go to the source code of this file.

Functions

void | SPI_BiDirectionalLineConfig (SPI_Direction_TypeDef SPI_Direction)
Selects the data transfer direction in bi-directional mode.
void | SPI_CalculateCRCCmd (FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_ClearFlag (SPI_Flag_TypeDef SPI_FLAG)
Clears the SPI flags.
void | SPI_ClearITPendingBit (SPI_IT_TypeDef SPI_IT)
Clears the interrupt pending bits.
void | SPI_Cmd (FunctionalState NewState)
Enables or disables the SPI peripheral.
void | SPI_DeInit (void)
Deinitializes the SPI peripheral registers to their default reset values.
uint8_t | SPI_GetCRC (SPI_CRC_TypeDef SPI_CRC)
Returns the transmit or the receive CRC register value.
uint8_t | SPI_GetCRCPolynomial (void)
Returns the CRC Polynomial register value.
FlagStatus | SPI_GetFlagStatus (SPI_Flag_TypeDef SPI_FLAG)
Checks whether the specified SPI flag is set or not.
ITStatus | SPI_GetITStatus (SPI_IT_TypeDef SPI_IT)
Checks whether the specified interrupt has occurred or not.
void | SPI_Init (SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)
Initializes the SPI according to the specified parameters.
void | SPI_ITConfig (SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
Enables or disables the specified interrupts.
void | SPI_NSSInternalSoftwareCmd (FunctionalState NewState)
Configures internally by software the NSS pin.
uint8_t | SPI_ReceiveData (void)
Returns the most recent received data by the SPI peripheral.
void | SPI_ResetCRC (void)
Reset the Rx CRCR and Tx CRCR registers.
void | SPI_SendData (uint8_t Data)
Transmits a Data through the SPI peripheral.
void | SPI_TransmitCRC (void)
Enables the transmit of the CRC value.

Detailed Description

This file contains all the functions for the SPI peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_spi.c.


STM8S/A Standard Peripherals Drivers: stm8s_spi.h File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_spi.h File Reference

This file contains all functions prototype and macros for the SPI peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_SPI_BAUDRATE_PRESCALER_OK(PRESCALER)
Macro used by the assert_param function in order to check the baudrate values.
#define | IS_SPI_CLEAR_FLAGS_OK(FLAG)
Macro used by the assert_param function in order to check the different sensitivity values for the flag that can be cleared by writing 0.
#define | IS_SPI_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert_param function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_SPI_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_SPI_CRC_OK(CRC)
Macro used by the assert_param function in order to check the CRC Transmit/Receive.
#define | IS_SPI_CRC_POLYNOMIAL_OK(POLYNOMIAL) ((POLYNOMIAL) > (uint8_t)0x00)
Macro used by the assert_param function in order to check the different sensitivity values for the CRC polynomial.
#define | IS_SPI_DATA_DIRECTION_OK(MODE)
Macro used by the assert_param function in order to check the data direction mode values.
#define | IS_SPI_DIRECTION_OK(DIRECTION)
Macro used by the assert_param function in order to check the mode half duplex data direction values.
#define | IS_SPI_FIRSTBIT_OK(BIT)
Macro used by the assert_param function in order to check the first bit to be transmited values.
#define | IS_SPI_FLAGS_OK(FLAG)
Macro used by the assert_param function in order to check the different flags values.
#define | IS_SPI_GET_IT_OK(ITPendingBit)
Macro used by the assert_param function in order to check the different sensitivity values for the pending bit.
#define | IS_SPI_MODE_OK(MODE)
Macro used by the assert_param function in order to check the SPI Mode values.
#define | IS_SPI_PHASE_OK(CLKPHA)
Macro used by the assert_param function in order to check the phase values.
#define | IS_SPI_POLARITY_OK(CLKPOL)
Macro used by the assert_param function in order to check the polarity values.
#define | IS_SPI_SLAVEMANAGEMENT_OK(NSS)
Macro used by the assert_param function in order to check the NSS management values.

Enumerations

enum SPI_BaudRatePrescaler_TypeDef {
SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x00, SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x08, SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x10, SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x18,
SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x20, SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x28, SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x30, SPI_BAUDRATEPRESCALER_256 = (uint8_t)0x38
}

SPI BaudRate Prescaler Warning: element values correspond to BR bits position.

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enum | SPI_ClockPhase_TypeDef { SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, SPI_CLOCKPHASE_2EDGE = (uint8_t)0x01 }

SPI Clock Phase Warning: element values correspond to CPHA bit position.

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enum | SPI_ClockPolarity_TypeDef { SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x02 }

SPI Clock Polarity Warning: element values correspond to CPOL bit position.

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enum | SPI_CRC_TypeDef { SPI_CRC_RX = (uint8_t)0x00, SPI_CRC_TX = (uint8_t)0x01 }

SPI CRC Transmit/Receive.

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enum | SPI_DataDirection_TypeDef { SPI_DATADIRECTION_2LINES_FULLDUPLEX = (uint8_t)0x00, SPI_DATADIRECTION_2LINES_RXONLY = (uint8_t)0x04, SPI_DATADIRECTION_1LINE_RX = (uint8_t)0x80, SPI_DATADIRECTION_1LINE_TX = (uint8_t)0xC0 }

SPI data direction mode Warning: element values correspond to BDM, BDOE, RXONLY bits position.

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enum | SPI_Direction_TypeDef { SPI_DIRECTION_RX = (uint8_t)0x00, SPI_DIRECTION_TX = (uint8_t)0x01 }

SPI direction transmit/receive.

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enum | SPI_FirstBit_TypeDef { SPI_FIRSTBIT_MSB = (uint8_t)0x00, SPI_FIRSTBIT_LSB = (uint8_t)0x80 }

SPI Frame Format: MSB or LSB transmitted first Warning: element values correspond to LSBFIRST bit position.

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enum SPI_Flag_TypeDef {
SPI_FLAG_BSY = (uint8_t)0x80, SPI_FLAG_OVR = (uint8_t)0x40, SPI_FLAG_MODF = (uint8_t)0x20, SPI_FLAG_CRCERR = (uint8_t)0x10,
SPI_FLAG_WKUP = (uint8_t)0x08, SPI_FLAG_TXE = (uint8_t)0x02, SPI_FLAG_RXNE = (uint8_t)0x01
}

SPI flags definition - Warning : FLAG value = mapping position register.

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enum SPI_IT_TypeDef {
SPI_IT_WKUP = (uint8_t)0x34, SPI_IT_OVR = (uint8_t)0x65, SPI_IT_MODF = (uint8_t)0x55, SPI_IT_CRCERR = (uint8_t)0x45,
SPI_IT_TXE = (uint8_t)0x17, SPI_IT_RXNE = (uint8_t)0x06, SPI_IT_ERR = (uint8_t)0x05
}

SPI_IT possible values Elements values convention: 0xYX X: Position of the corresponding Interrupt Y: ITPENDINGBIT position.

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enum | SPI_Mode_TypeDef { SPI_MODE_MASTER = (uint8_t)0x04, SPI_MODE_SLAVE = (uint8_t)0x00 }

SPI master/slave mode Warning: element values correspond to MSTR bit position.

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enum | SPI_NSS_TypeDef { SPI_NSS_SOFT = (uint8_t)0x02, SPI_NSS_HARD = (uint8_t)0x00 }

SPI Slave Select management Warning: element values correspond to LSBFIRST bit position.

More...

Functions

void | SPI_BiDirectionalLineConfig (SPI_Direction_TypeDef SPI_Direction)
Selects the data transfer direction in bi-directional mode.
void | SPI_CalculateCRCCmd (FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_ClearFlag (SPI_Flag_TypeDef SPI_FLAG)
Clears the SPI flags.
void | SPI_ClearITPendingBit (SPI_IT_TypeDef SPI_IT)
Clears the interrupt pending bits.
void | SPI_Cmd (FunctionalState NewState)
Enables or disables the SPI peripheral.
void | SPI_DeInit (void)
Deinitializes the SPI peripheral registers to their default reset values.
uint8_t | SPI_GetCRC (SPI_CRC_TypeDef SPI_CRC)
Returns the transmit or the receive CRC register value.
uint8_t | SPI_GetCRCPolynomial (void)
Returns the CRC Polynomial register value.
FlagStatus | SPI_GetFlagStatus (SPI_Flag_TypeDef SPI_FLAG)
Checks whether the specified SPI flag is set or not.
ITStatus | SPI_GetITStatus (SPI_IT_TypeDef SPI_IT)
Checks whether the specified interrupt has occurred or not.
void | SPI_Init (SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)
Initializes the SPI according to the specified parameters.
void | SPI_ITConfig (SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
Enables or disables the specified interrupts.
void | SPI_NSSInternalSoftwareCmd (FunctionalState NewState)
Configures internally by software the NSS pin.
uint8_t | SPI_ReceiveData (void)
Returns the most recent received data by the SPI peripheral.
void | SPI_ResetCRC (void)
Reset the Rx CRCR and Tx CRCR registers.
void | SPI_SendData (uint8_t Data)
Transmits a Data through the SPI peripheral.
void | SPI_TransmitCRC (void)
Enables the transmit of the CRC value.

Detailed Description

This file contains all functions prototype and macros for the SPI peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_spi.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim1.c File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_tim1.c File Reference

This file contains all the functions for the TIM1 peripheral. More...

#include "stm8s_tim1.h"

Go to the source code of this file.

Functions

static void | TI1_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI3 as Input.
static void | TI4_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI4 as Input.
void | TIM1_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM1 peripheral Preload register on ARR.
void | TIM1_BDTRConfig (TIM1_OSSIState_TypeDef TIM1_OSSIState, TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime, TIM1_BreakState_TypeDef TIM1_Break, TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).
void | TIM1_CCPreloadControl (FunctionalState NewState)
Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
void | TIM1_CCxCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
void | TIM1_CCxNCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
void | TIM1_ClearFlag (TIM1_FLAG_TypeDef TIM1_FLAG)
Clears the TIM1’s pending flags.
void | TIM1_ClearITPendingBit (TIM1_IT_TypeDef TIM1_IT)
Clears the TIM1's interrupt pending bits.
void | TIM1_Cmd (FunctionalState NewState)
Enables or disables the TIM1 peripheral.
void | TIM1_CounterModeConfig (TIM1_CounterMode_TypeDef TIM1_CounterMode)
Specifies the TIM1 Counter Mode to be used.
void | TIM1_CtrlPWMOutputs (FunctionalState NewState)
Enables or disables the TIM1 peripheral Main Outputs.
void | TIM1_DeInit (void)
Deinitializes the TIM1 peripheral registers to their default reset values.
void | TIM1_EncoderInterfaceConfig (TIM1_EncoderMode_TypeDef TIM1_EncoderMode, TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
Configures the TIM1 Encoder Interface.
void | TIM1_ETRClockMode1Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode1.
void | TIM1_ETRClockMode2Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode2.
void | TIM1_ETRConfig (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External Trigger.
void | TIM1_ForcedOC1Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel1 output waveform to active or inactive level.
void | TIM1_ForcedOC2Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel2 output waveform to active or inactive level.
void | TIM1_ForcedOC3Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel3 output waveform to active or inactive level.
void | TIM1_ForcedOC4Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel4 output waveform to active or inactive level.
void | TIM1_GenerateEvent (TIM1_EventSource_TypeDef TIM1_EventSource)
Configures the TIM1 event to be generated by software.
uint16_t | TIM1_GetCapture1 (void)
Gets the TIM1 Input Capture 1 value.
uint16_t | TIM1_GetCapture2 (void)
Gets the TIM1 Input Capture 2 value.
uint16_t | TIM1_GetCapture3 (void)
Gets the TIM1 Input Capture 3 value.
uint16_t | TIM1_GetCapture4 (void)
Gets the TIM1 Input Capture 4 value.
uint16_t | TIM1_GetCounter (void)
Gets the TIM1 Counter value.
FlagStatus | TIM1_GetFlagStatus (TIM1_FLAG_TypeDef TIM1_FLAG)
Checks whether the specified TIM1 flag is set or not.
ITStatus | TIM1_GetITStatus (TIM1_IT_TypeDef TIM1_IT)
Checks whether the TIM1 interrupt has occurred or not.
uint16_t | TIM1_GetPrescaler (void)
Gets the TIM1 Prescaler value.
void | TIM1_ICInit (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Initializes the TIM1 peripheral according to the specified parameters.
void | TIM1_InternalClockConfig (void)
Configures the TIM1 internal Clock.
void | TIM1_ITConfig (TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState)
Enables or disables the specified TIM1 interrupts.
void | TIM1_OC1FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 1 Fast feature.
void | TIM1_OC1Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel1 according to the specified parameters.
void | TIM1_OC1NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 1N polarity.
void | TIM1_OC1PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 1 polarity.
void | TIM1_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR1.
void | TIM1_OC2FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 2 Fast feature.
void | TIM1_OC2Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel2 according to the specified parameters.
void | TIM1_OC2NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 2N polarity.
void | TIM1_OC2PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 2 polarity.
void | TIM1_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR2.
void | TIM1_OC3FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 3 Fast feature.
void | TIM1_OC3Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel3 according to the specified parameters.
void | TIM1_OC3NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 3N polarity.
void | TIM1_OC3PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 3 polarity.
void | TIM1_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR3.
void | TIM1_OC4FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 4 Fast feature.
void | TIM1_OC4Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
Initializes the TIM1 Channel4 according to the specified parameters.
void | TIM1_OC4PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 4 polarity.
void | TIM1_OC4PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR4.
void | TIM1_PrescalerConfig (uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
Configures the TIM1 Prescaler.
void | TIM1_PWMIConfig (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.
void | TIM1_SelectCOM (FunctionalState NewState)
Selects the TIM1 peripheral Commutation event.
void | TIM1_SelectHallSensor (FunctionalState NewState)
Enables or Disables the TIM1’s Hall sensor interface.
void | TIM1_SelectInputTrigger (TIM1_TS_TypeDef TIM1_InputTriggerSource)
Selects the TIM1 Input Trigger source.
void | TIM1_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM1 Master/Slave Mode.
void | TIM1_SelectOCxM (TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
Selects the TIM1 Output Compare Mode.
void | TIM1_SelectOnePulseMode (TIM1_OPMode_TypeDef TIM1_OPMode)
Selects the TIM1’s One Pulse Mode.
void | TIM1_SelectOutputTrigger (TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
Selects the TIM1 Trigger Output Mode.
void | TIM1_SelectSlaveMode (TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
Selects the TIM1 Slave Mode.
void | TIM1_SetAutoreload (uint16_t Autoreload)
Sets the TIM1 Autoreload Register value.
void | TIM1_SetCompare1 (uint16_t Compare1)
Sets the TIM1 Capture Compare1 Register value.
void | TIM1_SetCompare2 (uint16_t Compare2)
Sets the TIM1 Capture Compare2 Register value.
void | TIM1_SetCompare3 (uint16_t Compare3)
Sets the TIM1 Capture Compare3 Register value.
void | TIM1_SetCompare4 (uint16_t Compare4)
Sets the TIM1 Capture Compare4 Register value.
void | TIM1_SetCounter (uint16_t Counter)
Sets the TIM1 Counter Register value.
void | TIM1_SetIC1Prescaler (TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
Sets the TIM1 Input Capture 1 prescaler.
void | TIM1_SetIC2Prescaler (TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
Sets the TIM1 Input Capture 2 prescaler.
void | TIM1_SetIC3Prescaler (TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
Sets the TIM1 Input Capture 3 prescaler.
void | TIM1_SetIC4Prescaler (TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
Sets the TIM1 Input Capture 4 prescaler.
void | TIM1_TimeBaseInit (uint16_t TIM1_Prescaler, TIM1_CounterMode_TypeDef TIM1_CounterMode, uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter)
Initializes the TIM1 Time Base Unit according to the specified parameters.
void | TIM1_TIxExternalClockConfig (TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, uint8_t ICFilter)
Configures the TIM1 Trigger as External Clock.
void | TIM1_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM1 Update event.
void | TIM1_UpdateRequestConfig (TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
Selects the TIM1 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM1 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim1.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim1.h File Reference

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Defines | Enumerations | Functions

stm8s_tim1.h File Reference

This file contains all functions prototype and macros for the TIM1 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(STATE)
#define | IS_TIM1_BREAK_POLARITY_OK(POLARITY)
#define | IS_TIM1_BREAK_STATE_OK(STATE)
#define | IS_TIM1_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
#define | IS_TIM1_COMPLEMENTARY_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_COUNTER_MODE_OK(MODE)
#define | IS_TIM1_ENCODER_MODE_OK(MODE)
#define | IS_TIM1_EVENT_SOURCE_OK(SOURCE) ((SOURCE) != 0x00)
#define | IS_TIM1_EXT_POLARITY_OK(POLARITY)
#define | IS_TIM1_EXT_PRESCALER_OK(PRESCALER)
#define | IS_TIM1_EXT_TRG_FILTER_OK(FILTER) ((FILTER) <= 0x0F)
TIM1 External Trigger Filer Value.
#define | IS_TIM1_FORCED_ACTION_OK(ACTION)
#define | IS_TIM1_GET_FLAG_OK(FLAG)
#define | IS_TIM1_GET_IT_OK(IT)
#define | IS_TIM1_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM1 Input Capture Filer Value.
#define | IS_TIM1_IC_POLARITY_OK(POLARITY)
#define | IS_TIM1_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM1_IC_SELECTION_OK(SELECTION)
#define | IS_TIM1_IT_OK(IT) ((IT) != 0x00)
#define | IS_TIM1_LOCK_LEVEL_OK(LEVEL)
#define | IS_TIM1_OC_MODE_OK(MODE)
#define | IS_TIM1_OC_POLARITY_OK(POLARITY)
#define | IS_TIM1_OCIDLE_STATE_OK(STATE)
#define | IS_TIM1_OCM_OK(MODE)
#define | IS_TIM1_OCN_POLARITY_OK(POLARITY)
#define | IS_TIM1_OCNIDLE_STATE_OK(STATE)
#define | IS_TIM1_OPM_MODE_OK(MODE)
#define | IS_TIM1_OSSI_STATE_OK(STATE)
#define | IS_TIM1_OUTPUT_STATE_OK(STATE)
#define | IS_TIM1_OUTPUTN_STATE_OK(STATE)
#define | IS_TIM1_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM1_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM1_SLAVE_MODE_OK(MODE)
#define | IS_TIM1_TIX_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM1_TIXCLK_SOURCE_OK(SOURCE)
#define | IS_TIM1_TRGO_SOURCE_OK(SOURCE)
#define | IS_TIM1_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM1_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM1_AutomaticOutput_TypeDef { TIM1_AUTOMATICOUTPUT_ENABLE = ((uint8_t)0x40), TIM1_AUTOMATICOUTPUT_DISABLE = ((uint8_t)0x00) }

TIM1 AOE Bit Set/Reset.

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enum | TIM1_BreakPolarity_TypeDef { TIM1_BREAKPOLARITY_LOW = ((uint8_t)0x00), TIM1_BREAKPOLARITY_HIGH = ((uint8_t)0x20) }

TIM1 Break Polarity.

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enum | TIM1_BreakState_TypeDef { TIM1_BREAK_ENABLE = ((uint8_t)0x10), TIM1_BREAK_DISABLE = ((uint8_t)0x00) }

TIM1 Break Input enable/disable.

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enum | TIM1_Channel_TypeDef { TIM1_CHANNEL_1 = ((uint8_t)0x00), TIM1_CHANNEL_2 = ((uint8_t)0x01), TIM1_CHANNEL_3 = ((uint8_t)0x02), TIM1_CHANNEL_4 = ((uint8_t)0x03) }

TIM1 Channel.

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enum TIM1_CounterMode_TypeDef {
TIM1_COUNTERMODE_UP = ((uint8_t)0x00), TIM1_COUNTERMODE_DOWN = ((uint8_t)0x10), TIM1_COUNTERMODE_CENTERALIGNED1 = ((uint8_t)0x20), TIM1_COUNTERMODE_CENTERALIGNED2 = ((uint8_t)0x40),
TIM1_COUNTERMODE_CENTERALIGNED3 = ((uint8_t)0x60)
}

TIM1 Counter Mode.

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enum | TIM1_EncoderMode_TypeDef { TIM1_ENCODERMODE_TI1 = ((uint8_t)0x01), TIM1_ENCODERMODE_TI2 = ((uint8_t)0x02), TIM1_ENCODERMODE_TI12 = ((uint8_t)0x03) }

TIM1 Encoder Mode.

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enum TIM1_EventSource_TypeDef {
TIM1_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM1_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM1_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM1_EVENTSOURCE_CC3 = ((uint8_t)0x08),
TIM1_EVENTSOURCE_CC4 = ((uint8_t)0x10), TIM1_EVENTSOURCE_COM = ((uint8_t)0x20), TIM1_EVENTSOURCE_TRIGGER = ((uint8_t)0x40), TIM1_EVENTSOURCE_BREAK = ((uint8_t)0x80)
}

TIM1 Event Source.

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enum | TIM1_ExtTRGPolarity_TypeDef { TIM1_EXTTRGPOLARITY_INVERTED = ((uint8_t)0x80), TIM1_EXTTRGPOLARITY_NONINVERTED = ((uint8_t)0x00) }

TIM1 External Trigger Polarity.

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enum | TIM1_ExtTRGPSC_TypeDef { TIM1_EXTTRGPSC_OFF = ((uint8_t)0x00), TIM1_EXTTRGPSC_DIV2 = ((uint8_t)0x10), TIM1_EXTTRGPSC_DIV4 = ((uint8_t)0x20), TIM1_EXTTRGPSC_DIV8 = ((uint8_t)0x30) }

TIM1 External Trigger Prescaler.

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enum TIM1_FLAG_TypeDef {
TIM1_FLAG_UPDATE = ((uint16_t)0x0001), TIM1_FLAG_CC1 = ((uint16_t)0x0002), TIM1_FLAG_CC2 = ((uint16_t)0x0004), TIM1_FLAG_CC3 = ((uint16_t)0x0008),
TIM1_FLAG_CC4 = ((uint16_t)0x0010), TIM1_FLAG_COM = ((uint16_t)0x0020), TIM1_FLAG_TRIGGER = ((uint16_t)0x0040), TIM1_FLAG_BREAK = ((uint16_t)0x0080),
TIM1_FLAG_CC1OF = ((uint16_t)0x0200), TIM1_FLAG_CC2OF = ((uint16_t)0x0400), TIM1_FLAG_CC3OF = ((uint16_t)0x0800), TIM1_FLAG_CC4OF = ((uint16_t)0x1000)
}

TIM1 Flags.

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enum | TIM1_ForcedAction_TypeDef { TIM1_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM1_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }

TIM1 Forced Action.

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enum | TIM1_ICPolarity_TypeDef { TIM1_ICPOLARITY_RISING = ((uint8_t)0x00), TIM1_ICPOLARITY_FALLING = ((uint8_t)0x01) }

TIM1 Input Capture Polarity.

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enum | TIM1_ICPSC_TypeDef { TIM1_ICPSC_DIV1 = ((uint8_t)0x00), TIM1_ICPSC_DIV2 = ((uint8_t)0x04), TIM1_ICPSC_DIV4 = ((uint8_t)0x08), TIM1_ICPSC_DIV8 = ((uint8_t)0x0C) }

TIM1 Input Capture Prescaler.

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enum | TIM1_ICSelection_TypeDef { TIM1_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM1_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM1_ICSELECTION_TRGI = ((uint8_t)0x03) }

TIM1 Input Capture Selection.

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enum TIM1_IT_TypeDef {
TIM1_IT_UPDATE = ((uint8_t)0x01), TIM1_IT_CC1 = ((uint8_t)0x02), TIM1_IT_CC2 = ((uint8_t)0x04), TIM1_IT_CC3 = ((uint8_t)0x08),
TIM1_IT_CC4 = ((uint8_t)0x10), TIM1_IT_COM = ((uint8_t)0x20), TIM1_IT_TRIGGER = ((uint8_t)0x40), TIM1_IT_BREAK = ((uint8_t)0x80)
}

TIM1 interrupt sources.

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enum | TIM1_LockLevel_TypeDef { TIM1_LOCKLEVEL_OFF = ((uint8_t)0x00), TIM1_LOCKLEVEL_1 = ((uint8_t)0x01), TIM1_LOCKLEVEL_2 = ((uint8_t)0x02), TIM1_LOCKLEVEL_3 = ((uint8_t)0x03) }

TIM1 Lock levels.

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enum | TIM1_OCIdleState_TypeDef { TIM1_OCIDLESTATE_SET = ((uint8_t)0x55), TIM1_OCIDLESTATE_RESET = ((uint8_t)0x00) }

TIM1 Output Compare Idle State.

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enum TIM1_OCMode_TypeDef {
TIM1_OCMODE_TIMING = ((uint8_t)0x00), TIM1_OCMODE_ACTIVE = ((uint8_t)0x10), TIM1_OCMODE_INACTIVE = ((uint8_t)0x20), TIM1_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM1_OCMODE_PWM1 = ((uint8_t)0x60), TIM1_OCMODE_PWM2 = ((uint8_t)0x70)
}

TIM1 Output Compare and PWM modes.

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enum | TIM1_OCNIdleState_TypeDef { TIM1_OCNIDLESTATE_SET = ((uint8_t)0x2A), TIM1_OCNIDLESTATE_RESET = ((uint8_t)0x00) }

TIM1 Output Compare N Idle State.

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enum | TIM1_OCNPolarity_TypeDef { TIM1_OCNPOLARITY_HIGH = ((uint8_t)0x00), TIM1_OCNPOLARITY_LOW = ((uint8_t)0x88) }

TIM1 Output Compare N Polarity.

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enum | TIM1_OCPolarity_TypeDef { TIM1_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM1_OCPOLARITY_LOW = ((uint8_t)0x22) }

TIM1 Output Compare Polarity.

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enum | TIM1_OPMode_TypeDef { TIM1_OPMODE_SINGLE = ((uint8_t)0x01), TIM1_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM1 One Pulse Mode.

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enum | TIM1_OSSIState_TypeDef { TIM1_OSSISTATE_ENABLE = ((uint8_t)0x04), TIM1_OSSISTATE_DISABLE = ((uint8_t)0x00) }

TIM1 OSSI: Off-State Selection for Idle mode states.

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enum | TIM1_OutputNState_TypeDef { TIM1_OUTPUTNSTATE_DISABLE = ((uint8_t)0x00), TIM1_OUTPUTNSTATE_ENABLE = ((uint8_t)0x44) }

TIM1 Output Compare N States.

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enum | TIM1_OutputState_TypeDef { TIM1_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM1_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }

TIM1 Output Compare states.

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enum | TIM1_PSCReloadMode_TypeDef { TIM1_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM1_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM1 Prescaler Reload Mode.

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enum | TIM1_SlaveMode_TypeDef { TIM1_SLAVEMODE_RESET = ((uint8_t)0x04), TIM1_SLAVEMODE_GATED = ((uint8_t)0x05), TIM1_SLAVEMODE_TRIGGER = ((uint8_t)0x06), TIM1_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07) }

TIM1 Slave Mode.

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enum | TIM1_TIxExternalCLK1Source_TypeDef { TIM1_TIXEXTERNALCLK1SOURCE_TI1ED = ((uint8_t)0x40), TIM1_TIXEXTERNALCLK1SOURCE_TI1 = ((uint8_t)0x50), TIM1_TIXEXTERNALCLK1SOURCE_TI2 = ((uint8_t)0x60) }

TIM1 TIx External Clock Source.

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enum TIM1_TRGOSource_TypeDef {
TIM1_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM1_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM1_TRGOSOURCE_UPDATE = ((uint8_t)0x20), TIM1_TRGOSource_OC1 = ((uint8_t)0x30),
TIM1_TRGOSOURCE_OC1REF = ((uint8_t)0x40), TIM1_TRGOSOURCE_OC2REF = ((uint8_t)0x50), TIM1_TRGOSOURCE_OC3REF = ((uint8_t)0x60)
}

TIM1 Trigger Output Source.

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enum TIM1_TS_TypeDef {
TIM1_TS_TIM6 = ((uint8_t)0x00), TIM1_TS_TIM5 = ((uint8_t)0x30), TIM1_TS_TI1F_ED = ((uint8_t)0x40), TIM1_TS_TI1FP1 = ((uint8_t)0x50),
TIM1_TS_TI2FP2 = ((uint8_t)0x60), TIM1_TS_ETRF = ((uint8_t)0x70)
}

TIM1 Internal Trigger Selection.

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enum | TIM1_UpdateSource_TypeDef { TIM1_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM1_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM1 Update Source.

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Functions

void | TIM1_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM1 peripheral Preload register on ARR.
void | TIM1_BDTRConfig (TIM1_OSSIState_TypeDef TIM1_OSSIState, TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime, TIM1_BreakState_TypeDef TIM1_Break, TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
Configures the Break feature, dead time, Lock level, the OSSI, and the AOE(automatic output enable).
void | TIM1_CCPreloadControl (FunctionalState NewState)
Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
void | TIM1_CCxCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
void | TIM1_CCxNCmd (TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
void | TIM1_ClearFlag (TIM1_FLAG_TypeDef TIM1_FLAG)
Clears the TIM1’s pending flags.
void | TIM1_ClearITPendingBit (TIM1_IT_TypeDef TIM1_IT)
Clears the TIM1's interrupt pending bits.
void | TIM1_Cmd (FunctionalState NewState)
Enables or disables the TIM1 peripheral.
void | TIM1_CounterModeConfig (TIM1_CounterMode_TypeDef TIM1_CounterMode)
Specifies the TIM1 Counter Mode to be used.
void | TIM1_CtrlPWMOutputs (FunctionalState NewState)
Enables or disables the TIM1 peripheral Main Outputs.
void | TIM1_DeInit (void)
Deinitializes the TIM1 peripheral registers to their default reset values.
void | TIM1_EncoderInterfaceConfig (TIM1_EncoderMode_TypeDef TIM1_EncoderMode, TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
Configures the TIM1 Encoder Interface.
void | TIM1_ETRClockMode1Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode1.
void | TIM1_ETRClockMode2Config (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External clock Mode2.
void | TIM1_ETRConfig (TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, uint8_t ExtTRGFilter)
Configures the TIM1 External Trigger.
void | TIM1_ForcedOC1Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel1 output waveform to active or inactive level.
void | TIM1_ForcedOC2Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel2 output waveform to active or inactive level.
void | TIM1_ForcedOC3Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel3 output waveform to active or inactive level.
void | TIM1_ForcedOC4Config (TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
Forces the TIM1 Channel4 output waveform to active or inactive level.
void | TIM1_GenerateEvent (TIM1_EventSource_TypeDef TIM1_EventSource)
Configures the TIM1 event to be generated by software.
uint16_t | TIM1_GetCapture1 (void)
Gets the TIM1 Input Capture 1 value.
uint16_t | TIM1_GetCapture2 (void)
Gets the TIM1 Input Capture 2 value.
uint16_t | TIM1_GetCapture3 (void)
Gets the TIM1 Input Capture 3 value.
uint16_t | TIM1_GetCapture4 (void)
Gets the TIM1 Input Capture 4 value.
uint16_t | TIM1_GetCounter (void)
Gets the TIM1 Counter value.
FlagStatus | TIM1_GetFlagStatus (TIM1_FLAG_TypeDef TIM1_FLAG)
Checks whether the specified TIM1 flag is set or not.
ITStatus | TIM1_GetITStatus (TIM1_IT_TypeDef TIM1_IT)
Checks whether the TIM1 interrupt has occurred or not.
uint16_t | TIM1_GetPrescaler (void)
Gets the TIM1 Prescaler value.
void | TIM1_ICInit (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Initializes the TIM1 peripheral according to the specified parameters.
void | TIM1_InternalClockConfig (void)
Configures the TIM1 internal Clock.
void | TIM1_ITConfig (TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState)
Enables or disables the specified TIM1 interrupts.
void | TIM1_OC1FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 1 Fast feature.
void | TIM1_OC1Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel1 according to the specified parameters.
void | TIM1_OC1NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 1N polarity.
void | TIM1_OC1PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 1 polarity.
void | TIM1_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR1.
void | TIM1_OC2FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 2 Fast feature.
void | TIM1_OC2Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel2 according to the specified parameters.
void | TIM1_OC2NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 2N polarity.
void | TIM1_OC2PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 2 polarity.
void | TIM1_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR2.
void | TIM1_OC3FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 3 Fast feature.
void | TIM1_OC3Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
Initializes the TIM1 Channel3 according to the specified parameters.
void | TIM1_OC3NPolarityConfig (TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
Configures the TIM1 Channel 3N polarity.
void | TIM1_OC3PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 3 polarity.
void | TIM1_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR3.
void | TIM1_OC4FastConfig (FunctionalState NewState)
Configures the TIM1 Capture Compare 4 Fast feature.
void | TIM1_OC4Init (TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
Initializes the TIM1 Channel4 according to the specified parameters.
void | TIM1_OC4PolarityConfig (TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
Configures the TIM1 Channel 4 polarity.
void | TIM1_OC4PreloadConfig (FunctionalState NewState)
Enables or disables the TIM1 peripheral Preload Register on CCR4.
void | TIM1_PrescalerConfig (uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
Configures the TIM1 Prescaler.
void | TIM1_PWMIConfig (TIM1_Channel_TypeDef TIM1_Channel, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, TIM1_ICSelection_TypeDef TIM1_ICSelection, TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter)
Configures the TIM1 peripheral in PWM Input Mode according to the specified parameters.
void | TIM1_SelectCOM (FunctionalState NewState)
Selects the TIM1 peripheral Commutation event.
void | TIM1_SelectHallSensor (FunctionalState NewState)
Enables or Disables the TIM1’s Hall sensor interface.
void | TIM1_SelectInputTrigger (TIM1_TS_TypeDef TIM1_InputTriggerSource)
Selects the TIM1 Input Trigger source.
void | TIM1_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM1 Master/Slave Mode.
void | TIM1_SelectOCxM (TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
Selects the TIM1 Output Compare Mode.
void | TIM1_SelectOnePulseMode (TIM1_OPMode_TypeDef TIM1_OPMode)
Selects the TIM1’s One Pulse Mode.
void | TIM1_SelectOutputTrigger (TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
Selects the TIM1 Trigger Output Mode.
void | TIM1_SelectSlaveMode (TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
Selects the TIM1 Slave Mode.
void | TIM1_SetAutoreload (uint16_t Autoreload)
Sets the TIM1 Autoreload Register value.
void | TIM1_SetCompare1 (uint16_t Compare1)
Sets the TIM1 Capture Compare1 Register value.
void | TIM1_SetCompare2 (uint16_t Compare2)
Sets the TIM1 Capture Compare2 Register value.
void | TIM1_SetCompare3 (uint16_t Compare3)
Sets the TIM1 Capture Compare3 Register value.
void | TIM1_SetCompare4 (uint16_t Compare4)
Sets the TIM1 Capture Compare4 Register value.
void | TIM1_SetCounter (uint16_t Counter)
Sets the TIM1 Counter Register value.
void | TIM1_SetIC1Prescaler (TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
Sets the TIM1 Input Capture 1 prescaler.
void | TIM1_SetIC2Prescaler (TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
Sets the TIM1 Input Capture 2 prescaler.
void | TIM1_SetIC3Prescaler (TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
Sets the TIM1 Input Capture 3 prescaler.
void | TIM1_SetIC4Prescaler (TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
Sets the TIM1 Input Capture 4 prescaler.
void | TIM1_TimeBaseInit (uint16_t TIM1_Prescaler, TIM1_CounterMode_TypeDef TIM1_CounterMode, uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter)
Initializes the TIM1 Time Base Unit according to the specified parameters.
void | TIM1_TIxExternalClockConfig (TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, TIM1_ICPolarity_TypeDef TIM1_ICPolarity, uint8_t ICFilter)
Configures the TIM1 Trigger as External Clock.
void | TIM1_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM1 Update event.
void | TIM1_UpdateRequestConfig (TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
Selects the TIM1 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM1 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim1.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim2.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_tim2.c File Reference

This file contains all the functions for the TIM2 peripheral. More...

#include "stm8s_tim2.h"

Go to the source code of this file.

Functions

static void | TI1_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI1 as Input.
static void | TI1_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI2 as Input.
static void | TI2_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI3 as Input.
static void | TI3_Config (uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter)
Configure the TI3 as Input.
void | TIM2_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM2 peripheral Preload register on ARR.
void | TIM2_CCxCmd (TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
Enables or disables the TIM2 Capture Compare Channel x.
void | TIM2_ClearFlag (TIM2_FLAG_TypeDef TIM2_FLAG)
Clears the TIM2’s pending flags.
void | TIM2_ClearITPendingBit (TIM2_IT_TypeDef TIM2_IT)
Clears the TIM2's interrupt pending bits.
void | TIM2_Cmd (FunctionalState NewState)
Enables or disables the TIM2 peripheral.
void | TIM2_DeInit (void)
Deinitializes the TIM2 peripheral registers to their default reset values.
void | TIM2_ForcedOC1Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel1 output waveform to active or inactive level.
void | TIM2_ForcedOC2Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel2 output waveform to active or inactive level.
void | TIM2_ForcedOC3Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel3 output waveform to active or inactive level.
void | TIM2_GenerateEvent (TIM2_EventSource_TypeDef TIM2_EventSource)
Configures the TIM2 event to be generated by software.
uint16_t | TIM2_GetCapture1 (void)
Gets the TIM2 Input Capture 1 value.
uint16_t | TIM2_GetCapture2 (void)
Gets the TIM2 Input Capture 2 value.
uint16_t | TIM2_GetCapture3 (void)
Gets the TIM2 Input Capture 3 value.
uint16_t | TIM2_GetCounter (void)
Gets the TIM2 Counter value.
FlagStatus | TIM2_GetFlagStatus (TIM2_FLAG_TypeDef TIM2_FLAG)
Checks whether the specified TIM2 flag is set or not.
ITStatus | TIM2_GetITStatus (TIM2_IT_TypeDef TIM2_IT)
Checks whether the TIM2 interrupt has occurred or not.
TIM2_Prescaler_TypeDef | TIM2_GetPrescaler (void)
Gets the TIM2 Prescaler value.
void | TIM2_ICInit (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Initializes the TIM2 peripheral according to the specified parameters.
void | TIM2_ITConfig (TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
Enables or disables the specified TIM2 interrupts.
void | TIM2_OC1Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel1 according to the specified parameters.
void | TIM2_OC1PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 1 polarity.
void | TIM2_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR1.
void | TIM2_OC2Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel2 according to the specified parameters.
void | TIM2_OC2PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 2 polarity.
void | TIM2_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR2.
void | TIM2_OC3Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel3 according to the specified parameters.
void | TIM2_OC3PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 3 polarity.
void | TIM2_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR3.
void | TIM2_PrescalerConfig (TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
Configures the TIM2 Prescaler.
void | TIM2_PWMIConfig (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.
void | TIM2_SelectOCxM (TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
Selects the TIM2 Output Compare Mode.
void | TIM2_SelectOnePulseMode (TIM2_OPMode_TypeDef TIM2_OPMode)
Selects the TIM2’s One Pulse Mode.
void | TIM2_SetAutoreload (uint16_t Autoreload)
Sets the TIM2 Autoreload Register value.
void | TIM2_SetCompare1 (uint16_t Compare1)
Sets the TIM2 Capture Compare1 Register value.
void | TIM2_SetCompare2 (uint16_t Compare2)
Sets the TIM2 Capture Compare2 Register value.
void | TIM2_SetCompare3 (uint16_t Compare3)
Sets the TIM2 Capture Compare3 Register value.
void | TIM2_SetCounter (uint16_t Counter)
Sets the TIM2 Counter Register value.
void | TIM2_SetIC1Prescaler (TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
Sets the TIM2 Input Capture 1 Prescaler.
void | TIM2_SetIC2Prescaler (TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
Sets the TIM2 Input Capture 2 prescaler.
void | TIM2_SetIC3Prescaler (TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
Sets the TIM2 Input Capture 3 prescaler.
void | TIM2_TimeBaseInit (TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period)
Initializes the TIM2 Time Base Unit according to the specified parameters.
void | TIM2_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM2 Update event.
void | TIM2_UpdateRequestConfig (TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
Selects the TIM2 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM2 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim2.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim2.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_tim2.h File Reference

This file contains all functions prototype and macros for the TIM2 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM2_CHANNEL_OK(CHANNEL)
#define | IS_TIM2_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
#define | IS_TIM2_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM2_FORCED_ACTION_OK(ACTION)
#define | IS_TIM2_GET_FLAG_OK(FLAG)
#define | IS_TIM2_GET_IT_OK(IT)
#define | IS_TIM2_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM2 Input Capture Filer Value.
#define | IS_TIM2_IC_POLARITY_OK(POLARITY)
#define | IS_TIM2_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM2_IC_SELECTION1_OK(SELECTION)
#define | IS_TIM2_IC_SELECTION_OK(SELECTION)
#define | IS_TIM2_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x0F))
#define | IS_TIM2_OC_MODE_OK(MODE)
#define | IS_TIM2_OC_POLARITY_OK(POLARITY)
#define | IS_TIM2_OCM_OK(MODE)
#define | IS_TIM2_OPM_MODE_OK(MODE)
#define | IS_TIM2_OUTPUT_STATE_OK(STATE)
#define | IS_TIM2_PRESCALER_OK(PRESCALER)
#define | IS_TIM2_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM2_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM2_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM2_Channel_TypeDef { TIM2_CHANNEL_1 = ((uint8_t)0x00), TIM2_CHANNEL_2 = ((uint8_t)0x01), TIM2_CHANNEL_3 = ((uint8_t)0x02) }

TIM2 Channel.

More...
enum | TIM2_EventSource_TypeDef { TIM2_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM2_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM2_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM2_EVENTSOURCE_CC3 = ((uint8_t)0x08) }

TIM2 Event Source.

More...
enum TIM2_FLAG_TypeDef {
TIM2_FLAG_UPDATE = ((uint16_t)0x0001), TIM2_FLAG_CC1 = ((uint16_t)0x0002), TIM2_FLAG_CC2 = ((uint16_t)0x0004), TIM2_FLAG_CC3 = ((uint16_t)0x0008),
TIM2_FLAG_CC1OF = ((uint16_t)0x0200), TIM2_FLAG_CC2OF = ((uint16_t)0x0400), TIM2_FLAG_CC3OF = ((uint16_t)0x0800)
}

TIM2 Flags.

More...
enum | TIM2_ForcedAction_TypeDef { TIM2_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM2_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }

TIM2 Forced Action.

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enum | TIM2_ICPolarity_TypeDef { TIM2_ICPOLARITY_RISING = ((uint8_t)0x00), TIM2_ICPOLARITY_FALLING = ((uint8_t)0x44) }

TIM2 Input Capture Polarity.

More...
enum | TIM2_ICPSC_TypeDef { TIM2_ICPSC_DIV1 = ((uint8_t)0x00), TIM2_ICPSC_DIV2 = ((uint8_t)0x04), TIM2_ICPSC_DIV4 = ((uint8_t)0x08), TIM2_ICPSC_DIV8 = ((uint8_t)0x0C) }

TIM2 Input Capture Prescaler.

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enum | TIM2_ICSelection_TypeDef { TIM2_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM2_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM2_ICSELECTION_TRGI = ((uint8_t)0x03) }

TIM2 Input Capture Selection.

More...
enum | TIM2_IT_TypeDef { TIM2_IT_UPDATE = ((uint8_t)0x01), TIM2_IT_CC1 = ((uint8_t)0x02), TIM2_IT_CC2 = ((uint8_t)0x04), TIM2_IT_CC3 = ((uint8_t)0x08) }

TIM2 interrupt sources.

More...
enum TIM2_OCMode_TypeDef {
TIM2_OCMODE_TIMING = ((uint8_t)0x00), TIM2_OCMODE_ACTIVE = ((uint8_t)0x10), TIM2_OCMODE_INACTIVE = ((uint8_t)0x20), TIM2_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM2_OCMODE_PWM1 = ((uint8_t)0x60), TIM2_OCMODE_PWM2 = ((uint8_t)0x70)
}

TIM2 Output Compare and PWM modes.

More...
enum | TIM2_OCPolarity_TypeDef { TIM2_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM2_OCPOLARITY_LOW = ((uint8_t)0x22) }

TIM2 Output Compare Polarity.

More...
enum | TIM2_OPMode_TypeDef { TIM2_OPMODE_SINGLE = ((uint8_t)0x01), TIM2_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM2 One Pulse Mode.

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enum | TIM2_OutputState_TypeDef { TIM2_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM2_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }

TIM2 Output Compare states.

More...
enum TIM2_Prescaler_TypeDef {
TIM2_PRESCALER_1 = ((uint8_t)0x00), TIM2_PRESCALER_2 = ((uint8_t)0x01), TIM2_PRESCALER_4 = ((uint8_t)0x02), TIM2_PRESCALER_8 = ((uint8_t)0x03),
TIM2_PRESCALER_16 = ((uint8_t)0x04), TIM2_PRESCALER_32 = ((uint8_t)0x05), TIM2_PRESCALER_64 = ((uint8_t)0x06), TIM2_PRESCALER_128 = ((uint8_t)0x07),
TIM2_PRESCALER_256 = ((uint8_t)0x08), TIM2_PRESCALER_512 = ((uint8_t)0x09), TIM2_PRESCALER_1024 = ((uint8_t)0x0A), TIM2_PRESCALER_2048 = ((uint8_t)0x0B),
TIM2_PRESCALER_4096 = ((uint8_t)0x0C), TIM2_PRESCALER_8192 = ((uint8_t)0x0D), TIM2_PRESCALER_16384 = ((uint8_t)0x0E), TIM2_PRESCALER_32768 = ((uint8_t)0x0F)
}

TIM2 Prescaler.

More...
enum | TIM2_PSCReloadMode_TypeDef { TIM2_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM2_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM2 Prescaler Reload Mode.

More...
enum | TIM2_UpdateSource_TypeDef { TIM2_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM2_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM2 Update Source.

More...

Functions

void | TIM2_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM2 peripheral Preload register on ARR.
void | TIM2_CCPreloadControl (FunctionalState NewState)
void | TIM2_CCxCmd (TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
Enables or disables the TIM2 Capture Compare Channel x.
void | TIM2_ClearFlag (TIM2_FLAG_TypeDef TIM2_FLAG)
Clears the TIM2’s pending flags.
void | TIM2_ClearITPendingBit (TIM2_IT_TypeDef TIM2_IT)
Clears the TIM2's interrupt pending bits.
void | TIM2_Cmd (FunctionalState NewState)
Enables or disables the TIM2 peripheral.
void | TIM2_DeInit (void)
Deinitializes the TIM2 peripheral registers to their default reset values.
void | TIM2_ForcedOC1Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel1 output waveform to active or inactive level.
void | TIM2_ForcedOC2Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel2 output waveform to active or inactive level.
void | TIM2_ForcedOC3Config (TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
Forces the TIM2 Channel3 output waveform to active or inactive level.
void | TIM2_GenerateEvent (TIM2_EventSource_TypeDef TIM2_EventSource)
Configures the TIM2 event to be generated by software.
uint16_t | TIM2_GetCapture1 (void)
Gets the TIM2 Input Capture 1 value.
uint16_t | TIM2_GetCapture2 (void)
Gets the TIM2 Input Capture 2 value.
uint16_t | TIM2_GetCapture3 (void)
Gets the TIM2 Input Capture 3 value.
uint16_t | TIM2_GetCounter (void)
Gets the TIM2 Counter value.
FlagStatus | TIM2_GetFlagStatus (TIM2_FLAG_TypeDef TIM2_FLAG)
Checks whether the specified TIM2 flag is set or not.
ITStatus | TIM2_GetITStatus (TIM2_IT_TypeDef TIM2_IT)
Checks whether the TIM2 interrupt has occurred or not.
TIM2_Prescaler_TypeDef | TIM2_GetPrescaler (void)
Gets the TIM2 Prescaler value.
void | TIM2_ICInit (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Initializes the TIM2 peripheral according to the specified parameters.
void | TIM2_InternalClockConfig (void)
void | TIM2_ITConfig (TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
Enables or disables the specified TIM2 interrupts.
void | TIM2_OC1Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel1 according to the specified parameters.
void | TIM2_OC1PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 1 polarity.
void | TIM2_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR1.
void | TIM2_OC2Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel2 according to the specified parameters.
void | TIM2_OC2PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 2 polarity.
void | TIM2_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR2.
void | TIM2_OC3Init (TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Initializes the TIM2 Channel3 according to the specified parameters.
void | TIM2_OC3PolarityConfig (TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
Configures the TIM2 Channel 3 polarity.
void | TIM2_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM2 peripheral Preload Register on CCR3.
void | TIM2_PrescalerConfig (TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
Configures the TIM2 Prescaler.
void | TIM2_PWMIConfig (TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter)
Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.
void | TIM2_SelectOCxM (TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
Selects the TIM2 Output Compare Mode.
void | TIM2_SelectOnePulseMode (TIM2_OPMode_TypeDef TIM2_OPMode)
Selects the TIM2’s One Pulse Mode.
void | TIM2_SetAutoreload (uint16_t Autoreload)
Sets the TIM2 Autoreload Register value.
void | TIM2_SetCompare1 (uint16_t Compare1)
Sets the TIM2 Capture Compare1 Register value.
void | TIM2_SetCompare2 (uint16_t Compare2)
Sets the TIM2 Capture Compare2 Register value.
void | TIM2_SetCompare3 (uint16_t Compare3)
Sets the TIM2 Capture Compare3 Register value.
void | TIM2_SetCounter (uint16_t Counter)
Sets the TIM2 Counter Register value.
void | TIM2_SetIC1Prescaler (TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
Sets the TIM2 Input Capture 1 Prescaler.
void | TIM2_SetIC2Prescaler (TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
Sets the TIM2 Input Capture 2 prescaler.
void | TIM2_SetIC3Prescaler (TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
Sets the TIM2 Input Capture 3 prescaler.
void | TIM2_TimeBaseInit (TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period)
Initializes the TIM2 Time Base Unit according to the specified parameters.
void | TIM2_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM2 Update event.
void | TIM2_UpdateRequestConfig (TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
Selects the TIM2 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM2 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim2.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim3.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_tim3.c File Reference

This file contains all the functions for the TIM3 peripheral. More...

#include "stm8s_tim3.h"

Go to the source code of this file.

Functions

static void | TI1_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI1 as Input.
static void | TI1_Config (uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI2 as Input.
static void | TI2_Config (uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter)
Configure the TI2 as Input.
void | TIM3_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM3 peripheral Preload register on ARR.
void | TIM3_CCxCmd (TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
Enables or disables the TIM3 Capture Compare Channel x.
void | TIM3_ClearFlag (TIM3_FLAG_TypeDef TIM3_FLAG)
Clears the TIM3’s pending flags.
void | TIM3_ClearITPendingBit (TIM3_IT_TypeDef TIM3_IT)
Clears the TIM3's interrupt pending bits.
void | TIM3_Cmd (FunctionalState NewState)
Enables or disables the TIM3 peripheral.
void | TIM3_DeInit (void)
Deinitializes the TIM3 peripheral registers to their default reset values.
void | TIM3_ForcedOC1Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel1 output waveform to active or inactive level.
void | TIM3_ForcedOC2Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel2 output waveform to active or inactive level.
void | TIM3_GenerateEvent (TIM3_EventSource_TypeDef TIM3_EventSource)
Configures the TIM3 event to be generated by software.
uint16_t | TIM3_GetCapture1 (void)
Gets the TIM3 Input Capture 1 value.
uint16_t | TIM3_GetCapture2 (void)
Gets the TIM3 Input Capture 2 value.
uint16_t | TIM3_GetCounter (void)
Gets the TIM3 Counter value.
FlagStatus | TIM3_GetFlagStatus (TIM3_FLAG_TypeDef TIM3_FLAG)
Checks whether the specified TIM3 flag is set or not.
ITStatus | TIM3_GetITStatus (TIM3_IT_TypeDef TIM3_IT)
Checks whether the TIM3 interrupt has occurred or not.
TIM3_Prescaler_TypeDef | TIM3_GetPrescaler (void)
Gets the TIM3 Prescaler value.
void | TIM3_ICInit (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Initializes the TIM3 peripheral according to the specified parameters.
void | TIM3_ITConfig (TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
Enables or disables the specified TIM3 interrupts.
void | TIM3_OC1Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel1 according to the specified parameters.
void | TIM3_OC1PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 1 polarity.
void | TIM3_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR1.
void | TIM3_OC2Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel2 according to the specified parameters.
void | TIM3_OC2PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 2 polarity.
void | TIM3_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR2.
void | TIM3_PrescalerConfig (TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
Configures the TIM3 Prescaler.
void | TIM3_PWMIConfig (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.
void | TIM3_SelectOCxM (TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
Selects the TIM3 Output Compare Mode.
void | TIM3_SelectOnePulseMode (TIM3_OPMode_TypeDef TIM3_OPMode)
Selects the TIM3’s One Pulse Mode.
void | TIM3_SetAutoreload (uint16_t Autoreload)
Sets the TIM3 Autoreload Register value.
void | TIM3_SetCompare1 (uint16_t Compare1)
Sets the TIM3 Capture Compare1 Register value.
void | TIM3_SetCompare2 (uint16_t Compare2)
Sets the TIM3 Capture Compare2 Register value.
void | TIM3_SetCounter (uint16_t Counter)
Sets the TIM3 Counter Register value.
void | TIM3_SetIC1Prescaler (TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
Sets the TIM3 Input Capture 1 prescaler.
void | TIM3_SetIC2Prescaler (TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
Sets the TIM3 Input Capture 2 prescaler.
void | TIM3_TimeBaseInit (TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period)
Initializes the TIM3 Time Base Unit according to the specified parameters.
void | TIM3_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM3 Update event.
void | TIM3_UpdateRequestConfig (TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
Selects the TIM3 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM3 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim3.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim3.h File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_tim3.h File Reference

This file contains all functions prototype and macros for the TIM3 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM3_CHANNEL_OK(CHANNEL)
#define | IS_TIM3_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF9F8) == 0x0000) && ((uint16_t)(FLAG)!= 0x0000))
#define | IS_TIM3_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM3_FORCED_ACTION_OK(ACTION)
#define | IS_TIM3_GET_FLAG_OK(FLAG)
#define | IS_TIM3_GET_IT_OK(IT)
#define | IS_TIM3_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM3 Input Capture Filer Value.
#define | IS_TIM3_IC_POLARITY_OK(POLARITY)
#define | IS_TIM3_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM3_IC_SELECTION_OK(SELECTION)
#define | IS_TIM3_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x07))
#define | IS_TIM3_OC_MODE_OK(MODE)
#define | IS_TIM3_OC_POLARITY_OK(POLARITY)
#define | IS_TIM3_OCM_OK(MODE)
#define | IS_TIM3_OPM_MODE_OK(MODE)
#define | IS_TIM3_OUTPUT_STATE_OK(STATE)
#define | IS_TIM3_PRESCALER_OK(PRESCALER)
#define | IS_TIM3_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM3_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM3_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM3_Channel_TypeDef { TIM3_CHANNEL_1 = ((uint8_t)0x00), TIM3_CHANNEL_2 = ((uint8_t)0x01) }

TIM3 Channel.

More...
enum | TIM3_EventSource_TypeDef { TIM3_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM3_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM3_EVENTSOURCE_CC2 = ((uint8_t)0x04) }

TIM3 Event Source.

More...
enum TIM3_FLAG_TypeDef {
TIM3_FLAG_UPDATE = ((uint16_t)0x0001), TIM3_FLAG_CC1 = ((uint16_t)0x0002), TIM3_FLAG_CC2 = ((uint16_t)0x0004), TIM3_FLAG_CC1OF = ((uint16_t)0x0200),
TIM3_FLAG_CC2OF = ((uint16_t)0x0400)
}

TIM3 Flags.

More...
enum | TIM3_ForcedAction_TypeDef { TIM3_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM3_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }

TIM3 Forced Action.

More...
enum | TIM3_ICPolarity_TypeDef { TIM3_ICPOLARITY_RISING = ((uint8_t)0x00), TIM3_ICPOLARITY_FALLING = ((uint8_t)0x44) }

TIM3 Input Capture Polarity.

More...
enum | TIM3_ICPSC_TypeDef { TIM3_ICPSC_DIV1 = ((uint8_t)0x00), TIM3_ICPSC_DIV2 = ((uint8_t)0x04), TIM3_ICPSC_DIV4 = ((uint8_t)0x08), TIM3_ICPSC_DIV8 = ((uint8_t)0x0C) }

TIM3 Input Capture Prescaler.

More...
enum | TIM3_ICSelection_TypeDef { TIM3_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM3_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM3_ICSELECTION_TRGI = ((uint8_t)0x03) }

TIM3 Input Capture Selection.

More...
enum | TIM3_IT_TypeDef { TIM3_IT_UPDATE = ((uint8_t)0x01), TIM3_IT_CC1 = ((uint8_t)0x02), TIM3_IT_CC2 = ((uint8_t)0x04) }

TIM3 interrupt sources.

More...
enum TIM3_OCMode_TypeDef {
TIM3_OCMODE_TIMING = ((uint8_t)0x00), TIM3_OCMODE_ACTIVE = ((uint8_t)0x10), TIM3_OCMODE_INACTIVE = ((uint8_t)0x20), TIM3_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM3_OCMODE_PWM1 = ((uint8_t)0x60), TIM3_OCMODE_PWM2 = ((uint8_t)0x70)
}

TIM3 Output Compare and PWM modes.

More...
enum | TIM3_OCPolarity_TypeDef { TIM3_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM3_OCPOLARITY_LOW = ((uint8_t)0x22) }

TIM3 Output Compare Polarity.

More...
enum | TIM3_OPMode_TypeDef { TIM3_OPMODE_SINGLE = ((uint8_t)0x01), TIM3_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM3 One Pulse Mode.

More...
enum | TIM3_OutputState_TypeDef { TIM3_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM3_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }

TIM3 Output Compare states.

More...
enum TIM3_Prescaler_TypeDef {
TIM3_PRESCALER_1 = ((uint8_t)0x00), TIM3_PRESCALER_2 = ((uint8_t)0x01), TIM3_PRESCALER_4 = ((uint8_t)0x02), TIM3_PRESCALER_8 = ((uint8_t)0x03),
TIM3_PRESCALER_16 = ((uint8_t)0x04), TIM3_PRESCALER_32 = ((uint8_t)0x05), TIM3_PRESCALER_64 = ((uint8_t)0x06), TIM3_PRESCALER_128 = ((uint8_t)0x07),
TIM3_PRESCALER_256 = ((uint8_t)0x08), TIM3_PRESCALER_512 = ((uint8_t)0x09), TIM3_PRESCALER_1024 = ((uint8_t)0x0A), TIM3_PRESCALER_2048 = ((uint8_t)0x0B),
TIM3_PRESCALER_4096 = ((uint8_t)0x0C), TIM3_PRESCALER_8192 = ((uint8_t)0x0D), TIM3_PRESCALER_16384 = ((uint8_t)0x0E), TIM3_PRESCALER_32768 = ((uint8_t)0x0F)
}

TIM3 Prescaler.

More...
enum | TIM3_PSCReloadMode_TypeDef { TIM3_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM3_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM3 Prescaler Reload Mode.

More...
enum | TIM3_UpdateSource_TypeDef { TIM3_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM3_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM3 Update Source.

More...

Functions

void | TIM3_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM3 peripheral Preload register on ARR.
void | TIM3_CCPreloadControl (FunctionalState NewState)
void | TIM3_CCxCmd (TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
Enables or disables the TIM3 Capture Compare Channel x.
void | TIM3_ClearFlag (TIM3_FLAG_TypeDef TIM3_FLAG)
Clears the TIM3’s pending flags.
void | TIM3_ClearITPendingBit (TIM3_IT_TypeDef TIM3_IT)
Clears the TIM3's interrupt pending bits.
void | TIM3_Cmd (FunctionalState NewState)
Enables or disables the TIM3 peripheral.
void | TIM3_DeInit (void)
Deinitializes the TIM3 peripheral registers to their default reset values.
void | TIM3_ForcedOC1Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel1 output waveform to active or inactive level.
void | TIM3_ForcedOC2Config (TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
Forces the TIM3 Channel2 output waveform to active or inactive level.
void | TIM3_GenerateEvent (TIM3_EventSource_TypeDef TIM3_EventSource)
Configures the TIM3 event to be generated by software.
uint16_t | TIM3_GetCapture1 (void)
Gets the TIM3 Input Capture 1 value.
uint16_t | TIM3_GetCapture2 (void)
Gets the TIM3 Input Capture 2 value.
uint16_t | TIM3_GetCounter (void)
Gets the TIM3 Counter value.
FlagStatus | TIM3_GetFlagStatus (TIM3_FLAG_TypeDef TIM3_FLAG)
Checks whether the specified TIM3 flag is set or not.
ITStatus | TIM3_GetITStatus (TIM3_IT_TypeDef TIM3_IT)
Checks whether the TIM3 interrupt has occurred or not.
TIM3_Prescaler_TypeDef | TIM3_GetPrescaler (void)
Gets the TIM3 Prescaler value.
void | TIM3_ICInit (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Initializes the TIM3 peripheral according to the specified parameters.
void | TIM3_InternalClockConfig (void)
void | TIM3_ITConfig (TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
Enables or disables the specified TIM3 interrupts.
void | TIM3_OC1Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel1 according to the specified parameters.
void | TIM3_OC1PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 1 polarity.
void | TIM3_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR1.
void | TIM3_OC2Init (TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Initializes the TIM3 Channel2 according to the specified parameters.
void | TIM3_OC2PolarityConfig (TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
Configures the TIM3 Channel 2 polarity.
void | TIM3_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM3 peripheral Preload Register on CCR2.
void | TIM3_PrescalerConfig (TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
Configures the TIM3 Prescaler.
void | TIM3_PWMIConfig (TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter)
Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.
void | TIM3_SelectOCxM (TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
Selects the TIM3 Output Compare Mode.
void | TIM3_SelectOnePulseMode (TIM3_OPMode_TypeDef TIM3_OPMode)
Selects the TIM3’s One Pulse Mode.
void | TIM3_SetAutoreload (uint16_t Autoreload)
Sets the TIM3 Autoreload Register value.
void | TIM3_SetCompare1 (uint16_t Compare1)
Sets the TIM3 Capture Compare1 Register value.
void | TIM3_SetCompare2 (uint16_t Compare2)
Sets the TIM3 Capture Compare2 Register value.
void | TIM3_SetCounter (uint16_t Counter)
Sets the TIM3 Counter Register value.
void | TIM3_SetIC1Prescaler (TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
Sets the TIM3 Input Capture 1 prescaler.
void | TIM3_SetIC2Prescaler (TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
Sets the TIM3 Input Capture 2 prescaler.
void | TIM3_TimeBaseInit (TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period)
Initializes the TIM3 Time Base Unit according to the specified parameters.
void | TIM3_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM3 Update event.
void | TIM3_UpdateRequestConfig (TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
Selects the TIM3 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM3 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim3.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim4.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_tim4.c File Reference

This file contains all the functions for the TIM4 peripheral. More...

#include "stm8s_tim4.h"

Go to the source code of this file.

Functions

void | TIM4_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM4 peripheral Preload register on ARR.
void | TIM4_ClearFlag (TIM4_FLAG_TypeDef TIM4_FLAG)
Clears the TIM4’s pending flags.
void | TIM4_ClearITPendingBit (TIM4_IT_TypeDef TIM4_IT)
Clears the TIM4's interrupt pending bits.
void | TIM4_Cmd (FunctionalState NewState)
Enables or disables the TIM4 peripheral.
void | TIM4_DeInit (void)
Deinitializes the TIM4 peripheral registers to their default reset values.
void | TIM4_GenerateEvent (TIM4_EventSource_TypeDef TIM4_EventSource)
Configures the TIM4 event to be generated by software.
uint8_t | TIM4_GetCounter (void)
Gets the TIM4 Counter value.
FlagStatus | TIM4_GetFlagStatus (TIM4_FLAG_TypeDef TIM4_FLAG)
Checks whether the specified TIM4 flag is set or not.
ITStatus | TIM4_GetITStatus (TIM4_IT_TypeDef TIM4_IT)
Checks whether the TIM4 interrupt has occurred or not.
TIM4_Prescaler_TypeDef | TIM4_GetPrescaler (void)
Gets the TIM4 Prescaler value.
void | TIM4_ITConfig (TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
Enables or disables the specified TIM4 interrupts.
void | TIM4_PrescalerConfig (TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
Configures the TIM4 Prescaler.
void | TIM4_SelectOnePulseMode (TIM4_OPMode_TypeDef TIM4_OPMode)
Selects the TIM4’s One Pulse Mode.
void | TIM4_SetAutoreload (uint8_t Autoreload)
Sets the TIM4 Autoreload Register value.
void | TIM4_SetCounter (uint8_t Counter)
Sets the TIM4 Counter Register value.
void | TIM4_TimeBaseInit (TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)
Initializes the TIM4 Time Base Unit according to the specified parameters.
void | TIM4_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM4 Update event.
void | TIM4_UpdateRequestConfig (TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
Selects the TIM4 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM4 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim4.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim4.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_tim4.h File Reference

This file contains all functions prototype and macros for the TIM4 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM4_EVENT_SOURCE_OK(SOURCE) (((SOURCE) == 0x01))
#define | IS_TIM4_GET_FLAG_OK(FLAG) ((FLAG) == TIM4_FLAG_UPDATE)
#define | IS_TIM4_IT_OK(IT) ((IT) == TIM4_IT_UPDATE)
#define | IS_TIM4_OPM_MODE_OK(MODE)
#define | IS_TIM4_PRESCALER_OK(PRESCALER)
#define | IS_TIM4_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM4_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM4_EventSource_TypeDef { TIM4_EVENTSOURCE_UPDATE = ((uint8_t)0x01) }

TIM4 Event Source.

More...
enum | TIM4_FLAG_TypeDef { TIM4_FLAG_UPDATE = ((uint8_t)0x01) }

TIM4 Flags.

More...
enum | TIM4_IT_TypeDef { TIM4_IT_UPDATE = ((uint8_t)0x01) }

TIM4 interrupt sources.

More...
enum | TIM4_OPMode_TypeDef { TIM4_OPMODE_SINGLE = ((uint8_t)0x01), TIM4_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM4 One Pulse Mode.

More...
enum TIM4_Prescaler_TypeDef {
TIM4_PRESCALER_1 = ((uint8_t)0x00), TIM4_PRESCALER_2 = ((uint8_t)0x01), TIM4_PRESCALER_4 = ((uint8_t)0x02), TIM4_PRESCALER_8 = ((uint8_t)0x03),
TIM4_PRESCALER_16 = ((uint8_t)0x04), TIM4_PRESCALER_32 = ((uint8_t)0x05), TIM4_PRESCALER_64 = ((uint8_t)0x06), TIM4_PRESCALER_128 = ((uint8_t)0x07)
}

TIM4 Prescaler.

More...
enum | TIM4_PSCReloadMode_TypeDef { TIM4_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM4_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM4 Prescaler Reload Mode.

More...
enum | TIM4_UpdateSource_TypeDef { TIM4_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM4_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM4 Update Source.

More...

Functions

void | TIM4_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM4 peripheral Preload register on ARR.
void | TIM4_ClearFlag (TIM4_FLAG_TypeDef TIM4_FLAG)
Clears the TIM4’s pending flags.
void | TIM4_ClearITPendingBit (TIM4_IT_TypeDef TIM4_IT)
Clears the TIM4's interrupt pending bits.
void | TIM4_Cmd (FunctionalState NewState)
Enables or disables the TIM4 peripheral.
void | TIM4_DeInit (void)
Deinitializes the TIM4 peripheral registers to their default reset values.
void | TIM4_GenerateEvent (TIM4_EventSource_TypeDef TIM4_EventSource)
Configures the TIM4 event to be generated by software.
uint8_t | TIM4_GetCounter (void)
Gets the TIM4 Counter value.
FlagStatus | TIM4_GetFlagStatus (TIM4_FLAG_TypeDef TIM4_FLAG)
Checks whether the specified TIM4 flag is set or not.
ITStatus | TIM4_GetITStatus (TIM4_IT_TypeDef TIM4_IT)
Checks whether the TIM4 interrupt has occurred or not.
TIM4_Prescaler_TypeDef | TIM4_GetPrescaler (void)
Gets the TIM4 Prescaler value.
void | TIM4_ITConfig (TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
Enables or disables the specified TIM4 interrupts.
void | TIM4_PrescalerConfig (TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
Configures the TIM4 Prescaler.
void | TIM4_SelectOnePulseMode (TIM4_OPMode_TypeDef TIM4_OPMode)
Selects the TIM4’s One Pulse Mode.
void | TIM4_SetAutoreload (uint8_t Autoreload)
Sets the TIM4 Autoreload Register value.
void | TIM4_SetCounter (uint8_t Counter)
Sets the TIM4 Counter Register value.
void | TIM4_TimeBaseInit (TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)
Initializes the TIM4 Time Base Unit according to the specified parameters.
void | TIM4_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM4 Update event.
void | TIM4_UpdateRequestConfig (TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
Selects the TIM4 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM4 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim4.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim5.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_tim5.c File Reference

This file contains all the functions for the TIM5 peripheral. More...

#include "stm8s_tim5.h"

Go to the source code of this file.

Functions

static void | TI1_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI1 as Input.
static void | TI1_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI2 as Input.
static void | TI2_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
Configure the TI3 as Input.
static void | TI3_Config (uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter)
Configure the TI3 as Input.
void | TIM5_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM5 peripheral Preload register on ARR.
void | TIM5_CCxCmd (TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)
Enables or disables the TIM5 Capture Compare Channel x.
void | TIM5_ClearFlag (TIM5_FLAG_TypeDef TIM5_FLAG)
Clears the TIM5’s pending flags.
void | TIM5_ClearITPendingBit (TIM5_IT_TypeDef TIM5_IT)
Clears the TIM5's interrupt pending bits.
void | TIM5_Cmd (FunctionalState NewState)
Enables or disables the TIM5 peripheral.
void | TIM5_DeInit (void)
Deinitializes the TIM5 peripheral registers to their default reset values.
void | TIM5_EncoderInterfaceConfig (TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
Configures the TIM5 Encoder Interface.
void | TIM5_ForcedOC1Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel1 output waveform to active or inactive level.
void | TIM5_ForcedOC2Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel2 output waveform to active or inactive level.
void | TIM5_ForcedOC3Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel3 output waveform to active or inactive level.
void | TIM5_GenerateEvent (TIM5_EventSource_TypeDef TIM5_EventSource)
Configures the TIM5 event to be generated by software.
uint16_t | TIM5_GetCapture1 (void)
Gets the TIM5 Input Capture 1 value.
uint16_t | TIM5_GetCapture2 (void)
Gets the TIM5 Input Capture 2 value.
uint16_t | TIM5_GetCapture3 (void)
Gets the TIM5 Input Capture 3 value.
uint16_t | TIM5_GetCounter (void)
Gets the TIM5 Counter value.
FlagStatus | TIM5_GetFlagStatus (TIM5_FLAG_TypeDef TIM5_FLAG)
Checks whether the specified TIM5 flag is set or not.
ITStatus | TIM5_GetITStatus (TIM5_IT_TypeDef TIM5_IT)
Checks whether the TIM5 interrupt has occurred or not.
TIM5_Prescaler_TypeDef | TIM5_GetPrescaler (void)
Gets the TIM5 Prescaler value.
void | TIM5_ICInit (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Initializes the TIM5 peripheral according to the specified parameters.
void | TIM5_InternalClockConfig (void)
Enables the TIM5 internal Clock.
void | TIM5_ITConfig (TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
Enables or disables the specified TIM5 interrupts.
void | TIM5_OC1Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel1 according to the specified parameters.
void | TIM5_OC1PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 1 polarity.
void | TIM5_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR1.
void | TIM5_OC2Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel2 according to the specified parameters.
void | TIM5_OC2PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 2 polarity.
void | TIM5_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR2.
void | TIM5_OC3Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel3 according to the specified parameters.
void | TIM5_OC3PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 3 polarity.
void | TIM5_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR3.
void | TIM5_PrescalerConfig (TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
Configures the TIM5 Prescaler.
void | TIM5_PWMIConfig (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.
void | TIM5_SelectInputTrigger (TIM5_TS_TypeDef TIM5_InputTriggerSource)
Selects the TIM5 Input Trigger source.
void | TIM5_SelectOCxM (TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)
Selects the TIM5 Output Compare Mode.
void | TIM5_SelectOnePulseMode (TIM5_OPMode_TypeDef TIM5_OPMode)
Selects the TIM5’s One Pulse Mode.
void | TIM5_SelectOutputTrigger (TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
Selects the TIM5 Trigger Output Mode.
void | TIM5_SelectSlaveMode (TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
Selects the TIM5 Slave Mode.
void | TIM5_SetAutoreload (uint16_t Autoreload)
Sets the TIM5 Autoreload Register value.
void | TIM5_SetCompare1 (uint16_t Compare1)
Sets the TIM5 Capture Compare1 Register value.
void | TIM5_SetCompare2 (uint16_t Compare2)
Sets the TIM5 Capture Compare2 Register value.
void | TIM5_SetCompare3 (uint16_t Compare3)
Sets the TIM5 Capture Compare3 Register value.
void | TIM5_SetCounter (uint16_t Counter)
Sets the TIM5 Counter Register value.
void | TIM5_SetIC1Prescaler (TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
Sets the TIM5 Input Capture 1 prescaler.
void | TIM5_SetIC2Prescaler (TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
Sets the TIM5 Input Capture 2 prescaler.
void | TIM5_SetIC3Prescaler (TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)
Sets the TIM5 Input Capture 3 prescaler.
void | TIM5_TimeBaseInit (TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period)
Initializes the TIM5 Time Base Unit according to the specified parameters.
void | TIM5_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM5 Update event.
void | TIM5_UpdateRequestConfig (TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
Selects the TIM5 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM5 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim5.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim5.h File Reference

  • File List
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  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_tim5.h File Reference

This file contains all functions prototype and macros for the TIM5 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM5_CHANNEL_OK(CHANNEL)
#define | IS_TIM5_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
#define | IS_TIM5_ENCODER_MODE_OK(MODE)
Macro TIM5 encoder mode.
#define | IS_TIM5_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
#define | IS_TIM5_EXT_FILTER_OK(EXTFILTER) ((EXTFILTER) <= 0x0F)
Macro TIM5 External Trigger Filter.
#define | IS_TIM5_EXT_POLARITY_OK(POLARITY)
Macro TIM5 Trigger Polarity.
#define | IS_TIM5_EXT_PRESCALER_OK(PRESCALER)
Macro TIM5 external trigger prescaler.
#define | IS_TIM5_FORCED_ACTION_OK(ACTION)
#define | IS_TIM5_GET_FLAG_OK(FLAG)
#define | IS_TIM5_GET_IT_OK(IT)
#define | IS_TIM5_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
TIM5 Input Capture Filer Value.
#define | IS_TIM5_IC_POLARITY_OK(POLARITY)
#define | IS_TIM5_IC_PRESCALER_OK(PRESCALER)
#define | IS_TIM5_IC_SELECTION1_OK(SELECTION)
#define | IS_TIM5_IC_SELECTION_OK(SELECTION)
#define | IS_TIM5_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x4F))
#define | IS_TIM5_OC_MODE_OK(MODE)
#define | IS_TIM5_OC_POLARITY_OK(POLARITY)
#define | IS_TIM5_OCM_OK(MODE)
#define | IS_TIM5_OPM_MODE_OK(MODE)
#define | IS_TIM5_OUTPUT_STATE_OK(STATE)
#define | IS_TIM5_PRESCALER_OK(PRESCALER)
#define | IS_TIM5_PRESCALER_RELOAD_OK(RELOAD)
#define | IS_TIM5_PWMI_CHANNEL_OK(CHANNEL)
#define | IS_TIM5_SLAVE_MODE_OK(MODE)
Macro TIM5 Slave mode.
#define | IS_TIM5_TIX_TRIGGER_SELECTION_OK(SELECTION)
#define | IS_TIM5_TRGO_SOURCE_OK(SOURCE)
Macro TIM5 TRGO source.
#define | IS_TIM5_TRIGGER_SELECTION_OK(SELECTION)
Macro TIM5 Trigger Selection.
#define | IS_TIM5_UPDATE_SOURCE_OK(SOURCE)

Enumerations

enum | TIM5_Channel_TypeDef { TIM5_CHANNEL_1 = ((uint8_t)0x00), TIM5_CHANNEL_2 = ((uint8_t)0x01), TIM5_CHANNEL_3 = ((uint8_t)0x02) }

TIM5 Channel.

More...
enum | TIM5_EncoderMode_TypeDef { TIM5_ENCODERMODE_TI1 = ((uint8_t)0x01), TIM5_ENCODERMODE_TI2 = ((uint8_t)0x02), TIM5_ENCODERMODE_TI12 = ((uint8_t)0x03) }

TIM5 Encoder Mode.

More...
enum TIM5_EventSource_TypeDef {
TIM5_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM5_EVENTSOURCE_CC1 = ((uint8_t)0x02), TIM5_EVENTSOURCE_CC2 = ((uint8_t)0x04), TIM5_EVENTSOURCE_CC3 = ((uint8_t)0x08),
TIM5_EVENTSOURCE_TRIGGER = ((uint8_t)0x40)
}

TIM5 Event Source.

More...
enum | TIM5_ExtTRGPolarity_TypeDef { TIM5_EXTTRGPOLARITY_INVERTED = ((uint8_t)0x80), TIM5_EXTTRGPOLARITY_NONINVERTED = ((uint8_t)0x00) }

TIM5 External Trigger Polarity.

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enum | TIM5_ExtTRGPSC_TypeDef { TIM5_EXTTRGPSC_OFF = ((uint8_t)0x00), TIM5_EXTTRGPSC_DIV2 = ((uint8_t)0x10), TIM5_EXTTRGPSC_DIV4 = ((uint8_t)0x20), TIM5_EXTTRGPSC_DIV8 = ((uint8_t)0x30) }

TIM5 External Trigger Prescaler.

More...
enum TIM5_FLAG_TypeDef {
TIM5_FLAG_UPDATE = ((uint16_t)0x0001), TIM5_FLAG_CC1 = ((uint16_t)0x0002), TIM5_FLAG_CC2 = ((uint16_t)0x0004), TIM5_FLAG_CC3 = ((uint16_t)0x0008),
TIM5_FLAG_TRIGGER = ((uint16_t)0x0040), TIM5_FLAG_CC1OF = ((uint16_t)0x0200), TIM5_FLAG_CC2OF = ((uint16_t)0x0400), TIM5_FLAG_CC3OF = ((uint16_t)0x0800)
}

TIM5 Flags.

More...
enum | TIM5_ForcedAction_TypeDef { TIM5_FORCEDACTION_ACTIVE = ((uint8_t)0x50), TIM5_FORCEDACTION_INACTIVE = ((uint8_t)0x40) }

TIM5 Forced Action.

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enum | TIM5_ICPolarity_TypeDef { TIM5_ICPOLARITY_RISING = ((uint8_t)0x00), TIM5_ICPOLARITY_FALLING = ((uint8_t)0x44) }

TIM5 Input Capture Polarity.

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enum | TIM5_ICPSC_TypeDef { TIM5_ICPSC_DIV1 = ((uint8_t)0x00), TIM5_ICPSC_DIV2 = ((uint8_t)0x04), TIM5_ICPSC_DIV4 = ((uint8_t)0x08), TIM5_ICPSC_DIV8 = ((uint8_t)0x0C) }

TIM5 Input Capture Prescaler.

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enum | TIM5_ICSelection_TypeDef { TIM5_ICSELECTION_DIRECTTI = ((uint8_t)0x01), TIM5_ICSELECTION_INDIRECTTI = ((uint8_t)0x02), TIM5_ICSELECTION_TRGI = ((uint8_t)0x03) }

TIM5 Input Capture Selection.

More...
enum TIM5_IT_TypeDef {
TIM5_IT_UPDATE = ((uint8_t)0x01), TIM5_IT_CC1 = ((uint8_t)0x02), TIM5_IT_CC2 = ((uint8_t)0x04), TIM5_IT_CC3 = ((uint8_t)0x08),
TIM5_IT_TRIGGER = ((uint8_t)0x40)
}

TIM5 interrupt sources.

More...
enum TIM5_OCMode_TypeDef {
TIM5_OCMODE_TIMING = ((uint8_t)0x00), TIM5_OCMODE_ACTIVE = ((uint8_t)0x10), TIM5_OCMODE_INACTIVE = ((uint8_t)0x20), TIM5_OCMODE_TOGGLE = ((uint8_t)0x30),
TIM5_OCMODE_PWM1 = ((uint8_t)0x60), TIM5_OCMODE_PWM2 = ((uint8_t)0x70)
}

TIM5 Output Compare and PWM modes.

More...
enum | TIM5_OCPolarity_TypeDef { TIM5_OCPOLARITY_HIGH = ((uint8_t)0x00), TIM5_OCPOLARITY_LOW = ((uint8_t)0x22) }

TIM5 Output Compare Polarity.

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enum | TIM5_OPMode_TypeDef { TIM5_OPMODE_SINGLE = ((uint8_t)0x01), TIM5_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM5 One Pulse Mode.

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enum | TIM5_OutputState_TypeDef { TIM5_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), TIM5_OUTPUTSTATE_ENABLE = ((uint8_t)0x11) }

TIM5 Output Compare states.

More...
enum TIM5_Prescaler_TypeDef {
TIM5_PRESCALER_1 = ((uint8_t)0x00), TIM5_PRESCALER_2 = ((uint8_t)0x01), TIM5_PRESCALER_4 = ((uint8_t)0x02), TIM5_PRESCALER_8 = ((uint8_t)0x03),
TIM5_PRESCALER_16 = ((uint8_t)0x04), TIM5_PRESCALER_32 = ((uint8_t)0x05), TIM5_PRESCALER_64 = ((uint8_t)0x06), TIM5_PRESCALER_128 = ((uint8_t)0x07),
TIM5_PRESCALER_256 = ((uint8_t)0x08), TIM5_PRESCALER_512 = ((uint8_t)0x09), TIM5_PRESCALER_1024 = ((uint8_t)0x0A), TIM5_PRESCALER_2048 = ((uint8_t)0x0B),
TIM5_PRESCALER_4096 = ((uint8_t)0x0C), TIM5_PRESCALER_8192 = ((uint8_t)0x0D), TIM5_PRESCALER_16384 = ((uint8_t)0x0E), TIM5_PRESCALER_32768 = ((uint8_t)0x0F)
}

TIM5 Prescaler.

More...
enum | TIM5_PSCReloadMode_TypeDef { TIM5_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM5_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM5 Prescaler Reload Mode.

More...
enum | TIM5_SlaveMode_TypeDef { TIM5_SLAVEMODE_RESET = ((uint8_t)0x04), TIM5_SLAVEMODE_GATED = ((uint8_t)0x05), TIM5_SLAVEMODE_TRIGGER = ((uint8_t)0x06), TIM5_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07) }

TIM5 Slave Mode.

More...
enum TIM5_TRGOSource_TypeDef {
TIM5_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM5_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM5_TRGOSOURCE_UPDATE = ((uint8_t)0x20), TIM5_TRGOSOURCE_OC1 = ((uint8_t)0x30),
TIM5_TRGOSOURCE_OC1REF = ((uint8_t)0x40), TIM5_TRGOSOURCE_OC2REF = ((uint8_t)0x50)
}

TIM5 Trigger Output Source.

More...
enum | TIM5_TS_TypeDef { TIM5_TS_TIM6 = ((uint8_t)0x00), TIM5_TS_TIM1 = ((uint8_t)0x03) }

TIM5 Internal Trigger Selection.

More...
enum | TIM5_UpdateSource_TypeDef { TIM5_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM5_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM5 Update Source.

More...

Functions

void | TIM5_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM5 peripheral Preload register on ARR.
void | TIM5_CCPreloadControl (FunctionalState NewState)
void | TIM5_CCxCmd (TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)
Enables or disables the TIM5 Capture Compare Channel x.
void | TIM5_ClearFlag (TIM5_FLAG_TypeDef TIM5_FLAG)
Clears the TIM5’s pending flags.
void | TIM5_ClearITPendingBit (TIM5_IT_TypeDef TIM5_IT)
Clears the TIM5's interrupt pending bits.
void | TIM5_Cmd (FunctionalState NewState)
Enables or disables the TIM5 peripheral.
void | TIM5_DeInit (void)
Deinitializes the TIM5 peripheral registers to their default reset values.
void | TIM5_EncoderInterfaceConfig (TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
Configures the TIM5 Encoder Interface.
void | TIM5_ForcedOC1Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel1 output waveform to active or inactive level.
void | TIM5_ForcedOC2Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel2 output waveform to active or inactive level.
void | TIM5_ForcedOC3Config (TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
Forces the TIM5 Channel3 output waveform to active or inactive level.
void | TIM5_GenerateEvent (TIM5_EventSource_TypeDef TIM5_EventSource)
Configures the TIM5 event to be generated by software.
uint16_t | TIM5_GetCapture1 (void)
Gets the TIM5 Input Capture 1 value.
uint16_t | TIM5_GetCapture2 (void)
Gets the TIM5 Input Capture 2 value.
uint16_t | TIM5_GetCapture3 (void)
Gets the TIM5 Input Capture 3 value.
uint16_t | TIM5_GetCounter (void)
Gets the TIM5 Counter value.
FlagStatus | TIM5_GetFlagStatus (TIM5_FLAG_TypeDef TIM5_FLAG)
Checks whether the specified TIM5 flag is set or not.
ITStatus | TIM5_GetITStatus (TIM5_IT_TypeDef TIM5_IT)
Checks whether the TIM5 interrupt has occurred or not.
TIM5_Prescaler_TypeDef | TIM5_GetPrescaler (void)
Gets the TIM5 Prescaler value.
void | TIM5_ICInit (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Initializes the TIM5 peripheral according to the specified parameters.
void | TIM5_InternalClockConfig (void)
Enables the TIM5 internal Clock.
void | TIM5_ITConfig (TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
Enables or disables the specified TIM5 interrupts.
void | TIM5_OC1Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel1 according to the specified parameters.
void | TIM5_OC1PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 1 polarity.
void | TIM5_OC1PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR1.
void | TIM5_OC2Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel2 according to the specified parameters.
void | TIM5_OC2PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 2 polarity.
void | TIM5_OC2PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR2.
void | TIM5_OC3Init (TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState, uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Initializes the TIM5 Channel3 according to the specified parameters.
void | TIM5_OC3PolarityConfig (TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
Configures the TIM5 Channel 3 polarity.
void | TIM5_OC3PreloadConfig (FunctionalState NewState)
Enables or disables the TIM5 peripheral Preload Register on CCR3.
void | TIM5_PrescalerConfig (TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
Configures the TIM5 Prescaler.
void | TIM5_PWMIConfig (TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter)
Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.
void | TIM5_SelectInputTrigger (TIM5_TS_TypeDef TIM5_InputTriggerSource)
Selects the TIM5 Input Trigger source.
void | TIM5_SelectOCxM (TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)
Selects the TIM5 Output Compare Mode.
void | TIM5_SelectOnePulseMode (TIM5_OPMode_TypeDef TIM5_OPMode)
Selects the TIM5’s One Pulse Mode.
void | TIM5_SelectOutputTrigger (TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
Selects the TIM5 Trigger Output Mode.
void | TIM5_SelectSlaveMode (TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
Selects the TIM5 Slave Mode.
void | TIM5_SetAutoreload (uint16_t Autoreload)
Sets the TIM5 Autoreload Register value.
void | TIM5_SetCompare1 (uint16_t Compare1)
Sets the TIM5 Capture Compare1 Register value.
void | TIM5_SetCompare2 (uint16_t Compare2)
Sets the TIM5 Capture Compare2 Register value.
void | TIM5_SetCompare3 (uint16_t Compare3)
Sets the TIM5 Capture Compare3 Register value.
void | TIM5_SetCounter (uint16_t Counter)
Sets the TIM5 Counter Register value.
void | TIM5_SetIC1Prescaler (TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
Sets the TIM5 Input Capture 1 prescaler.
void | TIM5_SetIC2Prescaler (TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
Sets the TIM5 Input Capture 2 prescaler.
void | TIM5_SetIC3Prescaler (TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)
Sets the TIM5 Input Capture 3 prescaler.
void | TIM5_TimeBaseInit (TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period)
Initializes the TIM5 Time Base Unit according to the specified parameters.
void | TIM5_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM5 Update event.
void | TIM5_UpdateRequestConfig (TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
Selects the TIM5 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM5 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim5.h.


STM8S/A Standard Peripherals Drivers: stm8s_tim6.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_tim6.c File Reference

This file contains all the functions for the TIM6 peripheral. More...

#include "stm8s_tim6.h"

Go to the source code of this file.

Functions

void | TIM6_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM6 peripheral Preload register on ARR.
void | TIM6_ClearFlag (TIM6_FLAG_TypeDef TIM6_FLAG)
Clears the TIM’s pending flags.
void | TIM6_ClearITPendingBit (TIM6_IT_TypeDef TIM6_IT)
Clears the TIM6's interrupt pending bits.
void | TIM6_Cmd (FunctionalState NewState)
Enables or disables the TIM6 peripheral.
void | TIM6_DeInit (void)
Deinitializes the TIM6 peripheral registers to their default reset values.
void | TIM6_GenerateEvent (TIM6_EventSource_TypeDef TIM6_EventSource)
Configures the TIM6 event to be generated by software.
uint8_t | TIM6_GetCounter (void)
Gets the TIM6 Counter value.
FlagStatus | TIM6_GetFlagStatus (TIM6_FLAG_TypeDef TIM6_FLAG)
Checks whether the specified TIM6 flag is set or not.
ITStatus | TIM6_GetITStatus (TIM6_IT_TypeDef TIM6_IT)
Checks whether the TIM6 interrupt has occurred or not.
TIM6_Prescaler_TypeDef | TIM6_GetPrescaler (void)
Gets the TIM6 Prescaler value.
void | TIM6_InternalClockConfig (void)
Enables the TIM6 internal Clock.
void | TIM6_ITConfig (TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)
Enables or disables the specified TIM6 interrupts.
void | TIM6_PrescalerConfig (TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)
Configures the TIM6 Prescaler.
void | TIM6_SelectInputTrigger (TIM6_TS_TypeDef TIM6_InputTriggerSource)
Selects the TIM6 Input Trigger source.
void | TIM6_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM6 Master/Slave Mode.
void | TIM6_SelectOnePulseMode (TIM6_OPMode_TypeDef TIM6_OPMode)
Selects the TIM6’s One Pulse Mode.
void | TIM6_SelectOutputTrigger (TIM6_TRGOSource_TypeDef TIM6_TRGOSource)
Selects the TIM6 Trigger Output Mode.
void | TIM6_SelectSlaveMode (TIM6_SlaveMode_TypeDef TIM6_SlaveMode)
Selects the TIM6 Slave Mode.
void | TIM6_SetAutoreload (uint8_t Autoreload)
Sets the TIM6 Autoreload Register value.
void | TIM6_SetCounter (uint8_t Counter)
Sets the TIM6 Counter Register value.
void | TIM6_TimeBaseInit (TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period)
Initializes the TIM6 Time Base Unit according to the specified parameters.
void | TIM6_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM6 Update event.
void | TIM6_UpdateRequestConfig (TIM6_UpdateSource_TypeDef TIM6_UpdateSource)
Selects the TIM6 Update Request Interrupt source.

Detailed Description

This file contains all the functions for the TIM6 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim6.c.


STM8S/A Standard Peripherals Drivers: stm8s_tim6.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_tim6.h File Reference

This file contains all functions prototype and macros for the TIM6 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_TIM6_CLEAR_FLAG_OK(FLAG) ((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))
#define | IS_TIM6_EVENT_SOURCE_OK(SOURCE)
Macro TIM6 Event source.
#define | IS_TIM6_GET_FLAG_OK(FLAG)
Macro TIM6 Flags.
#define | IS_TIM6_GET_IT_OK(IT)
#define | IS_TIM6_IT_OK(IT)
Macro TIM6 interrupts.
#define | IS_TIM6_OPM_MODE_OK(MODE)
Macro TIM6 One Pulse Mode.
#define | IS_TIM6_PRESCALER_OK(PRESCALER)
Macro used by the assert function to check the different functions parameters.
#define | IS_TIM6_PRESCALER_RELOAD_OK(RELOAD)
Macro TIM6 Prescaler reload.
#define | IS_TIM6_SLAVE_MODE_OK(MODE)
Macro TIM6 Slave mode.
#define | IS_TIM6_TRGO_SOURCE_OK(SOURCE)
Macro TIM6 TRGO source.
#define | IS_TIM6_TRIGGER_SELECTION_OK(SELECTION)
Macro TIM6 Trigger selection.
#define | IS_TIM6_UPDATE_SOURCE_OK(SOURCE)
Macro TIM6 Update source.

Enumerations

enum | TIM6_EventSource_TypeDef { TIM6_EVENTSOURCE_UPDATE = ((uint8_t)0x01), TIM6_EVENTSOURCE_TRIGGER = ((uint8_t)0x40) }

TIM6 Event Source.

More...
enum | TIM6_FLAG_TypeDef { TIM6_FLAG_UPDATE = ((uint8_t)0x01), TIM6_FLAG_TRIGGER = ((uint8_t)0x40) }

TIM6 Flags.

More...
enum | TIM6_IT_TypeDef { TIM6_IT_UPDATE = ((uint8_t)0x01), TIM6_IT_TRIGGER = ((uint8_t)0x40) }

TIM6 interrupt sources.

More...
enum | TIM6_OPMode_TypeDef { TIM6_OPMODE_SINGLE = ((uint8_t)0x01), TIM6_OPMODE_REPETITIVE = ((uint8_t)0x00) }

TIM6 One Pulse Mode.

More...
enum TIM6_Prescaler_TypeDef {
TIM6_PRESCALER_1 = ((uint8_t)0x00), TIM6_PRESCALER_2 = ((uint8_t)0x01), TIM6_PRESCALER_4 = ((uint8_t)0x02), TIM6_PRESCALER_8 = ((uint8_t)0x03),
TIM6_PRESCALER_16 = ((uint8_t)0x04), TIM6_PRESCALER_32 = ((uint8_t)0x05), TIM6_PRESCALER_64 = ((uint8_t)0x06), TIM6_PRESCALER_128 = ((uint8_t)0x07)
}

TIM6 Prescaler.

More...
enum | TIM6_PSCReloadMode_TypeDef { TIM6_PSCRELOADMODE_UPDATE = ((uint8_t)0x00), TIM6_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01) }

TIM6 Prescaler Reload Mode.

More...
enum TIM6_SlaveMode_TypeDef {
TIM6_SLAVEMODE_DISABLE = ((uint8_t)0x00), TIM6_SLAVEMODE_RESET = ((uint8_t)0x04), TIM6_SLAVEMODE_GATED = ((uint8_t)0x05), TIM6_SLAVEMODE_TRIGGER = ((uint8_t)0x06),
TIM6_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07)
}

TIM6 Slave Mode.

More...
enum | TIM6_TRGOSource_TypeDef { TIM6_TRGOSOURCE_RESET = ((uint8_t)0x00), TIM6_TRGOSOURCE_ENABLE = ((uint8_t)0x10), TIM6_TRGOSOURCE_UPDATE = ((uint8_t)0x20) }

TIM6 Trigger Output Source.

More...
enum | TIM6_TS_TypeDef { TIM6_TS_TIM1 = ((uint8_t)0x20), TIM6_TS_TIM5 = ((uint8_t)0x30) }

TIM6 Internal Trigger Selection.

More...
enum | TIM6_UpdateSource_TypeDef { TIM6_UPDATESOURCE_GLOBAL = ((uint8_t)0x00), TIM6_UPDATESOURCE_REGULAR = ((uint8_t)0x01) }

TIM6 Update Source.

More...

Functions

void | TIM6_ARRPreloadConfig (FunctionalState NewState)
Enables or disables TIM6 peripheral Preload register on ARR.
void | TIM6_ClearFlag (TIM6_FLAG_TypeDef TIM6_FLAG)
Clears the TIM’s pending flags.
void | TIM6_ClearITPendingBit (TIM6_IT_TypeDef TIM6_IT)
Clears the TIM6's interrupt pending bits.
void | TIM6_Cmd (FunctionalState NewState)
Enables or disables the TIM6 peripheral.
void | TIM6_DeInit (void)
Deinitializes the TIM6 peripheral registers to their default reset values.
void | TIM6_GenerateEvent (TIM6_EventSource_TypeDef TIM6_EventSource)
Configures the TIM6 event to be generated by software.
uint8_t | TIM6_GetCounter (void)
Gets the TIM6 Counter value.
FlagStatus | TIM6_GetFlagStatus (TIM6_FLAG_TypeDef TIM6_FLAG)
Checks whether the specified TIM6 flag is set or not.
ITStatus | TIM6_GetITStatus (TIM6_IT_TypeDef TIM6_IT)
Checks whether the TIM6 interrupt has occurred or not.
TIM6_Prescaler_TypeDef | TIM6_GetPrescaler (void)
Gets the TIM6 Prescaler value.
void | TIM6_InternalClockConfig (void)
Enables the TIM6 internal Clock.
void | TIM6_ITConfig (TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)
Enables or disables the specified TIM6 interrupts.
void | TIM6_PrescalerConfig (TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)
Configures the TIM6 Prescaler.
void | TIM6_SelectInputTrigger (TIM6_TS_TypeDef TIM6_InputTriggerSource)
Selects the TIM6 Input Trigger source.
void | TIM6_SelectMasterSlaveMode (FunctionalState NewState)
Sets or Resets the TIM6 Master/Slave Mode.
void | TIM6_SelectOnePulseMode (TIM6_OPMode_TypeDef TIM6_OPMode)
Selects the TIM6’s One Pulse Mode.
void | TIM6_SelectOutputTrigger (TIM6_TRGOSource_TypeDef TIM6_TRGOSource)
Selects the TIM6 Trigger Output Mode.
void | TIM6_SelectSlaveMode (TIM6_SlaveMode_TypeDef TIM6_SlaveMode)
Selects the TIM6 Slave Mode.
void | TIM6_SetAutoreload (uint8_t Autoreload)
Sets the TIM6 Autoreload Register value.
void | TIM6_SetCounter (uint8_t Counter)
Sets the TIM6 Counter Register value.
void | TIM6_TimeBaseInit (TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period)
Initializes the TIM6 Time Base Unit according to the specified parameters.
void | TIM6_UpdateDisableConfig (FunctionalState NewState)
Enables or Disables the TIM6 Update event.
void | TIM6_UpdateRequestConfig (TIM6_UpdateSource_TypeDef TIM6_UpdateSource)
Selects the TIM6 Update Request Interrupt source.

Detailed Description

This file contains all functions prototype and macros for the TIM6 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_tim6.h.


STM8S/A Standard Peripherals Drivers: stm8s_uart1.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_uart1.c File Reference

This file contains all the functions for the UART1 peripheral. More...

#include "stm8s_uart1.h"

Go to the source code of this file.

Functions

void | UART1_ClearFlag (UART1_Flag_TypeDef UART1_FLAG)
Clears the UART1 flags.
void | UART1_ClearITPendingBit (UART1_IT_TypeDef UART1_IT)
Clears the UART1 pending flags.
void | UART1_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART1_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART1_GetFlagStatus (UART1_Flag_TypeDef UART1_FLAG)
Checks whether the specified UART1 flag is set or not.
ITStatus | UART1_GetITStatus (UART1_IT_TypeDef UART1_IT)
Checks whether the specified UART1 interrupt has occurred or not.
void | UART1_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART1_Init (uint32_t BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
Initializes the UART1 according to the specified parameters.
void | UART1_IrDACmd (FunctionalState NewState)
Enables or disables the UART’s IrDA interface.
void | UART1_IrDAConfig (UART1_IrDAMode_TypeDef UART1_IrDAMode)
Configures the UART’s IrDA interface.
void | UART1_ITConfig (UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | UART1_LINBreakDetectionConfig (UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
Sets the UART1 LIN Break detection length.
void | UART1_LINCmd (FunctionalState NewState)
Enables or disables the UART1’s LIN mode.
uint8_t | UART1_ReceiveData8 (void)
Returns the most recent received data by the UART1 peripheral.
uint16_t | UART1_ReceiveData9 (void)
Returns the most recent received data by the UART1 peripheral.
void | UART1_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART1 is in mute mode or not.
void | UART1_SendBreak (void)
Transmits break characters.
void | UART1_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART1 peripheral.
void | UART1_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART peripheral.
void | UART1_SetAddress (uint8_t UART1_Address)
Sets the address of the UART1 node.
void | UART1_SetGuardTime (uint8_t UART1_GuardTime)
Sets the specified UART guard time.
void | UART1_SetPrescaler (uint8_t UART1_Prescaler)
Sets the system clock prescaler.
void | UART1_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART1 Smart Card mode.
void | UART1_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART1_WakeUpConfig (UART1_WakeUp_TypeDef UART1_WakeUp)
Selects the UART1 WakeUp method.

Detailed Description

This file contains all the functions for the UART1 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_uart1.c.


STM8S/A Standard Peripherals Drivers: stm8s_uart1.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_uart1.h File Reference

This file contains all functions prototypes and macros for the UART1 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_UART1_ADDRESS_OK(node) ((node) < UART1_ADDRESS_MAX )
#define | IS_UART1_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART1_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART1_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART1_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART1_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART1_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART1_IRDAMODE_OK(IrDAMode)
Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.
#define | IS_UART1_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART1_MODE_OK(Mode)
Macro used by the assert function to check the different functions parameters.
#define | IS_UART1_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.
#define | IS_UART1_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART1_StopBits.
#define | IS_UART1_SYNCMODE_OK(SyncMode)
Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART1_CLOCK_ENABLE|UART1_CLOCK_DISABLE.
#define | IS_UART1_WAKEUP_OK(WakeUp)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART1_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART1_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART1 or UART node.

Enumerations

enum UART1_Flag_TypeDef {
UART1_FLAG_TXE = (uint16_t)0x0080, UART1_FLAG_TC = (uint16_t)0x0040, UART1_FLAG_RXNE = (uint16_t)0x0020, UART1_FLAG_IDLE = (uint16_t)0x0010,
UART1_FLAG_OR = (uint16_t)0x0008, UART1_FLAG_NF = (uint16_t)0x0004, UART1_FLAG_FE = (uint16_t)0x0002, UART1_FLAG_PE = (uint16_t)0x0001,
UART1_FLAG_LBDF = (uint16_t)0x0210, UART1_FLAG_SBK = (uint16_t)0x0101
}

UART1 Flag possible values.

More...
enum | UART1_IrDAMode_TypeDef { UART1_IRDAMODE_NORMAL = (uint8_t)0x00, UART1_IRDAMODE_LOWPOWER = (uint8_t)0x01 }

UART1 Irda Modes.

More...
enum UART1_IT_TypeDef {
UART1_IT_TXE = (uint16_t)0x0277, UART1_IT_TC = (uint16_t)0x0266, UART1_IT_RXNE = (uint16_t)0x0255, UART1_IT_IDLE = (uint16_t)0x0244,
UART1_IT_OR = (uint16_t)0x0235, UART1_IT_PE = (uint16_t)0x0100, UART1_IT_LBDF = (uint16_t)0x0346, UART1_IT_RXNE_OR = (uint16_t)0x0205
}

UART1 Interrupt definition UART1_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt

  • For the following values, X means the interrupt position in the CR2 register.
More...
enum | UART1_LINBreakDetectionLength_TypeDef { UART1_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART1_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }

UART1 LIN Break detection length possible values.

More...
enum UART1_Mode_TypeDef {
UART1_MODE_RX_ENABLE = (uint8_t)0x08, UART1_MODE_TX_ENABLE = (uint8_t)0x04, UART1_MODE_TX_DISABLE = (uint8_t)0x80, UART1_MODE_RX_DISABLE = (uint8_t)0x40,
UART1_MODE_TXRX_ENABLE = (uint8_t)0x0C
}

UART1 Mode possible values.

More...
enum | UART1_Parity_TypeDef { UART1_PARITY_NO = (uint8_t)0x00, UART1_PARITY_EVEN = (uint8_t)0x04, UART1_PARITY_ODD = (uint8_t)0x06 }

UART1 parity possible values.

More...
enum | UART1_StopBits_TypeDef { UART1_STOPBITS_1 = (uint8_t)0x00, UART1_STOPBITS_0_5 = (uint8_t)0x10, UART1_STOPBITS_2 = (uint8_t)0x20, UART1_STOPBITS_1_5 = (uint8_t)0x30 }

UART1 stop bits possible values.

More...
enum UART1_SyncMode_TypeDef {
UART1_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, UART1_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, UART1_SYNCMODE_CPOL_LOW = (uint8_t)0x40, UART1_SYNCMODE_CPOL_HIGH = (uint8_t)0x04,
UART1_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, UART1_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, UART1_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, UART1_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01
}

UART1 Synchrone modes.

More...
enum | UART1_WakeUp_TypeDef { UART1_WAKEUP_IDLELINE = (uint8_t)0x00, UART1_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }

UART1 WakeUP Modes.

More...
enum | UART1_WordLength_TypeDef { UART1_WORDLENGTH_8D = (uint8_t)0x00, UART1_WORDLENGTH_9D = (uint8_t)0x10 }

UART1 Word length possible values.

More...

Functions

void | UART1_ClearFlag (UART1_Flag_TypeDef UART1_FLAG)
Clears the UART1 flags.
void | UART1_ClearITPendingBit (UART1_IT_TypeDef UART1_IT)
Clears the UART1 pending flags.
void | UART1_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART1_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART1_GetFlagStatus (UART1_Flag_TypeDef UART1_FLAG)
Checks whether the specified UART1 flag is set or not.
ITStatus | UART1_GetITStatus (UART1_IT_TypeDef UART1_IT)
Checks whether the specified UART1 interrupt has occurred or not.
void | UART1_HalfDuplexCmd (FunctionalState NewState)
Enables or disables the UART’s Half Duplex communication.
void | UART1_Init (uint32_t BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
Initializes the UART1 according to the specified parameters.
void | UART1_IrDACmd (FunctionalState NewState)
Enables or disables the UART’s IrDA interface.
void | UART1_IrDAConfig (UART1_IrDAMode_TypeDef UART1_IrDAMode)
Configures the UART’s IrDA interface.
void | UART1_ITConfig (UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | UART1_LINBreakDetectionConfig (UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
Sets the UART1 LIN Break detection length.
void | UART1_LINCmd (FunctionalState NewState)
Enables or disables the UART1’s LIN mode.
uint8_t | UART1_ReceiveData8 (void)
Returns the most recent received data by the UART1 peripheral.
uint16_t | UART1_ReceiveData9 (void)
Returns the most recent received data by the UART1 peripheral.
void | UART1_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART1 is in mute mode or not.
void | UART1_SendBreak (void)
Transmits break characters.
void | UART1_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART1 peripheral.
void | UART1_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART peripheral.
void | UART1_SetAddress (uint8_t UART1_Address)
Sets the address of the UART1 node.
void | UART1_SetGuardTime (uint8_t UART1_GuardTime)
Sets the specified UART guard time.
void | UART1_SetPrescaler (uint8_t UART1_Prescaler)
Sets the system clock prescaler.
void | UART1_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART1 Smart Card mode.
void | UART1_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART1_WakeUpConfig (UART1_WakeUp_TypeDef UART1_WakeUp)
Selects the UART1 WakeUp method.

Detailed Description

This file contains all functions prototypes and macros for the UART1 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_uart1.h.


STM8S/A Standard Peripherals Drivers: stm8s_uart2.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_uart2.c File Reference

This file contains all the functions for the UART2 peripheral. More...

#include "stm8s_uart2.h"

Go to the source code of this file.

Functions

void | UART2_ClearFlag (UART2_Flag_TypeDef UART2_FLAG)
Clears the UART2 flags.
void | UART2_ClearITPendingBit (UART2_IT_TypeDef UART2_IT)
Clears the UART2 pending flags.
void | UART2_Cmd (FunctionalState NewState)
Enable the UART2 peripheral.
void | UART2_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART2_GetFlagStatus (UART2_Flag_TypeDef UART2_FLAG)
Checks whether the specified UART2 flag is set or not.
ITStatus | UART2_GetITStatus (UART2_IT_TypeDef UART2_IT)
Checks whether the specified UART2 interrupt has occurred or not.
void | UART2_Init (uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
Initializes the UART2 according to the specified parameters.
void | UART2_IrDACmd (FunctionalState NewState)
Enables or disables the UART2’s IrDA interface.
void | UART2_IrDAConfig (UART2_IrDAMode_TypeDef UART2_IrDAMode)
Configures the UART2’s IrDA interface.
void | UART2_ITConfig (UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
Enables or disables the specified UART2 interrupts.
void | UART2_LINBreakDetectionConfig (UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
Sets the UART2 LIN Break detection length.
void | UART2_LINCmd (FunctionalState NewState)
Enables or disables the UART2 LIN mode.
void | UART2_LINConfig (UART2_LinMode_TypeDef UART2_Mode, UART2_LinAutosync_TypeDef UART2_Autosync, UART2_LinDivUp_TypeDef UART2_DivUp)
Configure the UART2 peripheral.
uint8_t | UART2_ReceiveData8 (void)
Returns the most recent received data by the UART2 peripheral.
uint16_t | UART2_ReceiveData9 (void)
Returns the most recent received data by the UART2 peripheral.
void | UART2_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART2 is in mute mode or not.
void | UART2_SendBreak (void)
Transmits break characters.
void | UART2_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART2 peripheral.
void | UART2_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART2 peripheral.
void | UART2_SetAddress (uint8_t UART2_Address)
Sets the address of the UART2 node.
void | UART2_SetGuardTime (uint8_t UART2_GuardTime)
Sets the specified UART2 guard time.
void | UART2_SetPrescaler (uint8_t UART2_Prescaler)
Sets the system clock prescaler.
void | UART2_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART2 Smart Card mode.
void | UART2_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART2_WakeUpConfig (UART2_WakeUp_TypeDef UART2_WakeUp)
Selects the UART2 WakeUp method.

Detailed Description

This file contains all the functions for the UART2 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_uart2.c.


STM8S/A Standard Peripherals Drivers: stm8s_uart2.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_uart2.h File Reference

This file contains all functions prototypes and macros for the UART2 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_UART2_ADDRESS_OK(node) ((node) < UART2_ADDRESS_MAX )
#define | IS_UART2_AUTOSYNC_OK(AutosyncMode)
Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.
#define | IS_UART2_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART2_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART2_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART2_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART2_DIVUP_OK(DivupMethode)
Macro used by the assert_param function in order to check the LIN divider update method.
#define | IS_UART2_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART2_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART2_IRDAMODE_OK(IrDAMode)
Macro used by the assert_param function in order to check the different sensitivity values for the IrDAModes.
#define | IS_UART2_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART2_MODE_OK(Mode)
Macro used by the assert function to check the different functions parameters.
#define | IS_UART2_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Paritys.
#define | IS_UART2_SLAVE_OK(Mode)
Macro used by the assert_param function in order to check the LIN mode.
#define | IS_UART2_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART2_StopBits.
#define | IS_UART2_SYNCMODE_OK(SyncMode)
Macro used by the assert_param function in order to check the different sensitivity values for the SyncModes; it should exclude values such as UART2_CLOCK_ENABLE|UART2_CLOCK_DISABLE.
#define | IS_UART2_WAKEUP_OK(WakeUp)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART2_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART2_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART2 or UART node.

Enumerations

enum UART2_Flag_TypeDef {
UART2_FLAG_TXE = (uint16_t)0x0080, UART2_FLAG_TC = (uint16_t)0x0040, UART2_FLAG_RXNE = (uint16_t)0x0020, UART2_FLAG_IDLE = (uint16_t)0x0010,
UART2_FLAG_OR_LHE = (uint16_t)0x0008, UART2_FLAG_NF = (uint16_t)0x0004, UART2_FLAG_FE = (uint16_t)0x0002, UART2_FLAG_PE = (uint16_t)0x0001,
UART2_FLAG_SBK = (uint16_t)0x0101, UART2_FLAG_LBDF = (uint16_t)0x0210, UART2_FLAG_LHDF = (uint16_t)0x0302, UART2_FLAG_LSF = (uint16_t)0x0301
}

UART2 Flag possible values.

More...
enum | UART2_IrDAMode_TypeDef { UART2_IRDAMODE_NORMAL = (uint8_t)0x00, UART2_IRDAMODE_LOWPOWER = (uint8_t)0x01 }

UART2 Irda Modes.

More...
enum UART2_IT_TypeDef {
UART2_IT_TXE = (uint16_t)0x0277, UART2_IT_TC = (uint16_t)0x0266, UART2_IT_RXNE = (uint16_t)0x0255, UART2_IT_IDLE = (uint16_t)0x0244,
UART2_IT_OR = (uint16_t)0x0235, UART2_IT_PE = (uint16_t)0x0100, UART2_IT_LBDF = (uint16_t)0x0346, UART2_IT_LHDF = (uint16_t)0x0412,
UART2_IT_RXNE_OR = (uint16_t)0x0205
}

UART2 Interrupt definition UART2_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt

  • For the following values, X means the interrupt position in the CR2 register.
More...
enum | UART2_LinAutosync_TypeDef { UART2_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, UART2_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 }

UART2 automatic resynchronisation possible values.

More...
enum | UART2_LINBreakDetectionLength_TypeDef { UART2_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART2_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }

UART2 LIN Break detection length possible values.

More...
enum | UART2_LinDivUp_TypeDef { UART2_LIN_DIVUP_LBRR1 = (uint8_t)0x00, UART2_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 }

UART2 Divider Update Method possible values.

More...
enum | UART2_LinMode_TypeDef { UART2_LIN_MODE_MASTER = (uint8_t)0x00, UART2_LIN_MODE_SLAVE = (uint8_t)0x01 }

UART2 Mode possible values.

More...
enum UART2_Mode_TypeDef {
UART2_MODE_RX_ENABLE = (uint8_t)0x08, UART2_MODE_TX_ENABLE = (uint8_t)0x04, UART2_MODE_TX_DISABLE = (uint8_t)0x80, UART2_MODE_RX_DISABLE = (uint8_t)0x40,
UART2_MODE_TXRX_ENABLE = (uint8_t)0x0C
}

UART2 Mode possible values.

More...
enum | UART2_Parity_TypeDef { UART2_PARITY_NO = (uint8_t)0x00, UART2_PARITY_EVEN = (uint8_t)0x04, UART2_PARITY_ODD = (uint8_t)0x06 }

UART2 parity possible values.

More...
enum | UART2_StopBits_TypeDef { UART2_STOPBITS_1 = (uint8_t)0x00, UART2_STOPBITS_0_5 = (uint8_t)0x10, UART2_STOPBITS_2 = (uint8_t)0x20, UART2_STOPBITS_1_5 = (uint8_t)0x30 }

UART2 stop bits possible values.

More...
enum UART2_SyncMode_TypeDef {
UART2_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, UART2_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, UART2_SYNCMODE_CPOL_LOW = (uint8_t)0x40, UART2_SYNCMODE_CPOL_HIGH = (uint8_t)0x04,
UART2_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, UART2_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, UART2_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, UART2_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01
}

UART2 Synchrone modes.

More...
enum | UART2_WakeUp_TypeDef { UART2_WAKEUP_IDLELINE = (uint8_t)0x00, UART2_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }

UART2 WakeUP Modes.

More...
enum | UART2_WordLength_TypeDef { UART2_WORDLENGTH_8D = (uint8_t)0x00, UART2_WORDLENGTH_9D = (uint8_t)0x10 }

UART2 Word length possible values.

More...

Functions

void | UART2_ClearFlag (UART2_Flag_TypeDef UART2_FLAG)
Clears the UART2 flags.
void | UART2_ClearITPendingBit (UART2_IT_TypeDef UART2_IT)
Clears the UART2 pending flags.
void | UART2_Cmd (FunctionalState NewState)
Enable the UART2 peripheral.
void | UART2_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART2_GetFlagStatus (UART2_Flag_TypeDef UART2_FLAG)
Checks whether the specified UART2 flag is set or not.
ITStatus | UART2_GetITStatus (UART2_IT_TypeDef UART2_IT)
Checks whether the specified UART2 interrupt has occurred or not.
void | UART2_HalfDuplexCmd (FunctionalState NewState)
void | UART2_Init (uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
Initializes the UART2 according to the specified parameters.
void | UART2_IrDACmd (FunctionalState NewState)
Enables or disables the UART2’s IrDA interface.
void | UART2_IrDAConfig (UART2_IrDAMode_TypeDef UART2_IrDAMode)
Configures the UART2’s IrDA interface.
void | UART2_ITConfig (UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
Enables or disables the specified UART2 interrupts.
void | UART2_LINBreakDetectionConfig (UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
Sets the UART2 LIN Break detection length.
void | UART2_LINCmd (FunctionalState NewState)
Enables or disables the UART2 LIN mode.
void | UART2_LINConfig (UART2_LinMode_TypeDef UART2_Mode, UART2_LinAutosync_TypeDef UART2_Autosync, UART2_LinDivUp_TypeDef UART2_DivUp)
Configure the UART2 peripheral.
uint8_t | UART2_ReceiveData8 (void)
Returns the most recent received data by the UART2 peripheral.
uint16_t | UART2_ReceiveData9 (void)
Returns the most recent received data by the UART2 peripheral.
void | UART2_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART2 is in mute mode or not.
void | UART2_SendBreak (void)
Transmits break characters.
void | UART2_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART2 peripheral.
void | UART2_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART2 peripheral.
void | UART2_SetAddress (uint8_t UART2_Address)
Sets the address of the UART2 node.
void | UART2_SetGuardTime (uint8_t UART2_GuardTime)
Sets the specified UART2 guard time.
void | UART2_SetPrescaler (uint8_t UART2_Prescaler)
Sets the system clock prescaler.
void | UART2_SmartCardCmd (FunctionalState NewState)
Enables or disables the UART2 Smart Card mode.
void | UART2_SmartCardNACKCmd (FunctionalState NewState)
Enables or disables NACK transmission.
void | UART2_WakeUpConfig (UART2_WakeUp_TypeDef UART2_WakeUp)
Selects the UART2 WakeUp method.

Detailed Description

This file contains all functions prototypes and macros for the UART2 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_uart2.h.


STM8S/A Standard Peripherals Drivers: stm8s_uart3.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Functions

stm8s_uart3.c File Reference

This file contains all the functions for the uart3 peripheral. More...

#include "stm8s_uart3.h"

Go to the source code of this file.

Functions

void | UART3_ClearFlag (UART3_Flag_TypeDef UART3_FLAG)
Clears the UART3 flags.
void | UART3_ClearITPendingBit (UART3_IT_TypeDef UART3_IT)
Clears the UART3 pending flags.
void | UART3_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART3_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART3_GetFlagStatus (UART3_Flag_TypeDef UART3_FLAG)
Checks whether the specified UART3 flag is set or not.
ITStatus | UART3_GetITStatus (UART3_IT_TypeDef UART3_IT)
Checks whether the specified UART3 interrupt has occurred or not.
void | UART3_Init (uint32_t BaudRate, UART3_WordLength_TypeDef WordLength, UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, UART3_Mode_TypeDef Mode)
Initializes the UART3 according to the specified parameters.
void | UART3_ITConfig (UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
Enables or disables the specified UART3 interrupts.
void | UART3_LINBreakDetectionConfig (UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
Sets the UART3 LIN Break detection length.
void | UART3_LINCmd (FunctionalState NewState)
Enables or disables the UART3 LIN mode.
void | UART3_LINConfig (UART3_LinMode_TypeDef UART3_Mode, UART3_LinAutosync_TypeDef UART3_Autosync, UART3_LinDivUp_TypeDef UART3_DivUp)
Configure the UART3 peripheral.
uint8_t | UART3_ReceiveData8 (void)
Returns the most recent received data by the UART3 peripheral.
uint16_t | UART3_ReceiveData9 (void)
Returns the most recent received data by the UART3 peripheral.
void | UART3_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART3 is in mute mode or not.
void | UART3_SendBreak (void)
Transmits break characters.
void | UART3_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART3 peripheral.
void | UART3_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART3 peripheral.
void | UART3_SetAddress (uint8_t UART3_Address)
Sets the address of the UART3 node.
void | UART3_WakeUpConfig (UART3_WakeUp_TypeDef UART3_WakeUp)
Selects the UART3 WakeUp method.

Detailed Description

This file contains all the functions for the uart3 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_uart3.c.


STM8S/A Standard Peripherals Drivers: stm8s_uart3.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm8s_uart3.h File Reference

This file contains all functions prototypes and macros for the UART3 peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_UART3_ADDRESS_OK(Node) ((Node) < UART3_ADDRESS_MAX)
#define | IS_UART3_AUTOSYNC_OK(AutosyncMode)
Macro used by the assert_param function in order to check the LIN automatic resynchronization mode.
#define | IS_UART3_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
Macro used by the assert_param function in order to check the maximum baudrate value.
#define | IS_UART3_CLEAR_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs that can be cleared by writing 0.
#define | IS_UART3_CLEAR_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit that can be cleared by writing 0.
#define | IS_UART3_CONFIG_IT_OK(Interrupt)
Macro used by the assert_param function in order to check the different sensitivity values for the Interrupts.
#define | IS_UART3_DIVUP_OK(DivupMethode)
Macro used by the assert_param function in order to check the LIN divider update method.
#define | IS_UART3_FLAG_OK(Flag)
Macro used by the assert_param function in order to check the different sensitivity values for the FLAGs.
#define | IS_UART3_GET_IT_OK(ITPendingBit)
Macro used by the assert function in order to check the different sensitivity values for the pending bit.
#define | IS_UART3_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLengths)
Macro used by the assert_param function in order to check the different sensitivity values for the LINBreakDetectionLengths.
#define | IS_UART3_MODE_OK(Mode)
Macro used by the assert_param function in order to check the different sensitivity values for the MODEs.
#define | IS_UART3_PARITY_OK(Parity)
Macro used by the assert_param function in order to check the different sensitivity values for the Parity.
#define | IS_UART3_SLAVE_OK(Mode)
Macro used by the assert_param function in order to check the LIN mode.
#define | IS_UART3_STOPBITS_OK(StopBit)
Macro used by the assert_param function in order to check the different sensitivity values for the UART3_StopBits.
#define | IS_UART3_WAKEUP_OK(WakeUpMode)
Macro used by the assert_param function in order to check the different sensitivity values for the WakeUps.
#define | IS_UART3_WORDLENGTH_OK(WordLength)
Macro used by the assert_param function in order to check the different sensitivity values for the WordLengths.
#define | UART3_ADDRESS_MAX ((uint8_t)16)
Macro used by the assert_param function in order to check the address of the UART3 or UART node.

Enumerations

enum UART3_Flag_TypeDef {
UART3_FLAG_TXE = (uint16_t)0x0080, UART3_FLAG_TC = (uint16_t)0x0040, UART3_FLAG_RXNE = (uint16_t)0x0020, UART3_FLAG_IDLE = (uint16_t)0x0010,
UART3_FLAG_OR_LHE = (uint16_t)0x0008, UART3_FLAG_NF = (uint16_t)0x0004, UART3_FLAG_FE = (uint16_t)0x0002, UART3_FLAG_PE = (uint16_t)0x0001,
UART3_FLAG_SBK = (uint16_t)0x0101, UART3_FLAG_LBDF = (uint16_t)0x0210, UART3_FLAG_LHDF = (uint16_t)0x0302, UART3_FLAG_LSF = (uint16_t)0x0301
}

UART3 Flag possible values.

More...
enum UART3_IT_TypeDef {
UART3_IT_TXE = (uint16_t)0x0277, UART3_IT_TC = (uint16_t)0x0266, UART3_IT_RXNE = (uint16_t)0x0255, UART3_IT_IDLE = (uint16_t)0x0244,
UART3_IT_OR = (uint16_t)0x0235, UART3_IT_PE = (uint16_t)0x0100, UART3_IT_LBDF = (uint16_t)0x0346, UART3_IT_LHDF = (uint16_t)0x0412,
UART3_IT_RXNE_OR = (uint16_t)0x0205
}

UART3 Interrupt definition UART3_IT possible values Elements values convention: 0xZYX X: Position of the corresponding Interrupt

  • For the following values, X means the interrupt position in the CR2 register.
More...
enum | UART3_LinAutosync_TypeDef { UART3_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, UART3_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 }

UART3 automatic resynchronisation possible values.

More...
enum | UART3_LINBreakDetectionLength_TypeDef { UART3_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, UART3_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 }

UART3 LIN Break detection length possible values.

More...
enum | UART3_LinDivUp_TypeDef { UART3_LIN_DIVUP_LBRR1 = (uint8_t)0x00, UART3_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 }

UART3 Divider Update Method possible values.

More...
enum | UART3_LinMode_TypeDef { UART3_LIN_MODE_MASTER = (uint8_t)0x00, UART3_LIN_MODE_SLAVE = (uint8_t)0x01 }

UART3 Mode possible values.

More...
enum UART3_Mode_TypeDef {
UART3_MODE_RX_ENABLE = (uint8_t)0x08, UART3_MODE_TX_ENABLE = (uint8_t)0x04, UART3_MODE_TX_DISABLE = (uint8_t)0x80, UART3_MODE_RX_DISABLE = (uint8_t)0x40,
UART3_MODE_TXRX_ENABLE = (uint8_t)0x0C
}

UART3 Mode Transmit/Receive possible values.

More...
enum | UART3_Parity_TypeDef { UART3_PARITY_NO = (uint8_t)0x00, UART3_PARITY_EVEN = (uint8_t)0x04, UART3_PARITY_ODD = (uint8_t)0x06 }

UART3 parity possible values.

More...
enum | UART3_StopBits_TypeDef { UART3_STOPBITS_1 = (uint8_t)0x00, UART3_STOPBITS_2 = (uint8_t)0x20 }

UART3 stop bits possible values.

More...
enum | UART3_WakeUp_TypeDef { UART3_WAKEUP_IDLELINE = (uint8_t)0x00, UART3_WAKEUP_ADDRESSMARK = (uint8_t)0x08 }

UART3 WakeUP Modes.

More...
enum | UART3_WordLength_TypeDef { UART3_WORDLENGTH_8D = (uint8_t)0x00, UART3_WORDLENGTH_9D = (uint8_t)0x10 }

UART3 Word length possible values.

More...

Functions

void | UART3_ClearFlag (UART3_Flag_TypeDef UART3_FLAG)
Clears the UART3 flags.
void | UART3_ClearITPendingBit (UART3_IT_TypeDef UART3_IT)
Clears the UART3 pending flags.
void | UART3_Cmd (FunctionalState NewState)
Enable the UART1 peripheral.
void | UART3_DeInit (void)
Deinitializes the UART peripheral.
FlagStatus | UART3_GetFlagStatus (UART3_Flag_TypeDef UART3_FLAG)
Checks whether the specified UART3 flag is set or not.
ITStatus | UART3_GetITStatus (UART3_IT_TypeDef UART3_IT)
Checks whether the specified UART3 interrupt has occurred or not.
void | UART3_Init (uint32_t BaudRate, UART3_WordLength_TypeDef WordLength, UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, UART3_Mode_TypeDef Mode)
Initializes the UART3 according to the specified parameters.
void | UART3_ITConfig (UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
Enables or disables the specified UART3 interrupts.
void | UART3_LINBreakDetectionConfig (UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
Sets the UART3 LIN Break detection length.
void | UART3_LINCmd (FunctionalState NewState)
Enables or disables the UART3 LIN mode.
void | UART3_LINConfig (UART3_LinMode_TypeDef UART3_Mode, UART3_LinAutosync_TypeDef UART3_Autosync, UART3_LinDivUp_TypeDef UART3_DivUp)
Configure the UART3 peripheral.
uint8_t | UART3_ReceiveData8 (void)
Returns the most recent received data by the UART3 peripheral.
uint16_t | UART3_ReceiveData9 (void)
Returns the most recent received data by the UART3 peripheral.
void | UART3_ReceiverWakeUpCmd (FunctionalState NewState)
Determines if the UART3 is in mute mode or not.
void | UART3_SendBreak (void)
Transmits break characters.
void | UART3_SendData8 (uint8_t Data)
Transmits 8 bit data through the UART3 peripheral.
void | UART3_SendData9 (uint16_t Data)
Transmits 9 bit data through the UART3 peripheral.
void | UART3_SetAddress (uint8_t UART3_Address)
Sets the address of the UART3 node.
void | UART3_WakeUpConfig (UART3_WakeUp_TypeDef UART3_WakeUp)
Selects the UART3 WakeUp method.

Detailed Description

This file contains all functions prototypes and macros for the UART3 peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_uart3.h.


STM8S/A Standard Peripherals Drivers: stm8s_wwdg.c File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • src
Defines | Functions

stm8s_wwdg.c File Reference

This file contains all the functions for the WWDG peripheral. More...

#include "stm8s_wwdg.h"

Go to the source code of this file.

Defines

#define | BIT_MASK ((uint8_t)0x7F)

Functions

uint8_t | WWDG_GetCounter (void)
Gets the WWDG Counter Value.
void | WWDG_Init (uint8_t Counter, uint8_t WindowValue)
Initializes the WWDG peripheral.
void | WWDG_SetCounter (uint8_t Counter)
Refreshes the WWDG peripheral.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.
void | WWDG_SWReset (void)
Generates immediate WWDG RESET.

Detailed Description

This file contains all the functions for the WWDG peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_wwdg.c.


STM8S/A Standard Peripherals Drivers: stm8s_wwdg.h File Reference

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc
Defines | Functions

stm8s_wwdg.h File Reference

This file contains all functions prototype and macros for the WWDG peripheral. More...

#include "stm8s.h"

Go to the source code of this file.

Defines

#define | IS_WWDG_COUNTERVALUE_OK(CounterValue) ((CounterValue) <= 0x7F)
Macro used by the assert function in order to check the different values of the counter register.
#define | IS_WWDG_WINDOWLIMITVALUE_OK(WindowLimitValue) ((WindowLimitValue) <= 0x7F)
Macro used by the assert function in order to check the values of the window register.

Functions

uint8_t | WWDG_GetCounter (void)
Gets the WWDG Counter Value.
void | WWDG_Init (uint8_t Counter, uint8_t WindowValue)
Initializes the WWDG peripheral.
void | WWDG_SetCounter (uint8_t Counter)
Refreshes the WWDG peripheral.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.
void | WWDG_SWReset (void)
Generates immediate WWDG RESET.

Detailed Description

This file contains all functions prototype and macros for the WWDG peripheral.

Author:
MCD Application Team
Version:
V2.1.0
Date:
18-November-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm8s_wwdg.h.


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __I : stm8s.h
  • __IO : stm8s.h
  • __O : stm8s.h
  • __STM8S_STDPERIPH_VERSION : stm8s.h
  • __STM8S_STDPERIPH_VERSION_MAIN : stm8s.h
  • __STM8S_STDPERIPH_VERSION_RC : stm8s.h
  • __STM8S_STDPERIPH_VERSION_SUB1 : stm8s.h
  • __STM8S_STDPERIPH_VERSION_SUB2 : stm8s.h
  • _Data : stm8s_can.c
  • _DLC : stm8s_can.c
  • _FMI : stm8s_can.c
  • _Id : stm8s_can.c
  • _IDE : stm8s_can.c
  • _RTR : stm8s_can.c


STM8S/A Standard Peripherals Drivers: Data Structures

  • Data Structures
  • Data Structure Index
  • Data Fields

Data Structures

Here are the data structures with brief descriptions:
AWU_struct | Auto Wake Up (AWU) peripheral registers
BEEP_struct | Beeper (BEEP) peripheral registers
CAN_TypeDef | Controller Area Network (CAN)
CFG_struct | Configuration Registers (CFG)
CLK_struct | Clock Controller (CLK)
EXTI_struct | External Interrupt Controller (EXTI)
FLASH_struct | FLASH program and Data memory (FLASH)
GPIO_struct | General Purpose I/Os (GPIO)
I2C_struct | Inter-Integrated Circuit (I2C)
ITC_struct | Interrupt Controller (ITC)
IWDG_struct | Independent Watchdog (IWDG)
OPT_struct | Option Bytes (OPT)
RST_struct | Reset Controller (RST)
SPI_struct | Serial Peripheral Interface (SPI)
TIM1_struct | 16-bit timer with complementary PWM outputs (TIM1)
TIM2_struct | 16-bit timer (TIM2)
TIM3_struct | 16-bit timer (TIM3)
TIM4_struct | 8-bit system timer (TIM4)
TIM5_struct | 16-bit timer with synchro module (TIM5)
TIM6_struct | 8-bit system timer with synchro module(TIM6)
UART1_struct | Universal Synchronous Asynchronous Receiver Transmitter (UART1)
UART2_struct | Universal Synchronous Asynchronous Receiver Transmitter (UART2)
UART3_struct | LIN Universal Asynchronous Receiver Transmitter (UART3)
WWDG_struct | Window Watchdog (WWDG)


STM8S/A Standard Peripherals Drivers: Data Structure Index

  • Data Structures
  • Data Structure Index
  • Data Fields

Data Structure Index

A | B | C | E | F | G | I | O | R | S | T | U | W
A
BEEP_struct CFG_struct EXTI_struct
G
I2C_struct
O
RST_struct SPI_struct TIM1_struct TIM3_struct TIM5_struct
U
UART2_struct
W
AWU_struct
C
CLK_struct
F
GPIO_struct ITC_struct OPT_struct
S
T
TIM2_struct TIM4_struct TIM6_struct UART1_struct UART3_struct WWDG_struct
B
CAN_TypeDef
E
FLASH_struct
I
IWDG_struct
R


STM8S/A Standard Peripherals Drivers: C:/STM8/Introduction Package/DOC/CHM_Generator/STM8S_StdPeriph_Driver/inc/ Directory Reference

  • STM8S_StdPeriph_Driver
  • inc

inc Directory Reference

Files

file | stm8s.h [code]

This file contains all HW registers definitions and memory mapping.

file | stm8s_adc1.h [code]

This file contains all the prototypes/macros for the ADC1 peripheral.

file | stm8s_adc2.h [code]

This file contains all the prototypes/macros for the ADC2 peripheral.

file | stm8s_awu.h [code]

This file contains all functions prototype and macros for the AWU peripheral.

file | stm8s_beep.h [code]

This file contains all functions prototype and macros for the BEEP peripheral.

file | stm8s_can.h [code]

This file contains all the functions for the CAN peripheral.

file | stm8s_clk.h [code]

This file contains all functions prototype and macros for the CLK peripheral.

file | stm8s_exti.h [code]

This file contains all functions prototype and macros for the EXTI peripheral.

file | stm8s_flash.h [code]

This file contains all functions prototype and macros for the FLASH peripheral.

file | stm8s_gpio.h [code]

This file contains all functions prototype and macros for the GPIO peripheral.

file | stm8s_i2c.h [code]

This file contains all functions prototype and macros for the I2C peripheral.

file | stm8s_itc.h [code]

This file contains all functions prototype and macros for the ITC peripheral.

file | stm8s_iwdg.h [code]

This file contains all functions prototypes and macros for the IWDG peripheral.

file | stm8s_rst.h [code]

This file contains all functions prototype and macros for the RST peripheral.

file | stm8s_spi.h [code]

This file contains all functions prototype and macros for the SPI peripheral.

file | stm8s_tim1.h [code]

This file contains all functions prototype and macros for the TIM1 peripheral.

file | stm8s_tim2.h [code]

This file contains all functions prototype and macros for the TIM2 peripheral.

file | stm8s_tim3.h [code]

This file contains all functions prototype and macros for the TIM3 peripheral.

file | stm8s_tim4.h [code]

This file contains all functions prototype and macros for the TIM4 peripheral.

file | stm8s_tim5.h [code]

This file contains all functions prototype and macros for the TIM5 peripheral.

file | stm8s_tim6.h [code]

This file contains all functions prototype and macros for the TIM6 peripheral.

file | stm8s_uart1.h [code]

This file contains all functions prototypes and macros for the UART1 peripheral.

file | stm8s_uart2.h [code]

This file contains all functions prototypes and macros for the UART2 peripheral.

file | stm8s_uart3.h [code]

This file contains all functions prototypes and macros for the UART3 peripheral.

file | stm8s_wwdg.h [code]

This file contains all functions prototype and macros for the WWDG peripheral.


STM8S/A Standard Peripherals Drivers: C:/STM8/Introduction Package/DOC/CHM_Generator/STM8S_StdPeriph_Driver/src/ Directory Reference

  • STM8S_StdPeriph_Driver
  • src

src Directory Reference

Files

file | stm8s_adc1.c [code]

This file contains all the functions/macros for the ADC1 peripheral.

file | stm8s_adc2.c [code]

This file contains all the functions/macros for the ADC2 peripheral.

file | stm8s_awu.c [code]

This file contains all the functions for the AWU peripheral.

file | stm8s_beep.c [code]

This file contains all the functions for the BEEP peripheral.

file | stm8s_can.c [code]

This file contains all the functions for the CAN peripheral.

file | stm8s_clk.c [code]

This file contains all the functions for the CLK peripheral.

file | stm8s_exti.c [code]

This file contains all the functions for the EXTI peripheral.

file | stm8s_flash.c [code]

This file contains all the functions for the FLASH peripheral.

file | stm8s_gpio.c [code]

This file contains all the functions for the GPIO peripheral.

file | stm8s_i2c.c [code]

This file contains all the functions for the I2C peripheral.

file | stm8s_itc.c [code]

This file contains all the functions for the ITC peripheral.

file | stm8s_iwdg.c [code]

This file contains all the functions for the IWDG peripheral.

file | stm8s_rst.c [code]

This file contains all the functions for the RST peripheral.

file | stm8s_spi.c [code]

This file contains all the functions for the SPI peripheral.

file | stm8s_tim1.c [code]

This file contains all the functions for the TIM1 peripheral.

file | stm8s_tim2.c [code]

This file contains all the functions for the TIM2 peripheral.

file | stm8s_tim3.c [code]

This file contains all the functions for the TIM3 peripheral.

file | stm8s_tim4.c [code]

This file contains all the functions for the TIM4 peripheral.

file | stm8s_tim5.c [code]

This file contains all the functions for the TIM5 peripheral.

file | stm8s_tim6.c [code]

This file contains all the functions for the TIM6 peripheral.

file | stm8s_uart1.c [code]

This file contains all the functions for the UART1 peripheral.

file | stm8s_uart2.c [code]

This file contains all the functions for the UART2 peripheral.

file | stm8s_uart3.c [code]

This file contains all the functions for the uart3 peripheral.

file | stm8s_wwdg.c [code]

This file contains all the functions for the WWDG peripheral.


STM8S/A Standard Peripherals Drivers: C:/STM8/Introduction Package/DOC/CHM_Generator/STM8S_StdPeriph_Driver/ Directory Reference

  • STM8S_StdPeriph_Driver

STM8S_StdPeriph_Driver Directory Reference

Directories

directory | inc
directory | src


STM8S/A Standard Peripherals Drivers: Directories

Directories

This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • STM8S_StdPeriph_Driver
    • inc
    • src


STM8S/A Standard Peripherals Drivers: File List

  • File List
  • Globals

File List

Here is a list of all files with brief descriptions:
stm8s.h [code] | This file contains all HW registers definitions and memory mapping
stm8s_adc1.c [code] | This file contains all the functions/macros for the ADC1 peripheral
stm8s_adc1.h [code] | This file contains all the prototypes/macros for the ADC1 peripheral
stm8s_adc2.c [code] | This file contains all the functions/macros for the ADC2 peripheral
stm8s_adc2.h [code] | This file contains all the prototypes/macros for the ADC2 peripheral
stm8s_awu.c [code] | This file contains all the functions for the AWU peripheral
stm8s_awu.h [code] | This file contains all functions prototype and macros for the AWU peripheral
stm8s_beep.c [code] | This file contains all the functions for the BEEP peripheral
stm8s_beep.h [code] | This file contains all functions prototype and macros for the BEEP peripheral
stm8s_can.c [code] | This file contains all the functions for the CAN peripheral
stm8s_can.h [code] | This file contains all the functions for the CAN peripheral
stm8s_clk.c [code] | This file contains all the functions for the CLK peripheral
stm8s_clk.h [code] | This file contains all functions prototype and macros for the CLK peripheral
stm8s_exti.c [code] | This file contains all the functions for the EXTI peripheral
stm8s_exti.h [code] | This file contains all functions prototype and macros for the EXTI peripheral
stm8s_flash.c [code] | This file contains all the functions for the FLASH peripheral
stm8s_flash.h [code] | This file contains all functions prototype and macros for the FLASH peripheral
stm8s_gpio.c [code] | This file contains all the functions for the GPIO peripheral
stm8s_gpio.h [code] | This file contains all functions prototype and macros for the GPIO peripheral
stm8s_i2c.c [code] | This file contains all the functions for the I2C peripheral
stm8s_i2c.h [code] | This file contains all functions prototype and macros for the I2C peripheral
stm8s_itc.c [code] | This file contains all the functions for the ITC peripheral
stm8s_itc.h [code] | This file contains all functions prototype and macros for the ITC peripheral
stm8s_iwdg.c [code] | This file contains all the functions for the IWDG peripheral
stm8s_iwdg.h [code] | This file contains all functions prototypes and macros for the IWDG peripheral
stm8s_rst.c [code] | This file contains all the functions for the RST peripheral
stm8s_rst.h [code] | This file contains all functions prototype and macros for the RST peripheral
stm8s_spi.c [code] | This file contains all the functions for the SPI peripheral
stm8s_spi.h [code] | This file contains all functions prototype and macros for the SPI peripheral
stm8s_tim1.c [code] | This file contains all the functions for the TIM1 peripheral
stm8s_tim1.h [code] | This file contains all functions prototype and macros for the TIM1 peripheral
stm8s_tim2.c [code] | This file contains all the functions for the TIM2 peripheral
stm8s_tim2.h [code] | This file contains all functions prototype and macros for the TIM2 peripheral
stm8s_tim3.c [code] | This file contains all the functions for the TIM3 peripheral
stm8s_tim3.h [code] | This file contains all functions prototype and macros for the TIM3 peripheral
stm8s_tim4.c [code] | This file contains all the functions for the TIM4 peripheral
stm8s_tim4.h [code] | This file contains all functions prototype and macros for the TIM4 peripheral
stm8s_tim5.c [code] | This file contains all the functions for the TIM5 peripheral
stm8s_tim5.h [code] | This file contains all functions prototype and macros for the TIM5 peripheral
stm8s_tim6.c [code] | This file contains all the functions for the TIM6 peripheral
stm8s_tim6.h [code] | This file contains all functions prototype and macros for the TIM6 peripheral
stm8s_uart1.c [code] | This file contains all the functions for the UART1 peripheral
stm8s_uart1.h [code] | This file contains all functions prototypes and macros for the UART1 peripheral
stm8s_uart2.c [code] | This file contains all the functions for the UART2 peripheral
stm8s_uart2.h [code] | This file contains all functions prototypes and macros for the UART2 peripheral
stm8s_uart3.c [code] | This file contains all the functions for the uart3 peripheral
stm8s_uart3.h [code] | This file contains all functions prototypes and macros for the UART3 peripheral
stm8s_wwdg.c [code] | This file contains all the functions for the WWDG peripheral
stm8s_wwdg.h [code] | This file contains all functions prototype and macros for the WWDG peripheral


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- k -

  • KR : IWDG_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • MCR : CAN_TypeDef
  • MCSR : CAN_TypeDef
  • MDAR1 : CAN_TypeDef
  • MDAR2 : CAN_TypeDef
  • MDAR3 : CAN_TypeDef
  • MDAR4 : CAN_TypeDef
  • MDAR5 : CAN_TypeDef
  • MDAR6 : CAN_TypeDef
  • MDAR7 : CAN_TypeDef
  • MDAR8 : CAN_TypeDef
  • MDLCR : CAN_TypeDef
  • MFMI : CAN_TypeDef
  • MIDR1 : CAN_TypeDef
  • MIDR2 : CAN_TypeDef
  • MIDR3 : CAN_TypeDef
  • MIDR4 : CAN_TypeDef
  • MSR : CAN_TypeDef
  • MTSRH : CAN_TypeDef
  • MTSRL : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NCR2 : FLASH_struct
  • NFPR : FLASH_struct
  • NOPT1 : OPT_struct
  • NOPT2 : OPT_struct
  • NOPT3 : OPT_struct
  • NOPT4 : OPT_struct
  • NOPT5 : OPT_struct
  • NOPT7 : OPT_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OARH : I2C_struct
  • OARL : I2C_struct
  • ODR : GPIO_struct
  • OISR : TIM1_struct
  • OPT0 : OPT_struct
  • OPT1 : OPT_struct
  • OPT2 : OPT_struct
  • OPT3 : OPT_struct
  • OPT4 : OPT_struct
  • OPT5 : OPT_struct
  • OPT7 : OPT_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • BKR : TIM1_struct
  • BRR1 : UART1_struct , UART3_struct , UART2_struct
  • BRR2 : UART2_struct , UART1_struct , UART3_struct
  • BTR1 : CAN_TypeDef
  • BTR2 : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • k
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • w
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • CCER1 : TIM1_struct , TIM2_struct , TIM5_struct , TIM3_struct
  • CCER2 : TIM1_struct , TIM2_struct , TIM5_struct
  • CCMR1 : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCMR2 : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCMR3 : TIM1_struct , TIM2_struct , TIM5_struct
  • CCMR4 : TIM1_struct
  • CCOR : CLK_struct
  • CCR1H : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR1L : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR2H : TIM5_struct , TIM1_struct , TIM2_struct , TIM3_struct
  • CCR2L : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR3H : TIM1_struct , TIM2_struct , TIM5_struct
  • CCR3L : TIM1_struct , TIM2_struct , TIM5_struct
  • CCR4H : TIM1_struct
  • CCR4L : TIM1_struct
  • CCRH : I2C_struct
  • CCRL : I2C_struct
  • CKDIVR : CLK_struct
  • CMSR : CLK_struct
  • CNTR : TIM4_struct , TIM6_struct
  • CNTRH : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CNTRL : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • Config : CAN_TypeDef
  • CR : WWDG_struct
  • CR1 : TIM2_struct , TIM3_struct , TIM4_struct , UART3_struct , TIM5_struct , I2C_struct , EXTI_struct , FLASH_struct , TIM6_struct , UART1_struct , GPIO_struct , TIM1_struct , SPI_struct , UART2_struct
  • CR2 : EXTI_struct , UART1_struct , UART3_struct , FLASH_struct , I2C_struct , UART2_struct , TIM5_struct , GPIO_struct , TIM1_struct , TIM6_struct , SPI_struct
  • CR3 : UART2_struct , UART3_struct , UART1_struct
  • CR4 : UART2_struct , UART3_struct , UART1_struct
  • CR5 : UART2_struct , UART1_struct
  • CR6 : UART3_struct , UART2_struct
  • CRCPR : SPI_struct
  • CSR : AWU_struct , BEEP_struct
  • CSSR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields

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  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DDR : GPIO_struct
  • DGR : CAN_TypeDef
  • DR : SPI_struct , UART3_struct , UART2_struct , UART1_struct , I2C_struct
  • DTR : TIM1_struct
  • DUKR : FLASH_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • ECKR : CLK_struct
  • EGR : TIM1_struct , TIM3_struct , TIM4_struct , TIM6_struct , TIM5_struct , TIM2_struct
  • EIER : CAN_TypeDef
  • ESR : CAN_TypeDef
  • ETR : TIM1_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • F0R1 : CAN_TypeDef
  • F0R2 : CAN_TypeDef
  • F0R3 : CAN_TypeDef
  • F0R4 : CAN_TypeDef
  • F0R5 : CAN_TypeDef
  • F0R6 : CAN_TypeDef
  • F0R7 : CAN_TypeDef
  • F0R8 : CAN_TypeDef
  • F1R1 : CAN_TypeDef
  • F1R2 : CAN_TypeDef
  • F1R3 : CAN_TypeDef
  • F1R4 : CAN_TypeDef
  • F1R5 : CAN_TypeDef
  • F1R6 : CAN_TypeDef
  • F1R7 : CAN_TypeDef
  • F1R8 : CAN_TypeDef
  • F2R1 : CAN_TypeDef
  • F2R2 : CAN_TypeDef
  • F2R3 : CAN_TypeDef
  • F2R4 : CAN_TypeDef
  • F2R5 : CAN_TypeDef
  • F2R6 : CAN_TypeDef
  • F2R7 : CAN_TypeDef
  • F2R8 : CAN_TypeDef
  • F3R1 : CAN_TypeDef
  • F3R2 : CAN_TypeDef
  • F3R3 : CAN_TypeDef
  • F3R4 : CAN_TypeDef
  • F3R5 : CAN_TypeDef
  • F3R6 : CAN_TypeDef
  • F3R7 : CAN_TypeDef
  • F3R8 : CAN_TypeDef
  • F4R1 : CAN_TypeDef
  • F4R2 : CAN_TypeDef
  • F4R3 : CAN_TypeDef
  • F4R4 : CAN_TypeDef
  • F4R5 : CAN_TypeDef
  • F4R6 : CAN_TypeDef
  • F4R7 : CAN_TypeDef
  • F4R8 : CAN_TypeDef
  • F5R1 : CAN_TypeDef
  • F5R2 : CAN_TypeDef
  • F5R3 : CAN_TypeDef
  • F5R4 : CAN_TypeDef
  • F5R5 : CAN_TypeDef
  • F5R6 : CAN_TypeDef
  • F5R7 : CAN_TypeDef
  • F5R8 : CAN_TypeDef
  • FCR1 : CAN_TypeDef
  • FCR2 : CAN_TypeDef
  • FCR3 : CAN_TypeDef
  • Filter : CAN_TypeDef
  • Filter01 : CAN_TypeDef
  • Filter23 : CAN_TypeDef
  • Filter45 : CAN_TypeDef
  • FMR1 : CAN_TypeDef
  • FMR2 : CAN_TypeDef
  • FPR : FLASH_struct
  • FR01 : CAN_TypeDef
  • FR02 : CAN_TypeDef
  • FR03 : CAN_TypeDef
  • FR04 : CAN_TypeDef
  • FR05 : CAN_TypeDef
  • FR06 : CAN_TypeDef
  • FR07 : CAN_TypeDef
  • FR08 : CAN_TypeDef
  • FR09 : CAN_TypeDef
  • FR10 : CAN_TypeDef
  • FR11 : CAN_TypeDef
  • FR12 : CAN_TypeDef
  • FR13 : CAN_TypeDef
  • FR14 : CAN_TypeDef
  • FR15 : CAN_TypeDef
  • FR16 : CAN_TypeDef
  • FREQR : I2C_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GCR : CFG_struct
  • GTR : UART2_struct , UART1_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • HSITRIMR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • IAPSR : FLASH_struct
  • ICKR : CLK_struct
  • ICR : SPI_struct
  • IDR : GPIO_struct
  • IER : TIM4_struct , TIM5_struct , TIM1_struct , TIM6_struct , CAN_TypeDef , TIM2_struct , TIM3_struct
  • ISPR1 : ITC_struct
  • ISPR2 : ITC_struct
  • ISPR3 : ITC_struct
  • ISPR4 : ITC_struct
  • ISPR5 : ITC_struct
  • ISPR6 : ITC_struct
  • ISPR7 : ITC_struct
  • ISPR8 : ITC_struct
  • ITR : I2C_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • Page : CAN_TypeDef
  • PCKENR1 : CLK_struct
  • PCKENR2 : CLK_struct
  • PR : IWDG_struct
  • PSCR : TIM5_struct , UART2_struct , UART1_struct , TIM6_struct , TIM2_struct , TIM4_struct , TIM3_struct
  • PSCRH : TIM1_struct
  • PSCRL : TIM1_struct
  • PSR : CAN_TypeDef
  • PUKR : FLASH_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RCR : TIM1_struct
  • RECR : CAN_TypeDef
  • RESERVED : UART3_struct , CLK_struct
  • RESERVED1 : OPT_struct
  • Reserved1 : CAN_TypeDef
  • RESERVED1 : CLK_struct , I2C_struct , FLASH_struct
  • RESERVED2 : OPT_struct
  • Reserved2 : CAN_TypeDef
  • RESERVED2 : I2C_struct , FLASH_struct
  • RESERVED3 : FLASH_struct
  • RFR : CAN_TypeDef
  • RLR : IWDG_struct
  • RXCRCR : SPI_struct
  • RxFIFO : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • SMCR : TIM1_struct , TIM5_struct , TIM6_struct
  • SR : RST_struct , UART3_struct , SPI_struct , UART1_struct , UART2_struct
  • SR1 : TIM1_struct , TIM2_struct , I2C_struct , TIM3_struct , TIM4_struct , TIM5_struct , TIM6_struct
  • SR2 : TIM5_struct , TIM3_struct , TIM1_struct , TIM2_struct , I2C_struct
  • SR3 : I2C_struct
  • SWCR : CLK_struct
  • SWIMCCR : CLK_struct
  • SWR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • TBR : AWU_struct
  • TECR : CAN_TypeDef
  • TPR : CAN_TypeDef
  • TRISER : I2C_struct
  • TSR : CAN_TypeDef
  • TXCRCR : SPI_struct
  • TxMailbox : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields

  • Data Structures
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WR : WWDG_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- a -

  • APR : AWU_struct
  • ARR : TIM4_struct , TIM6_struct
  • ARRH : TIM1_struct , TIM2_struct , TIM5_struct , TIM3_struct
  • ARRL : TIM2_struct , TIM5_struct , TIM3_struct , TIM1_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- k -

  • KR : IWDG_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

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- m -

  • MCR : CAN_TypeDef
  • MCSR : CAN_TypeDef
  • MDAR1 : CAN_TypeDef
  • MDAR2 : CAN_TypeDef
  • MDAR3 : CAN_TypeDef
  • MDAR4 : CAN_TypeDef
  • MDAR5 : CAN_TypeDef
  • MDAR6 : CAN_TypeDef
  • MDAR7 : CAN_TypeDef
  • MDAR8 : CAN_TypeDef
  • MDLCR : CAN_TypeDef
  • MFMI : CAN_TypeDef
  • MIDR1 : CAN_TypeDef
  • MIDR2 : CAN_TypeDef
  • MIDR3 : CAN_TypeDef
  • MIDR4 : CAN_TypeDef
  • MSR : CAN_TypeDef
  • MTSRH : CAN_TypeDef
  • MTSRL : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- n -

  • NCR2 : FLASH_struct
  • NFPR : FLASH_struct
  • NOPT1 : OPT_struct
  • NOPT2 : OPT_struct
  • NOPT3 : OPT_struct
  • NOPT4 : OPT_struct
  • NOPT5 : OPT_struct
  • NOPT7 : OPT_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- o -

  • OARH : I2C_struct
  • OARL : I2C_struct
  • ODR : GPIO_struct
  • OISR : TIM1_struct
  • OPT0 : OPT_struct
  • OPT1 : OPT_struct
  • OPT2 : OPT_struct
  • OPT3 : OPT_struct
  • OPT4 : OPT_struct
  • OPT5 : OPT_struct
  • OPT7 : OPT_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- b -

  • BKR : TIM1_struct
  • BRR1 : UART1_struct , UART3_struct , UART2_struct
  • BRR2 : UART2_struct , UART1_struct , UART3_struct
  • BTR1 : CAN_TypeDef
  • BTR2 : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- c -

  • CCER1 : TIM1_struct , TIM2_struct , TIM5_struct , TIM3_struct
  • CCER2 : TIM1_struct , TIM2_struct , TIM5_struct
  • CCMR1 : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCMR2 : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCMR3 : TIM1_struct , TIM2_struct , TIM5_struct
  • CCMR4 : TIM1_struct
  • CCOR : CLK_struct
  • CCR1H : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR1L : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR2H : TIM5_struct , TIM1_struct , TIM2_struct , TIM3_struct
  • CCR2L : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CCR3H : TIM1_struct , TIM2_struct , TIM5_struct
  • CCR3L : TIM1_struct , TIM2_struct , TIM5_struct
  • CCR4H : TIM1_struct
  • CCR4L : TIM1_struct
  • CCRH : I2C_struct
  • CCRL : I2C_struct
  • CKDIVR : CLK_struct
  • CMSR : CLK_struct
  • CNTR : TIM4_struct , TIM6_struct
  • CNTRH : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • CNTRL : TIM1_struct , TIM2_struct , TIM3_struct , TIM5_struct
  • Config : CAN_TypeDef
  • CR : WWDG_struct
  • CR1 : TIM2_struct , TIM3_struct , TIM4_struct , UART3_struct , TIM5_struct , I2C_struct , EXTI_struct , FLASH_struct , TIM6_struct , UART1_struct , GPIO_struct , TIM1_struct , SPI_struct , UART2_struct
  • CR2 : EXTI_struct , UART1_struct , UART3_struct , FLASH_struct , I2C_struct , UART2_struct , TIM5_struct , GPIO_struct , TIM1_struct , TIM6_struct , SPI_struct
  • CR3 : UART2_struct , UART3_struct , UART1_struct
  • CR4 : UART2_struct , UART3_struct , UART1_struct
  • CR5 : UART2_struct , UART1_struct
  • CR6 : UART3_struct , UART2_struct
  • CRCPR : SPI_struct
  • CSR : AWU_struct , BEEP_struct
  • CSSR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- d -

  • DDR : GPIO_struct
  • DGR : CAN_TypeDef
  • DR : SPI_struct , UART3_struct , UART2_struct , UART1_struct , I2C_struct
  • DTR : TIM1_struct
  • DUKR : FLASH_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- e -

  • ECKR : CLK_struct
  • EGR : TIM1_struct , TIM3_struct , TIM4_struct , TIM6_struct , TIM5_struct , TIM2_struct
  • EIER : CAN_TypeDef
  • ESR : CAN_TypeDef
  • ETR : TIM1_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • a
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- f -

  • F0R1 : CAN_TypeDef
  • F0R2 : CAN_TypeDef
  • F0R3 : CAN_TypeDef
  • F0R4 : CAN_TypeDef
  • F0R5 : CAN_TypeDef
  • F0R6 : CAN_TypeDef
  • F0R7 : CAN_TypeDef
  • F0R8 : CAN_TypeDef
  • F1R1 : CAN_TypeDef
  • F1R2 : CAN_TypeDef
  • F1R3 : CAN_TypeDef
  • F1R4 : CAN_TypeDef
  • F1R5 : CAN_TypeDef
  • F1R6 : CAN_TypeDef
  • F1R7 : CAN_TypeDef
  • F1R8 : CAN_TypeDef
  • F2R1 : CAN_TypeDef
  • F2R2 : CAN_TypeDef
  • F2R3 : CAN_TypeDef
  • F2R4 : CAN_TypeDef
  • F2R5 : CAN_TypeDef
  • F2R6 : CAN_TypeDef
  • F2R7 : CAN_TypeDef
  • F2R8 : CAN_TypeDef
  • F3R1 : CAN_TypeDef
  • F3R2 : CAN_TypeDef
  • F3R3 : CAN_TypeDef
  • F3R4 : CAN_TypeDef
  • F3R5 : CAN_TypeDef
  • F3R6 : CAN_TypeDef
  • F3R7 : CAN_TypeDef
  • F3R8 : CAN_TypeDef
  • F4R1 : CAN_TypeDef
  • F4R2 : CAN_TypeDef
  • F4R3 : CAN_TypeDef
  • F4R4 : CAN_TypeDef
  • F4R5 : CAN_TypeDef
  • F4R6 : CAN_TypeDef
  • F4R7 : CAN_TypeDef
  • F4R8 : CAN_TypeDef
  • F5R1 : CAN_TypeDef
  • F5R2 : CAN_TypeDef
  • F5R3 : CAN_TypeDef
  • F5R4 : CAN_TypeDef
  • F5R5 : CAN_TypeDef
  • F5R6 : CAN_TypeDef
  • F5R7 : CAN_TypeDef
  • F5R8 : CAN_TypeDef
  • FCR1 : CAN_TypeDef
  • FCR2 : CAN_TypeDef
  • FCR3 : CAN_TypeDef
  • Filter : CAN_TypeDef
  • Filter01 : CAN_TypeDef
  • Filter23 : CAN_TypeDef
  • Filter45 : CAN_TypeDef
  • FMR1 : CAN_TypeDef
  • FMR2 : CAN_TypeDef
  • FPR : FLASH_struct
  • FR01 : CAN_TypeDef
  • FR02 : CAN_TypeDef
  • FR03 : CAN_TypeDef
  • FR04 : CAN_TypeDef
  • FR05 : CAN_TypeDef
  • FR06 : CAN_TypeDef
  • FR07 : CAN_TypeDef
  • FR08 : CAN_TypeDef
  • FR09 : CAN_TypeDef
  • FR10 : CAN_TypeDef
  • FR11 : CAN_TypeDef
  • FR12 : CAN_TypeDef
  • FR13 : CAN_TypeDef
  • FR14 : CAN_TypeDef
  • FR15 : CAN_TypeDef
  • FR16 : CAN_TypeDef
  • FREQR : I2C_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- g -

  • GCR : CFG_struct
  • GTR : UART2_struct , UART1_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- h -

  • HSITRIMR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- i -

  • IAPSR : FLASH_struct
  • ICKR : CLK_struct
  • ICR : SPI_struct
  • IDR : GPIO_struct
  • IER : TIM4_struct , TIM5_struct , TIM1_struct , TIM6_struct , CAN_TypeDef , TIM2_struct , TIM3_struct
  • ISPR1 : ITC_struct
  • ISPR2 : ITC_struct
  • ISPR3 : ITC_struct
  • ISPR4 : ITC_struct
  • ISPR5 : ITC_struct
  • ISPR6 : ITC_struct
  • ISPR7 : ITC_struct
  • ISPR8 : ITC_struct
  • ITR : I2C_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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- p -

  • Page : CAN_TypeDef
  • PCKENR1 : CLK_struct
  • PCKENR2 : CLK_struct
  • PR : IWDG_struct
  • PSCR : TIM5_struct , UART2_struct , UART1_struct , TIM6_struct , TIM2_struct , TIM4_struct , TIM3_struct
  • PSCRH : TIM1_struct
  • PSCRL : TIM1_struct
  • PSR : CAN_TypeDef
  • PUKR : FLASH_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
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- r -

  • RCR : TIM1_struct
  • RECR : CAN_TypeDef
  • RESERVED : UART3_struct , CLK_struct
  • RESERVED1 : OPT_struct
  • Reserved1 : CAN_TypeDef
  • RESERVED1 : CLK_struct , I2C_struct , FLASH_struct
  • RESERVED2 : OPT_struct
  • Reserved2 : CAN_TypeDef
  • RESERVED2 : I2C_struct , FLASH_struct
  • RESERVED3 : FLASH_struct
  • RFR : CAN_TypeDef
  • RLR : IWDG_struct
  • RXCRCR : SPI_struct
  • RxFIFO : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- s -

  • SMCR : TIM1_struct , TIM5_struct , TIM6_struct
  • SR : RST_struct , UART3_struct , SPI_struct , UART1_struct , UART2_struct
  • SR1 : TIM1_struct , TIM2_struct , I2C_struct , TIM3_struct , TIM4_struct , TIM5_struct , TIM6_struct
  • SR2 : TIM5_struct , TIM3_struct , TIM1_struct , TIM2_struct , I2C_struct
  • SR3 : I2C_struct
  • SWCR : CLK_struct
  • SWIMCCR : CLK_struct
  • SWR : CLK_struct


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- t -

  • TBR : AWU_struct
  • TECR : CAN_TypeDef
  • TPR : CAN_TypeDef
  • TRISER : I2C_struct
  • TSR : CAN_TypeDef
  • TXCRCR : SPI_struct
  • TxMailbox : CAN_TypeDef


STM8S/A Standard Peripherals Drivers: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
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- w -

  • WR : WWDG_struct


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LSI_FREQUENCY_MAX : stm8s_awu.h , stm8s_beep.h
  • LSI_FREQUENCY_MIN : stm8s_beep.h , stm8s_awu.h
  • LSI_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MskBit : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NEAR : stm8s.h
  • nop : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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  • Functions
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OPERATION_TIMEOUT : stm8s_flash.c
  • OPT : stm8s.h
  • OPT_BaseAddress : stm8s.h
  • OPT_TypeDef : stm8s.h
  • OPTION_BYTE_END_PHYSICAL_ADDRESS : stm8s_flash.h
  • OPTION_BYTE_START_PHYSICAL_ADDRESS : stm8s_flash.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ADC1_ALIGN_LEFT : stm8s_adc1.h
  • ADC1_ALIGN_RIGHT : stm8s_adc1.h
  • ADC1_Align_TypeDef : stm8s_adc1.h
  • ADC1_AWDChannelConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_BaseAddress : stm8s.h
  • ADC1_CHANNEL_0 : stm8s_adc1.h
  • ADC1_CHANNEL_1 : stm8s_adc1.h
  • ADC1_CHANNEL_12 : stm8s_adc1.h
  • ADC1_CHANNEL_2 : stm8s_adc1.h
  • ADC1_CHANNEL_3 : stm8s_adc1.h
  • ADC1_CHANNEL_4 : stm8s_adc1.h
  • ADC1_CHANNEL_5 : stm8s_adc1.h
  • ADC1_CHANNEL_6 : stm8s_adc1.h
  • ADC1_CHANNEL_7 : stm8s_adc1.h
  • ADC1_CHANNEL_8 : stm8s_adc1.h
  • ADC1_CHANNEL_9 : stm8s_adc1.h
  • ADC1_Channel_TypeDef : stm8s_adc1.h
  • ADC1_ClearFlag() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ClearITPendingBit() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_Cmd() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ConversionConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_CONVERSIONMODE_CONTINUOUS : stm8s_adc1.h
  • ADC1_CONVERSIONMODE_SINGLE : stm8s_adc1.h
  • ADC1_ConvMode_TypeDef : stm8s_adc1.h
  • ADC1_DataBufferCmd() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_DeInit() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ExternalTriggerConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_EXTTRIG_GPIO : stm8s_adc1.h
  • ADC1_EXTTRIG_TIM : stm8s_adc1.h
  • ADC1_ExtTrig_TypeDef : stm8s_adc1.h
  • ADC1_FLAG_AWD : stm8s_adc1.h
  • ADC1_FLAG_AWS0 : stm8s_adc1.h
  • ADC1_FLAG_AWS1 : stm8s_adc1.h
  • ADC1_FLAG_AWS12 : stm8s_adc1.h
  • ADC1_FLAG_AWS2 : stm8s_adc1.h
  • ADC1_FLAG_AWS3 : stm8s_adc1.h
  • ADC1_FLAG_AWS4 : stm8s_adc1.h
  • ADC1_FLAG_AWS5 : stm8s_adc1.h
  • ADC1_FLAG_AWS6 : stm8s_adc1.h
  • ADC1_FLAG_AWS7 : stm8s_adc1.h
  • ADC1_FLAG_AWS8 : stm8s_adc1.h
  • ADC1_FLAG_AWS9 : stm8s_adc1.h
  • ADC1_FLAG_EOC : stm8s_adc1.h
  • ADC1_FLAG_OVR : stm8s_adc1.h
  • ADC1_Flag_TypeDef : stm8s_adc1.h
  • ADC1_GetAWDChannelStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetBufferValue() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetConversionValue() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetFlagStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetITStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_Init() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_IT_AWD : stm8s_adc1.h
  • ADC1_IT_AWDIE : stm8s_adc1.h
  • ADC1_IT_AWS0 : stm8s_adc1.h
  • ADC1_IT_AWS1 : stm8s_adc1.h
  • ADC1_IT_AWS12 : stm8s_adc1.h
  • ADC1_IT_AWS2 : stm8s_adc1.h
  • ADC1_IT_AWS3 : stm8s_adc1.h
  • ADC1_IT_AWS4 : stm8s_adc1.h
  • ADC1_IT_AWS5 : stm8s_adc1.h
  • ADC1_IT_AWS6 : stm8s_adc1.h
  • ADC1_IT_AWS7 : stm8s_adc1.h
  • ADC1_IT_AWS8 : stm8s_adc1.h
  • ADC1_IT_AWS9 : stm8s_adc1.h
  • ADC1_IT_EOC : stm8s_adc1.h
  • ADC1_IT_EOCIE : stm8s_adc1.h
  • ADC1_IT_TypeDef : stm8s_adc1.h
  • ADC1_ITConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_PrescalerConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_PRESSEL_FCPU_D10 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D12 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D18 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D2 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D3 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D4 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D6 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D8 : stm8s_adc1.h
  • ADC1_PresSel_TypeDef : stm8s_adc1.h
  • ADC1_ScanModeCmd() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SCHMITTTRIG_ALL : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL0 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL1 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL12 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL2 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL3 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL4 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL5 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL6 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL7 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL8 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL9 : stm8s_adc1.h
  • ADC1_SchmittTrigg_TypeDef : stm8s_adc1.h
  • ADC1_SchmittTriggerConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SetHighThreshold() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SetLowThreshold() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_StartConversion() : stm8s_adc1.h , stm8s_adc1.c
  • ADC2_ALIGN_LEFT : stm8s_adc2.h
  • ADC2_ALIGN_RIGHT : stm8s_adc2.h
  • ADC2_Align_TypeDef : stm8s_adc2.h
  • ADC2_BaseAddress : stm8s.h
  • ADC2_CHANNEL_0 : stm8s_adc2.h
  • ADC2_CHANNEL_1 : stm8s_adc2.h
  • ADC2_CHANNEL_10 : stm8s_adc2.h
  • ADC2_CHANNEL_11 : stm8s_adc2.h
  • ADC2_CHANNEL_12 : stm8s_adc2.h
  • ADC2_CHANNEL_13 : stm8s_adc2.h
  • ADC2_CHANNEL_14 : stm8s_adc2.h
  • ADC2_CHANNEL_15 : stm8s_adc2.h
  • ADC2_CHANNEL_2 : stm8s_adc2.h
  • ADC2_CHANNEL_3 : stm8s_adc2.h
  • ADC2_CHANNEL_4 : stm8s_adc2.h
  • ADC2_CHANNEL_5 : stm8s_adc2.h
  • ADC2_CHANNEL_6 : stm8s_adc2.h
  • ADC2_CHANNEL_7 : stm8s_adc2.h
  • ADC2_CHANNEL_8 : stm8s_adc2.h
  • ADC2_CHANNEL_9 : stm8s_adc2.h
  • ADC2_Channel_TypeDef : stm8s_adc2.h
  • ADC2_ClearFlag() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_ClearITPendingBit() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_Cmd() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_ConversionConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_CONVERSIONMODE_CONTINUOUS : stm8s_adc2.h
  • ADC2_CONVERSIONMODE_SINGLE : stm8s_adc2.h
  • ADC2_ConvMode_TypeDef : stm8s_adc2.h
  • ADC2_DeInit() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_ExternalTriggerConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_EXTTRIG_GPIO : stm8s_adc2.h
  • ADC2_EXTTRIG_TIM : stm8s_adc2.h
  • ADC2_ExtTrig_TypeDef : stm8s_adc2.h
  • ADC2_GetConversionValue() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_GetFlagStatus() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_GetITStatus() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_Init() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_ITConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_PrescalerConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_PRESSEL_FCPU_D10 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D12 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D18 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D2 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D3 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D4 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D6 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D8 : stm8s_adc2.h
  • ADC2_PresSel_TypeDef : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_ALL : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL0 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL1 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL10 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL11 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL12 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL13 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL14 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL15 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL2 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL3 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL4 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL5 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL6 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL7 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL8 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL9 : stm8s_adc2.h
  • ADC2_SchmittTrigg_TypeDef : stm8s_adc2.h
  • ADC2_SchmittTriggerConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_StartConversion() : stm8s_adc2.c , stm8s_adc2.h
  • AffBit : stm8s.h
  • APR_Array : stm8s_awu.c
  • AREA : stm8s.h
  • AWU : stm8s.h
  • AWU_APR_APR : stm8s.h
  • AWU_APR_RESET_VALUE : stm8s.h
  • AWU_BaseAddress : stm8s.h
  • AWU_Cmd() : stm8s_awu.h , stm8s_awu.c
  • AWU_CSR_AWUEN : stm8s.h
  • AWU_CSR_AWUF : stm8s.h
  • AWU_CSR_MSR : stm8s.h
  • AWU_CSR_RESET_VALUE : stm8s.h
  • AWU_DeInit() : stm8s_awu.c , stm8s_awu.h
  • AWU_GetFlagStatus() : stm8s_awu.h , stm8s_awu.c
  • AWU_IdleModeEnable() : stm8s_awu.c , stm8s_awu.h
  • AWU_Init() : stm8s_awu.h , stm8s_awu.c
  • AWU_LSICalibrationConfig() : stm8s_awu.c , stm8s_awu.h
  • AWU_TBR_AWUTB : stm8s.h
  • AWU_TBR_RESET_VALUE : stm8s.h
  • AWU_TIMEBASE_128MS : stm8s_awu.h
  • AWU_TIMEBASE_12S : stm8s_awu.h
  • AWU_TIMEBASE_16MS : stm8s_awu.h
  • AWU_TIMEBASE_1MS : stm8s_awu.h
  • AWU_TIMEBASE_1S : stm8s_awu.h
  • AWU_TIMEBASE_250US : stm8s_awu.h
  • AWU_TIMEBASE_256MS : stm8s_awu.h
  • AWU_TIMEBASE_2MS : stm8s_awu.h
  • AWU_TIMEBASE_2S : stm8s_awu.h
  • AWU_TIMEBASE_30S : stm8s_awu.h
  • AWU_TIMEBASE_32MS : stm8s_awu.h
  • AWU_TIMEBASE_4MS : stm8s_awu.h
  • AWU_TIMEBASE_500US : stm8s_awu.h
  • AWU_TIMEBASE_512MS : stm8s_awu.h
  • AWU_TIMEBASE_64MS : stm8s_awu.h
  • AWU_TIMEBASE_8MS : stm8s_awu.h
  • AWU_TIMEBASE_NO_IT : stm8s_awu.h
  • AWU_Timebase_TypeDef : stm8s_awu.h
  • AWU_TypeDef : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
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  • d
  • e
  • f
  • g
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  • i
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BEEP : stm8s.h
  • BEEP_BaseAddress : stm8s.h
  • BEEP_CALIBRATION_DEFAULT : stm8s_beep.h
  • BEEP_Cmd() : stm8s_beep.h , stm8s_beep.c
  • BEEP_CSR_BEEPDIV : stm8s.h
  • BEEP_CSR_BEEPEN : stm8s.h
  • BEEP_CSR_BEEPSEL : stm8s.h
  • BEEP_CSR_RESET_VALUE : stm8s.h
  • BEEP_DeInit() : stm8s_beep.h , stm8s_beep.c
  • BEEP_FREQUENCY_1KHZ : stm8s_beep.h
  • BEEP_FREQUENCY_2KHZ : stm8s_beep.h
  • BEEP_FREQUENCY_4KHZ : stm8s_beep.h
  • BEEP_Frequency_TypeDef : stm8s_beep.h
  • BEEP_Init() : stm8s_beep.h , stm8s_beep.c
  • BEEP_LSICalibrationConfig() : stm8s_beep.h , stm8s_beep.c
  • BEEP_TypeDef : stm8s.h
  • BIT_MASK : stm8s_wwdg.c
  • BitAction : stm8s.h
  • BitClr : stm8s.h
  • BitSet : stm8s.h
  • BitStatus : stm8s.h
  • BitVal : stm8s.h
  • bool : stm8s.h
  • BYTE_0 : stm8s.h
  • BYTE_1 : stm8s.h
  • BYTE_2 : stm8s.h
  • BYTE_3 : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CAN_ACKNOWLEDGE_TIMEOUT : stm8s_can.c
  • CAN_BaseAddress : stm8s.h
  • CAN_BitSeg1_10TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_11TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_12TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_13TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_14TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_15TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_16TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_1TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_2TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_3TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_4TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_5TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_6TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_7TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_8TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_9TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_TypeDef : stm8s_can.h
  • CAN_BitSeg2_1TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_2TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_3TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_4TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_5TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_6TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_7TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_8TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_TypeDef : stm8s_can.h
  • CAN_BTR1_RESET_VALUE : stm8s.h
  • CAN_BTR2_RESET_VALUE : stm8s.h
  • CAN_CancelTransmit() : stm8s_can.c , stm8s_can.h
  • CAN_ClearFlag() : stm8s_can.h , stm8s_can.c
  • CAN_ClearITPendingBit() : stm8s_can.h , stm8s_can.c
  • CAN_DeInit() : stm8s_can.h , stm8s_can.c
  • CAN_DGR_LBKM : stm8s.h
  • CAN_DGR_RESET_VALUE : stm8s.h
  • CAN_DGR_RX : stm8s.h
  • CAN_DGR_SAMP : stm8s.h
  • CAN_DGR_SLIM : stm8s.h
  • CAN_DGR_TXM2E : stm8s.h
  • CAN_DLC_MAX : stm8s_can.h
  • CAN_EIER_BOFIE : stm8s.h
  • CAN_EIER_EPVIE : stm8s.h
  • CAN_EIER_ERRIE : stm8s.h
  • CAN_EIER_EWGIE : stm8s.h
  • CAN_EIER_LECIE : stm8s.h
  • CAN_EIER_RESET_VALUE : stm8s.h
  • CAN_ErrorCode_ACKErr : stm8s_can.h
  • CAN_ErrorCode_BitDominantErr : stm8s_can.h
  • CAN_ErrorCode_BitRecessiveErr : stm8s_can.h
  • CAN_ErrorCode_CRCErr : stm8s_can.h
  • CAN_ErrorCode_FormErr : stm8s_can.h
  • CAN_ErrorCode_NoErr : stm8s_can.h
  • CAN_ErrorCode_SoftwareSetErr : stm8s_can.h
  • CAN_ErrorCode_StuffErr : stm8s_can.h
  • CAN_ErrorCode_TypeDef : stm8s_can.h
  • CAN_ESR_BOFF : stm8s.h
  • CAN_ESR_EPVF : stm8s.h
  • CAN_ESR_EWGF : stm8s.h
  • CAN_ESR_LEC : stm8s.h
  • CAN_ESR_LEC0 : stm8s.h
  • CAN_ESR_LEC1 : stm8s.h
  • CAN_ESR_LEC2 : stm8s.h
  • CAN_ESR_RESET_VALUE : stm8s.h
  • CAN_EXTID_SIZE : stm8s_can.h
  • CAN_FCR1_FACT0 : stm8s.h
  • CAN_FCR1_FACT1 : stm8s.h
  • CAN_FCR1_FSC00 : stm8s.h
  • CAN_FCR1_FSC01 : stm8s.h
  • CAN_FCR1_FSC10 : stm8s.h
  • CAN_FCR1_FSC11 : stm8s.h
  • CAN_FCR2_FACT2 : stm8s.h
  • CAN_FCR2_FACT3 : stm8s.h
  • CAN_FCR2_FSC20 : stm8s.h
  • CAN_FCR2_FSC21 : stm8s.h
  • CAN_FCR2_FSC30 : stm8s.h
  • CAN_FCR2_FSC31 : stm8s.h
  • CAN_FCR3_FACT4 : stm8s.h
  • CAN_FCR3_FACT5 : stm8s.h
  • CAN_FCR3_FSC40 : stm8s.h
  • CAN_FCR3_FSC41 : stm8s.h
  • CAN_FCR3_FSC50 : stm8s.h
  • CAN_FCR3_FSC51 : stm8s.h
  • CAN_FCR_RESET_VALUE : stm8s.h
  • CAN_FIFORelease() : stm8s_can.h , stm8s_can.c
  • CAN_FilterInit() : stm8s_can.h , stm8s_can.c
  • CAN_FilterMode_IdList : stm8s_can.h
  • CAN_FilterMode_IdList_IdMask : stm8s_can.h
  • CAN_FilterMode_IdMask : stm8s_can.h
  • CAN_FilterMode_IdMask_IdList : stm8s_can.h
  • CAN_FilterMode_TypeDef : stm8s_can.h
  • CAN_FilterNumber_0 : stm8s_can.h
  • CAN_FilterNumber_1 : stm8s_can.h
  • CAN_FilterNumber_2 : stm8s_can.h
  • CAN_FilterNumber_3 : stm8s_can.h
  • CAN_FilterNumber_4 : stm8s_can.h
  • CAN_FilterNumber_5 : stm8s_can.h
  • CAN_FilterNumber_TypeDef : stm8s_can.h
  • CAN_FilterScale_16_8Bit : stm8s_can.h
  • CAN_FilterScale_16Bit : stm8s_can.h
  • CAN_FilterScale_32Bit : stm8s_can.h
  • CAN_FilterScale_8Bit : stm8s_can.h
  • CAN_FilterScale_TypeDef : stm8s_can.h
  • CAN_FLAG_BOF : stm8s_can.h
  • CAN_FLAG_EPV : stm8s_can.h
  • CAN_FLAG_EWG : stm8s_can.h
  • CAN_FLAG_FF : stm8s_can.h
  • CAN_FLAG_FMP : stm8s_can.h
  • CAN_FLAG_FOV : stm8s_can.h
  • CAN_FLAG_LEC : stm8s_can.h
  • CAN_FLAG_RQCP0 : stm8s_can.h
  • CAN_FLAG_RQCP1 : stm8s_can.h
  • CAN_FLAG_RQCP2 : stm8s_can.h
  • CAN_FLAG_TypeDef : stm8s_can.h
  • CAN_FLAG_WKU : stm8s_can.h
  • CAN_FMR1_FMH0 : stm8s.h
  • CAN_FMR1_FMH1 : stm8s.h
  • CAN_FMR1_FMH2 : stm8s.h
  • CAN_FMR1_FMH3 : stm8s.h
  • CAN_FMR1_FML0 : stm8s.h
  • CAN_FMR1_FML1 : stm8s.h
  • CAN_FMR1_FML2 : stm8s.h
  • CAN_FMR1_FML3 : stm8s.h
  • CAN_FMR1_RESET_VALUE : stm8s.h
  • CAN_FMR2_FMH4 : stm8s.h
  • CAN_FMR2_FMH5 : stm8s.h
  • CAN_FMR2_FML4 : stm8s.h
  • CAN_FMR2_FML5 : stm8s.h
  • CAN_FMR2_RESET_VALUE : stm8s.h
  • CAN_GetFlagStatus() : stm8s_can.h , stm8s_can.c
  • CAN_GetITStatus() : stm8s_can.h , stm8s_can.c
  • CAN_GetLastErrorCode() : stm8s_can.h , stm8s_can.c
  • CAN_GetMessageTimeStamp() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedData() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedDLC() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedFMI() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedId() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedIDE() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedRTR() : stm8s_can.h , stm8s_can.c
  • CAN_GetSelectedPage() : stm8s_can.h , stm8s_can.c
  • CAN_Id_Extended : stm8s_can.h
  • CAN_Id_Standard : stm8s_can.h
  • CAN_Id_TypeDef : stm8s_can.h
  • CAN_IDLIST_IDMASK_MASK : stm8s_can.c
  • CAN_IDMASK_IDLIST_MASK : stm8s_can.c
  • CAN_IER_FFIE : stm8s.h
  • CAN_IER_FMPIE : stm8s.h
  • CAN_IER_FOVIE : stm8s.h
  • CAN_IER_RESET_VALUE : stm8s.h
  • CAN_IER_TMEIE : stm8s.h
  • CAN_IER_WKUIE : stm8s.h
  • CAN_Init() : stm8s_can.h , stm8s_can.c
  • CAN_InitStatus_Failed : stm8s_can.h
  • CAN_InitStatus_Success : stm8s_can.h
  • CAN_InitStatus_TypeDef : stm8s_can.h
  • CAN_IT_BOF : stm8s_can.h
  • CAN_IT_CONFIG_MASK : stm8s_can.h
  • CAN_IT_EPV : stm8s_can.h
  • CAN_IT_ERR : stm8s_can.h
  • CAN_IT_EWG : stm8s_can.h
  • CAN_IT_FF : stm8s_can.h
  • CAN_IT_FMP : stm8s_can.h
  • CAN_IT_FOV : stm8s_can.h
  • CAN_IT_LEC : stm8s_can.h
  • CAN_IT_TME : stm8s_can.h
  • CAN_IT_TypeDef : stm8s_can.h
  • CAN_IT_WKU : stm8s_can.h
  • CAN_ITConfig() : stm8s_can.h , stm8s_can.c
  • CAN_MasterCtrl_AllDisabled : stm8s_can.h
  • CAN_MasterCtrl_AllEnabled : stm8s_can.h
  • CAN_MasterCtrl_AutoBusOffManagement : stm8s_can.h
  • CAN_MasterCtrl_AutoWakeUpMode : stm8s_can.h
  • CAN_MasterCtrl_NoAutoReTx : stm8s_can.h
  • CAN_MasterCtrl_RxFifoLockedMode : stm8s_can.h
  • CAN_MasterCtrl_TimeTriggerCOMMode : stm8s_can.h
  • CAN_MasterCtrl_TxFifoPriority : stm8s_can.h
  • CAN_MasterCtrl_TypeDef : stm8s_can.h
  • CAN_MCR_ABOM : stm8s.h
  • CAN_MCR_AWUM : stm8s.h
  • CAN_MCR_INRQ : stm8s.h
  • CAN_MCR_NART : stm8s.h
  • CAN_MCR_RESET_VALUE : stm8s.h
  • CAN_MCR_RFLM : stm8s.h
  • CAN_MCR_SLEEP : stm8s.h
  • CAN_MCR_TTCM : stm8s.h
  • CAN_MCR_TXFP : stm8s.h
  • CAN_MCSR_ABRQ : stm8s.h
  • CAN_MCSR_ALST : stm8s.h
  • CAN_MCSR_RESET_VALUE : stm8s.h
  • CAN_MCSR_RQCP : stm8s.h
  • CAN_MCSR_TERR : stm8s.h
  • CAN_MCSR_TXOK : stm8s.h
  • CAN_MCSR_TXRQ : stm8s.h
  • CAN_MDLC_RESET_VALUE : stm8s.h
  • CAN_MDLCR_DLC : stm8s.h
  • CAN_MDLCR_TGT : stm8s.h
  • CAN_MessagePending() : stm8s_can.h , stm8s_can.c
  • CAN_MFMI_RESET_VALUE : stm8s.h
  • CAN_MIDR1_IDE : stm8s.h
  • CAN_MIDR1_RTR : stm8s.h
  • CAN_Mode_LoopBack : stm8s_can.h
  • CAN_MODE_MASK : stm8s_can.c
  • CAN_Mode_Normal : stm8s_can.h
  • CAN_Mode_Silent : stm8s_can.h
  • CAN_Mode_Silent_LoopBack : stm8s_can.h
  • CAN_Mode_TypeDef : stm8s_can.h
  • CAN_ModeStatus_Failed : stm8s_can.h
  • CAN_ModeStatus_Success : stm8s_can.h
  • CAN_ModeStatus_TypeDef : stm8s_can.h
  • CAN_MSR_ERRI : stm8s.h
  • CAN_MSR_INAK : stm8s.h
  • CAN_MSR_RESET_VALUE : stm8s.h
  • CAN_MSR_RX : stm8s.h
  • CAN_MSR_SLAK : stm8s.h
  • CAN_MSR_TX : stm8s.h
  • CAN_MSR_WKUI : stm8s.h
  • CAN_NbrPendingMessage_0 : stm8s_can.h
  • CAN_NbrPendingMessage_1 : stm8s_can.h
  • CAN_NbrPendingMessage_2 : stm8s_can.h
  • CAN_NbrPendingMessage_3 : stm8s_can.h
  • CAN_NbrPendingMessage_TypeDef : stm8s_can.h
  • CAN_OperatingMode_Initialization : stm8s_can.h
  • CAN_OperatingMode_Normal : stm8s_can.h
  • CAN_OperatingMode_Sleep : stm8s_can.h
  • CAN_OperatingMode_TypeDef : stm8s_can.h
  • CAN_OperatingModeRequest() : stm8s_can.h , stm8s_can.c
  • CAN_Page_Config : stm8s_can.h
  • CAN_Page_Filter01 : stm8s_can.h
  • CAN_Page_Filter23 : stm8s_can.h
  • CAN_Page_Filter45 : stm8s_can.h
  • CAN_Page_RxFifo : stm8s_can.h
  • CAN_Page_TxMailBox0 : stm8s_can.h
  • CAN_Page_TxMailBox1 : stm8s_can.h
  • CAN_Page_TxMailBox2 : stm8s_can.h
  • CAN_Page_TypeDef : stm8s_can.h
  • CAN_PSR_PS0 : stm8s.h
  • CAN_PSR_PS1 : stm8s.h
  • CAN_PSR_PS2 : stm8s.h
  • CAN_PSR_RESET_VALUE : stm8s.h
  • CAN_Receive() : stm8s_can.h , stm8s_can.c
  • CAN_RECR_REC0 : stm8s.h
  • CAN_RECR_REC1 : stm8s.h
  • CAN_RECR_REC2 : stm8s.h
  • CAN_RECR_REC3 : stm8s.h
  • CAN_RECR_REC4 : stm8s.h
  • CAN_RECR_REC5 : stm8s.h
  • CAN_RECR_REC6 : stm8s.h
  • CAN_RECR_REC7 : stm8s.h
  • CAN_RECR_RESET_VALUE : stm8s.h
  • CAN_RFR_FMP01 : stm8s.h
  • CAN_RFR_FOVR : stm8s.h
  • CAN_RFR_FULL : stm8s.h
  • CAN_RFR_RESET_VALUE : stm8s.h
  • CAN_RFR_RFOM : stm8s.h
  • CAN_RTR_Data : stm8s_can.h
  • CAN_RTR_Remote : stm8s_can.h
  • CAN_RTR_TypeDef : stm8s_can.h
  • CAN_SelectPage() : stm8s_can.h , stm8s_can.c
  • CAN_Sleep() : stm8s_can.c , stm8s_can.h
  • CAN_Sleep_Failed : stm8s_can.h
  • CAN_Sleep_Ok : stm8s_can.h
  • CAN_Sleep_TypeDef : stm8s_can.h
  • CAN_ST7Compatibility_Disable : stm8s_can.h
  • CAN_ST7Compatibility_Enable : stm8s_can.h
  • CAN_ST7Compatibility_TypeDef : stm8s_can.h
  • CAN_ST7CompatibilityCmd() : stm8s_can.h , stm8s_can.c
  • CAN_STDID_SIZE : stm8s_can.h
  • CAN_SynJumpWidth_1TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_2TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_3TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_4TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_TypeDef : stm8s_can.h
  • CAN_TECR_RESET_VALUE : stm8s.h
  • CAN_TECR_TEC0 : stm8s.h
  • CAN_TECR_TEC1 : stm8s.h
  • CAN_TECR_TEC2 : stm8s.h
  • CAN_TECR_TEC3 : stm8s.h
  • CAN_TECR_TEC4 : stm8s.h
  • CAN_TECR_TEC5 : stm8s.h
  • CAN_TECR_TEC6 : stm8s.h
  • CAN_TECR_TEC7 : stm8s.h
  • CAN_TPR_CODE0 : stm8s.h
  • CAN_TPR_LOW0 : stm8s.h
  • CAN_TPR_LOW1 : stm8s.h
  • CAN_TPR_LOW2 : stm8s.h
  • CAN_TPR_RESET_VALUE : stm8s.h
  • CAN_TPR_TME0 : stm8s.h
  • CAN_TPR_TME1 : stm8s.h
  • CAN_TPR_TME2 : stm8s.h
  • CAN_Transmit() : stm8s_can.c , stm8s_can.h
  • CAN_TransmitMailBox_0 : stm8s_can.h
  • CAN_TransmitMailBox_1 : stm8s_can.h
  • CAN_TransmitMailBox_2 : stm8s_can.h
  • CAN_TransmitMailBox_TypeDef : stm8s_can.h
  • CAN_TransmitStatus() : stm8s_can.h , stm8s_can.c
  • CAN_TSR_RESET_VALUE : stm8s.h
  • CAN_TSR_RQCP0 : stm8s.h
  • CAN_TSR_RQCP012 : stm8s.h
  • CAN_TSR_RQCP1 : stm8s.h
  • CAN_TSR_RQCP2 : stm8s.h
  • CAN_TSR_TXOK0 : stm8s.h
  • CAN_TSR_TXOK1 : stm8s.h
  • CAN_TSR_TXOK2 : stm8s.h
  • CAN_TTComModeCmd() : stm8s_can.c , stm8s_can.h
  • CAN_TxStatus_Failed : stm8s_can.h
  • CAN_TxStatus_MailBox0Ok : stm8s_can.h
  • CAN_TxStatus_MailBox1Ok : stm8s_can.h
  • CAN_TxStatus_MailBox2Ok : stm8s_can.h
  • CAN_TxStatus_MailBoxEmpty : stm8s_can.h
  • CAN_TxStatus_NoMailBox : stm8s_can.h
  • CAN_TxStatus_Ok : stm8s_can.h
  • CAN_TxStatus_Pending : stm8s_can.h
  • CAN_TxStatus_TypeDef : stm8s_can.h
  • CAN_WakeUp() : stm8s_can.h , stm8s_can.c
  • CAN_WakeUp_Failed : stm8s_can.h
  • CAN_WakeUp_Ok : stm8s_can.h
  • CAN_WakeUp_TypeDef : stm8s_can.h
  • CCMR_TIxDirect_Set : stm8s.h
  • CFG : stm8s.h
  • CFG_BaseAddress : stm8s.h
  • CFG_GCR_AL : stm8s.h
  • CFG_GCR_RESET_VALUE : stm8s.h
  • CFG_GCR_SWD : stm8s.h
  • CFG_TypeDef : stm8s.h
  • CheckITStatus() : stm8s_can.c
  • ChgBit : stm8s.h
  • CLK : stm8s.h
  • CLK_AdjustHSICalibrationValue() : stm8s_clk.h , stm8s_clk.c
  • CLK_BaseAddress : stm8s.h
  • CLK_CCOCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_CCOConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_CCOR_CCOBSY : stm8s.h
  • CLK_CCOR_CCOEN : stm8s.h
  • CLK_CCOR_CCORDY : stm8s.h
  • CLK_CCOR_CCOSEL : stm8s.h
  • CLK_CCOR_RESET_VALUE : stm8s.h
  • CLK_CKDIVR_CPUDIV : stm8s.h
  • CLK_CKDIVR_HSIDIV : stm8s.h
  • CLK_CKDIVR_RESET_VALUE : stm8s.h
  • CLK_ClearITPendingBit() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSecuritySystemEnable() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSwitchCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSwitchConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_CMSR_CKM : stm8s.h
  • CLK_CMSR_RESET_VALUE : stm8s.h
  • CLK_CSSCONFIG_DISABLE : stm8s_clk.h
  • CLK_CSSCONFIG_ENABLE : stm8s_clk.h
  • CLK_CSSCONFIG_ENABLEWITHIT : stm8s_clk.h
  • CLK_CSSConfig_TypeDef : stm8s_clk.h
  • CLK_CSSR_AUX : stm8s.h
  • CLK_CSSR_CSSD : stm8s.h
  • CLK_CSSR_CSSDIE : stm8s.h
  • CLK_CSSR_CSSEN : stm8s.h
  • CLK_CSSR_RESET_VALUE : stm8s.h
  • CLK_CURRENTCLOCKSTATE_DISABLE : stm8s_clk.h
  • CLK_CURRENTCLOCKSTATE_ENABLE : stm8s_clk.h
  • CLK_CurrentClockState_TypeDef : stm8s_clk.h
  • CLK_DeInit() : stm8s_clk.h , stm8s_clk.c
  • CLK_ECKR_HSEEN : stm8s.h
  • CLK_ECKR_HSERDY : stm8s.h
  • CLK_ECKR_RESET_VALUE : stm8s.h
  • CLK_FastHaltWakeUpCmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_FLAG_AUX : stm8s_clk.h
  • CLK_FLAG_CCOBSY : stm8s_clk.h
  • CLK_FLAG_CCORDY : stm8s_clk.h
  • CLK_FLAG_CSSD : stm8s_clk.h
  • CLK_FLAG_HSERDY : stm8s_clk.h
  • CLK_FLAG_HSIRDY : stm8s_clk.h
  • CLK_FLAG_LSIRDY : stm8s_clk.h
  • CLK_FLAG_SWBSY : stm8s_clk.h
  • CLK_FLAG_SWIF : stm8s_clk.h
  • CLK_Flag_TypeDef : stm8s_clk.h
  • CLK_GetClockFreq() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetFlagStatus() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetITStatus() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetSYSCLKSource() : stm8s_clk.c , stm8s_clk.h
  • CLK_HSECmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_HSICmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_HSIPrescalerConfig() : stm8s_clk.c , stm8s_clk.h
  • CLK_HSITRIMR_HSITRIM : stm8s.h
  • CLK_HSITRIMR_RESET_VALUE : stm8s.h
  • CLK_HSITRIMVALUE_0 : stm8s_clk.h
  • CLK_HSITRIMVALUE_1 : stm8s_clk.h
  • CLK_HSITRIMVALUE_2 : stm8s_clk.h
  • CLK_HSITRIMVALUE_3 : stm8s_clk.h
  • CLK_HSITRIMVALUE_4 : stm8s_clk.h
  • CLK_HSITRIMVALUE_5 : stm8s_clk.h
  • CLK_HSITRIMVALUE_6 : stm8s_clk.h
  • CLK_HSITRIMVALUE_7 : stm8s_clk.h
  • CLK_HSITrimValue_TypeDef : stm8s_clk.h
  • CLK_ICKR_FHWU : stm8s.h
  • CLK_ICKR_HSIEN : stm8s.h
  • CLK_ICKR_HSIRDY : stm8s.h
  • CLK_ICKR_LSIEN : stm8s.h
  • CLK_ICKR_LSIRDY : stm8s.h
  • CLK_ICKR_RESET_VALUE : stm8s.h
  • CLK_ICKR_SWUAH : stm8s.h
  • CLK_IT_CSSD : stm8s_clk.h
  • CLK_IT_SWIF : stm8s_clk.h
  • CLK_IT_TypeDef : stm8s_clk.h
  • CLK_ITConfig() : stm8s_clk.c , stm8s_clk.h
  • CLK_LSICmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_OUTPUT_CPU : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV16 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV2 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV32 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV4 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV64 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV8 : stm8s_clk.h
  • CLK_OUTPUT_HSE : stm8s_clk.h
  • CLK_OUTPUT_HSI : stm8s_clk.h
  • CLK_OUTPUT_HSIRC : stm8s_clk.h
  • CLK_OUTPUT_LSI : stm8s_clk.h
  • CLK_OUTPUT_MASTER : stm8s_clk.h
  • CLK_OUTPUT_OTHERS : stm8s_clk.h
  • CLK_Output_TypeDef : stm8s_clk.h
  • CLK_PCKENR1_I2C : stm8s.h
  • CLK_PCKENR1_RESET_VALUE : stm8s.h
  • CLK_PCKENR1_SPI : stm8s.h
  • CLK_PCKENR1_TIM1 : stm8s.h
  • CLK_PCKENR1_TIM2 : stm8s.h
  • CLK_PCKENR1_TIM3 : stm8s.h
  • CLK_PCKENR1_TIM4 : stm8s.h
  • CLK_PCKENR1_TIM5 : stm8s.h
  • CLK_PCKENR1_TIM6 : stm8s.h
  • CLK_PCKENR1_UART1 : stm8s.h
  • CLK_PCKENR1_UART2 : stm8s.h
  • CLK_PCKENR1_UART3 : stm8s.h
  • CLK_PCKENR2_ADC : stm8s.h
  • CLK_PCKENR2_AWU : stm8s.h
  • CLK_PCKENR2_CAN : stm8s.h
  • CLK_PCKENR2_RESET_VALUE : stm8s.h
  • CLK_PERIPHERAL_ADC : stm8s_clk.h
  • CLK_PERIPHERAL_AWU : stm8s_clk.h
  • CLK_PERIPHERAL_CAN : stm8s_clk.h
  • CLK_PERIPHERAL_I2C : stm8s_clk.h
  • CLK_PERIPHERAL_SPI : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER1 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER2 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER3 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER4 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER5 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER6 : stm8s_clk.h
  • CLK_Peripheral_TypeDef : stm8s_clk.h
  • CLK_PERIPHERAL_UART1 : stm8s_clk.h
  • CLK_PERIPHERAL_UART2 : stm8s_clk.h
  • CLK_PERIPHERAL_UART3 : stm8s_clk.h
  • CLK_PeripheralClockConfig() : stm8s_clk.c , stm8s_clk.h
  • CLK_PRESCALER_CPUDIV1 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV128 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV16 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV2 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV32 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV4 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV64 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV8 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV1 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV2 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV4 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV8 : stm8s_clk.h
  • CLK_Prescaler_TypeDef : stm8s_clk.h
  • CLK_SlowActiveHaltWakeUpCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_SOURCE_HSE : stm8s_clk.h
  • CLK_SOURCE_HSI : stm8s_clk.h
  • CLK_SOURCE_LSI : stm8s_clk.h
  • CLK_Source_TypeDef : stm8s_clk.h
  • CLK_SWCR_RESET_VALUE : stm8s.h
  • CLK_SWCR_SWBSY : stm8s.h
  • CLK_SWCR_SWEN : stm8s.h
  • CLK_SWCR_SWIEN : stm8s.h
  • CLK_SWCR_SWIF : stm8s.h
  • CLK_SWIMCCR_RESET_VALUE : stm8s.h
  • CLK_SWIMCCR_SWIMDIV : stm8s.h
  • CLK_SWIMConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_SWIMDIVIDER_2 : stm8s_clk.h
  • CLK_SWIMDIVIDER_OTHER : stm8s_clk.h
  • CLK_SWIMDivider_TypeDef : stm8s_clk.h
  • CLK_SWITCHMODE_AUTO : stm8s_clk.h
  • CLK_SWITCHMODE_MANUAL : stm8s_clk.h
  • CLK_SwitchMode_TypeDef : stm8s_clk.h
  • CLK_SWR_RESET_VALUE : stm8s.h
  • CLK_SWR_SWI : stm8s.h
  • CLK_SYSCLKConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_SYSCLKEmergencyClear() : stm8s_clk.c , stm8s_clk.h
  • CLK_TIMEOUT : stm8s_clk.h
  • CLK_TypeDef : stm8s.h
  • CLKPrescTable : stm8s_clk.c
  • ClrBit : stm8s.h
  • CONST : stm8s.h
  • CPU_CC_I1I0 : stm8s.h
  • CPU_SOFT_INT_DISABLED : stm8s_itc.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DISABLE : stm8s.h
  • disableInterrupts : stm8s.h
  • DM : stm8s.h
  • DM_BaseAddress : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • EEPROM : stm8s.h
  • ENABLE : stm8s.h
  • enableInterrupts : stm8s.h
  • ERROR : stm8s.h
  • ErrorStatus : stm8s.h
  • EXTI : stm8s.h
  • EXTI_BaseAddress : stm8s.h
  • EXTI_CR1_PAIS : stm8s.h
  • EXTI_CR1_PBIS : stm8s.h
  • EXTI_CR1_PCIS : stm8s.h
  • EXTI_CR1_PDIS : stm8s.h
  • EXTI_CR1_RESET_VALUE : stm8s.h
  • EXTI_CR2_PEIS : stm8s.h
  • EXTI_CR2_RESET_VALUE : stm8s.h
  • EXTI_CR2_TLIS : stm8s.h
  • EXTI_DeInit() : stm8s_exti.h , stm8s_exti.c
  • EXTI_GetExtIntSensitivity() : stm8s_exti.h , stm8s_exti.c
  • EXTI_GetTLISensitivity() : stm8s_exti.h , stm8s_exti.c
  • EXTI_PORT_GPIOA : stm8s_exti.h
  • EXTI_PORT_GPIOB : stm8s_exti.h
  • EXTI_PORT_GPIOC : stm8s_exti.h
  • EXTI_PORT_GPIOD : stm8s_exti.h
  • EXTI_PORT_GPIOE : stm8s_exti.h
  • EXTI_Port_TypeDef : stm8s_exti.h
  • EXTI_SENSITIVITY_FALL_LOW : stm8s_exti.h
  • EXTI_SENSITIVITY_FALL_ONLY : stm8s_exti.h
  • EXTI_SENSITIVITY_RISE_FALL : stm8s_exti.h
  • EXTI_SENSITIVITY_RISE_ONLY : stm8s_exti.h
  • EXTI_Sensitivity_TypeDef : stm8s_exti.h
  • EXTI_SetExtIntSensitivity() : stm8s_exti.h , stm8s_exti.c
  • EXTI_SetTLISensitivity() : stm8s_exti.c , stm8s_exti.h
  • EXTI_TLISENSITIVITY_FALL_ONLY : stm8s_exti.h
  • EXTI_TLISENSITIVITY_RISE_ONLY : stm8s_exti.h
  • EXTI_TLISensitivity_TypeDef : stm8s_exti.h
  • EXTI_TypeDef : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALSE : stm8s.h
  • FAR : stm8s.h
  • FLAG_Mask : stm8s_i2c.c
  • FlagStatus : stm8s.h
  • FLASH : stm8s.h
  • FLASH_BaseAddress : stm8s.h
  • FLASH_CLEAR_BYTE : stm8s_flash.c
  • FLASH_CR1_AHALT : stm8s.h
  • FLASH_CR1_FIX : stm8s.h
  • FLASH_CR1_HALT : stm8s.h
  • FLASH_CR1_IE : stm8s.h
  • FLASH_CR1_RESET_VALUE : stm8s.h
  • FLASH_CR2_ERASE : stm8s.h
  • FLASH_CR2_FPRG : stm8s.h
  • FLASH_CR2_OPT : stm8s.h
  • FLASH_CR2_PRG : stm8s.h
  • FLASH_CR2_RESET_VALUE : stm8s.h
  • FLASH_CR2_WPRG : stm8s.h
  • FLASH_DeInit() : stm8s_flash.h , stm8s_flash.c
  • FLASH_DUKR_DUK : stm8s.h
  • FLASH_DUKR_RESET_VALUE : stm8s.h
  • FLASH_EraseByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_EraseOptionByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_FLAG_DUL : stm8s_flash.h
  • FLASH_FLAG_EOP : stm8s_flash.h
  • FLASH_FLAG_PUL : stm8s_flash.h
  • FLASH_Flag_TypeDef : stm8s_flash.h
  • FLASH_FLAG_WR_PG_DIS : stm8s_flash.h
  • FLASH_GetBootSize() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetFlagStatus() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetLowPowerMode() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetProgrammingTime() : stm8s_flash.h , stm8s_flash.c
  • FLASH_IAPSR_DUL : stm8s.h
  • FLASH_IAPSR_EOP : stm8s.h
  • FLASH_IAPSR_HVOFF : stm8s.h
  • FLASH_IAPSR_PUL : stm8s.h
  • FLASH_IAPSR_RESET_VALUE : stm8s.h
  • FLASH_IAPSR_WR_PG_DIS : stm8s.h
  • FLASH_ITConfig() : stm8s_flash.h , stm8s_flash.c
  • FLASH_Lock() : stm8s_flash.h , stm8s_flash.c
  • FLASH_LPMODE_POWERDOWN : stm8s_flash.h
  • FLASH_LPMODE_POWERDOWN_STANDBY : stm8s_flash.h
  • FLASH_LPMODE_STANDBY : stm8s_flash.h
  • FLASH_LPMODE_STANDBY_POWERDOWN : stm8s_flash.h
  • FLASH_LPMode_TypeDef : stm8s_flash.h
  • FLASH_MEMTYPE_DATA : stm8s_flash.h
  • FLASH_MEMTYPE_PROG : stm8s_flash.h
  • FLASH_MemType_TypeDef : stm8s_flash.h
  • FLASH_NCR2_NERASE : stm8s.h
  • FLASH_NCR2_NFPRG : stm8s.h
  • FLASH_NCR2_NOPT : stm8s.h
  • FLASH_NCR2_NPRG : stm8s.h
  • FLASH_NCR2_NWPRG : stm8s.h
  • FLASH_NCR2_RESET_VALUE : stm8s.h
  • FLASH_OPTIONBYTE_ERROR : stm8s_flash.h
  • FLASH_PROG_START_PHYSICAL_ADDRESS : stm8s_flash.h
  • FLASH_ProgramByte() : stm8s_flash.c , stm8s_flash.h
  • FLASH_PROGRAMMODE_FAST : stm8s_flash.h
  • FLASH_PROGRAMMODE_STANDARD : stm8s_flash.h
  • FLASH_ProgramMode_TypeDef : stm8s_flash.h
  • FLASH_ProgramOptionByte() : stm8s_flash.c , stm8s_flash.h
  • FLASH_PROGRAMTIME_STANDARD : stm8s_flash.h
  • FLASH_PROGRAMTIME_TPROG : stm8s_flash.h
  • FLASH_ProgramTime_TypeDef : stm8s_flash.h
  • FLASH_ProgramWord() : stm8s_flash.h , stm8s_flash.c
  • FLASH_PUKR_PUK : stm8s.h
  • FLASH_PUKR_RESET_VALUE : stm8s.h
  • FLASH_RASS_KEY1 : stm8s_flash.h
  • FLASH_RASS_KEY2 : stm8s_flash.h
  • FLASH_ReadByte() : stm8s_flash.c , stm8s_flash.h
  • FLASH_ReadOptionByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_SET_BYTE : stm8s_flash.c
  • FLASH_SetLowPowerMode() : stm8s_flash.c , stm8s_flash.h
  • FLASH_SetProgrammingTime() : stm8s_flash.h , stm8s_flash.c
  • FLASH_STATUS_SUCCESSFUL_OPERATION : stm8s_flash.h
  • FLASH_STATUS_TIMEOUT : stm8s_flash.h
  • FLASH_Status_TypeDef : stm8s_flash.h
  • FLASH_STATUS_WRITE_PROTECTION_ERROR : stm8s_flash.h
  • FLASH_TypeDef : stm8s.h
  • FLASH_Unlock() : stm8s_flash.c , stm8s_flash.h
  • FunctionalState : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GPIO_CR1_RESET_VALUE : stm8s.h
  • GPIO_CR2_RESET_VALUE : stm8s.h
  • GPIO_DDR_RESET_VALUE : stm8s.h
  • GPIO_DeInit() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ExternalPullUpConfig() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_Init() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_MODE_IN_FL_IT : stm8s_gpio.h
  • GPIO_MODE_IN_FL_NO_IT : stm8s_gpio.h
  • GPIO_MODE_IN_PU_IT : stm8s_gpio.h
  • GPIO_MODE_IN_PU_NO_IT : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_HIZ_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_HIZ_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_LOW_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_LOW_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_HIGH_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_HIGH_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_LOW_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_LOW_SLOW : stm8s_gpio.h
  • GPIO_Mode_TypeDef : stm8s_gpio.h
  • GPIO_ODR_RESET_VALUE : stm8s.h
  • GPIO_PIN_0 : stm8s_gpio.h
  • GPIO_PIN_1 : stm8s_gpio.h
  • GPIO_PIN_2 : stm8s_gpio.h
  • GPIO_PIN_3 : stm8s_gpio.h
  • GPIO_PIN_4 : stm8s_gpio.h
  • GPIO_PIN_5 : stm8s_gpio.h
  • GPIO_PIN_6 : stm8s_gpio.h
  • GPIO_PIN_7 : stm8s_gpio.h
  • GPIO_PIN_ALL : stm8s_gpio.h
  • GPIO_PIN_HNIB : stm8s_gpio.h
  • GPIO_PIN_LNIB : stm8s_gpio.h
  • GPIO_Pin_TypeDef : stm8s_gpio.h
  • GPIO_ReadInputData() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ReadInputPin() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ReadOutputData() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_TypeDef : stm8s.h
  • GPIO_Write() : stm8s_gpio.c , stm8s_gpio.h
  • GPIO_WriteHigh() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_WriteLow() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_WriteReverse() : stm8s_gpio.c , stm8s_gpio.h
  • GPIOA : stm8s.h
  • GPIOA_BaseAddress : stm8s.h
  • GPIOB : stm8s.h
  • GPIOB_BaseAddress : stm8s.h
  • GPIOC : stm8s.h
  • GPIOC_BaseAddress : stm8s.h
  • GPIOD : stm8s.h
  • GPIOD_BaseAddress : stm8s.h
  • GPIOE : stm8s.h
  • GPIOE_BaseAddress : stm8s.h
  • GPIOF : stm8s.h
  • GPIOF_BaseAddress : stm8s.h
  • GPIOG_BaseAddress : stm8s.h
  • GPIOH_BaseAddress : stm8s.h
  • GPIOI_BaseAddress : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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  • Globals
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • halt : stm8s.h
  • HSE_VALUE : stm8s.h
  • HSI_VALUE : stm8s.h
  • HSIDivFactor : stm8s_clk.c


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C : stm8s.h
  • I2C_ACK_CURR : stm8s_i2c.h
  • I2C_ACK_NEXT : stm8s_i2c.h
  • I2C_ACK_NONE : stm8s_i2c.h
  • I2C_Ack_TypeDef : stm8s_i2c.h
  • I2C_AcknowledgeConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ADDMODE_10BIT : stm8s_i2c.h
  • I2C_ADDMODE_7BIT : stm8s_i2c.h
  • I2C_AddMode_TypeDef : stm8s_i2c.h
  • I2C_BaseAddress : stm8s.h
  • I2C_CCRH_CCR : stm8s.h
  • I2C_CCRH_DUTY : stm8s.h
  • I2C_CCRH_FS : stm8s.h
  • I2C_CCRH_RESET_VALUE : stm8s.h
  • I2C_CCRL_CCR : stm8s.h
  • I2C_CCRL_RESET_VALUE : stm8s.h
  • I2C_CheckEvent() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ClearFlag() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ClearITPendingBit() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_Cmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_CR1_ENGC : stm8s.h
  • I2C_CR1_NOSTRETCH : stm8s.h
  • I2C_CR1_PE : stm8s.h
  • I2C_CR1_RESET_VALUE : stm8s.h
  • I2C_CR2_ACK : stm8s.h
  • I2C_CR2_POS : stm8s.h
  • I2C_CR2_RESET_VALUE : stm8s.h
  • I2C_CR2_START : stm8s.h
  • I2C_CR2_STOP : stm8s.h
  • I2C_CR2_SWRST : stm8s.h
  • I2C_DeInit() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_DIRECTION_RX : stm8s_i2c.h
  • I2C_DIRECTION_TX : stm8s_i2c.h
  • I2C_Direction_TypeDef : stm8s_i2c.h
  • I2C_DR_DR : stm8s.h
  • I2C_DR_RESET_VALUE : stm8s.h
  • I2C_DUTYCYCLE_16_9 : stm8s_i2c.h
  • I2C_DUTYCYCLE_2 : stm8s_i2c.h
  • I2C_DutyCycle_TypeDef : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_RECEIVED : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : stm8s_i2c.h
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : stm8s_i2c.h
  • I2C_EVENT_MASTER_MODE_SELECT : stm8s_i2c.h
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : stm8s_i2c.h
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_ACK_FAILURE : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTING : stm8s_i2c.h
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_STOP_DETECTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : stm8s_i2c.h
  • I2C_Event_TypeDef : stm8s_i2c.h
  • I2C_FastModeDutyCycleConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_FLAG_ACKNOWLEDGEFAILURE : stm8s_i2c.h
  • I2C_FLAG_ADDRESSSENTMATCHED : stm8s_i2c.h
  • I2C_FLAG_ARBITRATIONLOSS : stm8s_i2c.h
  • I2C_FLAG_BUSBUSY : stm8s_i2c.h
  • I2C_FLAG_BUSERROR : stm8s_i2c.h
  • I2C_FLAG_GENERALCALL : stm8s_i2c.h
  • I2C_FLAG_HEADERSENT : stm8s_i2c.h
  • I2C_FLAG_MASTERSLAVE : stm8s_i2c.h
  • I2C_FLAG_OVERRUNUNDERRUN : stm8s_i2c.h
  • I2C_FLAG_RXNOTEMPTY : stm8s_i2c.h
  • I2C_FLAG_STARTDETECTION : stm8s_i2c.h
  • I2C_FLAG_STOPDETECTION : stm8s_i2c.h
  • I2C_FLAG_TRANSFERFINISHED : stm8s_i2c.h
  • I2C_FLAG_TRANSMITTERRECEIVER : stm8s_i2c.h
  • I2C_FLAG_TXEMPTY : stm8s_i2c.h
  • I2C_Flag_TypeDef : stm8s_i2c.h
  • I2C_FLAG_WAKEUPFROMHALT : stm8s_i2c.h
  • I2C_FREQR_FREQ : stm8s.h
  • I2C_FREQR_RESET_VALUE : stm8s.h
  • I2C_GeneralCallCmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GenerateSTART() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GenerateSTOP() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetFlagStatus() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetITStatus() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetLastEvent() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_Init() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_IT_BUF : stm8s_i2c.h
  • I2C_IT_ERR : stm8s_i2c.h
  • I2C_IT_EVT : stm8s_i2c.h
  • I2C_IT_TypeDef : stm8s_i2c.h
  • I2C_ITConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE : stm8s_i2c.h
  • I2C_ITPENDINGBIT_ADDRESSSENTMATCHED : stm8s_i2c.h
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS : stm8s_i2c.h
  • I2C_ITPENDINGBIT_BUSERROR : stm8s_i2c.h
  • I2C_ITPENDINGBIT_HEADERSENT : stm8s_i2c.h
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN : stm8s_i2c.h
  • I2C_ITPENDINGBIT_RXNOTEMPTY : stm8s_i2c.h
  • I2C_ITPENDINGBIT_STARTDETECTION : stm8s_i2c.h
  • I2C_ITPENDINGBIT_STOPDETECTION : stm8s_i2c.h
  • I2C_ITPENDINGBIT_TRANSFERFINISHED : stm8s_i2c.h
  • I2C_ITPENDINGBIT_TXEMPTY : stm8s_i2c.h
  • I2C_ITPendingBit_TypeDef : stm8s_i2c.h
  • I2C_ITPENDINGBIT_WAKEUPFROMHALT : stm8s_i2c.h
  • I2C_ITR_ITBUFEN : stm8s.h
  • I2C_ITR_ITERREN : stm8s.h
  • I2C_ITR_ITEVTEN : stm8s.h
  • I2C_ITR_RESET_VALUE : stm8s.h
  • I2C_MAX_FAST_FREQ : stm8s_i2c.h
  • I2C_MAX_INPUT_FREQ : stm8s_i2c.h
  • I2C_MAX_STANDARD_FREQ : stm8s_i2c.h
  • I2C_OARH_ADD : stm8s.h
  • I2C_OARH_ADDCONF : stm8s.h
  • I2C_OARH_ADDMODE : stm8s.h
  • I2C_OARH_RESET_VALUE : stm8s.h
  • I2C_OARL_ADD : stm8s.h
  • I2C_OARL_ADD0 : stm8s.h
  • I2C_OARL_RESET_VALUE : stm8s.h
  • I2C_ReceiveData() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_Send7bitAddress() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_SendData() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_SoftwareResetCmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_SR1_ADD10 : stm8s.h
  • I2C_SR1_ADDR : stm8s.h
  • I2C_SR1_BTF : stm8s.h
  • I2C_SR1_RESET_VALUE : stm8s.h
  • I2C_SR1_RXNE : stm8s.h
  • I2C_SR1_SB : stm8s.h
  • I2C_SR1_STOPF : stm8s.h
  • I2C_SR1_TXE : stm8s.h
  • I2C_SR2_AF : stm8s.h
  • I2C_SR2_ARLO : stm8s.h
  • I2C_SR2_BERR : stm8s.h
  • I2C_SR2_OVR : stm8s.h
  • I2C_SR2_RESET_VALUE : stm8s.h
  • I2C_SR2_WUFH : stm8s.h
  • I2C_SR3_BUSY : stm8s.h
  • I2C_SR3_GENCALL : stm8s.h
  • I2C_SR3_MSL : stm8s.h
  • I2C_SR3_RESET_VALUE : stm8s.h
  • I2C_SR3_TRA : stm8s.h
  • I2C_StretchClockCmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_TRISER_RESET_VALUE : stm8s.h
  • I2C_TRISER_TRISE : stm8s.h
  • I2C_TypeDef : stm8s.h
  • IN_RAM : stm8s.h , stm8s_flash.h
  • int16_t : stm8s.h
  • int32_t : stm8s.h
  • int8_t : stm8s.h
  • IS_ADC1_ALIGN_OK : stm8s_adc1.h
  • IS_ADC1_BUFFER_OK : stm8s_adc1.h
  • IS_ADC1_CHANNEL_OK : stm8s_adc1.h
  • IS_ADC1_CONVERSIONMODE_OK : stm8s_adc1.h
  • IS_ADC1_EXTTRIG_OK : stm8s_adc1.h
  • IS_ADC1_FLAG_OK : stm8s_adc1.h
  • IS_ADC1_IT_OK : stm8s_adc1.h
  • IS_ADC1_ITPENDINGBIT_OK : stm8s_adc1.h
  • IS_ADC1_PRESSEL_OK : stm8s_adc1.h
  • IS_ADC1_SCHMITTTRIG_OK : stm8s_adc1.h
  • IS_ADC2_ALIGN_OK : stm8s_adc2.h
  • IS_ADC2_CHANNEL_OK : stm8s_adc2.h
  • IS_ADC2_CONVERSIONMODE_OK : stm8s_adc2.h
  • IS_ADC2_EXTTRIG_OK : stm8s_adc2.h
  • IS_ADC2_PRESSEL_OK : stm8s_adc2.h
  • IS_ADC2_SCHMITTTRIG_OK : stm8s_adc2.h
  • IS_AWU_TIMEBASE_OK : stm8s_awu.h
  • IS_BEEP_FREQUENCY_OK : stm8s_beep.h
  • IS_CAN_BITSEG1_OK : stm8s_can.h
  • IS_CAN_BITSEG2_OK : stm8s_can.h
  • IS_CAN_DLC_OK : stm8s_can.h
  • IS_CAN_EXTID_OK : stm8s_can.h
  • IS_CAN_FILTER_MODE_OK : stm8s_can.h
  • IS_CAN_FILTER_NUMBER_OK : stm8s_can.h
  • IS_CAN_FILTER_SCALE_OK : stm8s_can.h
  • IS_CAN_FLAG_CLEAR_OK : stm8s_can.h
  • IS_CAN_FLAG_STATUS_OK : stm8s_can.h
  • IS_CAN_IDTYPE_OK : stm8s_can.h
  • IS_CAN_IT_CONFIG_OK : stm8s_can.h
  • IS_CAN_IT_PENDING_BIT_OK : stm8s_can.h
  • IS_CAN_IT_STATUS_OK : stm8s_can.h
  • IS_CAN_LAST_ERROR_CODE_OK : stm8s_can.h
  • IS_CAN_MASTERCTRL_OK : stm8s_can.h
  • IS_CAN_MODE_OK : stm8s_can.h
  • IS_CAN_OPERATINGMODE_OK : stm8s_can.h
  • IS_CAN_PRESCALER_OK : stm8s_can.h
  • IS_CAN_RTR_OK : stm8s_can.h
  • IS_CAN_ST7_COMPATIBILITY_OK : stm8s_can.h
  • IS_CAN_STDID_OK : stm8s_can.h
  • IS_CAN_SYNJUMPWIDTH_OK : stm8s_can.h
  • IS_CAN_TRANSMITMAILBOX_OK : stm8s_can.h
  • IS_CLK_CSSCONFIG_OK : stm8s_clk.h
  • IS_CLK_CURRENTCLOCKSTATE_OK : stm8s_clk.h
  • IS_CLK_FLAG_OK : stm8s_clk.h
  • IS_CLK_HSIPRESCALER_OK : stm8s_clk.h
  • IS_CLK_HSITRIMVALUE_OK : stm8s_clk.h
  • IS_CLK_IT_OK : stm8s_clk.h
  • IS_CLK_OUTPUT_OK : stm8s_clk.h
  • IS_CLK_PERIPHERAL_OK : stm8s_clk.h
  • IS_CLK_PRESCALER_OK : stm8s_clk.h
  • IS_CLK_SOURCE_OK : stm8s_clk.h
  • IS_CLK_SWIMDIVIDER_OK : stm8s_clk.h
  • IS_CLK_SWITCHMODE_OK : stm8s_clk.h
  • IS_EXTI_PINMASK_OK : stm8s_exti.h
  • IS_EXTI_PORT_OK : stm8s_exti.h
  • IS_EXTI_SENSITIVITY_OK : stm8s_exti.h
  • IS_EXTI_TLISENSITIVITY_OK : stm8s_exti.h
  • IS_FLASH_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_DATA_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_DATA_BLOCK_NUMBER_OK : stm8s_flash.h
  • IS_FLASH_FLAGS_OK : stm8s_flash.h
  • IS_FLASH_LOW_POWER_MODE_OK : stm8s_flash.h
  • IS_FLASH_PROG_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_PROG_BLOCK_NUMBER_OK : stm8s_flash.h
  • IS_FLASH_PROGRAM_MODE_OK : stm8s_flash.h
  • IS_FLASH_PROGRAM_TIME_OK : stm8s_flash.h
  • IS_FUNCTIONALSTATE_OK : stm8s.h
  • IS_GPIO_MODE_OK : stm8s_gpio.h
  • IS_GPIO_PIN_OK : stm8s_gpio.h
  • IS_I2C_ACK_OK : stm8s_i2c.h
  • IS_I2C_ADDMODE_OK : stm8s_i2c.h
  • IS_I2C_ADDRESS_OK : stm8s_i2c.h
  • IS_I2C_CLEAR_FLAG_OK : stm8s_i2c.h
  • IS_I2C_CLEAR_ITPENDINGBIT_OK : stm8s_i2c.h
  • IS_I2C_DIRECTION_OK : stm8s_i2c.h
  • IS_I2C_DUTYCYCLE_OK : stm8s_i2c.h
  • IS_I2C_EVENT_OK : stm8s_i2c.h
  • IS_I2C_FLAG_OK : stm8s_i2c.h
  • IS_I2C_INPUT_CLOCK_FREQ_OK : stm8s_i2c.h
  • IS_I2C_INTERRUPT_OK : stm8s_i2c.h
  • IS_I2C_ITPENDINGBIT_OK : stm8s_i2c.h
  • IS_I2C_OUTPUT_CLOCK_FREQ_OK : stm8s_i2c.h
  • IS_I2C_OWN_ADDRESS_OK : stm8s_i2c.h
  • IS_ITC_INTERRUPTS_DISABLED : stm8s_itc.h
  • IS_ITC_IRQ_OK : stm8s_itc.h
  • IS_ITC_PRIORITY_OK : stm8s_itc.h
  • IS_IWDG_PRESCALER_OK : stm8s_iwdg.h
  • IS_IWDG_WRITEACCESS_MODE_OK : stm8s_iwdg.h
  • IS_LSI_FREQUENCY_OK : stm8s_awu.h , stm8s_beep.h
  • IS_MEMORY_TYPE_OK : stm8s_flash.h
  • IS_OPTION_BYTE_ADDRESS_OK : stm8s_flash.h
  • IS_RST_FLAG_OK : stm8s_rst.h
  • IS_SPI_BAUDRATE_PRESCALER_OK : stm8s_spi.h
  • IS_SPI_CLEAR_FLAGS_OK : stm8s_spi.h
  • IS_SPI_CLEAR_IT_OK : stm8s_spi.h
  • IS_SPI_CONFIG_IT_OK : stm8s_spi.h
  • IS_SPI_CRC_OK : stm8s_spi.h
  • IS_SPI_CRC_POLYNOMIAL_OK : stm8s_spi.h
  • IS_SPI_DATA_DIRECTION_OK : stm8s_spi.h
  • IS_SPI_DIRECTION_OK : stm8s_spi.h
  • IS_SPI_FIRSTBIT_OK : stm8s_spi.h
  • IS_SPI_FLAGS_OK : stm8s_spi.h
  • IS_SPI_GET_IT_OK : stm8s_spi.h
  • IS_SPI_MODE_OK : stm8s_spi.h
  • IS_SPI_PHASE_OK : stm8s_spi.h
  • IS_SPI_POLARITY_OK : stm8s_spi.h
  • IS_SPI_SLAVEMANAGEMENT_OK : stm8s_spi.h
  • IS_STATE_VALUE_OK : stm8s.h
  • IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK : stm8s_tim1.h
  • IS_TIM1_BREAK_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_BREAK_STATE_OK : stm8s_tim1.h
  • IS_TIM1_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_CLEAR_FLAG_OK : stm8s_tim1.h
  • IS_TIM1_COMPLEMENTARY_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_COUNTER_MODE_OK : stm8s_tim1.h
  • IS_TIM1_ENCODER_MODE_OK : stm8s_tim1.h
  • IS_TIM1_EVENT_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_EXT_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_EXT_PRESCALER_OK : stm8s_tim1.h
  • IS_TIM1_EXT_TRG_FILTER_OK : stm8s_tim1.h
  • IS_TIM1_FORCED_ACTION_OK : stm8s_tim1.h
  • IS_TIM1_GET_FLAG_OK : stm8s_tim1.h
  • IS_TIM1_GET_IT_OK : stm8s_tim1.h
  • IS_TIM1_IC_FILTER_OK : stm8s_tim1.h
  • IS_TIM1_IC_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_IC_PRESCALER_OK : stm8s_tim1.h
  • IS_TIM1_IC_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_IT_OK : stm8s_tim1.h
  • IS_TIM1_LOCK_LEVEL_OK : stm8s_tim1.h
  • IS_TIM1_OC_MODE_OK : stm8s_tim1.h
  • IS_TIM1_OC_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_OCIDLE_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OCM_OK : stm8s_tim1.h
  • IS_TIM1_OCN_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_OCNIDLE_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OPM_MODE_OK : stm8s_tim1.h
  • IS_TIM1_OSSI_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OUTPUT_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OUTPUTN_STATE_OK : stm8s_tim1.h
  • IS_TIM1_PRESCALER_RELOAD_OK : stm8s_tim1.h
  • IS_TIM1_PWMI_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_SLAVE_MODE_OK : stm8s_tim1.h
  • IS_TIM1_TIX_TRIGGER_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_TIXCLK_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_TRGO_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_TRIGGER_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_UPDATE_SOURCE_OK : stm8s_tim1.h
  • IS_TIM2_CHANNEL_OK : stm8s_tim2.h
  • IS_TIM2_CLEAR_FLAG_OK : stm8s_tim2.h
  • IS_TIM2_EVENT_SOURCE_OK : stm8s_tim2.h
  • IS_TIM2_FORCED_ACTION_OK : stm8s_tim2.h
  • IS_TIM2_GET_FLAG_OK : stm8s_tim2.h
  • IS_TIM2_GET_IT_OK : stm8s_tim2.h
  • IS_TIM2_IC_FILTER_OK : stm8s_tim2.h
  • IS_TIM2_IC_POLARITY_OK : stm8s_tim2.h
  • IS_TIM2_IC_PRESCALER_OK : stm8s_tim2.h
  • IS_TIM2_IC_SELECTION1_OK : stm8s_tim2.h
  • IS_TIM2_IC_SELECTION_OK : stm8s_tim2.h
  • IS_TIM2_IT_OK : stm8s_tim2.h
  • IS_TIM2_OC_MODE_OK : stm8s_tim2.h
  • IS_TIM2_OC_POLARITY_OK : stm8s_tim2.h
  • IS_TIM2_OCM_OK : stm8s_tim2.h
  • IS_TIM2_OPM_MODE_OK : stm8s_tim2.h
  • IS_TIM2_OUTPUT_STATE_OK : stm8s_tim2.h
  • IS_TIM2_PRESCALER_OK : stm8s_tim2.h
  • IS_TIM2_PRESCALER_RELOAD_OK : stm8s_tim2.h
  • IS_TIM2_PWMI_CHANNEL_OK : stm8s_tim2.h
  • IS_TIM2_UPDATE_SOURCE_OK : stm8s_tim2.h
  • IS_TIM3_CHANNEL_OK : stm8s_tim3.h
  • IS_TIM3_CLEAR_FLAG_OK : stm8s_tim3.h
  • IS_TIM3_EVENT_SOURCE_OK : stm8s_tim3.h
  • IS_TIM3_FORCED_ACTION_OK : stm8s_tim3.h
  • IS_TIM3_GET_FLAG_OK : stm8s_tim3.h
  • IS_TIM3_GET_IT_OK : stm8s_tim3.h
  • IS_TIM3_IC_FILTER_OK : stm8s_tim3.h
  • IS_TIM3_IC_POLARITY_OK : stm8s_tim3.h
  • IS_TIM3_IC_PRESCALER_OK : stm8s_tim3.h
  • IS_TIM3_IC_SELECTION_OK : stm8s_tim3.h
  • IS_TIM3_IT_OK : stm8s_tim3.h
  • IS_TIM3_OC_MODE_OK : stm8s_tim3.h
  • IS_TIM3_OC_POLARITY_OK : stm8s_tim3.h
  • IS_TIM3_OCM_OK : stm8s_tim3.h
  • IS_TIM3_OPM_MODE_OK : stm8s_tim3.h
  • IS_TIM3_OUTPUT_STATE_OK : stm8s_tim3.h
  • IS_TIM3_PRESCALER_OK : stm8s_tim3.h
  • IS_TIM3_PRESCALER_RELOAD_OK : stm8s_tim3.h
  • IS_TIM3_PWMI_CHANNEL_OK : stm8s_tim3.h
  • IS_TIM3_UPDATE_SOURCE_OK : stm8s_tim3.h
  • IS_TIM4_EVENT_SOURCE_OK : stm8s_tim4.h
  • IS_TIM4_GET_FLAG_OK : stm8s_tim4.h
  • IS_TIM4_IT_OK : stm8s_tim4.h
  • IS_TIM4_OPM_MODE_OK : stm8s_tim4.h
  • IS_TIM4_PRESCALER_OK : stm8s_tim4.h
  • IS_TIM4_PRESCALER_RELOAD_OK : stm8s_tim4.h
  • IS_TIM4_UPDATE_SOURCE_OK : stm8s_tim4.h
  • IS_TIM5_CHANNEL_OK : stm8s_tim5.h
  • IS_TIM5_CLEAR_FLAG_OK : stm8s_tim5.h
  • IS_TIM5_ENCODER_MODE_OK : stm8s_tim5.h
  • IS_TIM5_EVENT_SOURCE_OK : stm8s_tim5.h
  • IS_TIM5_EXT_FILTER_OK : stm8s_tim5.h
  • IS_TIM5_EXT_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_EXT_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_FORCED_ACTION_OK : stm8s_tim5.h
  • IS_TIM5_GET_FLAG_OK : stm8s_tim5.h
  • IS_TIM5_GET_IT_OK : stm8s_tim5.h
  • IS_TIM5_IC_FILTER_OK : stm8s_tim5.h
  • IS_TIM5_IC_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_IC_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_IC_SELECTION1_OK : stm8s_tim5.h
  • IS_TIM5_IC_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_IT_OK : stm8s_tim5.h
  • IS_TIM5_OC_MODE_OK : stm8s_tim5.h
  • IS_TIM5_OC_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_OCM_OK : stm8s_tim5.h
  • IS_TIM5_OPM_MODE_OK : stm8s_tim5.h
  • IS_TIM5_OUTPUT_STATE_OK : stm8s_tim5.h
  • IS_TIM5_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_PRESCALER_RELOAD_OK : stm8s_tim5.h
  • IS_TIM5_PWMI_CHANNEL_OK : stm8s_tim5.h
  • IS_TIM5_SLAVE_MODE_OK : stm8s_tim5.h
  • IS_TIM5_TIX_TRIGGER_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_TRGO_SOURCE_OK : stm8s_tim5.h
  • IS_TIM5_TRIGGER_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_UPDATE_SOURCE_OK : stm8s_tim5.h
  • IS_TIM6_CLEAR_FLAG_OK : stm8s_tim6.h
  • IS_TIM6_EVENT_SOURCE_OK : stm8s_tim6.h
  • IS_TIM6_GET_FLAG_OK : stm8s_tim6.h
  • IS_TIM6_GET_IT_OK : stm8s_tim6.h
  • IS_TIM6_IT_OK : stm8s_tim6.h
  • IS_TIM6_OPM_MODE_OK : stm8s_tim6.h
  • IS_TIM6_PRESCALER_OK : stm8s_tim6.h
  • IS_TIM6_PRESCALER_RELOAD_OK : stm8s_tim6.h
  • IS_TIM6_SLAVE_MODE_OK : stm8s_tim6.h
  • IS_TIM6_TRGO_SOURCE_OK : stm8s_tim6.h
  • IS_TIM6_TRIGGER_SELECTION_OK : stm8s_tim6.h
  • IS_TIM6_UPDATE_SOURCE_OK : stm8s_tim6.h
  • IS_UART1_ADDRESS_OK : stm8s_uart1.h
  • IS_UART1_BAUDRATE_OK : stm8s_uart1.h
  • IS_UART1_CLEAR_FLAG_OK : stm8s_uart1.h
  • IS_UART1_CLEAR_IT_OK : stm8s_uart1.h
  • IS_UART1_CONFIG_IT_OK : stm8s_uart1.h
  • IS_UART1_FLAG_OK : stm8s_uart1.h
  • IS_UART1_GET_IT_OK : stm8s_uart1.h
  • IS_UART1_IRDAMODE_OK : stm8s_uart1.h
  • IS_UART1_LINBREAKDETECTIONLENGTH_OK : stm8s_uart1.h
  • IS_UART1_MODE_OK : stm8s_uart1.h
  • IS_UART1_PARITY_OK : stm8s_uart1.h
  • IS_UART1_STOPBITS_OK : stm8s_uart1.h
  • IS_UART1_SYNCMODE_OK : stm8s_uart1.h
  • IS_UART1_WAKEUP_OK : stm8s_uart1.h
  • IS_UART1_WORDLENGTH_OK : stm8s_uart1.h
  • IS_UART2_ADDRESS_OK : stm8s_uart2.h
  • IS_UART2_AUTOSYNC_OK : stm8s_uart2.h
  • IS_UART2_BAUDRATE_OK : stm8s_uart2.h
  • IS_UART2_CLEAR_FLAG_OK : stm8s_uart2.h
  • IS_UART2_CLEAR_IT_OK : stm8s_uart2.h
  • IS_UART2_CONFIG_IT_OK : stm8s_uart2.h
  • IS_UART2_DIVUP_OK : stm8s_uart2.h
  • IS_UART2_FLAG_OK : stm8s_uart2.h
  • IS_UART2_GET_IT_OK : stm8s_uart2.h
  • IS_UART2_IRDAMODE_OK : stm8s_uart2.h
  • IS_UART2_LINBREAKDETECTIONLENGTH_OK : stm8s_uart2.h
  • IS_UART2_MODE_OK : stm8s_uart2.h
  • IS_UART2_PARITY_OK : stm8s_uart2.h
  • IS_UART2_SLAVE_OK : stm8s_uart2.h
  • IS_UART2_STOPBITS_OK : stm8s_uart2.h
  • IS_UART2_SYNCMODE_OK : stm8s_uart2.h
  • IS_UART2_WAKEUP_OK : stm8s_uart2.h
  • IS_UART2_WORDLENGTH_OK : stm8s_uart2.h
  • IS_UART3_ADDRESS_OK : stm8s_uart3.h
  • IS_UART3_AUTOSYNC_OK : stm8s_uart3.h
  • IS_UART3_BAUDRATE_OK : stm8s_uart3.h
  • IS_UART3_CLEAR_FLAG_OK : stm8s_uart3.h
  • IS_UART3_CLEAR_IT_OK : stm8s_uart3.h
  • IS_UART3_CONFIG_IT_OK : stm8s_uart3.h
  • IS_UART3_DIVUP_OK : stm8s_uart3.h
  • IS_UART3_FLAG_OK : stm8s_uart3.h
  • IS_UART3_GET_IT_OK : stm8s_uart3.h
  • IS_UART3_LINBREAKDETECTIONLENGTH_OK : stm8s_uart3.h
  • IS_UART3_MODE_OK : stm8s_uart3.h
  • IS_UART3_PARITY_OK : stm8s_uart3.h
  • IS_UART3_SLAVE_OK : stm8s_uart3.h
  • IS_UART3_STOPBITS_OK : stm8s_uart3.h
  • IS_UART3_WAKEUP_OK : stm8s_uart3.h
  • IS_UART3_WORDLENGTH_OK : stm8s_uart3.h
  • IS_WWDG_COUNTERVALUE_OK : stm8s_wwdg.h
  • IS_WWDG_WINDOWLIMITVALUE_OK : stm8s_wwdg.h
  • ITC : stm8s.h
  • ITC_BaseAddress : stm8s.h
  • ITC_DeInit() : stm8s_itc.h , stm8s_itc.c
  • ITC_GetCPUCC() : stm8s_itc.c , stm8s_itc.h
  • ITC_GetSoftIntStatus() : stm8s_itc.c , stm8s_itc.h
  • ITC_GetSoftwarePriority() : stm8s_itc.h , stm8s_itc.c
  • ITC_IRQ_AWU : stm8s_itc.h
  • ITC_IRQ_CLK : stm8s_itc.h
  • ITC_IRQ_EEPROM_EEC : stm8s_itc.h
  • ITC_IRQ_I2C : stm8s_itc.h
  • ITC_IRQ_PORTA : stm8s_itc.h
  • ITC_IRQ_PORTB : stm8s_itc.h
  • ITC_IRQ_PORTC : stm8s_itc.h
  • ITC_IRQ_PORTD : stm8s_itc.h
  • ITC_IRQ_PORTE : stm8s_itc.h
  • ITC_IRQ_SPI : stm8s_itc.h
  • ITC_IRQ_TIM1_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM1_OVF : stm8s_itc.h
  • ITC_IRQ_TIM2_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM2_OVF : stm8s_itc.h
  • ITC_IRQ_TIM3_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM3_OVF : stm8s_itc.h
  • ITC_IRQ_TIM4_OVF : stm8s_itc.h
  • ITC_IRQ_TLI : stm8s_itc.h
  • ITC_Irq_TypeDef : stm8s_itc.h
  • ITC_IRQ_UART1_RX : stm8s_itc.h
  • ITC_IRQ_UART1_TX : stm8s_itc.h
  • ITC_PRIORITYLEVEL_0 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_1 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_2 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_3 : stm8s_itc.h
  • ITC_PriorityLevel_TypeDef : stm8s_itc.h
  • ITC_SetSoftwarePriority() : stm8s_itc.c , stm8s_itc.h
  • ITC_SPRX_RESET_VALUE : stm8s.h
  • ITC_TypeDef : stm8s.h
  • ITEN_Mask : stm8s_i2c.c
  • ITStatus : stm8s.h
  • IWDG : stm8s.h
  • IWDG_BaseAddress : stm8s.h
  • IWDG_Enable() : stm8s_iwdg.h , stm8s_iwdg.c
  • IWDG_KEY_ENABLE : stm8s_iwdg.h
  • IWDG_KEY_REFRESH : stm8s_iwdg.h
  • IWDG_PR_RESET_VALUE : stm8s.h
  • IWDG_Prescaler_128 : stm8s_iwdg.h
  • IWDG_Prescaler_16 : stm8s_iwdg.h
  • IWDG_Prescaler_256 : stm8s_iwdg.h
  • IWDG_Prescaler_32 : stm8s_iwdg.h
  • IWDG_Prescaler_4 : stm8s_iwdg.h
  • IWDG_Prescaler_64 : stm8s_iwdg.h
  • IWDG_Prescaler_8 : stm8s_iwdg.h
  • IWDG_Prescaler_TypeDef : stm8s_iwdg.h
  • IWDG_ReloadCounter() : stm8s_iwdg.c , stm8s_iwdg.h
  • IWDG_RLR_RESET_VALUE : stm8s.h
  • IWDG_SetPrescaler() : stm8s_iwdg.h , stm8s_iwdg.c
  • IWDG_SetReload() : stm8s_iwdg.h , stm8s_iwdg.c
  • IWDG_TypeDef : stm8s.h
  • IWDG_WriteAccess_Disable : stm8s_iwdg.h
  • IWDG_WriteAccess_Enable : stm8s_iwdg.h
  • IWDG_WriteAccess_TypeDef : stm8s_iwdg.h
  • IWDG_WriteAccessCmd() : stm8s_iwdg.c , stm8s_iwdg.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PointerAttr : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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  • Globals
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • REGISTER_Mask : stm8s_i2c.c
  • REGISTER_SR1_Index : stm8s_i2c.c
  • REGISTER_SR2_Index : stm8s_i2c.c
  • RESET : stm8s.h
  • rim : stm8s.h
  • RST : stm8s.h
  • RST_BaseAddress : stm8s.h
  • RST_ClearFlag() : stm8s_rst.h , stm8s_rst.c
  • RST_FLAG_EMCF : stm8s_rst.h
  • RST_FLAG_ILLOPF : stm8s_rst.h
  • RST_FLAG_IWDGF : stm8s_rst.h
  • RST_FLAG_SWIMF : stm8s_rst.h
  • RST_Flag_TypeDef : stm8s_rst.h
  • RST_FLAG_WWDGF : stm8s_rst.h
  • RST_GetFlagStatus() : stm8s_rst.c , stm8s_rst.h
  • RST_SR_EMCF : stm8s.h
  • RST_SR_ILLOPF : stm8s.h
  • RST_SR_IWDGF : stm8s.h
  • RST_SR_SWIMF : stm8s.h
  • RST_SR_WWDGF : stm8s.h
  • RST_TypeDef : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • s16 : stm8s.h
  • S16_MAX : stm8s.h
  • S16_MIN : stm8s.h
  • s32 : stm8s.h
  • S32_MAX : stm8s.h
  • S32_MIN : stm8s.h
  • s8 : stm8s.h
  • S8_MAX : stm8s.h
  • S8_MIN : stm8s.h
  • SET : stm8s.h
  • SetBit : stm8s.h
  • sim : stm8s.h
  • SPI : stm8s.h
  • SPI_BaseAddress : stm8s.h
  • SPI_BAUDRATEPRESCALER_128 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm8s_spi.h
  • SPI_BaudRatePrescaler_TypeDef : stm8s_spi.h
  • SPI_BiDirectionalLineConfig() : stm8s_spi.h , stm8s_spi.c
  • SPI_CalculateCRCCmd() : stm8s_spi.h , stm8s_spi.c
  • SPI_ClearFlag() : stm8s_spi.h , stm8s_spi.c
  • SPI_ClearITPendingBit() : stm8s_spi.h , stm8s_spi.c
  • SPI_CLOCKPHASE_1EDGE : stm8s_spi.h
  • SPI_CLOCKPHASE_2EDGE : stm8s_spi.h
  • SPI_ClockPhase_TypeDef : stm8s_spi.h
  • SPI_CLOCKPOLARITY_HIGH : stm8s_spi.h
  • SPI_CLOCKPOLARITY_LOW : stm8s_spi.h
  • SPI_ClockPolarity_TypeDef : stm8s_spi.h
  • SPI_Cmd() : stm8s_spi.h , stm8s_spi.c
  • SPI_CR1_BR : stm8s.h
  • SPI_CR1_CPHA : stm8s.h
  • SPI_CR1_CPOL : stm8s.h
  • SPI_CR1_LSBFIRST : stm8s.h
  • SPI_CR1_MSTR : stm8s.h
  • SPI_CR1_RESET_VALUE : stm8s.h
  • SPI_CR1_SPE : stm8s.h
  • SPI_CR2_BDM : stm8s.h
  • SPI_CR2_BDOE : stm8s.h
  • SPI_CR2_CRCEN : stm8s.h
  • SPI_CR2_CRCNEXT : stm8s.h
  • SPI_CR2_RESET_VALUE : stm8s.h
  • SPI_CR2_RXONLY : stm8s.h
  • SPI_CR2_SSI : stm8s.h
  • SPI_CR2_SSM : stm8s.h
  • SPI_CRC_RX : stm8s_spi.h
  • SPI_CRC_TX : stm8s_spi.h
  • SPI_CRC_TypeDef : stm8s_spi.h
  • SPI_CRCPR_RESET_VALUE : stm8s.h
  • SPI_DATADIRECTION_1LINE_RX : stm8s_spi.h
  • SPI_DATADIRECTION_1LINE_TX : stm8s_spi.h
  • SPI_DATADIRECTION_2LINES_FULLDUPLEX : stm8s_spi.h
  • SPI_DATADIRECTION_2LINES_RXONLY : stm8s_spi.h
  • SPI_DataDirection_TypeDef : stm8s_spi.h
  • SPI_DeInit() : stm8s_spi.h , stm8s_spi.c
  • SPI_DIRECTION_RX : stm8s_spi.h
  • SPI_DIRECTION_TX : stm8s_spi.h
  • SPI_Direction_TypeDef : stm8s_spi.h
  • SPI_DR_RESET_VALUE : stm8s.h
  • SPI_FIRSTBIT_LSB : stm8s_spi.h
  • SPI_FIRSTBIT_MSB : stm8s_spi.h
  • SPI_FirstBit_TypeDef : stm8s_spi.h
  • SPI_FLAG_BSY : stm8s_spi.h
  • SPI_FLAG_CRCERR : stm8s_spi.h
  • SPI_FLAG_MODF : stm8s_spi.h
  • SPI_FLAG_OVR : stm8s_spi.h
  • SPI_FLAG_RXNE : stm8s_spi.h
  • SPI_FLAG_TXE : stm8s_spi.h
  • SPI_Flag_TypeDef : stm8s_spi.h
  • SPI_FLAG_WKUP : stm8s_spi.h
  • SPI_GetCRC() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetCRCPolynomial() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetFlagStatus() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetITStatus() : stm8s_spi.c , stm8s_spi.h
  • SPI_ICR_ERRIE : stm8s.h
  • SPI_ICR_RESET_VALUE : stm8s.h
  • SPI_ICR_RXEI : stm8s.h
  • SPI_ICR_TXEI : stm8s.h
  • SPI_ICR_WKIE : stm8s.h
  • SPI_Init() : stm8s_spi.h , stm8s_spi.c
  • SPI_IT_CRCERR : stm8s_spi.h
  • SPI_IT_ERR : stm8s_spi.h
  • SPI_IT_MODF : stm8s_spi.h
  • SPI_IT_OVR : stm8s_spi.h
  • SPI_IT_RXNE : stm8s_spi.h
  • SPI_IT_TXE : stm8s_spi.h
  • SPI_IT_TypeDef : stm8s_spi.h
  • SPI_IT_WKUP : stm8s_spi.h
  • SPI_ITConfig() : stm8s_spi.h , stm8s_spi.c
  • SPI_MODE_MASTER : stm8s_spi.h
  • SPI_MODE_SLAVE : stm8s_spi.h
  • SPI_Mode_TypeDef : stm8s_spi.h
  • SPI_NSS_HARD : stm8s_spi.h
  • SPI_NSS_SOFT : stm8s_spi.h
  • SPI_NSS_TypeDef : stm8s_spi.h
  • SPI_NSSInternalSoftwareCmd() : stm8s_spi.h , stm8s_spi.c
  • SPI_ReceiveData() : stm8s_spi.h , stm8s_spi.c
  • SPI_ResetCRC() : stm8s_spi.c , stm8s_spi.h
  • SPI_RXCRCR_RESET_VALUE : stm8s.h
  • SPI_SendData() : stm8s_spi.h , stm8s_spi.c
  • SPI_SR_BSY : stm8s.h
  • SPI_SR_CRCERR : stm8s.h
  • SPI_SR_MODF : stm8s.h
  • SPI_SR_OVR : stm8s.h
  • SPI_SR_RESET_VALUE : stm8s.h
  • SPI_SR_RXNE : stm8s.h
  • SPI_SR_TXE : stm8s.h
  • SPI_SR_WKUP : stm8s.h
  • SPI_TransmitCRC() : stm8s_spi.h , stm8s_spi.c
  • SPI_TXCRCR_RESET_VALUE : stm8s.h
  • SPI_TypeDef : stm8s.h
  • SUCCESS : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TBR_Array : stm8s_awu.c
  • TI1_Config() : stm8s_tim1.c , stm8s_tim3.c , stm8s_tim5.c , stm8s_tim2.c
  • TI2_Config() : stm8s_tim3.c , stm8s_tim5.c , stm8s_tim1.c , stm8s_tim2.c
  • TI3_Config() : stm8s_tim1.c , stm8s_tim2.c , stm8s_tim5.c
  • TI4_Config() : stm8s_tim1.c
  • TIM1 : stm8s.h
  • TIM1_ARRH_ARR : stm8s.h
  • TIM1_ARRH_RESET_VALUE : stm8s.h
  • TIM1_ARRL_ARR : stm8s.h
  • TIM1_ARRL_RESET_VALUE : stm8s.h
  • TIM1_ARRPreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_AUTOMATICOUTPUT_DISABLE : stm8s_tim1.h
  • TIM1_AUTOMATICOUTPUT_ENABLE : stm8s_tim1.h
  • TIM1_AutomaticOutput_TypeDef : stm8s_tim1.h
  • TIM1_BaseAddress : stm8s.h
  • TIM1_BDTRConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_BKR_AOE : stm8s.h
  • TIM1_BKR_BKE : stm8s.h
  • TIM1_BKR_BKP : stm8s.h
  • TIM1_BKR_LOCK : stm8s.h
  • TIM1_BKR_MOE : stm8s.h
  • TIM1_BKR_OSSI : stm8s.h
  • TIM1_BKR_OSSR : stm8s.h
  • TIM1_BKR_RESET_VALUE : stm8s.h
  • TIM1_BREAK_DISABLE : stm8s_tim1.h
  • TIM1_BREAK_ENABLE : stm8s_tim1.h
  • TIM1_BREAKPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_BREAKPOLARITY_LOW : stm8s_tim1.h
  • TIM1_BreakPolarity_TypeDef : stm8s_tim1.h
  • TIM1_BreakState_TypeDef : stm8s_tim1.h
  • TIM1_CCER1_CC1E : stm8s.h
  • TIM1_CCER1_CC1NE : stm8s.h
  • TIM1_CCER1_CC1NP : stm8s.h
  • TIM1_CCER1_CC1P : stm8s.h
  • TIM1_CCER1_CC2E : stm8s.h
  • TIM1_CCER1_CC2NE : stm8s.h
  • TIM1_CCER1_CC2NP : stm8s.h
  • TIM1_CCER1_CC2P : stm8s.h
  • TIM1_CCER1_RESET_VALUE : stm8s.h
  • TIM1_CCER2_CC3E : stm8s.h
  • TIM1_CCER2_CC3NE : stm8s.h
  • TIM1_CCER2_CC3NP : stm8s.h
  • TIM1_CCER2_CC3P : stm8s.h
  • TIM1_CCER2_CC4E : stm8s.h
  • TIM1_CCER2_CC4P : stm8s.h
  • TIM1_CCER2_RESET_VALUE : stm8s.h
  • TIM1_CCMR1_RESET_VALUE : stm8s.h
  • TIM1_CCMR2_RESET_VALUE : stm8s.h
  • TIM1_CCMR3_RESET_VALUE : stm8s.h
  • TIM1_CCMR4_RESET_VALUE : stm8s.h
  • TIM1_CCMR_CCxS : stm8s.h
  • TIM1_CCMR_ICxF : stm8s.h
  • TIM1_CCMR_ICxPSC : stm8s.h
  • TIM1_CCMR_OCM : stm8s.h
  • TIM1_CCMR_OCxFE : stm8s.h
  • TIM1_CCMR_OCxPE : stm8s.h
  • TIM1_CCPreloadControl() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CCR1H_CCR1 : stm8s.h
  • TIM1_CCR1H_RESET_VALUE : stm8s.h
  • TIM1_CCR1L_CCR1 : stm8s.h
  • TIM1_CCR1L_RESET_VALUE : stm8s.h
  • TIM1_CCR2H_CCR2 : stm8s.h
  • TIM1_CCR2H_RESET_VALUE : stm8s.h
  • TIM1_CCR2L_CCR2 : stm8s.h
  • TIM1_CCR2L_RESET_VALUE : stm8s.h
  • TIM1_CCR3H_CCR3 : stm8s.h
  • TIM1_CCR3H_RESET_VALUE : stm8s.h
  • TIM1_CCR3L_CCR3 : stm8s.h
  • TIM1_CCR3L_RESET_VALUE : stm8s.h
  • TIM1_CCR4H_CCR4 : stm8s.h
  • TIM1_CCR4H_RESET_VALUE : stm8s.h
  • TIM1_CCR4L_CCR4 : stm8s.h
  • TIM1_CCR4L_RESET_VALUE : stm8s.h
  • TIM1_CCxCmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CCxNCmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CHANNEL_1 : stm8s_tim1.h
  • TIM1_CHANNEL_2 : stm8s_tim1.h
  • TIM1_CHANNEL_3 : stm8s_tim1.h
  • TIM1_CHANNEL_4 : stm8s_tim1.h
  • TIM1_Channel_TypeDef : stm8s_tim1.h
  • TIM1_ClearFlag() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ClearITPendingBit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_Cmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CNTRH_CNT : stm8s.h
  • TIM1_CNTRH_RESET_VALUE : stm8s.h
  • TIM1_CNTRL_CNT : stm8s.h
  • TIM1_CNTRL_RESET_VALUE : stm8s.h
  • TIM1_COUNTERMODE_CENTERALIGNED1 : stm8s_tim1.h
  • TIM1_COUNTERMODE_CENTERALIGNED2 : stm8s_tim1.h
  • TIM1_COUNTERMODE_CENTERALIGNED3 : stm8s_tim1.h
  • TIM1_COUNTERMODE_DOWN : stm8s_tim1.h
  • TIM1_CounterMode_TypeDef : stm8s_tim1.h
  • TIM1_COUNTERMODE_UP : stm8s_tim1.h
  • TIM1_CounterModeConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CR1_ARPE : stm8s.h
  • TIM1_CR1_CEN : stm8s.h
  • TIM1_CR1_CMS : stm8s.h
  • TIM1_CR1_DIR : stm8s.h
  • TIM1_CR1_OPM : stm8s.h
  • TIM1_CR1_RESET_VALUE : stm8s.h
  • TIM1_CR1_UDIS : stm8s.h
  • TIM1_CR1_URS : stm8s.h
  • TIM1_CR2_CCPC : stm8s.h
  • TIM1_CR2_COMS : stm8s.h
  • TIM1_CR2_MMS : stm8s.h
  • TIM1_CR2_RESET_VALUE : stm8s.h
  • TIM1_CR2_TI1S : stm8s.h
  • TIM1_CtrlPWMOutputs() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_DeInit() : stm8s_tim1.c , stm8s_tim1.h
  • TIM1_DTR_DTG : stm8s.h
  • TIM1_DTR_RESET_VALUE : stm8s.h
  • TIM1_EGR_BG : stm8s.h
  • TIM1_EGR_CC1G : stm8s.h
  • TIM1_EGR_CC2G : stm8s.h
  • TIM1_EGR_CC3G : stm8s.h
  • TIM1_EGR_CC4G : stm8s.h
  • TIM1_EGR_COMG : stm8s.h
  • TIM1_EGR_RESET_VALUE : stm8s.h
  • TIM1_EGR_TG : stm8s.h
  • TIM1_EGR_UG : stm8s.h
  • TIM1_EncoderInterfaceConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ENCODERMODE_TI1 : stm8s_tim1.h
  • TIM1_ENCODERMODE_TI12 : stm8s_tim1.h
  • TIM1_ENCODERMODE_TI2 : stm8s_tim1.h
  • TIM1_EncoderMode_TypeDef : stm8s_tim1.h
  • TIM1_ETR_ECE : stm8s.h
  • TIM1_ETR_ETF : stm8s.h
  • TIM1_ETR_ETP : stm8s.h
  • TIM1_ETR_ETPS : stm8s.h
  • TIM1_ETR_RESET_VALUE : stm8s.h
  • TIM1_ETRClockMode1Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ETRClockMode2Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ETRConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_EVENTSOURCE_BREAK : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC1 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC2 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC3 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC4 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_COM : stm8s_tim1.h
  • TIM1_EVENTSOURCE_TRIGGER : stm8s_tim1.h
  • TIM1_EventSource_TypeDef : stm8s_tim1.h
  • TIM1_EVENTSOURCE_UPDATE : stm8s_tim1.h
  • TIM1_EXTTRGPOLARITY_INVERTED : stm8s_tim1.h
  • TIM1_EXTTRGPOLARITY_NONINVERTED : stm8s_tim1.h
  • TIM1_ExtTRGPolarity_TypeDef : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV2 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV4 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV8 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_OFF : stm8s_tim1.h
  • TIM1_ExtTRGPSC_TypeDef : stm8s_tim1.h
  • TIM1_FLAG_BREAK : stm8s_tim1.h
  • TIM1_FLAG_CC1 : stm8s_tim1.h
  • TIM1_FLAG_CC1OF : stm8s_tim1.h
  • TIM1_FLAG_CC2 : stm8s_tim1.h
  • TIM1_FLAG_CC2OF : stm8s_tim1.h
  • TIM1_FLAG_CC3 : stm8s_tim1.h
  • TIM1_FLAG_CC3OF : stm8s_tim1.h
  • TIM1_FLAG_CC4 : stm8s_tim1.h
  • TIM1_FLAG_CC4OF : stm8s_tim1.h
  • TIM1_FLAG_COM : stm8s_tim1.h
  • TIM1_FLAG_TRIGGER : stm8s_tim1.h
  • TIM1_FLAG_TypeDef : stm8s_tim1.h
  • TIM1_FLAG_UPDATE : stm8s_tim1.h
  • TIM1_FORCEDACTION_ACTIVE : stm8s_tim1.h
  • TIM1_FORCEDACTION_INACTIVE : stm8s_tim1.h
  • TIM1_ForcedAction_TypeDef : stm8s_tim1.h
  • TIM1_ForcedOC1Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC2Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC3Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC4Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GenerateEvent() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture1() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture2() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture3() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture4() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCounter() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetFlagStatus() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetITStatus() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetPrescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ICInit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ICPOLARITY_FALLING : stm8s_tim1.h
  • TIM1_ICPOLARITY_RISING : stm8s_tim1.h
  • TIM1_ICPolarity_TypeDef : stm8s_tim1.h
  • TIM1_ICPSC_DIV1 : stm8s_tim1.h
  • TIM1_ICPSC_DIV2 : stm8s_tim1.h
  • TIM1_ICPSC_DIV4 : stm8s_tim1.h
  • TIM1_ICPSC_DIV8 : stm8s_tim1.h
  • TIM1_ICPSC_TypeDef : stm8s_tim1.h
  • TIM1_ICSELECTION_DIRECTTI : stm8s_tim1.h
  • TIM1_ICSELECTION_INDIRECTTI : stm8s_tim1.h
  • TIM1_ICSELECTION_TRGI : stm8s_tim1.h
  • TIM1_ICSelection_TypeDef : stm8s_tim1.h
  • TIM1_IER_BIE : stm8s.h
  • TIM1_IER_CC1IE : stm8s.h
  • TIM1_IER_CC2IE : stm8s.h
  • TIM1_IER_CC3IE : stm8s.h
  • TIM1_IER_CC4IE : stm8s.h
  • TIM1_IER_COMIE : stm8s.h
  • TIM1_IER_RESET_VALUE : stm8s.h
  • TIM1_IER_TIE : stm8s.h
  • TIM1_IER_UIE : stm8s.h
  • TIM1_InternalClockConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_IT_BREAK : stm8s_tim1.h
  • TIM1_IT_CC1 : stm8s_tim1.h
  • TIM1_IT_CC2 : stm8s_tim1.h
  • TIM1_IT_CC3 : stm8s_tim1.h
  • TIM1_IT_CC4 : stm8s_tim1.h
  • TIM1_IT_COM : stm8s_tim1.h
  • TIM1_IT_TRIGGER : stm8s_tim1.h
  • TIM1_IT_TypeDef : stm8s_tim1.h
  • TIM1_IT_UPDATE : stm8s_tim1.h
  • TIM1_ITConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_LOCKLEVEL_1 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_2 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_3 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_OFF : stm8s_tim1.h
  • TIM1_LockLevel_TypeDef : stm8s_tim1.h
  • TIM1_OC1FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OCIDLESTATE_RESET : stm8s_tim1.h
  • TIM1_OCIDLESTATE_SET : stm8s_tim1.h
  • TIM1_OCIdleState_TypeDef : stm8s_tim1.h
  • TIM1_OCMODE_ACTIVE : stm8s_tim1.h
  • TIM1_OCMODE_INACTIVE : stm8s_tim1.h
  • TIM1_OCMODE_PWM1 : stm8s_tim1.h
  • TIM1_OCMODE_PWM2 : stm8s_tim1.h
  • TIM1_OCMODE_TIMING : stm8s_tim1.h
  • TIM1_OCMODE_TOGGLE : stm8s_tim1.h
  • TIM1_OCMode_TypeDef : stm8s_tim1.h
  • TIM1_OCNIDLESTATE_RESET : stm8s_tim1.h
  • TIM1_OCNIDLESTATE_SET : stm8s_tim1.h
  • TIM1_OCNIdleState_TypeDef : stm8s_tim1.h
  • TIM1_OCNPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_OCNPOLARITY_LOW : stm8s_tim1.h
  • TIM1_OCNPolarity_TypeDef : stm8s_tim1.h
  • TIM1_OCPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_OCPOLARITY_LOW : stm8s_tim1.h
  • TIM1_OCPolarity_TypeDef : stm8s_tim1.h
  • TIM1_OISR_OIS1 : stm8s.h
  • TIM1_OISR_OIS1N : stm8s.h
  • TIM1_OISR_OIS2 : stm8s.h
  • TIM1_OISR_OIS2N : stm8s.h
  • TIM1_OISR_OIS3 : stm8s.h
  • TIM1_OISR_OIS3N : stm8s.h
  • TIM1_OISR_OIS4 : stm8s.h
  • TIM1_OISR_RESET_VALUE : stm8s.h
  • TIM1_OPMODE_REPETITIVE : stm8s_tim1.h
  • TIM1_OPMODE_SINGLE : stm8s_tim1.h
  • TIM1_OPMode_TypeDef : stm8s_tim1.h
  • TIM1_OSSISTATE_DISABLE : stm8s_tim1.h
  • TIM1_OSSISTATE_ENABLE : stm8s_tim1.h
  • TIM1_OSSIState_TypeDef : stm8s_tim1.h
  • TIM1_OUTPUTNSTATE_DISABLE : stm8s_tim1.h
  • TIM1_OUTPUTNSTATE_ENABLE : stm8s_tim1.h
  • TIM1_OutputNState_TypeDef : stm8s_tim1.h
  • TIM1_OUTPUTSTATE_DISABLE : stm8s_tim1.h
  • TIM1_OUTPUTSTATE_ENABLE : stm8s_tim1.h
  • TIM1_OutputState_TypeDef : stm8s_tim1.h
  • TIM1_PrescalerConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_PSCH_PSC : stm8s.h
  • TIM1_PSCL_PSC : stm8s.h
  • TIM1_PSCRELOADMODE_IMMEDIATE : stm8s_tim1.h
  • TIM1_PSCReloadMode_TypeDef : stm8s_tim1.h
  • TIM1_PSCRELOADMODE_UPDATE : stm8s_tim1.h
  • TIM1_PSCRH_RESET_VALUE : stm8s.h
  • TIM1_PSCRL_RESET_VALUE : stm8s.h
  • TIM1_PWMIConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_RCR_REP : stm8s.h
  • TIM1_RCR_RESET_VALUE : stm8s.h
  • TIM1_SelectCOM() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectHallSensor() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectInputTrigger() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectMasterSlaveMode() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectOCxM() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectOnePulseMode() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectOutputTrigger() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectSlaveMode() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetAutoreload() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare1() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare2() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare3() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare4() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCounter() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC1Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC2Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC3Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC4Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SLAVEMODE_EXTERNAL1 : stm8s_tim1.h
  • TIM1_SLAVEMODE_GATED : stm8s_tim1.h
  • TIM1_SLAVEMODE_RESET : stm8s_tim1.h
  • TIM1_SLAVEMODE_TRIGGER : stm8s_tim1.h
  • TIM1_SlaveMode_TypeDef : stm8s_tim1.h
  • TIM1_SMCR_MSM : stm8s.h
  • TIM1_SMCR_RESET_VALUE : stm8s.h
  • TIM1_SMCR_SMS : stm8s.h
  • TIM1_SMCR_TS : stm8s.h
  • TIM1_SR1_BIF : stm8s.h
  • TIM1_SR1_CC1IF : stm8s.h
  • TIM1_SR1_CC2IF : stm8s.h
  • TIM1_SR1_CC3IF : stm8s.h
  • TIM1_SR1_CC4IF : stm8s.h
  • TIM1_SR1_COMIF : stm8s.h
  • TIM1_SR1_RESET_VALUE : stm8s.h
  • TIM1_SR1_TIF : stm8s.h
  • TIM1_SR1_UIF : stm8s.h
  • TIM1_SR2_CC1OF : stm8s.h
  • TIM1_SR2_CC2OF : stm8s.h
  • TIM1_SR2_CC3OF : stm8s.h
  • TIM1_SR2_CC4OF : stm8s.h
  • TIM1_SR2_RESET_VALUE : stm8s.h
  • TIM1_TimeBaseInit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1 : stm8s_tim1.h
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1ED : stm8s_tim1.h
  • TIM1_TIXEXTERNALCLK1SOURCE_TI2 : stm8s_tim1.h
  • TIM1_TIxExternalCLK1Source_TypeDef : stm8s_tim1.h
  • TIM1_TIxExternalClockConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_TRGOSOURCE_ENABLE : stm8s_tim1.h
  • TIM1_TRGOSource_OC1 : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC1REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC2REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC3REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_RESET : stm8s_tim1.h
  • TIM1_TRGOSource_TypeDef : stm8s_tim1.h
  • TIM1_TRGOSOURCE_UPDATE : stm8s_tim1.h
  • TIM1_TS_ETRF : stm8s_tim1.h
  • TIM1_TS_TI1F_ED : stm8s_tim1.h
  • TIM1_TS_TI1FP1 : stm8s_tim1.h
  • TIM1_TS_TI2FP2 : stm8s_tim1.h
  • TIM1_TS_TIM5 : stm8s_tim1.h
  • TIM1_TS_TIM6 : stm8s_tim1.h
  • TIM1_TS_TypeDef : stm8s_tim1.h
  • TIM1_TypeDef : stm8s.h
  • TIM1_UpdateDisableConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_UpdateRequestConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_UPDATESOURCE_GLOBAL : stm8s_tim1.h
  • TIM1_UPDATESOURCE_REGULAR : stm8s_tim1.h
  • TIM1_UpdateSource_TypeDef : stm8s_tim1.h
  • TIM2_ARRH_ARR : stm8s.h
  • TIM2_ARRH_RESET_VALUE : stm8s.h
  • TIM2_ARRL_ARR : stm8s.h
  • TIM2_ARRL_RESET_VALUE : stm8s.h
  • TIM2_ARRPreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_BaseAddress : stm8s.h
  • TIM2_CCER1_CC1E : stm8s.h
  • TIM2_CCER1_CC1P : stm8s.h
  • TIM2_CCER1_CC2E : stm8s.h
  • TIM2_CCER1_CC2P : stm8s.h
  • TIM2_CCER1_RESET_VALUE : stm8s.h
  • TIM2_CCER2_CC3E : stm8s.h
  • TIM2_CCER2_CC3P : stm8s.h
  • TIM2_CCER2_RESET_VALUE : stm8s.h
  • TIM2_CCMR1_RESET_VALUE : stm8s.h
  • TIM2_CCMR2_RESET_VALUE : stm8s.h
  • TIM2_CCMR3_RESET_VALUE : stm8s.h
  • TIM2_CCMR_CCxS : stm8s.h
  • TIM2_CCMR_ICxF : stm8s.h
  • TIM2_CCMR_ICxPSC : stm8s.h
  • TIM2_CCMR_OCM : stm8s.h
  • TIM2_CCMR_OCxPE : stm8s.h
  • TIM2_CCPreloadControl() : stm8s_tim2.h
  • TIM2_CCR1H_CCR1 : stm8s.h
  • TIM2_CCR1H_RESET_VALUE : stm8s.h
  • TIM2_CCR1L_CCR1 : stm8s.h
  • TIM2_CCR1L_RESET_VALUE : stm8s.h
  • TIM2_CCR2H_CCR2 : stm8s.h
  • TIM2_CCR2H_RESET_VALUE : stm8s.h
  • TIM2_CCR2L_CCR2 : stm8s.h
  • TIM2_CCR2L_RESET_VALUE : stm8s.h
  • TIM2_CCR3H_CCR3 : stm8s.h
  • TIM2_CCR3H_RESET_VALUE : stm8s.h
  • TIM2_CCR3L_CCR3 : stm8s.h
  • TIM2_CCR3L_RESET_VALUE : stm8s.h
  • TIM2_CCxCmd() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_CHANNEL_1 : stm8s_tim2.h
  • TIM2_CHANNEL_2 : stm8s_tim2.h
  • TIM2_CHANNEL_3 : stm8s_tim2.h
  • TIM2_Channel_TypeDef : stm8s_tim2.h
  • TIM2_ClearFlag() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ClearITPendingBit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_Cmd() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_CNTRH_CNT : stm8s.h
  • TIM2_CNTRH_RESET_VALUE : stm8s.h
  • TIM2_CNTRL_CNT : stm8s.h
  • TIM2_CNTRL_RESET_VALUE : stm8s.h
  • TIM2_CR1_ARPE : stm8s.h
  • TIM2_CR1_CEN : stm8s.h
  • TIM2_CR1_OPM : stm8s.h
  • TIM2_CR1_RESET_VALUE : stm8s.h
  • TIM2_CR1_UDIS : stm8s.h
  • TIM2_CR1_URS : stm8s.h
  • TIM2_DeInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_EGR_CC1G : stm8s.h
  • TIM2_EGR_CC2G : stm8s.h
  • TIM2_EGR_CC3G : stm8s.h
  • TIM2_EGR_RESET_VALUE : stm8s.h
  • TIM2_EGR_UG : stm8s.h
  • TIM2_EVENTSOURCE_CC1 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_CC2 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_CC3 : stm8s_tim2.h
  • TIM2_EventSource_TypeDef : stm8s_tim2.h
  • TIM2_EVENTSOURCE_UPDATE : stm8s_tim2.h
  • TIM2_FLAG_CC1 : stm8s_tim2.h
  • TIM2_FLAG_CC1OF : stm8s_tim2.h
  • TIM2_FLAG_CC2 : stm8s_tim2.h
  • TIM2_FLAG_CC2OF : stm8s_tim2.h
  • TIM2_FLAG_CC3 : stm8s_tim2.h
  • TIM2_FLAG_CC3OF : stm8s_tim2.h
  • TIM2_FLAG_TypeDef : stm8s_tim2.h
  • TIM2_FLAG_UPDATE : stm8s_tim2.h
  • TIM2_FORCEDACTION_ACTIVE : stm8s_tim2.h
  • TIM2_FORCEDACTION_INACTIVE : stm8s_tim2.h
  • TIM2_ForcedAction_TypeDef : stm8s_tim2.h
  • TIM2_ForcedOC1Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ForcedOC2Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ForcedOC3Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GenerateEvent() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture1() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture2() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture3() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCounter() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetFlagStatus() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetITStatus() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetPrescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ICInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ICPOLARITY_FALLING : stm8s_tim2.h
  • TIM2_ICPOLARITY_RISING : stm8s_tim2.h
  • TIM2_ICPolarity_TypeDef : stm8s_tim2.h
  • TIM2_ICPSC_DIV1 : stm8s_tim2.h
  • TIM2_ICPSC_DIV2 : stm8s_tim2.h
  • TIM2_ICPSC_DIV4 : stm8s_tim2.h
  • TIM2_ICPSC_DIV8 : stm8s_tim2.h
  • TIM2_ICPSC_TypeDef : stm8s_tim2.h
  • TIM2_ICSELECTION_DIRECTTI : stm8s_tim2.h
  • TIM2_ICSELECTION_INDIRECTTI : stm8s_tim2.h
  • TIM2_ICSELECTION_TRGI : stm8s_tim2.h
  • TIM2_ICSelection_TypeDef : stm8s_tim2.h
  • TIM2_IER_CC1IE : stm8s.h
  • TIM2_IER_CC2IE : stm8s.h
  • TIM2_IER_CC3IE : stm8s.h
  • TIM2_IER_RESET_VALUE : stm8s.h
  • TIM2_IER_UIE : stm8s.h
  • TIM2_InternalClockConfig() : stm8s_tim2.h
  • TIM2_IT_CC1 : stm8s_tim2.h
  • TIM2_IT_CC2 : stm8s_tim2.h
  • TIM2_IT_CC3 : stm8s_tim2.h
  • TIM2_IT_TypeDef : stm8s_tim2.h
  • TIM2_IT_UPDATE : stm8s_tim2.h
  • TIM2_ITConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OCMODE_ACTIVE : stm8s_tim2.h
  • TIM2_OCMODE_INACTIVE : stm8s_tim2.h
  • TIM2_OCMODE_PWM1 : stm8s_tim2.h
  • TIM2_OCMODE_PWM2 : stm8s_tim2.h
  • TIM2_OCMODE_TIMING : stm8s_tim2.h
  • TIM2_OCMODE_TOGGLE : stm8s_tim2.h
  • TIM2_OCMode_TypeDef : stm8s_tim2.h
  • TIM2_OCPOLARITY_HIGH : stm8s_tim2.h
  • TIM2_OCPOLARITY_LOW : stm8s_tim2.h
  • TIM2_OCPolarity_TypeDef : stm8s_tim2.h
  • TIM2_OPMODE_REPETITIVE : stm8s_tim2.h
  • TIM2_OPMODE_SINGLE : stm8s_tim2.h
  • TIM2_OPMode_TypeDef : stm8s_tim2.h
  • TIM2_OUTPUTSTATE_DISABLE : stm8s_tim2.h
  • TIM2_OUTPUTSTATE_ENABLE : stm8s_tim2.h
  • TIM2_OutputState_TypeDef : stm8s_tim2.h
  • TIM2_PRESCALER_1 : stm8s_tim2.h
  • TIM2_PRESCALER_1024 : stm8s_tim2.h
  • TIM2_PRESCALER_128 : stm8s_tim2.h
  • TIM2_PRESCALER_16 : stm8s_tim2.h
  • TIM2_PRESCALER_16384 : stm8s_tim2.h
  • TIM2_PRESCALER_2 : stm8s_tim2.h
  • TIM2_PRESCALER_2048 : stm8s_tim2.h
  • TIM2_PRESCALER_256 : stm8s_tim2.h
  • TIM2_PRESCALER_32 : stm8s_tim2.h
  • TIM2_PRESCALER_32768 : stm8s_tim2.h
  • TIM2_PRESCALER_4 : stm8s_tim2.h
  • TIM2_PRESCALER_4096 : stm8s_tim2.h
  • TIM2_PRESCALER_512 : stm8s_tim2.h
  • TIM2_PRESCALER_64 : stm8s_tim2.h
  • TIM2_PRESCALER_8 : stm8s_tim2.h
  • TIM2_PRESCALER_8192 : stm8s_tim2.h
  • TIM2_Prescaler_TypeDef : stm8s_tim2.h
  • TIM2_PrescalerConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_PSCR_PSC : stm8s.h
  • TIM2_PSCR_RESET_VALUE : stm8s.h
  • TIM2_PSCRELOADMODE_IMMEDIATE : stm8s_tim2.h
  • TIM2_PSCReloadMode_TypeDef : stm8s_tim2.h
  • TIM2_PSCRELOADMODE_UPDATE : stm8s_tim2.h
  • TIM2_PWMIConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SelectOCxM() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SelectOnePulseMode() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetAutoreload() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare1() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare2() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare3() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCounter() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC1Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC2Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC3Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SR1_CC1IF : stm8s.h
  • TIM2_SR1_CC2IF : stm8s.h
  • TIM2_SR1_CC3IF : stm8s.h
  • TIM2_SR1_RESET_VALUE : stm8s.h
  • TIM2_SR1_UIF : stm8s.h
  • TIM2_SR2_CC1OF : stm8s.h
  • TIM2_SR2_CC2OF : stm8s.h
  • TIM2_SR2_CC3OF : stm8s.h
  • TIM2_SR2_RESET_VALUE : stm8s.h
  • TIM2_TimeBaseInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_TypeDef : stm8s.h
  • TIM2_UpdateDisableConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_UpdateRequestConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_UPDATESOURCE_GLOBAL : stm8s_tim2.h
  • TIM2_UPDATESOURCE_REGULAR : stm8s_tim2.h
  • TIM2_UpdateSource_TypeDef : stm8s_tim2.h
  • TIM3_ARRH_ARR : stm8s.h
  • TIM3_ARRH_RESET_VALUE : stm8s.h
  • TIM3_ARRL_ARR : stm8s.h
  • TIM3_ARRL_RESET_VALUE : stm8s.h
  • TIM3_ARRPreloadConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_BaseAddress : stm8s.h
  • TIM3_CCER1_CC1E : stm8s.h
  • TIM3_CCER1_CC1P : stm8s.h
  • TIM3_CCER1_CC2E : stm8s.h
  • TIM3_CCER1_CC2P : stm8s.h
  • TIM3_CCER1_RESET_VALUE : stm8s.h
  • TIM3_CCMR1_RESET_VALUE : stm8s.h
  • TIM3_CCMR2_RESET_VALUE : stm8s.h
  • TIM3_CCMR_CCxS : stm8s.h
  • TIM3_CCMR_ICxF : stm8s.h
  • TIM3_CCMR_ICxPSC : stm8s.h
  • TIM3_CCMR_OCM : stm8s.h
  • TIM3_CCMR_OCxPE : stm8s.h
  • TIM3_CCPreloadControl() : stm8s_tim3.h
  • TIM3_CCR1H_CCR1 : stm8s.h
  • TIM3_CCR1H_RESET_VALUE : stm8s.h
  • TIM3_CCR1L_CCR1 : stm8s.h
  • TIM3_CCR1L_RESET_VALUE : stm8s.h
  • TIM3_CCR2H_CCR2 : stm8s.h
  • TIM3_CCR2H_RESET_VALUE : stm8s.h
  • TIM3_CCR2L_CCR2 : stm8s.h
  • TIM3_CCR2L_RESET_VALUE : stm8s.h
  • TIM3_CCxCmd() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_CHANNEL_1 : stm8s_tim3.h
  • TIM3_CHANNEL_2 : stm8s_tim3.h
  • TIM3_Channel_TypeDef : stm8s_tim3.h
  • TIM3_ClearFlag() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ClearITPendingBit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_Cmd() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_CNTRH_CNT : stm8s.h
  • TIM3_CNTRH_RESET_VALUE : stm8s.h
  • TIM3_CNTRL_CNT : stm8s.h
  • TIM3_CNTRL_RESET_VALUE : stm8s.h
  • TIM3_CR1_ARPE : stm8s.h
  • TIM3_CR1_CEN : stm8s.h
  • TIM3_CR1_OPM : stm8s.h
  • TIM3_CR1_RESET_VALUE : stm8s.h
  • TIM3_CR1_UDIS : stm8s.h
  • TIM3_CR1_URS : stm8s.h
  • TIM3_DeInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_EGR_CC1G : stm8s.h
  • TIM3_EGR_CC2G : stm8s.h
  • TIM3_EGR_RESET_VALUE : stm8s.h
  • TIM3_EGR_UG : stm8s.h
  • TIM3_EVENTSOURCE_CC1 : stm8s_tim3.h
  • TIM3_EVENTSOURCE_CC2 : stm8s_tim3.h
  • TIM3_EventSource_TypeDef : stm8s_tim3.h
  • TIM3_EVENTSOURCE_UPDATE : stm8s_tim3.h
  • TIM3_FLAG_CC1 : stm8s_tim3.h
  • TIM3_FLAG_CC1OF : stm8s_tim3.h
  • TIM3_FLAG_CC2 : stm8s_tim3.h
  • TIM3_FLAG_CC2OF : stm8s_tim3.h
  • TIM3_FLAG_TypeDef : stm8s_tim3.h
  • TIM3_FLAG_UPDATE : stm8s_tim3.h
  • TIM3_FORCEDACTION_ACTIVE : stm8s_tim3.h
  • TIM3_FORCEDACTION_INACTIVE : stm8s_tim3.h
  • TIM3_ForcedAction_TypeDef : stm8s_tim3.h
  • TIM3_ForcedOC1Config() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_ForcedOC2Config() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GenerateEvent() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetCapture1() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetCapture2() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_GetCounter() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetFlagStatus() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_GetITStatus() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetPrescaler() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_ICInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ICPOLARITY_FALLING : stm8s_tim3.h
  • TIM3_ICPOLARITY_RISING : stm8s_tim3.h
  • TIM3_ICPolarity_TypeDef : stm8s_tim3.h
  • TIM3_ICPSC_DIV1 : stm8s_tim3.h
  • TIM3_ICPSC_DIV2 : stm8s_tim3.h
  • TIM3_ICPSC_DIV4 : stm8s_tim3.h
  • TIM3_ICPSC_DIV8 : stm8s_tim3.h
  • TIM3_ICPSC_TypeDef : stm8s_tim3.h
  • TIM3_ICSELECTION_DIRECTTI : stm8s_tim3.h
  • TIM3_ICSELECTION_INDIRECTTI : stm8s_tim3.h
  • TIM3_ICSELECTION_TRGI : stm8s_tim3.h
  • TIM3_ICSelection_TypeDef : stm8s_tim3.h
  • TIM3_IER_CC1IE : stm8s.h
  • TIM3_IER_CC2IE : stm8s.h
  • TIM3_IER_RESET_VALUE : stm8s.h
  • TIM3_IER_UIE : stm8s.h
  • TIM3_InternalClockConfig() : stm8s_tim3.h
  • TIM3_IT_CC1 : stm8s_tim3.h
  • TIM3_IT_CC2 : stm8s_tim3.h
  • TIM3_IT_TypeDef : stm8s_tim3.h
  • TIM3_IT_UPDATE : stm8s_tim3.h
  • TIM3_ITConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC1Init() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC1PolarityConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC1PreloadConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2Init() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2PolarityConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2PreloadConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OCMODE_ACTIVE : stm8s_tim3.h
  • TIM3_OCMODE_INACTIVE : stm8s_tim3.h
  • TIM3_OCMODE_PWM1 : stm8s_tim3.h
  • TIM3_OCMODE_PWM2 : stm8s_tim3.h
  • TIM3_OCMODE_TIMING : stm8s_tim3.h
  • TIM3_OCMODE_TOGGLE : stm8s_tim3.h
  • TIM3_OCMode_TypeDef : stm8s_tim3.h
  • TIM3_OCPOLARITY_HIGH : stm8s_tim3.h
  • TIM3_OCPOLARITY_LOW : stm8s_tim3.h
  • TIM3_OCPolarity_TypeDef : stm8s_tim3.h
  • TIM3_OPMODE_REPETITIVE : stm8s_tim3.h
  • TIM3_OPMODE_SINGLE : stm8s_tim3.h
  • TIM3_OPMode_TypeDef : stm8s_tim3.h
  • TIM3_OUTPUTSTATE_DISABLE : stm8s_tim3.h
  • TIM3_OUTPUTSTATE_ENABLE : stm8s_tim3.h
  • TIM3_OutputState_TypeDef : stm8s_tim3.h
  • TIM3_PRESCALER_1 : stm8s_tim3.h
  • TIM3_PRESCALER_1024 : stm8s_tim3.h
  • TIM3_PRESCALER_128 : stm8s_tim3.h
  • TIM3_PRESCALER_16 : stm8s_tim3.h
  • TIM3_PRESCALER_16384 : stm8s_tim3.h
  • TIM3_PRESCALER_2 : stm8s_tim3.h
  • TIM3_PRESCALER_2048 : stm8s_tim3.h
  • TIM3_PRESCALER_256 : stm8s_tim3.h
  • TIM3_PRESCALER_32 : stm8s_tim3.h
  • TIM3_PRESCALER_32768 : stm8s_tim3.h
  • TIM3_PRESCALER_4 : stm8s_tim3.h
  • TIM3_PRESCALER_4096 : stm8s_tim3.h
  • TIM3_PRESCALER_512 : stm8s_tim3.h
  • TIM3_PRESCALER_64 : stm8s_tim3.h
  • TIM3_PRESCALER_8 : stm8s_tim3.h
  • TIM3_PRESCALER_8192 : stm8s_tim3.h
  • TIM3_Prescaler_TypeDef : stm8s_tim3.h
  • TIM3_PrescalerConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_PSCR_PSC : stm8s.h
  • TIM3_PSCR_RESET_VALUE : stm8s.h
  • TIM3_PSCRELOADMODE_IMMEDIATE : stm8s_tim3.h
  • TIM3_PSCReloadMode_TypeDef : stm8s_tim3.h
  • TIM3_PSCRELOADMODE_UPDATE : stm8s_tim3.h
  • TIM3_PWMIConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SelectOCxM() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SelectOnePulseMode() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetAutoreload() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetCompare1() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetCompare2() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_SetCounter() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetIC1Prescaler() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_SetIC2Prescaler() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SR1_CC1IF : stm8s.h
  • TIM3_SR1_CC2IF : stm8s.h
  • TIM3_SR1_RESET_VALUE : stm8s.h
  • TIM3_SR1_UIF : stm8s.h
  • TIM3_SR2_CC1OF : stm8s.h
  • TIM3_SR2_CC2OF : stm8s.h
  • TIM3_SR2_RESET_VALUE : stm8s.h
  • TIM3_TimeBaseInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_TypeDef : stm8s.h
  • TIM3_UpdateDisableConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_UpdateRequestConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_UPDATESOURCE_GLOBAL : stm8s_tim3.h
  • TIM3_UPDATESOURCE_REGULAR : stm8s_tim3.h
  • TIM3_UpdateSource_TypeDef : stm8s_tim3.h
  • TIM4_ARR_ARR : stm8s.h
  • TIM4_ARR_RESET_VALUE : stm8s.h
  • TIM4_ARRPreloadConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_BaseAddress : stm8s.h
  • TIM4_ClearFlag() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_ClearITPendingBit() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_Cmd() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_CNTR_CNT : stm8s.h
  • TIM4_CNTR_RESET_VALUE : stm8s.h
  • TIM4_CR1_ARPE : stm8s.h
  • TIM4_CR1_CEN : stm8s.h
  • TIM4_CR1_OPM : stm8s.h
  • TIM4_CR1_RESET_VALUE : stm8s.h
  • TIM4_CR1_UDIS : stm8s.h
  • TIM4_CR1_URS : stm8s.h
  • TIM4_DeInit() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_EGR_RESET_VALUE : stm8s.h
  • TIM4_EGR_UG : stm8s.h
  • TIM4_EventSource_TypeDef : stm8s_tim4.h
  • TIM4_EVENTSOURCE_UPDATE : stm8s_tim4.h
  • TIM4_FLAG_TypeDef : stm8s_tim4.h
  • TIM4_FLAG_UPDATE : stm8s_tim4.h
  • TIM4_GenerateEvent() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_GetCounter() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_GetFlagStatus() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_GetITStatus() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_GetPrescaler() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_IER_RESET_VALUE : stm8s.h
  • TIM4_IER_UIE : stm8s.h
  • TIM4_IT_TypeDef : stm8s_tim4.h
  • TIM4_IT_UPDATE : stm8s_tim4.h
  • TIM4_ITConfig() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_OPMODE_REPETITIVE : stm8s_tim4.h
  • TIM4_OPMODE_SINGLE : stm8s_tim4.h
  • TIM4_OPMode_TypeDef : stm8s_tim4.h
  • TIM4_PRESCALER_1 : stm8s_tim4.h
  • TIM4_PRESCALER_128 : stm8s_tim4.h
  • TIM4_PRESCALER_16 : stm8s_tim4.h
  • TIM4_PRESCALER_2 : stm8s_tim4.h
  • TIM4_PRESCALER_32 : stm8s_tim4.h
  • TIM4_PRESCALER_4 : stm8s_tim4.h
  • TIM4_PRESCALER_64 : stm8s_tim4.h
  • TIM4_PRESCALER_8 : stm8s_tim4.h
  • TIM4_Prescaler_TypeDef : stm8s_tim4.h
  • TIM4_PrescalerConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_PSCR_PSC : stm8s.h
  • TIM4_PSCR_RESET_VALUE : stm8s.h
  • TIM4_PSCRELOADMODE_IMMEDIATE : stm8s_tim4.h
  • TIM4_PSCReloadMode_TypeDef : stm8s_tim4.h
  • TIM4_PSCRELOADMODE_UPDATE : stm8s_tim4.h
  • TIM4_SelectOnePulseMode() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_SetAutoreload() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_SetCounter() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_SR1_RESET_VALUE : stm8s.h
  • TIM4_SR1_UIF : stm8s.h
  • TIM4_TimeBaseInit() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_TypeDef : stm8s.h
  • TIM4_UpdateDisableConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_UpdateRequestConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_UPDATESOURCE_GLOBAL : stm8s_tim4.h
  • TIM4_UPDATESOURCE_REGULAR : stm8s_tim4.h
  • TIM4_UpdateSource_TypeDef : stm8s_tim4.h
  • TIM5_ARRH_ARR : stm8s.h
  • TIM5_ARRH_RESET_VALUE : stm8s.h
  • TIM5_ARRL_ARR : stm8s.h
  • TIM5_ARRL_RESET_VALUE : stm8s.h
  • TIM5_ARRPreloadConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_BaseAddress : stm8s.h
  • TIM5_CCER1_CC1E : stm8s.h
  • TIM5_CCER1_CC1P : stm8s.h
  • TIM5_CCER1_CC2E : stm8s.h
  • TIM5_CCER1_CC2P : stm8s.h
  • TIM5_CCER1_RESET_VALUE : stm8s.h
  • TIM5_CCER2_CC3E : stm8s.h
  • TIM5_CCER2_CC3P : stm8s.h
  • TIM5_CCER2_RESET_VALUE : stm8s.h
  • TIM5_CCMR1_RESET_VALUE : stm8s.h
  • TIM5_CCMR2_RESET_VALUE : stm8s.h
  • TIM5_CCMR3_RESET_VALUE : stm8s.h
  • TIM5_CCMR_CCxS : stm8s.h
  • TIM5_CCMR_ICxF : stm8s.h
  • TIM5_CCMR_ICxPSC : stm8s.h
  • TIM5_CCMR_OCM : stm8s.h
  • TIM5_CCMR_OCxPE : stm8s.h
  • TIM5_CCMR_TIxDirect_Set : stm8s.h
  • TIM5_CCPreloadControl() : stm8s_tim5.h
  • TIM5_CCR1H_CCR1 : stm8s.h
  • TIM5_CCR1H_RESET_VALUE : stm8s.h
  • TIM5_CCR1L_CCR1 : stm8s.h
  • TIM5_CCR1L_RESET_VALUE : stm8s.h
  • TIM5_CCR2H_CCR2 : stm8s.h
  • TIM5_CCR2H_RESET_VALUE : stm8s.h
  • TIM5_CCR2L_CCR2 : stm8s.h
  • TIM5_CCR2L_RESET_VALUE : stm8s.h
  • TIM5_CCR3H_CCR3 : stm8s.h
  • TIM5_CCR3H_RESET_VALUE : stm8s.h
  • TIM5_CCR3L_CCR3 : stm8s.h
  • TIM5_CCR3L_RESET_VALUE : stm8s.h
  • TIM5_CCxCmd() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_CHANNEL_1 : stm8s_tim5.h
  • TIM5_CHANNEL_2 : stm8s_tim5.h
  • TIM5_CHANNEL_3 : stm8s_tim5.h
  • TIM5_Channel_TypeDef : stm8s_tim5.h
  • TIM5_ClearFlag() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ClearITPendingBit() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_Cmd() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_CNTRH_CNT : stm8s.h
  • TIM5_CNTRH_RESET_VALUE : stm8s.h
  • TIM5_CNTRL_CNT : stm8s.h
  • TIM5_CNTRL_RESET_VALUE : stm8s.h
  • TIM5_CR1_ARPE : stm8s.h
  • TIM5_CR1_CEN : stm8s.h
  • TIM5_CR1_OPM : stm8s.h
  • TIM5_CR1_RESET_VALUE : stm8s.h
  • TIM5_CR1_UDIS : stm8s.h
  • TIM5_CR1_URS : stm8s.h
  • TIM5_CR2_MMS : stm8s.h
  • TIM5_CR2_RESET_VALUE : stm8s.h
  • TIM5_CR2_TI1S : stm8s.h
  • TIM5_DeInit() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_EGR_CC1G : stm8s.h
  • TIM5_EGR_CC2G : stm8s.h
  • TIM5_EGR_CC3G : stm8s.h
  • TIM5_EGR_RESET_VALUE : stm8s.h
  • TIM5_EGR_TG : stm8s.h
  • TIM5_EGR_UG : stm8s.h
  • TIM5_EncoderInterfaceConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_ENCODERMODE_TI1 : stm8s_tim5.h
  • TIM5_ENCODERMODE_TI12 : stm8s_tim5.h
  • TIM5_ENCODERMODE_TI2 : stm8s_tim5.h
  • TIM5_EncoderMode_TypeDef : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC1 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC2 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC3 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_TRIGGER : stm8s_tim5.h
  • TIM5_EventSource_TypeDef : stm8s_tim5.h
  • TIM5_EVENTSOURCE_UPDATE : stm8s_tim5.h
  • TIM5_EXTTRGPOLARITY_INVERTED : stm8s_tim5.h
  • TIM5_EXTTRGPOLARITY_NONINVERTED : stm8s_tim5.h
  • TIM5_ExtTRGPolarity_TypeDef : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV2 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV4 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV8 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_OFF : stm8s_tim5.h
  • TIM5_ExtTRGPSC_TypeDef : stm8s_tim5.h
  • TIM5_FLAG_CC1 : stm8s_tim5.h
  • TIM5_FLAG_CC1OF : stm8s_tim5.h
  • TIM5_FLAG_CC2 : stm8s_tim5.h
  • TIM5_FLAG_CC2OF : stm8s_tim5.h
  • TIM5_FLAG_CC3 : stm8s_tim5.h
  • TIM5_FLAG_CC3OF : stm8s_tim5.h
  • TIM5_FLAG_TRIGGER : stm8s_tim5.h
  • TIM5_FLAG_TypeDef : stm8s_tim5.h
  • TIM5_FLAG_UPDATE : stm8s_tim5.h
  • TIM5_FORCEDACTION_ACTIVE : stm8s_tim5.h
  • TIM5_FORCEDACTION_INACTIVE : stm8s_tim5.h
  • TIM5_ForcedAction_TypeDef : stm8s_tim5.h
  • TIM5_ForcedOC1Config() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_ForcedOC2Config() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ForcedOC3Config() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GenerateEvent() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetCapture1() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_GetCapture2() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetCapture3() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_GetCounter() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetFlagStatus() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_GetITStatus() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetPrescaler() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ICInit() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ICPOLARITY_FALLING : stm8s_tim5.h
  • TIM5_ICPOLARITY_RISING : stm8s_tim5.h
  • TIM5_ICPolarity_TypeDef : stm8s_tim5.h
  • TIM5_ICPSC_DIV1 : stm8s_tim5.h
  • TIM5_ICPSC_DIV2 : stm8s_tim5.h
  • TIM5_ICPSC_DIV4 : stm8s_tim5.h
  • TIM5_ICPSC_DIV8 : stm8s_tim5.h
  • TIM5_ICPSC_TypeDef : stm8s_tim5.h
  • TIM5_ICSELECTION_DIRECTTI : stm8s_tim5.h
  • TIM5_ICSELECTION_INDIRECTTI : stm8s_tim5.h
  • TIM5_ICSELECTION_TRGI : stm8s_tim5.h
  • TIM5_ICSelection_TypeDef : stm8s_tim5.h
  • TIM5_IER_CC1IE : stm8s.h
  • TIM5_IER_CC2IE : stm8s.h
  • TIM5_IER_CC3IE : stm8s.h
  • TIM5_IER_RESET_VALUE : stm8s.h
  • TIM5_IER_TIE : stm8s.h
  • TIM5_IER_UIE : stm8s.h
  • TIM5_InternalClockConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_IT_CC1 : stm8s_tim5.h
  • TIM5_IT_CC2 : stm8s_tim5.h
  • TIM5_IT_CC3 : stm8s_tim5.h
  • TIM5_IT_TRIGGER : stm8s_tim5.h
  • TIM5_IT_TypeDef : stm8s_tim5.h
  • TIM5_IT_UPDATE : stm8s_tim5.h
  • TIM5_ITConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1Init() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1PolarityConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1PreloadConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC2Init() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC2PolarityConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_OC2PreloadConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC3Init() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC3PolarityConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC3PreloadConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_OCMODE_ACTIVE : stm8s_tim5.h
  • TIM5_OCMODE_INACTIVE : stm8s_tim5.h
  • TIM5_OCMODE_PWM1 : stm8s_tim5.h
  • TIM5_OCMODE_PWM2 : stm8s_tim5.h
  • TIM5_OCMODE_TIMING : stm8s_tim5.h
  • TIM5_OCMODE_TOGGLE : stm8s_tim5.h
  • TIM5_OCMode_TypeDef : stm8s_tim5.h
  • TIM5_OCPOLARITY_HIGH : stm8s_tim5.h
  • TIM5_OCPOLARITY_LOW : stm8s_tim5.h
  • TIM5_OCPolarity_TypeDef : stm8s_tim5.h
  • TIM5_OPMODE_REPETITIVE : stm8s_tim5.h
  • TIM5_OPMODE_SINGLE : stm8s_tim5.h
  • TIM5_OPMode_TypeDef : stm8s_tim5.h
  • TIM5_OUTPUTSTATE_DISABLE : stm8s_tim5.h
  • TIM5_OUTPUTSTATE_ENABLE : stm8s_tim5.h
  • TIM5_OutputState_TypeDef : stm8s_tim5.h
  • TIM5_PRESCALER_1 : stm8s_tim5.h
  • TIM5_PRESCALER_1024 : stm8s_tim5.h
  • TIM5_PRESCALER_128 : stm8s_tim5.h
  • TIM5_PRESCALER_16 : stm8s_tim5.h
  • TIM5_PRESCALER_16384 : stm8s_tim5.h
  • TIM5_PRESCALER_2 : stm8s_tim5.h
  • TIM5_PRESCALER_2048 : stm8s_tim5.h
  • TIM5_PRESCALER_256 : stm8s_tim5.h
  • TIM5_PRESCALER_32 : stm8s_tim5.h
  • TIM5_PRESCALER_32768 : stm8s_tim5.h
  • TIM5_PRESCALER_4 : stm8s_tim5.h
  • TIM5_PRESCALER_4096 : stm8s_tim5.h
  • TIM5_PRESCALER_512 : stm8s_tim5.h
  • TIM5_PRESCALER_64 : stm8s_tim5.h
  • TIM5_PRESCALER_8 : stm8s_tim5.h
  • TIM5_PRESCALER_8192 : stm8s_tim5.h
  • TIM5_Prescaler_TypeDef : stm8s_tim5.h
  • TIM5_PrescalerConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_PSCR_PSC : stm8s.h
  • TIM5_PSCR_RESET_VALUE : stm8s.h
  • TIM5_PSCRELOADMODE_IMMEDIATE : stm8s_tim5.h
  • TIM5_PSCReloadMode_TypeDef : stm8s_tim5.h
  • TIM5_PSCRELOADMODE_UPDATE : stm8s_tim5.h
  • TIM5_PWMIConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SelectInputTrigger() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SelectOCxM() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SelectOnePulseMode() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectOutputTrigger() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectSlaveMode() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetAutoreload() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCompare1() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCompare2() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCompare3() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCounter() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetIC1Prescaler() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetIC2Prescaler() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetIC3Prescaler() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SLAVEMODE_EXTERNAL1 : stm8s_tim5.h
  • TIM5_SLAVEMODE_GATED : stm8s_tim5.h
  • TIM5_SLAVEMODE_RESET : stm8s_tim5.h
  • TIM5_SLAVEMODE_TRIGGER : stm8s_tim5.h
  • TIM5_SlaveMode_TypeDef : stm8s_tim5.h
  • TIM5_SMCR_MSM : stm8s.h
  • TIM5_SMCR_RESET_VALUE : stm8s.h
  • TIM5_SMCR_SMS : stm8s.h
  • TIM5_SMCR_TS : stm8s.h
  • TIM5_SR1_CC1IF : stm8s.h
  • TIM5_SR1_CC2IF : stm8s.h
  • TIM5_SR1_CC3IF : stm8s.h
  • TIM5_SR1_RESET_VALUE : stm8s.h
  • TIM5_SR1_TIF : stm8s.h
  • TIM5_SR1_UIF : stm8s.h
  • TIM5_SR2_CC1OF : stm8s.h
  • TIM5_SR2_CC2OF : stm8s.h
  • TIM5_SR2_CC3OF : stm8s.h
  • TIM5_SR2_RESET_VALUE : stm8s.h
  • TIM5_TimeBaseInit() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_TRGOSOURCE_ENABLE : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC1 : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC1REF : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC2REF : stm8s_tim5.h
  • TIM5_TRGOSOURCE_RESET : stm8s_tim5.h
  • TIM5_TRGOSource_TypeDef : stm8s_tim5.h
  • TIM5_TRGOSOURCE_UPDATE : stm8s_tim5.h
  • TIM5_TS_TIM1 : stm8s_tim5.h
  • TIM5_TS_TIM6 : stm8s_tim5.h
  • TIM5_TS_TypeDef : stm8s_tim5.h
  • TIM5_TypeDef : stm8s.h
  • TIM5_UpdateDisableConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_UpdateRequestConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_UPDATESOURCE_GLOBAL : stm8s_tim5.h
  • TIM5_UPDATESOURCE_REGULAR : stm8s_tim5.h
  • TIM5_UpdateSource_TypeDef : stm8s_tim5.h
  • TIM6_ARR_ARR : stm8s.h
  • TIM6_ARR_RESET_VALUE : stm8s.h
  • TIM6_ARRPreloadConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_BaseAddress : stm8s.h
  • TIM6_ClearFlag() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_ClearITPendingBit() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_Cmd() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_CNTR_CNT : stm8s.h
  • TIM6_CNTR_RESET_VALUE : stm8s.h
  • TIM6_CR1_ARPE : stm8s.h
  • TIM6_CR1_CEN : stm8s.h
  • TIM6_CR1_OPM : stm8s.h
  • TIM6_CR1_RESET_VALUE : stm8s.h
  • TIM6_CR1_UDIS : stm8s.h
  • TIM6_CR1_URS : stm8s.h
  • TIM6_CR2_MMS : stm8s.h
  • TIM6_CR2_RESET_VALUE : stm8s.h
  • TIM6_DeInit() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_EGR_RESET_VALUE : stm8s.h
  • TIM6_EGR_TG : stm8s.h
  • TIM6_EGR_UG : stm8s.h
  • TIM6_EVENTSOURCE_TRIGGER : stm8s_tim6.h
  • TIM6_EventSource_TypeDef : stm8s_tim6.h
  • TIM6_EVENTSOURCE_UPDATE : stm8s_tim6.h
  • TIM6_FLAG_TRIGGER : stm8s_tim6.h
  • TIM6_FLAG_TypeDef : stm8s_tim6.h
  • TIM6_FLAG_UPDATE : stm8s_tim6.h
  • TIM6_GenerateEvent() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_GetCounter() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GetFlagStatus() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GetITStatus() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_GetPrescaler() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_IER_RESET_VALUE : stm8s.h
  • TIM6_IER_TIE : stm8s.h
  • TIM6_IER_UIE : stm8s.h
  • TIM6_InternalClockConfig() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_IT_TRIGGER : stm8s_tim6.h
  • TIM6_IT_TypeDef : stm8s_tim6.h
  • TIM6_IT_UPDATE : stm8s_tim6.h
  • TIM6_ITConfig() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_OPMODE_REPETITIVE : stm8s_tim6.h
  • TIM6_OPMODE_SINGLE : stm8s_tim6.h
  • TIM6_OPMode_TypeDef : stm8s_tim6.h
  • TIM6_PRESCALER_1 : stm8s_tim6.h
  • TIM6_PRESCALER_128 : stm8s_tim6.h
  • TIM6_PRESCALER_16 : stm8s_tim6.h
  • TIM6_PRESCALER_2 : stm8s_tim6.h
  • TIM6_PRESCALER_32 : stm8s_tim6.h
  • TIM6_PRESCALER_4 : stm8s_tim6.h
  • TIM6_PRESCALER_64 : stm8s_tim6.h
  • TIM6_PRESCALER_8 : stm8s_tim6.h
  • TIM6_Prescaler_TypeDef : stm8s_tim6.h
  • TIM6_PrescalerConfig() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_PSCR_PSC : stm8s.h
  • TIM6_PSCR_RESET_VALUE : stm8s.h
  • TIM6_PSCRELOADMODE_IMMEDIATE : stm8s_tim6.h
  • TIM6_PSCReloadMode_TypeDef : stm8s_tim6.h
  • TIM6_PSCRELOADMODE_UPDATE : stm8s_tim6.h
  • TIM6_SelectInputTrigger() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_SelectMasterSlaveMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectOnePulseMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectOutputTrigger() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectSlaveMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SetAutoreload() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SetCounter() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_SLAVEMODE_DISABLE : stm8s_tim6.h
  • TIM6_SLAVEMODE_EXTERNAL1 : stm8s_tim6.h
  • TIM6_SLAVEMODE_GATED : stm8s_tim6.h
  • TIM6_SLAVEMODE_RESET : stm8s_tim6.h
  • TIM6_SLAVEMODE_TRIGGER : stm8s_tim6.h
  • TIM6_SlaveMode_TypeDef : stm8s_tim6.h
  • TIM6_SMCR_MSM : stm8s.h
  • TIM6_SMCR_RESET_VALUE : stm8s.h
  • TIM6_SMCR_SMS : stm8s.h
  • TIM6_SMCR_TS : stm8s.h
  • TIM6_SR1_RESET_VALUE : stm8s.h
  • TIM6_SR1_TIF : stm8s.h
  • TIM6_SR1_UIF : stm8s.h
  • TIM6_TimeBaseInit() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_TRGOSOURCE_ENABLE : stm8s_tim6.h
  • TIM6_TRGOSOURCE_RESET : stm8s_tim6.h
  • TIM6_TRGOSource_TypeDef : stm8s_tim6.h
  • TIM6_TRGOSOURCE_UPDATE : stm8s_tim6.h
  • TIM6_TS_TIM1 : stm8s_tim6.h
  • TIM6_TS_TIM5 : stm8s_tim6.h
  • TIM6_TS_TypeDef : stm8s_tim6.h
  • TIM6_TypeDef : stm8s.h
  • TIM6_UpdateDisableConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_UpdateRequestConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_UPDATESOURCE_GLOBAL : stm8s_tim6.h
  • TIM6_UPDATESOURCE_REGULAR : stm8s_tim6.h
  • TIM6_UpdateSource_TypeDef : stm8s_tim6.h
  • TINY : stm8s.h
  • trap : stm8s.h
  • TRUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • _
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  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • u16 : stm8s.h
  • U16_MAX : stm8s.h
  • u32 : stm8s.h
  • U32_MAX : stm8s.h
  • u8 : stm8s.h
  • U8_MAX : stm8s.h
  • UART1_ADDRESS_MAX : stm8s_uart1.h
  • UART1_BaseAddress : stm8s.h
  • UART1_BRR1_DIVM : stm8s.h
  • UART1_BRR1_RESET_VALUE : stm8s.h
  • UART1_BRR2_DIVF : stm8s.h
  • UART1_BRR2_DIVM : stm8s.h
  • UART1_BRR2_RESET_VALUE : stm8s.h
  • UART1_ClearFlag() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ClearITPendingBit() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_Cmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_CR1_M : stm8s.h
  • UART1_CR1_PCEN : stm8s.h
  • UART1_CR1_PIEN : stm8s.h
  • UART1_CR1_PS : stm8s.h
  • UART1_CR1_R8 : stm8s.h
  • UART1_CR1_RESET_VALUE : stm8s.h
  • UART1_CR1_T8 : stm8s.h
  • UART1_CR1_UARTD : stm8s.h
  • UART1_CR1_WAKE : stm8s.h
  • UART1_CR2_ILIEN : stm8s.h
  • UART1_CR2_REN : stm8s.h
  • UART1_CR2_RESET_VALUE : stm8s.h
  • UART1_CR2_RIEN : stm8s.h
  • UART1_CR2_RWU : stm8s.h
  • UART1_CR2_SBK : stm8s.h
  • UART1_CR2_TCIEN : stm8s.h
  • UART1_CR2_TEN : stm8s.h
  • UART1_CR2_TIEN : stm8s.h
  • UART1_CR3_CKEN : stm8s.h
  • UART1_CR3_CPHA : stm8s.h
  • UART1_CR3_CPOL : stm8s.h
  • UART1_CR3_LBCL : stm8s.h
  • UART1_CR3_LINEN : stm8s.h
  • UART1_CR3_RESET_VALUE : stm8s.h
  • UART1_CR3_STOP : stm8s.h
  • UART1_CR4_ADD : stm8s.h
  • UART1_CR4_LBDF : stm8s.h
  • UART1_CR4_LBDIEN : stm8s.h
  • UART1_CR4_LBDL : stm8s.h
  • UART1_CR4_RESET_VALUE : stm8s.h
  • UART1_CR5_HDSEL : stm8s.h
  • UART1_CR5_IREN : stm8s.h
  • UART1_CR5_IRLP : stm8s.h
  • UART1_CR5_NACK : stm8s.h
  • UART1_CR5_RESET_VALUE : stm8s.h
  • UART1_CR5_SCEN : stm8s.h
  • UART1_DeInit() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_FLAG_FE : stm8s_uart1.h
  • UART1_FLAG_IDLE : stm8s_uart1.h
  • UART1_FLAG_LBDF : stm8s_uart1.h
  • UART1_FLAG_NF : stm8s_uart1.h
  • UART1_FLAG_OR : stm8s_uart1.h
  • UART1_FLAG_PE : stm8s_uart1.h
  • UART1_FLAG_RXNE : stm8s_uart1.h
  • UART1_FLAG_SBK : stm8s_uart1.h
  • UART1_FLAG_TC : stm8s_uart1.h
  • UART1_FLAG_TXE : stm8s_uart1.h
  • UART1_Flag_TypeDef : stm8s_uart1.h
  • UART1_GetFlagStatus() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_GetITStatus() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_GTR_RESET_VALUE : stm8s.h
  • UART1_HalfDuplexCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_Init() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_IrDACmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_IrDAConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_IRDAMODE_LOWPOWER : stm8s_uart1.h
  • UART1_IRDAMODE_NORMAL : stm8s_uart1.h
  • UART1_IrDAMode_TypeDef : stm8s_uart1.h
  • UART1_IT_IDLE : stm8s_uart1.h
  • UART1_IT_LBDF : stm8s_uart1.h
  • UART1_IT_OR : stm8s_uart1.h
  • UART1_IT_PE : stm8s_uart1.h
  • UART1_IT_RXNE : stm8s_uart1.h
  • UART1_IT_RXNE_OR : stm8s_uart1.h
  • UART1_IT_TC : stm8s_uart1.h
  • UART1_IT_TXE : stm8s_uart1.h
  • UART1_IT_TypeDef : stm8s_uart1.h
  • UART1_ITConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_LINBreakDetectionConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart1.h
  • UART1_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart1.h
  • UART1_LINBreakDetectionLength_TypeDef : stm8s_uart1.h
  • UART1_LINCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_MODE_RX_DISABLE : stm8s_uart1.h
  • UART1_MODE_RX_ENABLE : stm8s_uart1.h
  • UART1_MODE_TX_DISABLE : stm8s_uart1.h
  • UART1_MODE_TX_ENABLE : stm8s_uart1.h
  • UART1_MODE_TXRX_ENABLE : stm8s_uart1.h
  • UART1_Mode_TypeDef : stm8s_uart1.h
  • UART1_PARITY_EVEN : stm8s_uart1.h
  • UART1_PARITY_NO : stm8s_uart1.h
  • UART1_PARITY_ODD : stm8s_uart1.h
  • UART1_Parity_TypeDef : stm8s_uart1.h
  • UART1_PSCR_RESET_VALUE : stm8s.h
  • UART1_ReceiveData8() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ReceiveData9() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ReceiverWakeUpCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SendBreak() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SendData8() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SendData9() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetAddress() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetGuardTime() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetPrescaler() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SmartCardCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SmartCardNACKCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SR_FE : stm8s.h
  • UART1_SR_IDLE : stm8s.h
  • UART1_SR_NF : stm8s.h
  • UART1_SR_OR : stm8s.h
  • UART1_SR_PE : stm8s.h
  • UART1_SR_RESET_VALUE : stm8s.h
  • UART1_SR_RXNE : stm8s.h
  • UART1_SR_TC : stm8s.h
  • UART1_SR_TXE : stm8s.h
  • UART1_STOPBITS_0_5 : stm8s_uart1.h
  • UART1_STOPBITS_1 : stm8s_uart1.h
  • UART1_STOPBITS_1_5 : stm8s_uart1.h
  • UART1_STOPBITS_2 : stm8s_uart1.h
  • UART1_StopBits_TypeDef : stm8s_uart1.h
  • UART1_SYNCMODE_CLOCK_DISABLE : stm8s_uart1.h
  • UART1_SYNCMODE_CLOCK_ENABLE : stm8s_uart1.h
  • UART1_SYNCMODE_CPHA_BEGINING : stm8s_uart1.h
  • UART1_SYNCMODE_CPHA_MIDDLE : stm8s_uart1.h
  • UART1_SYNCMODE_CPOL_HIGH : stm8s_uart1.h
  • UART1_SYNCMODE_CPOL_LOW : stm8s_uart1.h
  • UART1_SYNCMODE_LASTBIT_DISABLE : stm8s_uart1.h
  • UART1_SYNCMODE_LASTBIT_ENABLE : stm8s_uart1.h
  • UART1_SyncMode_TypeDef : stm8s_uart1.h
  • UART1_TypeDef : stm8s.h
  • UART1_WAKEUP_ADDRESSMARK : stm8s_uart1.h
  • UART1_WAKEUP_IDLELINE : stm8s_uart1.h
  • UART1_WakeUp_TypeDef : stm8s_uart1.h
  • UART1_WakeUpConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_WORDLENGTH_8D : stm8s_uart1.h
  • UART1_WORDLENGTH_9D : stm8s_uart1.h
  • UART1_WordLength_TypeDef : stm8s_uart1.h
  • UART2_ADDRESS_MAX : stm8s_uart2.h
  • UART2_BaseAddress : stm8s.h
  • UART2_BRR1_DIVM : stm8s.h
  • UART2_BRR1_RESET_VALUE : stm8s.h
  • UART2_BRR2_DIVF : stm8s.h
  • UART2_BRR2_DIVM : stm8s.h
  • UART2_BRR2_RESET_VALUE : stm8s.h
  • UART2_ClearFlag() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ClearITPendingBit() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_Cmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_CR1_M : stm8s.h
  • UART2_CR1_PCEN : stm8s.h
  • UART2_CR1_PIEN : stm8s.h
  • UART2_CR1_PS : stm8s.h
  • UART2_CR1_R8 : stm8s.h
  • UART2_CR1_RESET_VALUE : stm8s.h
  • UART2_CR1_T8 : stm8s.h
  • UART2_CR1_UARTD : stm8s.h
  • UART2_CR1_WAKE : stm8s.h
  • UART2_CR2_ILIEN : stm8s.h
  • UART2_CR2_REN : stm8s.h
  • UART2_CR2_RESET_VALUE : stm8s.h
  • UART2_CR2_RIEN : stm8s.h
  • UART2_CR2_RWU : stm8s.h
  • UART2_CR2_SBK : stm8s.h
  • UART2_CR2_TCIEN : stm8s.h
  • UART2_CR2_TEN : stm8s.h
  • UART2_CR2_TIEN : stm8s.h
  • UART2_CR3_CKEN : stm8s.h
  • UART2_CR3_CPHA : stm8s.h
  • UART2_CR3_CPOL : stm8s.h
  • UART2_CR3_LBCL : stm8s.h
  • UART2_CR3_LINEN : stm8s.h
  • UART2_CR3_RESET_VALUE : stm8s.h
  • UART2_CR3_STOP : stm8s.h
  • UART2_CR4_ADD : stm8s.h
  • UART2_CR4_LBDF : stm8s.h
  • UART2_CR4_LBDIEN : stm8s.h
  • UART2_CR4_LBDL : stm8s.h
  • UART2_CR4_RESET_VALUE : stm8s.h
  • UART2_CR5_HDSEL : stm8s.h
  • UART2_CR5_IREN : stm8s.h
  • UART2_CR5_IRLP : stm8s.h
  • UART2_CR5_NACK : stm8s.h
  • UART2_CR5_RESET_VALUE : stm8s.h
  • UART2_CR5_SCEN : stm8s.h
  • UART2_CR6_LASE : stm8s.h
  • UART2_CR6_LDUM : stm8s.h
  • UART2_CR6_LHDF : stm8s.h
  • UART2_CR6_LHDIEN : stm8s.h
  • UART2_CR6_LSF : stm8s.h
  • UART2_CR6_LSLV : stm8s.h
  • UART2_CR6_RESET_VALUE : stm8s.h
  • UART2_DeInit() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_FLAG_FE : stm8s_uart2.h
  • UART2_FLAG_IDLE : stm8s_uart2.h
  • UART2_FLAG_LBDF : stm8s_uart2.h
  • UART2_FLAG_LHDF : stm8s_uart2.h
  • UART2_FLAG_LSF : stm8s_uart2.h
  • UART2_FLAG_NF : stm8s_uart2.h
  • UART2_FLAG_OR_LHE : stm8s_uart2.h
  • UART2_FLAG_PE : stm8s_uart2.h
  • UART2_FLAG_RXNE : stm8s_uart2.h
  • UART2_FLAG_SBK : stm8s_uart2.h
  • UART2_FLAG_TC : stm8s_uart2.h
  • UART2_FLAG_TXE : stm8s_uart2.h
  • UART2_Flag_TypeDef : stm8s_uart2.h
  • UART2_GetFlagStatus() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_GetITStatus() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_GTR_RESET_VALUE : stm8s.h
  • UART2_HalfDuplexCmd() : stm8s_uart2.h
  • UART2_Init() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_IrDACmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_IrDAConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_IRDAMODE_LOWPOWER : stm8s_uart2.h
  • UART2_IRDAMODE_NORMAL : stm8s_uart2.h
  • UART2_IrDAMode_TypeDef : stm8s_uart2.h
  • UART2_IT_IDLE : stm8s_uart2.h
  • UART2_IT_LBDF : stm8s_uart2.h
  • UART2_IT_LHDF : stm8s_uart2.h
  • UART2_IT_OR : stm8s_uart2.h
  • UART2_IT_PE : stm8s_uart2.h
  • UART2_IT_RXNE : stm8s_uart2.h
  • UART2_IT_RXNE_OR : stm8s_uart2.h
  • UART2_IT_TC : stm8s_uart2.h
  • UART2_IT_TXE : stm8s_uart2.h
  • UART2_IT_TypeDef : stm8s_uart2.h
  • UART2_ITConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LIN_AUTOSYNC_DISABLE : stm8s_uart2.h
  • UART2_LIN_AUTOSYNC_ENABLE : stm8s_uart2.h
  • UART2_LIN_DIVUP_LBRR1 : stm8s_uart2.h
  • UART2_LIN_DIVUP_NEXTRXNE : stm8s_uart2.h
  • UART2_LIN_MODE_MASTER : stm8s_uart2.h
  • UART2_LIN_MODE_SLAVE : stm8s_uart2.h
  • UART2_LinAutosync_TypeDef : stm8s_uart2.h
  • UART2_LINBreakDetectionConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart2.h
  • UART2_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart2.h
  • UART2_LINBreakDetectionLength_TypeDef : stm8s_uart2.h
  • UART2_LINCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LINConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LinDivUp_TypeDef : stm8s_uart2.h
  • UART2_LinMode_TypeDef : stm8s_uart2.h
  • UART2_MODE_RX_DISABLE : stm8s_uart2.h
  • UART2_MODE_RX_ENABLE : stm8s_uart2.h
  • UART2_MODE_TX_DISABLE : stm8s_uart2.h
  • UART2_MODE_TX_ENABLE : stm8s_uart2.h
  • UART2_MODE_TXRX_ENABLE : stm8s_uart2.h
  • UART2_Mode_TypeDef : stm8s_uart2.h
  • UART2_PARITY_EVEN : stm8s_uart2.h
  • UART2_PARITY_NO : stm8s_uart2.h
  • UART2_PARITY_ODD : stm8s_uart2.h
  • UART2_Parity_TypeDef : stm8s_uart2.h
  • UART2_PSCR_RESET_VALUE : stm8s.h
  • UART2_ReceiveData8() : stm8s_uart2.c , stm8s_uart2.h
  • UART2_ReceiveData9() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ReceiverWakeUpCmd() : stm8s_uart2.c , stm8s_uart2.h
  • UART2_SendBreak() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SendData8() : stm8s_uart2.c , stm8s_uart2.h
  • UART2_SendData9() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetAddress() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetGuardTime() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetPrescaler() : stm8s_uart2.c , stm8s_uart2.h
  • UART2_SmartCardCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SmartCardNACKCmd() : stm8s_uart2.c , stm8s_uart2.h
  • UART2_SR_FE : stm8s.h
  • UART2_SR_IDLE : stm8s.h
  • UART2_SR_NF : stm8s.h
  • UART2_SR_OR : stm8s.h
  • UART2_SR_PE : stm8s.h
  • UART2_SR_RESET_VALUE : stm8s.h
  • UART2_SR_RXNE : stm8s.h
  • UART2_SR_TC : stm8s.h
  • UART2_SR_TXE : stm8s.h
  • UART2_STOPBITS_0_5 : stm8s_uart2.h
  • UART2_STOPBITS_1 : stm8s_uart2.h
  • UART2_STOPBITS_1_5 : stm8s_uart2.h
  • UART2_STOPBITS_2 : stm8s_uart2.h
  • UART2_StopBits_TypeDef : stm8s_uart2.h
  • UART2_SYNCMODE_CLOCK_DISABLE : stm8s_uart2.h
  • UART2_SYNCMODE_CLOCK_ENABLE : stm8s_uart2.h
  • UART2_SYNCMODE_CPHA_BEGINING : stm8s_uart2.h
  • UART2_SYNCMODE_CPHA_MIDDLE : stm8s_uart2.h
  • UART2_SYNCMODE_CPOL_HIGH : stm8s_uart2.h
  • UART2_SYNCMODE_CPOL_LOW : stm8s_uart2.h
  • UART2_SYNCMODE_LASTBIT_DISABLE : stm8s_uart2.h
  • UART2_SYNCMODE_LASTBIT_ENABLE : stm8s_uart2.h
  • UART2_SyncMode_TypeDef : stm8s_uart2.h
  • UART2_TypeDef : stm8s.h
  • UART2_WAKEUP_ADDRESSMARK : stm8s_uart2.h
  • UART2_WAKEUP_IDLELINE : stm8s_uart2.h
  • UART2_WakeUp_TypeDef : stm8s_uart2.h
  • UART2_WakeUpConfig() : stm8s_uart2.c , stm8s_uart2.h
  • UART2_WORDLENGTH_8D : stm8s_uart2.h
  • UART2_WORDLENGTH_9D : stm8s_uart2.h
  • UART2_WordLength_TypeDef : stm8s_uart2.h
  • UART3_ADDRESS_MAX : stm8s_uart3.h
  • UART3_BaseAddress : stm8s.h
  • UART3_BRR1_DIVM : stm8s.h
  • UART3_BRR1_RESET_VALUE : stm8s.h
  • UART3_BRR2_DIVF : stm8s.h
  • UART3_BRR2_DIVM : stm8s.h
  • UART3_BRR2_RESET_VALUE : stm8s.h
  • UART3_ClearFlag() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_ClearITPendingBit() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_Cmd() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_CR1_M : stm8s.h
  • UART3_CR1_PCEN : stm8s.h
  • UART3_CR1_PIEN : stm8s.h
  • UART3_CR1_PS : stm8s.h
  • UART3_CR1_R8 : stm8s.h
  • UART3_CR1_RESET_VALUE : stm8s.h
  • UART3_CR1_T8 : stm8s.h
  • UART3_CR1_UARTD : stm8s.h
  • UART3_CR1_WAKE : stm8s.h
  • UART3_CR2_ILIEN : stm8s.h
  • UART3_CR2_REN : stm8s.h
  • UART3_CR2_RESET_VALUE : stm8s.h
  • UART3_CR2_RIEN : stm8s.h
  • UART3_CR2_RWU : stm8s.h
  • UART3_CR2_SBK : stm8s.h
  • UART3_CR2_TCIEN : stm8s.h
  • UART3_CR2_TEN : stm8s.h
  • UART3_CR2_TIEN : stm8s.h
  • UART3_CR3_LINEN : stm8s.h
  • UART3_CR3_RESET_VALUE : stm8s.h
  • UART3_CR3_STOP : stm8s.h
  • UART3_CR4_ADD : stm8s.h
  • UART3_CR4_LBDF : stm8s.h
  • UART3_CR4_LBDIEN : stm8s.h
  • UART3_CR4_LBDL : stm8s.h
  • UART3_CR4_RESET_VALUE : stm8s.h
  • UART3_CR6_LASE : stm8s.h
  • UART3_CR6_LDUM : stm8s.h
  • UART3_CR6_LHDF : stm8s.h
  • UART3_CR6_LHDIEN : stm8s.h
  • UART3_CR6_LSF : stm8s.h
  • UART3_CR6_LSLV : stm8s.h
  • UART3_CR6_RESET_VALUE : stm8s.h
  • UART3_DeInit() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_FLAG_FE : stm8s_uart3.h
  • UART3_FLAG_IDLE : stm8s_uart3.h
  • UART3_FLAG_LBDF : stm8s_uart3.h
  • UART3_FLAG_LHDF : stm8s_uart3.h
  • UART3_FLAG_LSF : stm8s_uart3.h
  • UART3_FLAG_NF : stm8s_uart3.h
  • UART3_FLAG_OR_LHE : stm8s_uart3.h
  • UART3_FLAG_PE : stm8s_uart3.h
  • UART3_FLAG_RXNE : stm8s_uart3.h
  • UART3_FLAG_SBK : stm8s_uart3.h
  • UART3_FLAG_TC : stm8s_uart3.h
  • UART3_FLAG_TXE : stm8s_uart3.h
  • UART3_Flag_TypeDef : stm8s_uart3.h
  • UART3_GetFlagStatus() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_GetITStatus() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_Init() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_IT_IDLE : stm8s_uart3.h
  • UART3_IT_LBDF : stm8s_uart3.h
  • UART3_IT_LHDF : stm8s_uart3.h
  • UART3_IT_OR : stm8s_uart3.h
  • UART3_IT_PE : stm8s_uart3.h
  • UART3_IT_RXNE : stm8s_uart3.h
  • UART3_IT_RXNE_OR : stm8s_uart3.h
  • UART3_IT_TC : stm8s_uart3.h
  • UART3_IT_TXE : stm8s_uart3.h
  • UART3_IT_TypeDef : stm8s_uart3.h
  • UART3_ITConfig() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_LIN_AUTOSYNC_DISABLE : stm8s_uart3.h
  • UART3_LIN_AUTOSYNC_ENABLE : stm8s_uart3.h
  • UART3_LIN_DIVUP_LBRR1 : stm8s_uart3.h
  • UART3_LIN_DIVUP_NEXTRXNE : stm8s_uart3.h
  • UART3_LIN_MODE_MASTER : stm8s_uart3.h
  • UART3_LIN_MODE_SLAVE : stm8s_uart3.h
  • UART3_LinAutosync_TypeDef : stm8s_uart3.h
  • UART3_LINBreakDetectionConfig() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart3.h
  • UART3_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart3.h
  • UART3_LINBreakDetectionLength_TypeDef : stm8s_uart3.h
  • UART3_LINCmd() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_LINConfig() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_LinDivUp_TypeDef : stm8s_uart3.h
  • UART3_LinMode_TypeDef : stm8s_uart3.h
  • UART3_MODE_RX_DISABLE : stm8s_uart3.h
  • UART3_MODE_RX_ENABLE : stm8s_uart3.h
  • UART3_MODE_TX_DISABLE : stm8s_uart3.h
  • UART3_MODE_TX_ENABLE : stm8s_uart3.h
  • UART3_MODE_TXRX_ENABLE : stm8s_uart3.h
  • UART3_Mode_TypeDef : stm8s_uart3.h
  • UART3_PARITY_EVEN : stm8s_uart3.h
  • UART3_PARITY_NO : stm8s_uart3.h
  • UART3_PARITY_ODD : stm8s_uart3.h
  • UART3_Parity_TypeDef : stm8s_uart3.h
  • UART3_ReceiveData8() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_ReceiveData9() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_ReceiverWakeUpCmd() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_SendBreak() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_SendData8() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SendData9() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_SetAddress() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SR_FE : stm8s.h
  • UART3_SR_IDLE : stm8s.h
  • UART3_SR_NF : stm8s.h
  • UART3_SR_OR : stm8s.h
  • UART3_SR_PE : stm8s.h
  • UART3_SR_RESET_VALUE : stm8s.h
  • UART3_SR_RXNE : stm8s.h
  • UART3_SR_TC : stm8s.h
  • UART3_SR_TXE : stm8s.h
  • UART3_STOPBITS_1 : stm8s_uart3.h
  • UART3_STOPBITS_2 : stm8s_uart3.h
  • UART3_StopBits_TypeDef : stm8s_uart3.h
  • UART3_TypeDef : stm8s.h
  • UART3_WAKEUP_ADDRESSMARK : stm8s_uart3.h
  • UART3_WAKEUP_IDLELINE : stm8s_uart3.h
  • UART3_WakeUp_TypeDef : stm8s_uart3.h
  • UART3_WakeUpConfig() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_WORDLENGTH_8D : stm8s_uart3.h
  • UART3_WORDLENGTH_9D : stm8s_uart3.h
  • UART3_WordLength_TypeDef : stm8s_uart3.h
  • uint16_t : stm8s.h
  • uint32_t : stm8s.h
  • uint8_t : stm8s.h
  • USE_STDPERIPH_DRIVER : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • ValBit : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • wfi : stm8s.h
  • WWDG : stm8s.h
  • WWDG_BaseAddress : stm8s.h
  • WWDG_CR_RESET_VALUE : stm8s.h
  • WWDG_CR_T : stm8s.h
  • WWDG_CR_T6 : stm8s.h
  • WWDG_CR_WDGA : stm8s.h
  • WWDG_GetCounter() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_Init() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_SetCounter() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_SetWindowValue() : stm8s_wwdg.c , stm8s_wwdg.h
  • WWDG_SWReset() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_TypeDef : stm8s.h
  • WWDG_WR_MSB : stm8s.h
  • WWDG_WR_RESET_VALUE : stm8s.h
  • WWDG_WR_W : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- _ -

  • __I : stm8s.h
  • __IO : stm8s.h
  • __O : stm8s.h
  • __STM8S_STDPERIPH_VERSION : stm8s.h
  • __STM8S_STDPERIPH_VERSION_MAIN : stm8s.h
  • __STM8S_STDPERIPH_VERSION_RC : stm8s.h
  • __STM8S_STDPERIPH_VERSION_SUB1 : stm8s.h
  • __STM8S_STDPERIPH_VERSION_SUB2 : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- l -

  • LSI_FREQUENCY_MAX : stm8s_awu.h , stm8s_beep.h
  • LSI_FREQUENCY_MIN : stm8s_beep.h , stm8s_awu.h
  • LSI_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- m -

  • MskBit : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- n -

  • NEAR : stm8s.h
  • nop : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- o -

  • OPERATION_TIMEOUT : stm8s_flash.c
  • OPT : stm8s.h
  • OPT_BaseAddress : stm8s.h
  • OPTION_BYTE_END_PHYSICAL_ADDRESS : stm8s_flash.h
  • OPTION_BYTE_START_PHYSICAL_ADDRESS : stm8s_flash.h


STM8S/A Standard Peripherals Drivers: Globals

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- a -

  • ADC1_BaseAddress : stm8s.h
  • ADC2_BaseAddress : stm8s.h
  • AffBit : stm8s.h
  • AREA : stm8s.h
  • AWU : stm8s.h
  • AWU_APR_APR : stm8s.h
  • AWU_APR_RESET_VALUE : stm8s.h
  • AWU_BaseAddress : stm8s.h
  • AWU_CSR_AWUEN : stm8s.h
  • AWU_CSR_AWUF : stm8s.h
  • AWU_CSR_MSR : stm8s.h
  • AWU_CSR_RESET_VALUE : stm8s.h
  • AWU_TBR_AWUTB : stm8s.h
  • AWU_TBR_RESET_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- b -

  • BEEP : stm8s.h
  • BEEP_BaseAddress : stm8s.h
  • BEEP_CALIBRATION_DEFAULT : stm8s_beep.h
  • BEEP_CSR_BEEPDIV : stm8s.h
  • BEEP_CSR_BEEPEN : stm8s.h
  • BEEP_CSR_BEEPSEL : stm8s.h
  • BEEP_CSR_RESET_VALUE : stm8s.h
  • BIT_MASK : stm8s_wwdg.c
  • BitClr : stm8s.h
  • BitSet : stm8s.h
  • BitVal : stm8s.h
  • BYTE_0 : stm8s.h
  • BYTE_1 : stm8s.h
  • BYTE_2 : stm8s.h
  • BYTE_3 : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- c -

  • CAN_ACKNOWLEDGE_TIMEOUT : stm8s_can.c
  • CAN_BaseAddress : stm8s.h
  • CAN_BTR1_RESET_VALUE : stm8s.h
  • CAN_BTR2_RESET_VALUE : stm8s.h
  • CAN_DGR_LBKM : stm8s.h
  • CAN_DGR_RESET_VALUE : stm8s.h
  • CAN_DGR_RX : stm8s.h
  • CAN_DGR_SAMP : stm8s.h
  • CAN_DGR_SLIM : stm8s.h
  • CAN_DGR_TXM2E : stm8s.h
  • CAN_DLC_MAX : stm8s_can.h
  • CAN_EIER_BOFIE : stm8s.h
  • CAN_EIER_EPVIE : stm8s.h
  • CAN_EIER_ERRIE : stm8s.h
  • CAN_EIER_EWGIE : stm8s.h
  • CAN_EIER_LECIE : stm8s.h
  • CAN_EIER_RESET_VALUE : stm8s.h
  • CAN_ESR_BOFF : stm8s.h
  • CAN_ESR_EPVF : stm8s.h
  • CAN_ESR_EWGF : stm8s.h
  • CAN_ESR_LEC : stm8s.h
  • CAN_ESR_LEC0 : stm8s.h
  • CAN_ESR_LEC1 : stm8s.h
  • CAN_ESR_LEC2 : stm8s.h
  • CAN_ESR_RESET_VALUE : stm8s.h
  • CAN_EXTID_SIZE : stm8s_can.h
  • CAN_FCR1_FACT0 : stm8s.h
  • CAN_FCR1_FACT1 : stm8s.h
  • CAN_FCR1_FSC00 : stm8s.h
  • CAN_FCR1_FSC01 : stm8s.h
  • CAN_FCR1_FSC10 : stm8s.h
  • CAN_FCR1_FSC11 : stm8s.h
  • CAN_FCR2_FACT2 : stm8s.h
  • CAN_FCR2_FACT3 : stm8s.h
  • CAN_FCR2_FSC20 : stm8s.h
  • CAN_FCR2_FSC21 : stm8s.h
  • CAN_FCR2_FSC30 : stm8s.h
  • CAN_FCR2_FSC31 : stm8s.h
  • CAN_FCR3_FACT4 : stm8s.h
  • CAN_FCR3_FACT5 : stm8s.h
  • CAN_FCR3_FSC40 : stm8s.h
  • CAN_FCR3_FSC41 : stm8s.h
  • CAN_FCR3_FSC50 : stm8s.h
  • CAN_FCR3_FSC51 : stm8s.h
  • CAN_FCR_RESET_VALUE : stm8s.h
  • CAN_FMR1_FMH0 : stm8s.h
  • CAN_FMR1_FMH1 : stm8s.h
  • CAN_FMR1_FMH2 : stm8s.h
  • CAN_FMR1_FMH3 : stm8s.h
  • CAN_FMR1_FML0 : stm8s.h
  • CAN_FMR1_FML1 : stm8s.h
  • CAN_FMR1_FML2 : stm8s.h
  • CAN_FMR1_FML3 : stm8s.h
  • CAN_FMR1_RESET_VALUE : stm8s.h
  • CAN_FMR2_FMH4 : stm8s.h
  • CAN_FMR2_FMH5 : stm8s.h
  • CAN_FMR2_FML4 : stm8s.h
  • CAN_FMR2_FML5 : stm8s.h
  • CAN_FMR2_RESET_VALUE : stm8s.h
  • CAN_IDLIST_IDMASK_MASK : stm8s_can.c
  • CAN_IDMASK_IDLIST_MASK : stm8s_can.c
  • CAN_IER_FFIE : stm8s.h
  • CAN_IER_FMPIE : stm8s.h
  • CAN_IER_FOVIE : stm8s.h
  • CAN_IER_RESET_VALUE : stm8s.h
  • CAN_IER_TMEIE : stm8s.h
  • CAN_IER_WKUIE : stm8s.h
  • CAN_IT_CONFIG_MASK : stm8s_can.h
  • CAN_MCR_ABOM : stm8s.h
  • CAN_MCR_AWUM : stm8s.h
  • CAN_MCR_INRQ : stm8s.h
  • CAN_MCR_NART : stm8s.h
  • CAN_MCR_RESET_VALUE : stm8s.h
  • CAN_MCR_RFLM : stm8s.h
  • CAN_MCR_SLEEP : stm8s.h
  • CAN_MCR_TTCM : stm8s.h
  • CAN_MCR_TXFP : stm8s.h
  • CAN_MCSR_ABRQ : stm8s.h
  • CAN_MCSR_ALST : stm8s.h
  • CAN_MCSR_RESET_VALUE : stm8s.h
  • CAN_MCSR_RQCP : stm8s.h
  • CAN_MCSR_TERR : stm8s.h
  • CAN_MCSR_TXOK : stm8s.h
  • CAN_MCSR_TXRQ : stm8s.h
  • CAN_MDLC_RESET_VALUE : stm8s.h
  • CAN_MDLCR_DLC : stm8s.h
  • CAN_MDLCR_TGT : stm8s.h
  • CAN_MFMI_RESET_VALUE : stm8s.h
  • CAN_MIDR1_IDE : stm8s.h
  • CAN_MIDR1_RTR : stm8s.h
  • CAN_MODE_MASK : stm8s_can.c
  • CAN_MSR_ERRI : stm8s.h
  • CAN_MSR_INAK : stm8s.h
  • CAN_MSR_RESET_VALUE : stm8s.h
  • CAN_MSR_RX : stm8s.h
  • CAN_MSR_SLAK : stm8s.h
  • CAN_MSR_TX : stm8s.h
  • CAN_MSR_WKUI : stm8s.h
  • CAN_PSR_PS0 : stm8s.h
  • CAN_PSR_PS1 : stm8s.h
  • CAN_PSR_PS2 : stm8s.h
  • CAN_PSR_RESET_VALUE : stm8s.h
  • CAN_RECR_REC0 : stm8s.h
  • CAN_RECR_REC1 : stm8s.h
  • CAN_RECR_REC2 : stm8s.h
  • CAN_RECR_REC3 : stm8s.h
  • CAN_RECR_REC4 : stm8s.h
  • CAN_RECR_REC5 : stm8s.h
  • CAN_RECR_REC6 : stm8s.h
  • CAN_RECR_REC7 : stm8s.h
  • CAN_RECR_RESET_VALUE : stm8s.h
  • CAN_RFR_FMP01 : stm8s.h
  • CAN_RFR_FOVR : stm8s.h
  • CAN_RFR_FULL : stm8s.h
  • CAN_RFR_RESET_VALUE : stm8s.h
  • CAN_RFR_RFOM : stm8s.h
  • CAN_STDID_SIZE : stm8s_can.h
  • CAN_TECR_RESET_VALUE : stm8s.h
  • CAN_TECR_TEC0 : stm8s.h
  • CAN_TECR_TEC1 : stm8s.h
  • CAN_TECR_TEC2 : stm8s.h
  • CAN_TECR_TEC3 : stm8s.h
  • CAN_TECR_TEC4 : stm8s.h
  • CAN_TECR_TEC5 : stm8s.h
  • CAN_TECR_TEC6 : stm8s.h
  • CAN_TECR_TEC7 : stm8s.h
  • CAN_TPR_CODE0 : stm8s.h
  • CAN_TPR_LOW0 : stm8s.h
  • CAN_TPR_LOW1 : stm8s.h
  • CAN_TPR_LOW2 : stm8s.h
  • CAN_TPR_RESET_VALUE : stm8s.h
  • CAN_TPR_TME0 : stm8s.h
  • CAN_TPR_TME1 : stm8s.h
  • CAN_TPR_TME2 : stm8s.h
  • CAN_TSR_RESET_VALUE : stm8s.h
  • CAN_TSR_RQCP0 : stm8s.h
  • CAN_TSR_RQCP012 : stm8s.h
  • CAN_TSR_RQCP1 : stm8s.h
  • CAN_TSR_RQCP2 : stm8s.h
  • CAN_TSR_TXOK0 : stm8s.h
  • CAN_TSR_TXOK1 : stm8s.h
  • CAN_TSR_TXOK2 : stm8s.h
  • CCMR_TIxDirect_Set : stm8s.h
  • CFG : stm8s.h
  • CFG_BaseAddress : stm8s.h
  • CFG_GCR_AL : stm8s.h
  • CFG_GCR_RESET_VALUE : stm8s.h
  • CFG_GCR_SWD : stm8s.h
  • ChgBit : stm8s.h
  • CLK : stm8s.h
  • CLK_BaseAddress : stm8s.h
  • CLK_CCOR_CCOBSY : stm8s.h
  • CLK_CCOR_CCOEN : stm8s.h
  • CLK_CCOR_CCORDY : stm8s.h
  • CLK_CCOR_CCOSEL : stm8s.h
  • CLK_CCOR_RESET_VALUE : stm8s.h
  • CLK_CKDIVR_CPUDIV : stm8s.h
  • CLK_CKDIVR_HSIDIV : stm8s.h
  • CLK_CKDIVR_RESET_VALUE : stm8s.h
  • CLK_CMSR_CKM : stm8s.h
  • CLK_CMSR_RESET_VALUE : stm8s.h
  • CLK_CSSR_AUX : stm8s.h
  • CLK_CSSR_CSSD : stm8s.h
  • CLK_CSSR_CSSDIE : stm8s.h
  • CLK_CSSR_CSSEN : stm8s.h
  • CLK_CSSR_RESET_VALUE : stm8s.h
  • CLK_ECKR_HSEEN : stm8s.h
  • CLK_ECKR_HSERDY : stm8s.h
  • CLK_ECKR_RESET_VALUE : stm8s.h
  • CLK_HSITRIMR_HSITRIM : stm8s.h
  • CLK_HSITRIMR_RESET_VALUE : stm8s.h
  • CLK_ICKR_FHWU : stm8s.h
  • CLK_ICKR_HSIEN : stm8s.h
  • CLK_ICKR_HSIRDY : stm8s.h
  • CLK_ICKR_LSIEN : stm8s.h
  • CLK_ICKR_LSIRDY : stm8s.h
  • CLK_ICKR_RESET_VALUE : stm8s.h
  • CLK_ICKR_SWUAH : stm8s.h
  • CLK_PCKENR1_I2C : stm8s.h
  • CLK_PCKENR1_RESET_VALUE : stm8s.h
  • CLK_PCKENR1_SPI : stm8s.h
  • CLK_PCKENR1_TIM1 : stm8s.h
  • CLK_PCKENR1_TIM2 : stm8s.h
  • CLK_PCKENR1_TIM3 : stm8s.h
  • CLK_PCKENR1_TIM4 : stm8s.h
  • CLK_PCKENR1_TIM5 : stm8s.h
  • CLK_PCKENR1_TIM6 : stm8s.h
  • CLK_PCKENR1_UART1 : stm8s.h
  • CLK_PCKENR1_UART2 : stm8s.h
  • CLK_PCKENR1_UART3 : stm8s.h
  • CLK_PCKENR2_ADC : stm8s.h
  • CLK_PCKENR2_AWU : stm8s.h
  • CLK_PCKENR2_CAN : stm8s.h
  • CLK_PCKENR2_RESET_VALUE : stm8s.h
  • CLK_SWCR_RESET_VALUE : stm8s.h
  • CLK_SWCR_SWBSY : stm8s.h
  • CLK_SWCR_SWEN : stm8s.h
  • CLK_SWCR_SWIEN : stm8s.h
  • CLK_SWCR_SWIF : stm8s.h
  • CLK_SWIMCCR_RESET_VALUE : stm8s.h
  • CLK_SWIMCCR_SWIMDIV : stm8s.h
  • CLK_SWR_RESET_VALUE : stm8s.h
  • CLK_SWR_SWI : stm8s.h
  • CLK_TIMEOUT : stm8s_clk.h
  • ClrBit : stm8s.h
  • CONST : stm8s.h
  • CPU_CC_I1I0 : stm8s.h
  • CPU_SOFT_INT_DISABLED : stm8s_itc.h


STM8S/A Standard Peripherals Drivers: Globals

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- d -

  • disableInterrupts : stm8s.h
  • DM : stm8s.h
  • DM_BaseAddress : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- e -

  • EEPROM : stm8s.h
  • enableInterrupts : stm8s.h
  • EXTI : stm8s.h
  • EXTI_BaseAddress : stm8s.h
  • EXTI_CR1_PAIS : stm8s.h
  • EXTI_CR1_PBIS : stm8s.h
  • EXTI_CR1_PCIS : stm8s.h
  • EXTI_CR1_PDIS : stm8s.h
  • EXTI_CR1_RESET_VALUE : stm8s.h
  • EXTI_CR2_PEIS : stm8s.h
  • EXTI_CR2_RESET_VALUE : stm8s.h
  • EXTI_CR2_TLIS : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- f -

  • FAR : stm8s.h
  • FLAG_Mask : stm8s_i2c.c
  • FLASH : stm8s.h
  • FLASH_BaseAddress : stm8s.h
  • FLASH_CLEAR_BYTE : stm8s_flash.c
  • FLASH_CR1_AHALT : stm8s.h
  • FLASH_CR1_FIX : stm8s.h
  • FLASH_CR1_HALT : stm8s.h
  • FLASH_CR1_IE : stm8s.h
  • FLASH_CR1_RESET_VALUE : stm8s.h
  • FLASH_CR2_ERASE : stm8s.h
  • FLASH_CR2_FPRG : stm8s.h
  • FLASH_CR2_OPT : stm8s.h
  • FLASH_CR2_PRG : stm8s.h
  • FLASH_CR2_RESET_VALUE : stm8s.h
  • FLASH_CR2_WPRG : stm8s.h
  • FLASH_DUKR_DUK : stm8s.h
  • FLASH_DUKR_RESET_VALUE : stm8s.h
  • FLASH_IAPSR_DUL : stm8s.h
  • FLASH_IAPSR_EOP : stm8s.h
  • FLASH_IAPSR_HVOFF : stm8s.h
  • FLASH_IAPSR_PUL : stm8s.h
  • FLASH_IAPSR_RESET_VALUE : stm8s.h
  • FLASH_IAPSR_WR_PG_DIS : stm8s.h
  • FLASH_NCR2_NERASE : stm8s.h
  • FLASH_NCR2_NFPRG : stm8s.h
  • FLASH_NCR2_NOPT : stm8s.h
  • FLASH_NCR2_NPRG : stm8s.h
  • FLASH_NCR2_NWPRG : stm8s.h
  • FLASH_NCR2_RESET_VALUE : stm8s.h
  • FLASH_OPTIONBYTE_ERROR : stm8s_flash.h
  • FLASH_PROG_START_PHYSICAL_ADDRESS : stm8s_flash.h
  • FLASH_PUKR_PUK : stm8s.h
  • FLASH_PUKR_RESET_VALUE : stm8s.h
  • FLASH_RASS_KEY1 : stm8s_flash.h
  • FLASH_RASS_KEY2 : stm8s_flash.h
  • FLASH_SET_BYTE : stm8s_flash.c


STM8S/A Standard Peripherals Drivers: Globals

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- g -

  • GPIO_CR1_RESET_VALUE : stm8s.h
  • GPIO_CR2_RESET_VALUE : stm8s.h
  • GPIO_DDR_RESET_VALUE : stm8s.h
  • GPIO_ODR_RESET_VALUE : stm8s.h
  • GPIOA : stm8s.h
  • GPIOA_BaseAddress : stm8s.h
  • GPIOB : stm8s.h
  • GPIOB_BaseAddress : stm8s.h
  • GPIOC : stm8s.h
  • GPIOC_BaseAddress : stm8s.h
  • GPIOD : stm8s.h
  • GPIOD_BaseAddress : stm8s.h
  • GPIOE : stm8s.h
  • GPIOE_BaseAddress : stm8s.h
  • GPIOF : stm8s.h
  • GPIOF_BaseAddress : stm8s.h
  • GPIOG_BaseAddress : stm8s.h
  • GPIOH_BaseAddress : stm8s.h
  • GPIOI_BaseAddress : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- h -

  • halt : stm8s.h
  • HSE_VALUE : stm8s.h
  • HSI_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
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- i -

  • I2C : stm8s.h
  • I2C_BaseAddress : stm8s.h
  • I2C_CCRH_CCR : stm8s.h
  • I2C_CCRH_DUTY : stm8s.h
  • I2C_CCRH_FS : stm8s.h
  • I2C_CCRH_RESET_VALUE : stm8s.h
  • I2C_CCRL_CCR : stm8s.h
  • I2C_CCRL_RESET_VALUE : stm8s.h
  • I2C_CR1_ENGC : stm8s.h
  • I2C_CR1_NOSTRETCH : stm8s.h
  • I2C_CR1_PE : stm8s.h
  • I2C_CR1_RESET_VALUE : stm8s.h
  • I2C_CR2_ACK : stm8s.h
  • I2C_CR2_POS : stm8s.h
  • I2C_CR2_RESET_VALUE : stm8s.h
  • I2C_CR2_START : stm8s.h
  • I2C_CR2_STOP : stm8s.h
  • I2C_CR2_SWRST : stm8s.h
  • I2C_DR_DR : stm8s.h
  • I2C_DR_RESET_VALUE : stm8s.h
  • I2C_FREQR_FREQ : stm8s.h
  • I2C_FREQR_RESET_VALUE : stm8s.h
  • I2C_ITR_ITBUFEN : stm8s.h
  • I2C_ITR_ITERREN : stm8s.h
  • I2C_ITR_ITEVTEN : stm8s.h
  • I2C_ITR_RESET_VALUE : stm8s.h
  • I2C_MAX_FAST_FREQ : stm8s_i2c.h
  • I2C_MAX_INPUT_FREQ : stm8s_i2c.h
  • I2C_MAX_STANDARD_FREQ : stm8s_i2c.h
  • I2C_OARH_ADD : stm8s.h
  • I2C_OARH_ADDCONF : stm8s.h
  • I2C_OARH_ADDMODE : stm8s.h
  • I2C_OARH_RESET_VALUE : stm8s.h
  • I2C_OARL_ADD : stm8s.h
  • I2C_OARL_ADD0 : stm8s.h
  • I2C_OARL_RESET_VALUE : stm8s.h
  • I2C_SR1_ADD10 : stm8s.h
  • I2C_SR1_ADDR : stm8s.h
  • I2C_SR1_BTF : stm8s.h
  • I2C_SR1_RESET_VALUE : stm8s.h
  • I2C_SR1_RXNE : stm8s.h
  • I2C_SR1_SB : stm8s.h
  • I2C_SR1_STOPF : stm8s.h
  • I2C_SR1_TXE : stm8s.h
  • I2C_SR2_AF : stm8s.h
  • I2C_SR2_ARLO : stm8s.h
  • I2C_SR2_BERR : stm8s.h
  • I2C_SR2_OVR : stm8s.h
  • I2C_SR2_RESET_VALUE : stm8s.h
  • I2C_SR2_WUFH : stm8s.h
  • I2C_SR3_BUSY : stm8s.h
  • I2C_SR3_GENCALL : stm8s.h
  • I2C_SR3_MSL : stm8s.h
  • I2C_SR3_RESET_VALUE : stm8s.h
  • I2C_SR3_TRA : stm8s.h
  • I2C_TRISER_RESET_VALUE : stm8s.h
  • I2C_TRISER_TRISE : stm8s.h
  • IN_RAM : stm8s.h
  • IS_ADC1_ALIGN_OK : stm8s_adc1.h
  • IS_ADC1_BUFFER_OK : stm8s_adc1.h
  • IS_ADC1_CHANNEL_OK : stm8s_adc1.h
  • IS_ADC1_CONVERSIONMODE_OK : stm8s_adc1.h
  • IS_ADC1_EXTTRIG_OK : stm8s_adc1.h
  • IS_ADC1_FLAG_OK : stm8s_adc1.h
  • IS_ADC1_IT_OK : stm8s_adc1.h
  • IS_ADC1_ITPENDINGBIT_OK : stm8s_adc1.h
  • IS_ADC1_PRESSEL_OK : stm8s_adc1.h
  • IS_ADC1_SCHMITTTRIG_OK : stm8s_adc1.h
  • IS_ADC2_ALIGN_OK : stm8s_adc2.h
  • IS_ADC2_CHANNEL_OK : stm8s_adc2.h
  • IS_ADC2_CONVERSIONMODE_OK : stm8s_adc2.h
  • IS_ADC2_EXTTRIG_OK : stm8s_adc2.h
  • IS_ADC2_PRESSEL_OK : stm8s_adc2.h
  • IS_ADC2_SCHMITTTRIG_OK : stm8s_adc2.h
  • IS_AWU_TIMEBASE_OK : stm8s_awu.h
  • IS_BEEP_FREQUENCY_OK : stm8s_beep.h
  • IS_CAN_BITSEG1_OK : stm8s_can.h
  • IS_CAN_BITSEG2_OK : stm8s_can.h
  • IS_CAN_DLC_OK : stm8s_can.h
  • IS_CAN_EXTID_OK : stm8s_can.h
  • IS_CAN_FILTER_MODE_OK : stm8s_can.h
  • IS_CAN_FILTER_NUMBER_OK : stm8s_can.h
  • IS_CAN_FILTER_SCALE_OK : stm8s_can.h
  • IS_CAN_FLAG_CLEAR_OK : stm8s_can.h
  • IS_CAN_FLAG_STATUS_OK : stm8s_can.h
  • IS_CAN_IDTYPE_OK : stm8s_can.h
  • IS_CAN_IT_CONFIG_OK : stm8s_can.h
  • IS_CAN_IT_PENDING_BIT_OK : stm8s_can.h
  • IS_CAN_IT_STATUS_OK : stm8s_can.h
  • IS_CAN_LAST_ERROR_CODE_OK : stm8s_can.h
  • IS_CAN_MASTERCTRL_OK : stm8s_can.h
  • IS_CAN_MODE_OK : stm8s_can.h
  • IS_CAN_OPERATINGMODE_OK : stm8s_can.h
  • IS_CAN_PRESCALER_OK : stm8s_can.h
  • IS_CAN_RTR_OK : stm8s_can.h
  • IS_CAN_ST7_COMPATIBILITY_OK : stm8s_can.h
  • IS_CAN_STDID_OK : stm8s_can.h
  • IS_CAN_SYNJUMPWIDTH_OK : stm8s_can.h
  • IS_CAN_TRANSMITMAILBOX_OK : stm8s_can.h
  • IS_CLK_CSSCONFIG_OK : stm8s_clk.h
  • IS_CLK_CURRENTCLOCKSTATE_OK : stm8s_clk.h
  • IS_CLK_FLAG_OK : stm8s_clk.h
  • IS_CLK_HSIPRESCALER_OK : stm8s_clk.h
  • IS_CLK_HSITRIMVALUE_OK : stm8s_clk.h
  • IS_CLK_IT_OK : stm8s_clk.h
  • IS_CLK_OUTPUT_OK : stm8s_clk.h
  • IS_CLK_PERIPHERAL_OK : stm8s_clk.h
  • IS_CLK_PRESCALER_OK : stm8s_clk.h
  • IS_CLK_SOURCE_OK : stm8s_clk.h
  • IS_CLK_SWIMDIVIDER_OK : stm8s_clk.h
  • IS_CLK_SWITCHMODE_OK : stm8s_clk.h
  • IS_EXTI_PINMASK_OK : stm8s_exti.h
  • IS_EXTI_PORT_OK : stm8s_exti.h
  • IS_EXTI_SENSITIVITY_OK : stm8s_exti.h
  • IS_EXTI_TLISENSITIVITY_OK : stm8s_exti.h
  • IS_FLASH_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_DATA_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_DATA_BLOCK_NUMBER_OK : stm8s_flash.h
  • IS_FLASH_FLAGS_OK : stm8s_flash.h
  • IS_FLASH_LOW_POWER_MODE_OK : stm8s_flash.h
  • IS_FLASH_PROG_ADDRESS_OK : stm8s_flash.h
  • IS_FLASH_PROG_BLOCK_NUMBER_OK : stm8s_flash.h
  • IS_FLASH_PROGRAM_MODE_OK : stm8s_flash.h
  • IS_FLASH_PROGRAM_TIME_OK : stm8s_flash.h
  • IS_FUNCTIONALSTATE_OK : stm8s.h
  • IS_GPIO_MODE_OK : stm8s_gpio.h
  • IS_GPIO_PIN_OK : stm8s_gpio.h
  • IS_I2C_ACK_OK : stm8s_i2c.h
  • IS_I2C_ADDMODE_OK : stm8s_i2c.h
  • IS_I2C_ADDRESS_OK : stm8s_i2c.h
  • IS_I2C_CLEAR_FLAG_OK : stm8s_i2c.h
  • IS_I2C_CLEAR_ITPENDINGBIT_OK : stm8s_i2c.h
  • IS_I2C_DIRECTION_OK : stm8s_i2c.h
  • IS_I2C_DUTYCYCLE_OK : stm8s_i2c.h
  • IS_I2C_EVENT_OK : stm8s_i2c.h
  • IS_I2C_FLAG_OK : stm8s_i2c.h
  • IS_I2C_INPUT_CLOCK_FREQ_OK : stm8s_i2c.h
  • IS_I2C_INTERRUPT_OK : stm8s_i2c.h
  • IS_I2C_ITPENDINGBIT_OK : stm8s_i2c.h
  • IS_I2C_OUTPUT_CLOCK_FREQ_OK : stm8s_i2c.h
  • IS_I2C_OWN_ADDRESS_OK : stm8s_i2c.h
  • IS_ITC_INTERRUPTS_DISABLED : stm8s_itc.h
  • IS_ITC_IRQ_OK : stm8s_itc.h
  • IS_ITC_PRIORITY_OK : stm8s_itc.h
  • IS_IWDG_PRESCALER_OK : stm8s_iwdg.h
  • IS_IWDG_WRITEACCESS_MODE_OK : stm8s_iwdg.h
  • IS_LSI_FREQUENCY_OK : stm8s_awu.h , stm8s_beep.h
  • IS_MEMORY_TYPE_OK : stm8s_flash.h
  • IS_OPTION_BYTE_ADDRESS_OK : stm8s_flash.h
  • IS_RST_FLAG_OK : stm8s_rst.h
  • IS_SPI_BAUDRATE_PRESCALER_OK : stm8s_spi.h
  • IS_SPI_CLEAR_FLAGS_OK : stm8s_spi.h
  • IS_SPI_CLEAR_IT_OK : stm8s_spi.h
  • IS_SPI_CONFIG_IT_OK : stm8s_spi.h
  • IS_SPI_CRC_OK : stm8s_spi.h
  • IS_SPI_CRC_POLYNOMIAL_OK : stm8s_spi.h
  • IS_SPI_DATA_DIRECTION_OK : stm8s_spi.h
  • IS_SPI_DIRECTION_OK : stm8s_spi.h
  • IS_SPI_FIRSTBIT_OK : stm8s_spi.h
  • IS_SPI_FLAGS_OK : stm8s_spi.h
  • IS_SPI_GET_IT_OK : stm8s_spi.h
  • IS_SPI_MODE_OK : stm8s_spi.h
  • IS_SPI_PHASE_OK : stm8s_spi.h
  • IS_SPI_POLARITY_OK : stm8s_spi.h
  • IS_SPI_SLAVEMANAGEMENT_OK : stm8s_spi.h
  • IS_STATE_VALUE_OK : stm8s.h
  • IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK : stm8s_tim1.h
  • IS_TIM1_BREAK_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_BREAK_STATE_OK : stm8s_tim1.h
  • IS_TIM1_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_CLEAR_FLAG_OK : stm8s_tim1.h
  • IS_TIM1_COMPLEMENTARY_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_COUNTER_MODE_OK : stm8s_tim1.h
  • IS_TIM1_ENCODER_MODE_OK : stm8s_tim1.h
  • IS_TIM1_EVENT_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_EXT_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_EXT_PRESCALER_OK : stm8s_tim1.h
  • IS_TIM1_EXT_TRG_FILTER_OK : stm8s_tim1.h
  • IS_TIM1_FORCED_ACTION_OK : stm8s_tim1.h
  • IS_TIM1_GET_FLAG_OK : stm8s_tim1.h
  • IS_TIM1_GET_IT_OK : stm8s_tim1.h
  • IS_TIM1_IC_FILTER_OK : stm8s_tim1.h
  • IS_TIM1_IC_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_IC_PRESCALER_OK : stm8s_tim1.h
  • IS_TIM1_IC_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_IT_OK : stm8s_tim1.h
  • IS_TIM1_LOCK_LEVEL_OK : stm8s_tim1.h
  • IS_TIM1_OC_MODE_OK : stm8s_tim1.h
  • IS_TIM1_OC_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_OCIDLE_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OCM_OK : stm8s_tim1.h
  • IS_TIM1_OCN_POLARITY_OK : stm8s_tim1.h
  • IS_TIM1_OCNIDLE_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OPM_MODE_OK : stm8s_tim1.h
  • IS_TIM1_OSSI_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OUTPUT_STATE_OK : stm8s_tim1.h
  • IS_TIM1_OUTPUTN_STATE_OK : stm8s_tim1.h
  • IS_TIM1_PRESCALER_RELOAD_OK : stm8s_tim1.h
  • IS_TIM1_PWMI_CHANNEL_OK : stm8s_tim1.h
  • IS_TIM1_SLAVE_MODE_OK : stm8s_tim1.h
  • IS_TIM1_TIX_TRIGGER_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_TIXCLK_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_TRGO_SOURCE_OK : stm8s_tim1.h
  • IS_TIM1_TRIGGER_SELECTION_OK : stm8s_tim1.h
  • IS_TIM1_UPDATE_SOURCE_OK : stm8s_tim1.h
  • IS_TIM2_CHANNEL_OK : stm8s_tim2.h
  • IS_TIM2_CLEAR_FLAG_OK : stm8s_tim2.h
  • IS_TIM2_EVENT_SOURCE_OK : stm8s_tim2.h
  • IS_TIM2_FORCED_ACTION_OK : stm8s_tim2.h
  • IS_TIM2_GET_FLAG_OK : stm8s_tim2.h
  • IS_TIM2_GET_IT_OK : stm8s_tim2.h
  • IS_TIM2_IC_FILTER_OK : stm8s_tim2.h
  • IS_TIM2_IC_POLARITY_OK : stm8s_tim2.h
  • IS_TIM2_IC_PRESCALER_OK : stm8s_tim2.h
  • IS_TIM2_IC_SELECTION1_OK : stm8s_tim2.h
  • IS_TIM2_IC_SELECTION_OK : stm8s_tim2.h
  • IS_TIM2_IT_OK : stm8s_tim2.h
  • IS_TIM2_OC_MODE_OK : stm8s_tim2.h
  • IS_TIM2_OC_POLARITY_OK : stm8s_tim2.h
  • IS_TIM2_OCM_OK : stm8s_tim2.h
  • IS_TIM2_OPM_MODE_OK : stm8s_tim2.h
  • IS_TIM2_OUTPUT_STATE_OK : stm8s_tim2.h
  • IS_TIM2_PRESCALER_OK : stm8s_tim2.h
  • IS_TIM2_PRESCALER_RELOAD_OK : stm8s_tim2.h
  • IS_TIM2_PWMI_CHANNEL_OK : stm8s_tim2.h
  • IS_TIM2_UPDATE_SOURCE_OK : stm8s_tim2.h
  • IS_TIM3_CHANNEL_OK : stm8s_tim3.h
  • IS_TIM3_CLEAR_FLAG_OK : stm8s_tim3.h
  • IS_TIM3_EVENT_SOURCE_OK : stm8s_tim3.h
  • IS_TIM3_FORCED_ACTION_OK : stm8s_tim3.h
  • IS_TIM3_GET_FLAG_OK : stm8s_tim3.h
  • IS_TIM3_GET_IT_OK : stm8s_tim3.h
  • IS_TIM3_IC_FILTER_OK : stm8s_tim3.h
  • IS_TIM3_IC_POLARITY_OK : stm8s_tim3.h
  • IS_TIM3_IC_PRESCALER_OK : stm8s_tim3.h
  • IS_TIM3_IC_SELECTION_OK : stm8s_tim3.h
  • IS_TIM3_IT_OK : stm8s_tim3.h
  • IS_TIM3_OC_MODE_OK : stm8s_tim3.h
  • IS_TIM3_OC_POLARITY_OK : stm8s_tim3.h
  • IS_TIM3_OCM_OK : stm8s_tim3.h
  • IS_TIM3_OPM_MODE_OK : stm8s_tim3.h
  • IS_TIM3_OUTPUT_STATE_OK : stm8s_tim3.h
  • IS_TIM3_PRESCALER_OK : stm8s_tim3.h
  • IS_TIM3_PRESCALER_RELOAD_OK : stm8s_tim3.h
  • IS_TIM3_PWMI_CHANNEL_OK : stm8s_tim3.h
  • IS_TIM3_UPDATE_SOURCE_OK : stm8s_tim3.h
  • IS_TIM4_EVENT_SOURCE_OK : stm8s_tim4.h
  • IS_TIM4_GET_FLAG_OK : stm8s_tim4.h
  • IS_TIM4_IT_OK : stm8s_tim4.h
  • IS_TIM4_OPM_MODE_OK : stm8s_tim4.h
  • IS_TIM4_PRESCALER_OK : stm8s_tim4.h
  • IS_TIM4_PRESCALER_RELOAD_OK : stm8s_tim4.h
  • IS_TIM4_UPDATE_SOURCE_OK : stm8s_tim4.h
  • IS_TIM5_CHANNEL_OK : stm8s_tim5.h
  • IS_TIM5_CLEAR_FLAG_OK : stm8s_tim5.h
  • IS_TIM5_ENCODER_MODE_OK : stm8s_tim5.h
  • IS_TIM5_EVENT_SOURCE_OK : stm8s_tim5.h
  • IS_TIM5_EXT_FILTER_OK : stm8s_tim5.h
  • IS_TIM5_EXT_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_EXT_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_FORCED_ACTION_OK : stm8s_tim5.h
  • IS_TIM5_GET_FLAG_OK : stm8s_tim5.h
  • IS_TIM5_GET_IT_OK : stm8s_tim5.h
  • IS_TIM5_IC_FILTER_OK : stm8s_tim5.h
  • IS_TIM5_IC_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_IC_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_IC_SELECTION1_OK : stm8s_tim5.h
  • IS_TIM5_IC_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_IT_OK : stm8s_tim5.h
  • IS_TIM5_OC_MODE_OK : stm8s_tim5.h
  • IS_TIM5_OC_POLARITY_OK : stm8s_tim5.h
  • IS_TIM5_OCM_OK : stm8s_tim5.h
  • IS_TIM5_OPM_MODE_OK : stm8s_tim5.h
  • IS_TIM5_OUTPUT_STATE_OK : stm8s_tim5.h
  • IS_TIM5_PRESCALER_OK : stm8s_tim5.h
  • IS_TIM5_PRESCALER_RELOAD_OK : stm8s_tim5.h
  • IS_TIM5_PWMI_CHANNEL_OK : stm8s_tim5.h
  • IS_TIM5_SLAVE_MODE_OK : stm8s_tim5.h
  • IS_TIM5_TIX_TRIGGER_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_TRGO_SOURCE_OK : stm8s_tim5.h
  • IS_TIM5_TRIGGER_SELECTION_OK : stm8s_tim5.h
  • IS_TIM5_UPDATE_SOURCE_OK : stm8s_tim5.h
  • IS_TIM6_CLEAR_FLAG_OK : stm8s_tim6.h
  • IS_TIM6_EVENT_SOURCE_OK : stm8s_tim6.h
  • IS_TIM6_GET_FLAG_OK : stm8s_tim6.h
  • IS_TIM6_GET_IT_OK : stm8s_tim6.h
  • IS_TIM6_IT_OK : stm8s_tim6.h
  • IS_TIM6_OPM_MODE_OK : stm8s_tim6.h
  • IS_TIM6_PRESCALER_OK : stm8s_tim6.h
  • IS_TIM6_PRESCALER_RELOAD_OK : stm8s_tim6.h
  • IS_TIM6_SLAVE_MODE_OK : stm8s_tim6.h
  • IS_TIM6_TRGO_SOURCE_OK : stm8s_tim6.h
  • IS_TIM6_TRIGGER_SELECTION_OK : stm8s_tim6.h
  • IS_TIM6_UPDATE_SOURCE_OK : stm8s_tim6.h
  • IS_UART1_ADDRESS_OK : stm8s_uart1.h
  • IS_UART1_BAUDRATE_OK : stm8s_uart1.h
  • IS_UART1_CLEAR_FLAG_OK : stm8s_uart1.h
  • IS_UART1_CLEAR_IT_OK : stm8s_uart1.h
  • IS_UART1_CONFIG_IT_OK : stm8s_uart1.h
  • IS_UART1_FLAG_OK : stm8s_uart1.h
  • IS_UART1_GET_IT_OK : stm8s_uart1.h
  • IS_UART1_IRDAMODE_OK : stm8s_uart1.h
  • IS_UART1_LINBREAKDETECTIONLENGTH_OK : stm8s_uart1.h
  • IS_UART1_MODE_OK : stm8s_uart1.h
  • IS_UART1_PARITY_OK : stm8s_uart1.h
  • IS_UART1_STOPBITS_OK : stm8s_uart1.h
  • IS_UART1_SYNCMODE_OK : stm8s_uart1.h
  • IS_UART1_WAKEUP_OK : stm8s_uart1.h
  • IS_UART1_WORDLENGTH_OK : stm8s_uart1.h
  • IS_UART2_ADDRESS_OK : stm8s_uart2.h
  • IS_UART2_AUTOSYNC_OK : stm8s_uart2.h
  • IS_UART2_BAUDRATE_OK : stm8s_uart2.h
  • IS_UART2_CLEAR_FLAG_OK : stm8s_uart2.h
  • IS_UART2_CLEAR_IT_OK : stm8s_uart2.h
  • IS_UART2_CONFIG_IT_OK : stm8s_uart2.h
  • IS_UART2_DIVUP_OK : stm8s_uart2.h
  • IS_UART2_FLAG_OK : stm8s_uart2.h
  • IS_UART2_GET_IT_OK : stm8s_uart2.h
  • IS_UART2_IRDAMODE_OK : stm8s_uart2.h
  • IS_UART2_LINBREAKDETECTIONLENGTH_OK : stm8s_uart2.h
  • IS_UART2_MODE_OK : stm8s_uart2.h
  • IS_UART2_PARITY_OK : stm8s_uart2.h
  • IS_UART2_SLAVE_OK : stm8s_uart2.h
  • IS_UART2_STOPBITS_OK : stm8s_uart2.h
  • IS_UART2_SYNCMODE_OK : stm8s_uart2.h
  • IS_UART2_WAKEUP_OK : stm8s_uart2.h
  • IS_UART2_WORDLENGTH_OK : stm8s_uart2.h
  • IS_UART3_ADDRESS_OK : stm8s_uart3.h
  • IS_UART3_AUTOSYNC_OK : stm8s_uart3.h
  • IS_UART3_BAUDRATE_OK : stm8s_uart3.h
  • IS_UART3_CLEAR_FLAG_OK : stm8s_uart3.h
  • IS_UART3_CLEAR_IT_OK : stm8s_uart3.h
  • IS_UART3_CONFIG_IT_OK : stm8s_uart3.h
  • IS_UART3_DIVUP_OK : stm8s_uart3.h
  • IS_UART3_FLAG_OK : stm8s_uart3.h
  • IS_UART3_GET_IT_OK : stm8s_uart3.h
  • IS_UART3_LINBREAKDETECTIONLENGTH_OK : stm8s_uart3.h
  • IS_UART3_MODE_OK : stm8s_uart3.h
  • IS_UART3_PARITY_OK : stm8s_uart3.h
  • IS_UART3_SLAVE_OK : stm8s_uart3.h
  • IS_UART3_STOPBITS_OK : stm8s_uart3.h
  • IS_UART3_WAKEUP_OK : stm8s_uart3.h
  • IS_UART3_WORDLENGTH_OK : stm8s_uart3.h
  • IS_WWDG_COUNTERVALUE_OK : stm8s_wwdg.h
  • IS_WWDG_WINDOWLIMITVALUE_OK : stm8s_wwdg.h
  • ITC : stm8s.h
  • ITC_BaseAddress : stm8s.h
  • ITC_SPRX_RESET_VALUE : stm8s.h
  • ITEN_Mask : stm8s_i2c.c
  • IWDG : stm8s.h
  • IWDG_BaseAddress : stm8s.h
  • IWDG_KEY_ENABLE : stm8s_iwdg.h
  • IWDG_KEY_REFRESH : stm8s_iwdg.h
  • IWDG_PR_RESET_VALUE : stm8s.h
  • IWDG_RLR_RESET_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- p -

  • PointerAttr : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- r -

  • REGISTER_Mask : stm8s_i2c.c
  • REGISTER_SR1_Index : stm8s_i2c.c
  • REGISTER_SR2_Index : stm8s_i2c.c
  • rim : stm8s.h
  • RST : stm8s.h
  • RST_BaseAddress : stm8s.h
  • RST_SR_EMCF : stm8s.h
  • RST_SR_ILLOPF : stm8s.h
  • RST_SR_IWDGF : stm8s.h
  • RST_SR_SWIMF : stm8s.h
  • RST_SR_WWDGF : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- s -

  • S16_MAX : stm8s.h
  • S16_MIN : stm8s.h
  • S32_MAX : stm8s.h
  • S32_MIN : stm8s.h
  • S8_MAX : stm8s.h
  • S8_MIN : stm8s.h
  • SetBit : stm8s.h
  • sim : stm8s.h
  • SPI : stm8s.h
  • SPI_BaseAddress : stm8s.h
  • SPI_CR1_BR : stm8s.h
  • SPI_CR1_CPHA : stm8s.h
  • SPI_CR1_CPOL : stm8s.h
  • SPI_CR1_LSBFIRST : stm8s.h
  • SPI_CR1_MSTR : stm8s.h
  • SPI_CR1_RESET_VALUE : stm8s.h
  • SPI_CR1_SPE : stm8s.h
  • SPI_CR2_BDM : stm8s.h
  • SPI_CR2_BDOE : stm8s.h
  • SPI_CR2_CRCEN : stm8s.h
  • SPI_CR2_CRCNEXT : stm8s.h
  • SPI_CR2_RESET_VALUE : stm8s.h
  • SPI_CR2_RXONLY : stm8s.h
  • SPI_CR2_SSI : stm8s.h
  • SPI_CR2_SSM : stm8s.h
  • SPI_CRCPR_RESET_VALUE : stm8s.h
  • SPI_DR_RESET_VALUE : stm8s.h
  • SPI_ICR_ERRIE : stm8s.h
  • SPI_ICR_RESET_VALUE : stm8s.h
  • SPI_ICR_RXEI : stm8s.h
  • SPI_ICR_TXEI : stm8s.h
  • SPI_ICR_WKIE : stm8s.h
  • SPI_RXCRCR_RESET_VALUE : stm8s.h
  • SPI_SR_BSY : stm8s.h
  • SPI_SR_CRCERR : stm8s.h
  • SPI_SR_MODF : stm8s.h
  • SPI_SR_OVR : stm8s.h
  • SPI_SR_RESET_VALUE : stm8s.h
  • SPI_SR_RXNE : stm8s.h
  • SPI_SR_TXE : stm8s.h
  • SPI_SR_WKUP : stm8s.h
  • SPI_TXCRCR_RESET_VALUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- t -

  • TIM1 : stm8s.h
  • TIM1_ARRH_ARR : stm8s.h
  • TIM1_ARRH_RESET_VALUE : stm8s.h
  • TIM1_ARRL_ARR : stm8s.h
  • TIM1_ARRL_RESET_VALUE : stm8s.h
  • TIM1_BaseAddress : stm8s.h
  • TIM1_BKR_AOE : stm8s.h
  • TIM1_BKR_BKE : stm8s.h
  • TIM1_BKR_BKP : stm8s.h
  • TIM1_BKR_LOCK : stm8s.h
  • TIM1_BKR_MOE : stm8s.h
  • TIM1_BKR_OSSI : stm8s.h
  • TIM1_BKR_OSSR : stm8s.h
  • TIM1_BKR_RESET_VALUE : stm8s.h
  • TIM1_CCER1_CC1E : stm8s.h
  • TIM1_CCER1_CC1NE : stm8s.h
  • TIM1_CCER1_CC1NP : stm8s.h
  • TIM1_CCER1_CC1P : stm8s.h
  • TIM1_CCER1_CC2E : stm8s.h
  • TIM1_CCER1_CC2NE : stm8s.h
  • TIM1_CCER1_CC2NP : stm8s.h
  • TIM1_CCER1_CC2P : stm8s.h
  • TIM1_CCER1_RESET_VALUE : stm8s.h
  • TIM1_CCER2_CC3E : stm8s.h
  • TIM1_CCER2_CC3NE : stm8s.h
  • TIM1_CCER2_CC3NP : stm8s.h
  • TIM1_CCER2_CC3P : stm8s.h
  • TIM1_CCER2_CC4E : stm8s.h
  • TIM1_CCER2_CC4P : stm8s.h
  • TIM1_CCER2_RESET_VALUE : stm8s.h
  • TIM1_CCMR1_RESET_VALUE : stm8s.h
  • TIM1_CCMR2_RESET_VALUE : stm8s.h
  • TIM1_CCMR3_RESET_VALUE : stm8s.h
  • TIM1_CCMR4_RESET_VALUE : stm8s.h
  • TIM1_CCMR_CCxS : stm8s.h
  • TIM1_CCMR_ICxF : stm8s.h
  • TIM1_CCMR_ICxPSC : stm8s.h
  • TIM1_CCMR_OCM : stm8s.h
  • TIM1_CCMR_OCxFE : stm8s.h
  • TIM1_CCMR_OCxPE : stm8s.h
  • TIM1_CCR1H_CCR1 : stm8s.h
  • TIM1_CCR1H_RESET_VALUE : stm8s.h
  • TIM1_CCR1L_CCR1 : stm8s.h
  • TIM1_CCR1L_RESET_VALUE : stm8s.h
  • TIM1_CCR2H_CCR2 : stm8s.h
  • TIM1_CCR2H_RESET_VALUE : stm8s.h
  • TIM1_CCR2L_CCR2 : stm8s.h
  • TIM1_CCR2L_RESET_VALUE : stm8s.h
  • TIM1_CCR3H_CCR3 : stm8s.h
  • TIM1_CCR3H_RESET_VALUE : stm8s.h
  • TIM1_CCR3L_CCR3 : stm8s.h
  • TIM1_CCR3L_RESET_VALUE : stm8s.h
  • TIM1_CCR4H_CCR4 : stm8s.h
  • TIM1_CCR4H_RESET_VALUE : stm8s.h
  • TIM1_CCR4L_CCR4 : stm8s.h
  • TIM1_CCR4L_RESET_VALUE : stm8s.h
  • TIM1_CNTRH_CNT : stm8s.h
  • TIM1_CNTRH_RESET_VALUE : stm8s.h
  • TIM1_CNTRL_CNT : stm8s.h
  • TIM1_CNTRL_RESET_VALUE : stm8s.h
  • TIM1_CR1_ARPE : stm8s.h
  • TIM1_CR1_CEN : stm8s.h
  • TIM1_CR1_CMS : stm8s.h
  • TIM1_CR1_DIR : stm8s.h
  • TIM1_CR1_OPM : stm8s.h
  • TIM1_CR1_RESET_VALUE : stm8s.h
  • TIM1_CR1_UDIS : stm8s.h
  • TIM1_CR1_URS : stm8s.h
  • TIM1_CR2_CCPC : stm8s.h
  • TIM1_CR2_COMS : stm8s.h
  • TIM1_CR2_MMS : stm8s.h
  • TIM1_CR2_RESET_VALUE : stm8s.h
  • TIM1_CR2_TI1S : stm8s.h
  • TIM1_DTR_DTG : stm8s.h
  • TIM1_DTR_RESET_VALUE : stm8s.h
  • TIM1_EGR_BG : stm8s.h
  • TIM1_EGR_CC1G : stm8s.h
  • TIM1_EGR_CC2G : stm8s.h
  • TIM1_EGR_CC3G : stm8s.h
  • TIM1_EGR_CC4G : stm8s.h
  • TIM1_EGR_COMG : stm8s.h
  • TIM1_EGR_RESET_VALUE : stm8s.h
  • TIM1_EGR_TG : stm8s.h
  • TIM1_EGR_UG : stm8s.h
  • TIM1_ETR_ECE : stm8s.h
  • TIM1_ETR_ETF : stm8s.h
  • TIM1_ETR_ETP : stm8s.h
  • TIM1_ETR_ETPS : stm8s.h
  • TIM1_ETR_RESET_VALUE : stm8s.h
  • TIM1_IER_BIE : stm8s.h
  • TIM1_IER_CC1IE : stm8s.h
  • TIM1_IER_CC2IE : stm8s.h
  • TIM1_IER_CC3IE : stm8s.h
  • TIM1_IER_CC4IE : stm8s.h
  • TIM1_IER_COMIE : stm8s.h
  • TIM1_IER_RESET_VALUE : stm8s.h
  • TIM1_IER_TIE : stm8s.h
  • TIM1_IER_UIE : stm8s.h
  • TIM1_OISR_OIS1 : stm8s.h
  • TIM1_OISR_OIS1N : stm8s.h
  • TIM1_OISR_OIS2 : stm8s.h
  • TIM1_OISR_OIS2N : stm8s.h
  • TIM1_OISR_OIS3 : stm8s.h
  • TIM1_OISR_OIS3N : stm8s.h
  • TIM1_OISR_OIS4 : stm8s.h
  • TIM1_OISR_RESET_VALUE : stm8s.h
  • TIM1_PSCH_PSC : stm8s.h
  • TIM1_PSCL_PSC : stm8s.h
  • TIM1_PSCRH_RESET_VALUE : stm8s.h
  • TIM1_PSCRL_RESET_VALUE : stm8s.h
  • TIM1_RCR_REP : stm8s.h
  • TIM1_RCR_RESET_VALUE : stm8s.h
  • TIM1_SMCR_MSM : stm8s.h
  • TIM1_SMCR_RESET_VALUE : stm8s.h
  • TIM1_SMCR_SMS : stm8s.h
  • TIM1_SMCR_TS : stm8s.h
  • TIM1_SR1_BIF : stm8s.h
  • TIM1_SR1_CC1IF : stm8s.h
  • TIM1_SR1_CC2IF : stm8s.h
  • TIM1_SR1_CC3IF : stm8s.h
  • TIM1_SR1_CC4IF : stm8s.h
  • TIM1_SR1_COMIF : stm8s.h
  • TIM1_SR1_RESET_VALUE : stm8s.h
  • TIM1_SR1_TIF : stm8s.h
  • TIM1_SR1_UIF : stm8s.h
  • TIM1_SR2_CC1OF : stm8s.h
  • TIM1_SR2_CC2OF : stm8s.h
  • TIM1_SR2_CC3OF : stm8s.h
  • TIM1_SR2_CC4OF : stm8s.h
  • TIM1_SR2_RESET_VALUE : stm8s.h
  • TIM2_ARRH_ARR : stm8s.h
  • TIM2_ARRH_RESET_VALUE : stm8s.h
  • TIM2_ARRL_ARR : stm8s.h
  • TIM2_ARRL_RESET_VALUE : stm8s.h
  • TIM2_BaseAddress : stm8s.h
  • TIM2_CCER1_CC1E : stm8s.h
  • TIM2_CCER1_CC1P : stm8s.h
  • TIM2_CCER1_CC2E : stm8s.h
  • TIM2_CCER1_CC2P : stm8s.h
  • TIM2_CCER1_RESET_VALUE : stm8s.h
  • TIM2_CCER2_CC3E : stm8s.h
  • TIM2_CCER2_CC3P : stm8s.h
  • TIM2_CCER2_RESET_VALUE : stm8s.h
  • TIM2_CCMR1_RESET_VALUE : stm8s.h
  • TIM2_CCMR2_RESET_VALUE : stm8s.h
  • TIM2_CCMR3_RESET_VALUE : stm8s.h
  • TIM2_CCMR_CCxS : stm8s.h
  • TIM2_CCMR_ICxF : stm8s.h
  • TIM2_CCMR_ICxPSC : stm8s.h
  • TIM2_CCMR_OCM : stm8s.h
  • TIM2_CCMR_OCxPE : stm8s.h
  • TIM2_CCR1H_CCR1 : stm8s.h
  • TIM2_CCR1H_RESET_VALUE : stm8s.h
  • TIM2_CCR1L_CCR1 : stm8s.h
  • TIM2_CCR1L_RESET_VALUE : stm8s.h
  • TIM2_CCR2H_CCR2 : stm8s.h
  • TIM2_CCR2H_RESET_VALUE : stm8s.h
  • TIM2_CCR2L_CCR2 : stm8s.h
  • TIM2_CCR2L_RESET_VALUE : stm8s.h
  • TIM2_CCR3H_CCR3 : stm8s.h
  • TIM2_CCR3H_RESET_VALUE : stm8s.h
  • TIM2_CCR3L_CCR3 : stm8s.h
  • TIM2_CCR3L_RESET_VALUE : stm8s.h
  • TIM2_CNTRH_CNT : stm8s.h
  • TIM2_CNTRH_RESET_VALUE : stm8s.h
  • TIM2_CNTRL_CNT : stm8s.h
  • TIM2_CNTRL_RESET_VALUE : stm8s.h
  • TIM2_CR1_ARPE : stm8s.h
  • TIM2_CR1_CEN : stm8s.h
  • TIM2_CR1_OPM : stm8s.h
  • TIM2_CR1_RESET_VALUE : stm8s.h
  • TIM2_CR1_UDIS : stm8s.h
  • TIM2_CR1_URS : stm8s.h
  • TIM2_EGR_CC1G : stm8s.h
  • TIM2_EGR_CC2G : stm8s.h
  • TIM2_EGR_CC3G : stm8s.h
  • TIM2_EGR_RESET_VALUE : stm8s.h
  • TIM2_EGR_UG : stm8s.h
  • TIM2_IER_CC1IE : stm8s.h
  • TIM2_IER_CC2IE : stm8s.h
  • TIM2_IER_CC3IE : stm8s.h
  • TIM2_IER_RESET_VALUE : stm8s.h
  • TIM2_IER_UIE : stm8s.h
  • TIM2_PSCR_PSC : stm8s.h
  • TIM2_PSCR_RESET_VALUE : stm8s.h
  • TIM2_SR1_CC1IF : stm8s.h
  • TIM2_SR1_CC2IF : stm8s.h
  • TIM2_SR1_CC3IF : stm8s.h
  • TIM2_SR1_RESET_VALUE : stm8s.h
  • TIM2_SR1_UIF : stm8s.h
  • TIM2_SR2_CC1OF : stm8s.h
  • TIM2_SR2_CC2OF : stm8s.h
  • TIM2_SR2_CC3OF : stm8s.h
  • TIM2_SR2_RESET_VALUE : stm8s.h
  • TIM3_ARRH_ARR : stm8s.h
  • TIM3_ARRH_RESET_VALUE : stm8s.h
  • TIM3_ARRL_ARR : stm8s.h
  • TIM3_ARRL_RESET_VALUE : stm8s.h
  • TIM3_BaseAddress : stm8s.h
  • TIM3_CCER1_CC1E : stm8s.h
  • TIM3_CCER1_CC1P : stm8s.h
  • TIM3_CCER1_CC2E : stm8s.h
  • TIM3_CCER1_CC2P : stm8s.h
  • TIM3_CCER1_RESET_VALUE : stm8s.h
  • TIM3_CCMR1_RESET_VALUE : stm8s.h
  • TIM3_CCMR2_RESET_VALUE : stm8s.h
  • TIM3_CCMR_CCxS : stm8s.h
  • TIM3_CCMR_ICxF : stm8s.h
  • TIM3_CCMR_ICxPSC : stm8s.h
  • TIM3_CCMR_OCM : stm8s.h
  • TIM3_CCMR_OCxPE : stm8s.h
  • TIM3_CCR1H_CCR1 : stm8s.h
  • TIM3_CCR1H_RESET_VALUE : stm8s.h
  • TIM3_CCR1L_CCR1 : stm8s.h
  • TIM3_CCR1L_RESET_VALUE : stm8s.h
  • TIM3_CCR2H_CCR2 : stm8s.h
  • TIM3_CCR2H_RESET_VALUE : stm8s.h
  • TIM3_CCR2L_CCR2 : stm8s.h
  • TIM3_CCR2L_RESET_VALUE : stm8s.h
  • TIM3_CNTRH_CNT : stm8s.h
  • TIM3_CNTRH_RESET_VALUE : stm8s.h
  • TIM3_CNTRL_CNT : stm8s.h
  • TIM3_CNTRL_RESET_VALUE : stm8s.h
  • TIM3_CR1_ARPE : stm8s.h
  • TIM3_CR1_CEN : stm8s.h
  • TIM3_CR1_OPM : stm8s.h
  • TIM3_CR1_RESET_VALUE : stm8s.h
  • TIM3_CR1_UDIS : stm8s.h
  • TIM3_CR1_URS : stm8s.h
  • TIM3_EGR_CC1G : stm8s.h
  • TIM3_EGR_CC2G : stm8s.h
  • TIM3_EGR_RESET_VALUE : stm8s.h
  • TIM3_EGR_UG : stm8s.h
  • TIM3_IER_CC1IE : stm8s.h
  • TIM3_IER_CC2IE : stm8s.h
  • TIM3_IER_RESET_VALUE : stm8s.h
  • TIM3_IER_UIE : stm8s.h
  • TIM3_PSCR_PSC : stm8s.h
  • TIM3_PSCR_RESET_VALUE : stm8s.h
  • TIM3_SR1_CC1IF : stm8s.h
  • TIM3_SR1_CC2IF : stm8s.h
  • TIM3_SR1_RESET_VALUE : stm8s.h
  • TIM3_SR1_UIF : stm8s.h
  • TIM3_SR2_CC1OF : stm8s.h
  • TIM3_SR2_CC2OF : stm8s.h
  • TIM3_SR2_RESET_VALUE : stm8s.h
  • TIM4_ARR_ARR : stm8s.h
  • TIM4_ARR_RESET_VALUE : stm8s.h
  • TIM4_BaseAddress : stm8s.h
  • TIM4_CNTR_CNT : stm8s.h
  • TIM4_CNTR_RESET_VALUE : stm8s.h
  • TIM4_CR1_ARPE : stm8s.h
  • TIM4_CR1_CEN : stm8s.h
  • TIM4_CR1_OPM : stm8s.h
  • TIM4_CR1_RESET_VALUE : stm8s.h
  • TIM4_CR1_UDIS : stm8s.h
  • TIM4_CR1_URS : stm8s.h
  • TIM4_EGR_RESET_VALUE : stm8s.h
  • TIM4_EGR_UG : stm8s.h
  • TIM4_IER_RESET_VALUE : stm8s.h
  • TIM4_IER_UIE : stm8s.h
  • TIM4_PSCR_PSC : stm8s.h
  • TIM4_PSCR_RESET_VALUE : stm8s.h
  • TIM4_SR1_RESET_VALUE : stm8s.h
  • TIM4_SR1_UIF : stm8s.h
  • TIM5_ARRH_ARR : stm8s.h
  • TIM5_ARRH_RESET_VALUE : stm8s.h
  • TIM5_ARRL_ARR : stm8s.h
  • TIM5_ARRL_RESET_VALUE : stm8s.h
  • TIM5_BaseAddress : stm8s.h
  • TIM5_CCER1_CC1E : stm8s.h
  • TIM5_CCER1_CC1P : stm8s.h
  • TIM5_CCER1_CC2E : stm8s.h
  • TIM5_CCER1_CC2P : stm8s.h
  • TIM5_CCER1_RESET_VALUE : stm8s.h
  • TIM5_CCER2_CC3E : stm8s.h
  • TIM5_CCER2_CC3P : stm8s.h
  • TIM5_CCER2_RESET_VALUE : stm8s.h
  • TIM5_CCMR1_RESET_VALUE : stm8s.h
  • TIM5_CCMR2_RESET_VALUE : stm8s.h
  • TIM5_CCMR3_RESET_VALUE : stm8s.h
  • TIM5_CCMR_CCxS : stm8s.h
  • TIM5_CCMR_ICxF : stm8s.h
  • TIM5_CCMR_ICxPSC : stm8s.h
  • TIM5_CCMR_OCM : stm8s.h
  • TIM5_CCMR_OCxPE : stm8s.h
  • TIM5_CCMR_TIxDirect_Set : stm8s.h
  • TIM5_CCR1H_CCR1 : stm8s.h
  • TIM5_CCR1H_RESET_VALUE : stm8s.h
  • TIM5_CCR1L_CCR1 : stm8s.h
  • TIM5_CCR1L_RESET_VALUE : stm8s.h
  • TIM5_CCR2H_CCR2 : stm8s.h
  • TIM5_CCR2H_RESET_VALUE : stm8s.h
  • TIM5_CCR2L_CCR2 : stm8s.h
  • TIM5_CCR2L_RESET_VALUE : stm8s.h
  • TIM5_CCR3H_CCR3 : stm8s.h
  • TIM5_CCR3H_RESET_VALUE : stm8s.h
  • TIM5_CCR3L_CCR3 : stm8s.h
  • TIM5_CCR3L_RESET_VALUE : stm8s.h
  • TIM5_CNTRH_CNT : stm8s.h
  • TIM5_CNTRH_RESET_VALUE : stm8s.h
  • TIM5_CNTRL_CNT : stm8s.h
  • TIM5_CNTRL_RESET_VALUE : stm8s.h
  • TIM5_CR1_ARPE : stm8s.h
  • TIM5_CR1_CEN : stm8s.h
  • TIM5_CR1_OPM : stm8s.h
  • TIM5_CR1_RESET_VALUE : stm8s.h
  • TIM5_CR1_UDIS : stm8s.h
  • TIM5_CR1_URS : stm8s.h
  • TIM5_CR2_MMS : stm8s.h
  • TIM5_CR2_RESET_VALUE : stm8s.h
  • TIM5_CR2_TI1S : stm8s.h
  • TIM5_EGR_CC1G : stm8s.h
  • TIM5_EGR_CC2G : stm8s.h
  • TIM5_EGR_CC3G : stm8s.h
  • TIM5_EGR_RESET_VALUE : stm8s.h
  • TIM5_EGR_TG : stm8s.h
  • TIM5_EGR_UG : stm8s.h
  • TIM5_IER_CC1IE : stm8s.h
  • TIM5_IER_CC2IE : stm8s.h
  • TIM5_IER_CC3IE : stm8s.h
  • TIM5_IER_RESET_VALUE : stm8s.h
  • TIM5_IER_TIE : stm8s.h
  • TIM5_IER_UIE : stm8s.h
  • TIM5_PSCR_PSC : stm8s.h
  • TIM5_PSCR_RESET_VALUE : stm8s.h
  • TIM5_SMCR_MSM : stm8s.h
  • TIM5_SMCR_RESET_VALUE : stm8s.h
  • TIM5_SMCR_SMS : stm8s.h
  • TIM5_SMCR_TS : stm8s.h
  • TIM5_SR1_CC1IF : stm8s.h
  • TIM5_SR1_CC2IF : stm8s.h
  • TIM5_SR1_CC3IF : stm8s.h
  • TIM5_SR1_RESET_VALUE : stm8s.h
  • TIM5_SR1_TIF : stm8s.h
  • TIM5_SR1_UIF : stm8s.h
  • TIM5_SR2_CC1OF : stm8s.h
  • TIM5_SR2_CC2OF : stm8s.h
  • TIM5_SR2_CC3OF : stm8s.h
  • TIM5_SR2_RESET_VALUE : stm8s.h
  • TIM6_ARR_ARR : stm8s.h
  • TIM6_ARR_RESET_VALUE : stm8s.h
  • TIM6_BaseAddress : stm8s.h
  • TIM6_CNTR_CNT : stm8s.h
  • TIM6_CNTR_RESET_VALUE : stm8s.h
  • TIM6_CR1_ARPE : stm8s.h
  • TIM6_CR1_CEN : stm8s.h
  • TIM6_CR1_OPM : stm8s.h
  • TIM6_CR1_RESET_VALUE : stm8s.h
  • TIM6_CR1_UDIS : stm8s.h
  • TIM6_CR1_URS : stm8s.h
  • TIM6_CR2_MMS : stm8s.h
  • TIM6_CR2_RESET_VALUE : stm8s.h
  • TIM6_EGR_RESET_VALUE : stm8s.h
  • TIM6_EGR_TG : stm8s.h
  • TIM6_EGR_UG : stm8s.h
  • TIM6_IER_RESET_VALUE : stm8s.h
  • TIM6_IER_TIE : stm8s.h
  • TIM6_IER_UIE : stm8s.h
  • TIM6_PSCR_PSC : stm8s.h
  • TIM6_PSCR_RESET_VALUE : stm8s.h
  • TIM6_SMCR_MSM : stm8s.h
  • TIM6_SMCR_RESET_VALUE : stm8s.h
  • TIM6_SMCR_SMS : stm8s.h
  • TIM6_SMCR_TS : stm8s.h
  • TIM6_SR1_RESET_VALUE : stm8s.h
  • TIM6_SR1_TIF : stm8s.h
  • TIM6_SR1_UIF : stm8s.h
  • TINY : stm8s.h
  • trap : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
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- u -

  • U16_MAX : stm8s.h
  • U32_MAX : stm8s.h
  • U8_MAX : stm8s.h
  • UART1_ADDRESS_MAX : stm8s_uart1.h
  • UART1_BaseAddress : stm8s.h
  • UART1_BRR1_DIVM : stm8s.h
  • UART1_BRR1_RESET_VALUE : stm8s.h
  • UART1_BRR2_DIVF : stm8s.h
  • UART1_BRR2_DIVM : stm8s.h
  • UART1_BRR2_RESET_VALUE : stm8s.h
  • UART1_CR1_M : stm8s.h
  • UART1_CR1_PCEN : stm8s.h
  • UART1_CR1_PIEN : stm8s.h
  • UART1_CR1_PS : stm8s.h
  • UART1_CR1_R8 : stm8s.h
  • UART1_CR1_RESET_VALUE : stm8s.h
  • UART1_CR1_T8 : stm8s.h
  • UART1_CR1_UARTD : stm8s.h
  • UART1_CR1_WAKE : stm8s.h
  • UART1_CR2_ILIEN : stm8s.h
  • UART1_CR2_REN : stm8s.h
  • UART1_CR2_RESET_VALUE : stm8s.h
  • UART1_CR2_RIEN : stm8s.h
  • UART1_CR2_RWU : stm8s.h
  • UART1_CR2_SBK : stm8s.h
  • UART1_CR2_TCIEN : stm8s.h
  • UART1_CR2_TEN : stm8s.h
  • UART1_CR2_TIEN : stm8s.h
  • UART1_CR3_CKEN : stm8s.h
  • UART1_CR3_CPHA : stm8s.h
  • UART1_CR3_CPOL : stm8s.h
  • UART1_CR3_LBCL : stm8s.h
  • UART1_CR3_LINEN : stm8s.h
  • UART1_CR3_RESET_VALUE : stm8s.h
  • UART1_CR3_STOP : stm8s.h
  • UART1_CR4_ADD : stm8s.h
  • UART1_CR4_LBDF : stm8s.h
  • UART1_CR4_LBDIEN : stm8s.h
  • UART1_CR4_LBDL : stm8s.h
  • UART1_CR4_RESET_VALUE : stm8s.h
  • UART1_CR5_HDSEL : stm8s.h
  • UART1_CR5_IREN : stm8s.h
  • UART1_CR5_IRLP : stm8s.h
  • UART1_CR5_NACK : stm8s.h
  • UART1_CR5_RESET_VALUE : stm8s.h
  • UART1_CR5_SCEN : stm8s.h
  • UART1_GTR_RESET_VALUE : stm8s.h
  • UART1_PSCR_RESET_VALUE : stm8s.h
  • UART1_SR_FE : stm8s.h
  • UART1_SR_IDLE : stm8s.h
  • UART1_SR_NF : stm8s.h
  • UART1_SR_OR : stm8s.h
  • UART1_SR_PE : stm8s.h
  • UART1_SR_RESET_VALUE : stm8s.h
  • UART1_SR_RXNE : stm8s.h
  • UART1_SR_TC : stm8s.h
  • UART1_SR_TXE : stm8s.h
  • UART2_ADDRESS_MAX : stm8s_uart2.h
  • UART2_BaseAddress : stm8s.h
  • UART2_BRR1_DIVM : stm8s.h
  • UART2_BRR1_RESET_VALUE : stm8s.h
  • UART2_BRR2_DIVF : stm8s.h
  • UART2_BRR2_DIVM : stm8s.h
  • UART2_BRR2_RESET_VALUE : stm8s.h
  • UART2_CR1_M : stm8s.h
  • UART2_CR1_PCEN : stm8s.h
  • UART2_CR1_PIEN : stm8s.h
  • UART2_CR1_PS : stm8s.h
  • UART2_CR1_R8 : stm8s.h
  • UART2_CR1_RESET_VALUE : stm8s.h
  • UART2_CR1_T8 : stm8s.h
  • UART2_CR1_UARTD : stm8s.h
  • UART2_CR1_WAKE : stm8s.h
  • UART2_CR2_ILIEN : stm8s.h
  • UART2_CR2_REN : stm8s.h
  • UART2_CR2_RESET_VALUE : stm8s.h
  • UART2_CR2_RIEN : stm8s.h
  • UART2_CR2_RWU : stm8s.h
  • UART2_CR2_SBK : stm8s.h
  • UART2_CR2_TCIEN : stm8s.h
  • UART2_CR2_TEN : stm8s.h
  • UART2_CR2_TIEN : stm8s.h
  • UART2_CR3_CKEN : stm8s.h
  • UART2_CR3_CPHA : stm8s.h
  • UART2_CR3_CPOL : stm8s.h
  • UART2_CR3_LBCL : stm8s.h
  • UART2_CR3_LINEN : stm8s.h
  • UART2_CR3_RESET_VALUE : stm8s.h
  • UART2_CR3_STOP : stm8s.h
  • UART2_CR4_ADD : stm8s.h
  • UART2_CR4_LBDF : stm8s.h
  • UART2_CR4_LBDIEN : stm8s.h
  • UART2_CR4_LBDL : stm8s.h
  • UART2_CR4_RESET_VALUE : stm8s.h
  • UART2_CR5_HDSEL : stm8s.h
  • UART2_CR5_IREN : stm8s.h
  • UART2_CR5_IRLP : stm8s.h
  • UART2_CR5_NACK : stm8s.h
  • UART2_CR5_RESET_VALUE : stm8s.h
  • UART2_CR5_SCEN : stm8s.h
  • UART2_CR6_LASE : stm8s.h
  • UART2_CR6_LDUM : stm8s.h
  • UART2_CR6_LHDF : stm8s.h
  • UART2_CR6_LHDIEN : stm8s.h
  • UART2_CR6_LSF : stm8s.h
  • UART2_CR6_LSLV : stm8s.h
  • UART2_CR6_RESET_VALUE : stm8s.h
  • UART2_GTR_RESET_VALUE : stm8s.h
  • UART2_PSCR_RESET_VALUE : stm8s.h
  • UART2_SR_FE : stm8s.h
  • UART2_SR_IDLE : stm8s.h
  • UART2_SR_NF : stm8s.h
  • UART2_SR_OR : stm8s.h
  • UART2_SR_PE : stm8s.h
  • UART2_SR_RESET_VALUE : stm8s.h
  • UART2_SR_RXNE : stm8s.h
  • UART2_SR_TC : stm8s.h
  • UART2_SR_TXE : stm8s.h
  • UART3_ADDRESS_MAX : stm8s_uart3.h
  • UART3_BaseAddress : stm8s.h
  • UART3_BRR1_DIVM : stm8s.h
  • UART3_BRR1_RESET_VALUE : stm8s.h
  • UART3_BRR2_DIVF : stm8s.h
  • UART3_BRR2_DIVM : stm8s.h
  • UART3_BRR2_RESET_VALUE : stm8s.h
  • UART3_CR1_M : stm8s.h
  • UART3_CR1_PCEN : stm8s.h
  • UART3_CR1_PIEN : stm8s.h
  • UART3_CR1_PS : stm8s.h
  • UART3_CR1_R8 : stm8s.h
  • UART3_CR1_RESET_VALUE : stm8s.h
  • UART3_CR1_T8 : stm8s.h
  • UART3_CR1_UARTD : stm8s.h
  • UART3_CR1_WAKE : stm8s.h
  • UART3_CR2_ILIEN : stm8s.h
  • UART3_CR2_REN : stm8s.h
  • UART3_CR2_RESET_VALUE : stm8s.h
  • UART3_CR2_RIEN : stm8s.h
  • UART3_CR2_RWU : stm8s.h
  • UART3_CR2_SBK : stm8s.h
  • UART3_CR2_TCIEN : stm8s.h
  • UART3_CR2_TEN : stm8s.h
  • UART3_CR2_TIEN : stm8s.h
  • UART3_CR3_LINEN : stm8s.h
  • UART3_CR3_RESET_VALUE : stm8s.h
  • UART3_CR3_STOP : stm8s.h
  • UART3_CR4_ADD : stm8s.h
  • UART3_CR4_LBDF : stm8s.h
  • UART3_CR4_LBDIEN : stm8s.h
  • UART3_CR4_LBDL : stm8s.h
  • UART3_CR4_RESET_VALUE : stm8s.h
  • UART3_CR6_LASE : stm8s.h
  • UART3_CR6_LDUM : stm8s.h
  • UART3_CR6_LHDF : stm8s.h
  • UART3_CR6_LHDIEN : stm8s.h
  • UART3_CR6_LSF : stm8s.h
  • UART3_CR6_LSLV : stm8s.h
  • UART3_CR6_RESET_VALUE : stm8s.h
  • UART3_SR_FE : stm8s.h
  • UART3_SR_IDLE : stm8s.h
  • UART3_SR_NF : stm8s.h
  • UART3_SR_OR : stm8s.h
  • UART3_SR_PE : stm8s.h
  • UART3_SR_RESET_VALUE : stm8s.h
  • UART3_SR_RXNE : stm8s.h
  • UART3_SR_TC : stm8s.h
  • UART3_SR_TXE : stm8s.h
  • USE_STDPERIPH_DRIVER : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- v -

  • ValBit : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- w -

  • wfi : stm8s.h
  • WWDG : stm8s.h
  • WWDG_BaseAddress : stm8s.h
  • WWDG_CR_RESET_VALUE : stm8s.h
  • WWDG_CR_T : stm8s.h
  • WWDG_CR_T6 : stm8s.h
  • WWDG_CR_WDGA : stm8s.h
  • WWDG_WR_MSB : stm8s.h
  • WWDG_WR_RESET_VALUE : stm8s.h
  • WWDG_WR_W : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- a -

  • ADC1_Align_TypeDef : stm8s_adc1.h
  • ADC1_Channel_TypeDef : stm8s_adc1.h
  • ADC1_ConvMode_TypeDef : stm8s_adc1.h
  • ADC1_ExtTrig_TypeDef : stm8s_adc1.h
  • ADC1_Flag_TypeDef : stm8s_adc1.h
  • ADC1_IT_TypeDef : stm8s_adc1.h
  • ADC1_PresSel_TypeDef : stm8s_adc1.h
  • ADC1_SchmittTrigg_TypeDef : stm8s_adc1.h
  • ADC2_Align_TypeDef : stm8s_adc2.h
  • ADC2_Channel_TypeDef : stm8s_adc2.h
  • ADC2_ConvMode_TypeDef : stm8s_adc2.h
  • ADC2_ExtTrig_TypeDef : stm8s_adc2.h
  • ADC2_PresSel_TypeDef : stm8s_adc2.h
  • ADC2_SchmittTrigg_TypeDef : stm8s_adc2.h
  • AWU_Timebase_TypeDef : stm8s_awu.h


STM8S/A Standard Peripherals Drivers: Globals

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- b -

  • BEEP_Frequency_TypeDef : stm8s_beep.h
  • bool : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- c -

  • CAN_BitSeg1_TypeDef : stm8s_can.h
  • CAN_BitSeg2_TypeDef : stm8s_can.h
  • CAN_ErrorCode_TypeDef : stm8s_can.h
  • CAN_FilterMode_TypeDef : stm8s_can.h
  • CAN_FilterNumber_TypeDef : stm8s_can.h
  • CAN_FilterScale_TypeDef : stm8s_can.h
  • CAN_FLAG_TypeDef : stm8s_can.h
  • CAN_Id_TypeDef : stm8s_can.h
  • CAN_InitStatus_TypeDef : stm8s_can.h
  • CAN_IT_TypeDef : stm8s_can.h
  • CAN_MasterCtrl_TypeDef : stm8s_can.h
  • CAN_Mode_TypeDef : stm8s_can.h
  • CAN_ModeStatus_TypeDef : stm8s_can.h
  • CAN_NbrPendingMessage_TypeDef : stm8s_can.h
  • CAN_OperatingMode_TypeDef : stm8s_can.h
  • CAN_Page_TypeDef : stm8s_can.h
  • CAN_RTR_TypeDef : stm8s_can.h
  • CAN_Sleep_TypeDef : stm8s_can.h
  • CAN_ST7Compatibility_TypeDef : stm8s_can.h
  • CAN_SynJumpWidth_TypeDef : stm8s_can.h
  • CAN_TransmitMailBox_TypeDef : stm8s_can.h
  • CAN_TxStatus_TypeDef : stm8s_can.h
  • CAN_WakeUp_TypeDef : stm8s_can.h
  • CLK_CSSConfig_TypeDef : stm8s_clk.h
  • CLK_CurrentClockState_TypeDef : stm8s_clk.h
  • CLK_Flag_TypeDef : stm8s_clk.h
  • CLK_HSITrimValue_TypeDef : stm8s_clk.h
  • CLK_IT_TypeDef : stm8s_clk.h
  • CLK_Output_TypeDef : stm8s_clk.h
  • CLK_Peripheral_TypeDef : stm8s_clk.h
  • CLK_Prescaler_TypeDef : stm8s_clk.h
  • CLK_Source_TypeDef : stm8s_clk.h
  • CLK_SWIMDivider_TypeDef : stm8s_clk.h
  • CLK_SwitchMode_TypeDef : stm8s_clk.h


STM8S/A Standard Peripherals Drivers: Globals

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- e -

  • ErrorStatus : stm8s.h
  • EXTI_Port_TypeDef : stm8s_exti.h
  • EXTI_Sensitivity_TypeDef : stm8s_exti.h
  • EXTI_TLISensitivity_TypeDef : stm8s_exti.h


STM8S/A Standard Peripherals Drivers: Globals

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- f -

  • FlagStatus : stm8s.h
  • FLASH_Flag_TypeDef : stm8s_flash.h
  • FLASH_LPMode_TypeDef : stm8s_flash.h
  • FLASH_MemType_TypeDef : stm8s_flash.h
  • FLASH_ProgramMode_TypeDef : stm8s_flash.h
  • FLASH_ProgramTime_TypeDef : stm8s_flash.h
  • FLASH_Status_TypeDef : stm8s_flash.h
  • FunctionalState : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- g -

  • GPIO_Mode_TypeDef : stm8s_gpio.h
  • GPIO_Pin_TypeDef : stm8s_gpio.h


STM8S/A Standard Peripherals Drivers: Globals

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- i -

  • I2C_Ack_TypeDef : stm8s_i2c.h
  • I2C_AddMode_TypeDef : stm8s_i2c.h
  • I2C_Direction_TypeDef : stm8s_i2c.h
  • I2C_DutyCycle_TypeDef : stm8s_i2c.h
  • I2C_Event_TypeDef : stm8s_i2c.h
  • I2C_Flag_TypeDef : stm8s_i2c.h
  • I2C_IT_TypeDef : stm8s_i2c.h
  • I2C_ITPendingBit_TypeDef : stm8s_i2c.h
  • ITC_Irq_TypeDef : stm8s_itc.h
  • ITC_PriorityLevel_TypeDef : stm8s_itc.h
  • IWDG_Prescaler_TypeDef : stm8s_iwdg.h
  • IWDG_WriteAccess_TypeDef : stm8s_iwdg.h


STM8S/A Standard Peripherals Drivers: Globals

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- r -

  • RST_Flag_TypeDef : stm8s_rst.h


STM8S/A Standard Peripherals Drivers: Globals

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- s -

  • SPI_BaudRatePrescaler_TypeDef : stm8s_spi.h
  • SPI_ClockPhase_TypeDef : stm8s_spi.h
  • SPI_ClockPolarity_TypeDef : stm8s_spi.h
  • SPI_CRC_TypeDef : stm8s_spi.h
  • SPI_DataDirection_TypeDef : stm8s_spi.h
  • SPI_Direction_TypeDef : stm8s_spi.h
  • SPI_FirstBit_TypeDef : stm8s_spi.h
  • SPI_Flag_TypeDef : stm8s_spi.h
  • SPI_IT_TypeDef : stm8s_spi.h
  • SPI_Mode_TypeDef : stm8s_spi.h
  • SPI_NSS_TypeDef : stm8s_spi.h


STM8S/A Standard Peripherals Drivers: Globals

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- t -

  • TIM1_AutomaticOutput_TypeDef : stm8s_tim1.h
  • TIM1_BreakPolarity_TypeDef : stm8s_tim1.h
  • TIM1_BreakState_TypeDef : stm8s_tim1.h
  • TIM1_Channel_TypeDef : stm8s_tim1.h
  • TIM1_CounterMode_TypeDef : stm8s_tim1.h
  • TIM1_EncoderMode_TypeDef : stm8s_tim1.h
  • TIM1_EventSource_TypeDef : stm8s_tim1.h
  • TIM1_ExtTRGPolarity_TypeDef : stm8s_tim1.h
  • TIM1_ExtTRGPSC_TypeDef : stm8s_tim1.h
  • TIM1_FLAG_TypeDef : stm8s_tim1.h
  • TIM1_ForcedAction_TypeDef : stm8s_tim1.h
  • TIM1_ICPolarity_TypeDef : stm8s_tim1.h
  • TIM1_ICPSC_TypeDef : stm8s_tim1.h
  • TIM1_ICSelection_TypeDef : stm8s_tim1.h
  • TIM1_IT_TypeDef : stm8s_tim1.h
  • TIM1_LockLevel_TypeDef : stm8s_tim1.h
  • TIM1_OCIdleState_TypeDef : stm8s_tim1.h
  • TIM1_OCMode_TypeDef : stm8s_tim1.h
  • TIM1_OCNIdleState_TypeDef : stm8s_tim1.h
  • TIM1_OCNPolarity_TypeDef : stm8s_tim1.h
  • TIM1_OCPolarity_TypeDef : stm8s_tim1.h
  • TIM1_OPMode_TypeDef : stm8s_tim1.h
  • TIM1_OSSIState_TypeDef : stm8s_tim1.h
  • TIM1_OutputNState_TypeDef : stm8s_tim1.h
  • TIM1_OutputState_TypeDef : stm8s_tim1.h
  • TIM1_PSCReloadMode_TypeDef : stm8s_tim1.h
  • TIM1_SlaveMode_TypeDef : stm8s_tim1.h
  • TIM1_TIxExternalCLK1Source_TypeDef : stm8s_tim1.h
  • TIM1_TRGOSource_TypeDef : stm8s_tim1.h
  • TIM1_TS_TypeDef : stm8s_tim1.h
  • TIM1_UpdateSource_TypeDef : stm8s_tim1.h
  • TIM2_Channel_TypeDef : stm8s_tim2.h
  • TIM2_EventSource_TypeDef : stm8s_tim2.h
  • TIM2_FLAG_TypeDef : stm8s_tim2.h
  • TIM2_ForcedAction_TypeDef : stm8s_tim2.h
  • TIM2_ICPolarity_TypeDef : stm8s_tim2.h
  • TIM2_ICPSC_TypeDef : stm8s_tim2.h
  • TIM2_ICSelection_TypeDef : stm8s_tim2.h
  • TIM2_IT_TypeDef : stm8s_tim2.h
  • TIM2_OCMode_TypeDef : stm8s_tim2.h
  • TIM2_OCPolarity_TypeDef : stm8s_tim2.h
  • TIM2_OPMode_TypeDef : stm8s_tim2.h
  • TIM2_OutputState_TypeDef : stm8s_tim2.h
  • TIM2_Prescaler_TypeDef : stm8s_tim2.h
  • TIM2_PSCReloadMode_TypeDef : stm8s_tim2.h
  • TIM2_UpdateSource_TypeDef : stm8s_tim2.h
  • TIM3_Channel_TypeDef : stm8s_tim3.h
  • TIM3_EventSource_TypeDef : stm8s_tim3.h
  • TIM3_FLAG_TypeDef : stm8s_tim3.h
  • TIM3_ForcedAction_TypeDef : stm8s_tim3.h
  • TIM3_ICPolarity_TypeDef : stm8s_tim3.h
  • TIM3_ICPSC_TypeDef : stm8s_tim3.h
  • TIM3_ICSelection_TypeDef : stm8s_tim3.h
  • TIM3_IT_TypeDef : stm8s_tim3.h
  • TIM3_OCMode_TypeDef : stm8s_tim3.h
  • TIM3_OCPolarity_TypeDef : stm8s_tim3.h
  • TIM3_OPMode_TypeDef : stm8s_tim3.h
  • TIM3_OutputState_TypeDef : stm8s_tim3.h
  • TIM3_Prescaler_TypeDef : stm8s_tim3.h
  • TIM3_PSCReloadMode_TypeDef : stm8s_tim3.h
  • TIM3_UpdateSource_TypeDef : stm8s_tim3.h
  • TIM4_EventSource_TypeDef : stm8s_tim4.h
  • TIM4_FLAG_TypeDef : stm8s_tim4.h
  • TIM4_IT_TypeDef : stm8s_tim4.h
  • TIM4_OPMode_TypeDef : stm8s_tim4.h
  • TIM4_Prescaler_TypeDef : stm8s_tim4.h
  • TIM4_PSCReloadMode_TypeDef : stm8s_tim4.h
  • TIM4_UpdateSource_TypeDef : stm8s_tim4.h
  • TIM5_Channel_TypeDef : stm8s_tim5.h
  • TIM5_EncoderMode_TypeDef : stm8s_tim5.h
  • TIM5_EventSource_TypeDef : stm8s_tim5.h
  • TIM5_ExtTRGPolarity_TypeDef : stm8s_tim5.h
  • TIM5_ExtTRGPSC_TypeDef : stm8s_tim5.h
  • TIM5_FLAG_TypeDef : stm8s_tim5.h
  • TIM5_ForcedAction_TypeDef : stm8s_tim5.h
  • TIM5_ICPolarity_TypeDef : stm8s_tim5.h
  • TIM5_ICPSC_TypeDef : stm8s_tim5.h
  • TIM5_ICSelection_TypeDef : stm8s_tim5.h
  • TIM5_IT_TypeDef : stm8s_tim5.h
  • TIM5_OCMode_TypeDef : stm8s_tim5.h
  • TIM5_OCPolarity_TypeDef : stm8s_tim5.h
  • TIM5_OPMode_TypeDef : stm8s_tim5.h
  • TIM5_OutputState_TypeDef : stm8s_tim5.h
  • TIM5_Prescaler_TypeDef : stm8s_tim5.h
  • TIM5_PSCReloadMode_TypeDef : stm8s_tim5.h
  • TIM5_SlaveMode_TypeDef : stm8s_tim5.h
  • TIM5_TRGOSource_TypeDef : stm8s_tim5.h
  • TIM5_TS_TypeDef : stm8s_tim5.h
  • TIM5_UpdateSource_TypeDef : stm8s_tim5.h
  • TIM6_EventSource_TypeDef : stm8s_tim6.h
  • TIM6_FLAG_TypeDef : stm8s_tim6.h
  • TIM6_IT_TypeDef : stm8s_tim6.h
  • TIM6_OPMode_TypeDef : stm8s_tim6.h
  • TIM6_Prescaler_TypeDef : stm8s_tim6.h
  • TIM6_PSCReloadMode_TypeDef : stm8s_tim6.h
  • TIM6_SlaveMode_TypeDef : stm8s_tim6.h
  • TIM6_TRGOSource_TypeDef : stm8s_tim6.h
  • TIM6_TS_TypeDef : stm8s_tim6.h
  • TIM6_UpdateSource_TypeDef : stm8s_tim6.h


STM8S/A Standard Peripherals Drivers: Globals

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- u -

  • UART1_Flag_TypeDef : stm8s_uart1.h
  • UART1_IrDAMode_TypeDef : stm8s_uart1.h
  • UART1_IT_TypeDef : stm8s_uart1.h
  • UART1_LINBreakDetectionLength_TypeDef : stm8s_uart1.h
  • UART1_Mode_TypeDef : stm8s_uart1.h
  • UART1_Parity_TypeDef : stm8s_uart1.h
  • UART1_StopBits_TypeDef : stm8s_uart1.h
  • UART1_SyncMode_TypeDef : stm8s_uart1.h
  • UART1_WakeUp_TypeDef : stm8s_uart1.h
  • UART1_WordLength_TypeDef : stm8s_uart1.h
  • UART2_Flag_TypeDef : stm8s_uart2.h
  • UART2_IrDAMode_TypeDef : stm8s_uart2.h
  • UART2_IT_TypeDef : stm8s_uart2.h
  • UART2_LinAutosync_TypeDef : stm8s_uart2.h
  • UART2_LINBreakDetectionLength_TypeDef : stm8s_uart2.h
  • UART2_LinDivUp_TypeDef : stm8s_uart2.h
  • UART2_LinMode_TypeDef : stm8s_uart2.h
  • UART2_Mode_TypeDef : stm8s_uart2.h
  • UART2_Parity_TypeDef : stm8s_uart2.h
  • UART2_StopBits_TypeDef : stm8s_uart2.h
  • UART2_SyncMode_TypeDef : stm8s_uart2.h
  • UART2_WakeUp_TypeDef : stm8s_uart2.h
  • UART2_WordLength_TypeDef : stm8s_uart2.h
  • UART3_Flag_TypeDef : stm8s_uart3.h
  • UART3_IT_TypeDef : stm8s_uart3.h
  • UART3_LinAutosync_TypeDef : stm8s_uart3.h
  • UART3_LINBreakDetectionLength_TypeDef : stm8s_uart3.h
  • UART3_LinDivUp_TypeDef : stm8s_uart3.h
  • UART3_LinMode_TypeDef : stm8s_uart3.h
  • UART3_Mode_TypeDef : stm8s_uart3.h
  • UART3_Parity_TypeDef : stm8s_uart3.h
  • UART3_StopBits_TypeDef : stm8s_uart3.h
  • UART3_WakeUp_TypeDef : stm8s_uart3.h
  • UART3_WordLength_TypeDef : stm8s_uart3.h


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- a -

  • ADC1_ALIGN_LEFT : stm8s_adc1.h
  • ADC1_ALIGN_RIGHT : stm8s_adc1.h
  • ADC1_CHANNEL_0 : stm8s_adc1.h
  • ADC1_CHANNEL_1 : stm8s_adc1.h
  • ADC1_CHANNEL_12 : stm8s_adc1.h
  • ADC1_CHANNEL_2 : stm8s_adc1.h
  • ADC1_CHANNEL_3 : stm8s_adc1.h
  • ADC1_CHANNEL_4 : stm8s_adc1.h
  • ADC1_CHANNEL_5 : stm8s_adc1.h
  • ADC1_CHANNEL_6 : stm8s_adc1.h
  • ADC1_CHANNEL_7 : stm8s_adc1.h
  • ADC1_CHANNEL_8 : stm8s_adc1.h
  • ADC1_CHANNEL_9 : stm8s_adc1.h
  • ADC1_CONVERSIONMODE_CONTINUOUS : stm8s_adc1.h
  • ADC1_CONVERSIONMODE_SINGLE : stm8s_adc1.h
  • ADC1_EXTTRIG_GPIO : stm8s_adc1.h
  • ADC1_EXTTRIG_TIM : stm8s_adc1.h
  • ADC1_FLAG_AWD : stm8s_adc1.h
  • ADC1_FLAG_AWS0 : stm8s_adc1.h
  • ADC1_FLAG_AWS1 : stm8s_adc1.h
  • ADC1_FLAG_AWS12 : stm8s_adc1.h
  • ADC1_FLAG_AWS2 : stm8s_adc1.h
  • ADC1_FLAG_AWS3 : stm8s_adc1.h
  • ADC1_FLAG_AWS4 : stm8s_adc1.h
  • ADC1_FLAG_AWS5 : stm8s_adc1.h
  • ADC1_FLAG_AWS6 : stm8s_adc1.h
  • ADC1_FLAG_AWS7 : stm8s_adc1.h
  • ADC1_FLAG_AWS8 : stm8s_adc1.h
  • ADC1_FLAG_AWS9 : stm8s_adc1.h
  • ADC1_FLAG_EOC : stm8s_adc1.h
  • ADC1_FLAG_OVR : stm8s_adc1.h
  • ADC1_IT_AWD : stm8s_adc1.h
  • ADC1_IT_AWDIE : stm8s_adc1.h
  • ADC1_IT_AWS0 : stm8s_adc1.h
  • ADC1_IT_AWS1 : stm8s_adc1.h
  • ADC1_IT_AWS12 : stm8s_adc1.h
  • ADC1_IT_AWS2 : stm8s_adc1.h
  • ADC1_IT_AWS3 : stm8s_adc1.h
  • ADC1_IT_AWS4 : stm8s_adc1.h
  • ADC1_IT_AWS5 : stm8s_adc1.h
  • ADC1_IT_AWS6 : stm8s_adc1.h
  • ADC1_IT_AWS7 : stm8s_adc1.h
  • ADC1_IT_AWS8 : stm8s_adc1.h
  • ADC1_IT_AWS9 : stm8s_adc1.h
  • ADC1_IT_EOC : stm8s_adc1.h
  • ADC1_IT_EOCIE : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D10 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D12 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D18 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D2 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D3 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D4 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D6 : stm8s_adc1.h
  • ADC1_PRESSEL_FCPU_D8 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_ALL : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL0 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL1 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL12 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL2 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL3 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL4 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL5 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL6 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL7 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL8 : stm8s_adc1.h
  • ADC1_SCHMITTTRIG_CHANNEL9 : stm8s_adc1.h
  • ADC2_ALIGN_LEFT : stm8s_adc2.h
  • ADC2_ALIGN_RIGHT : stm8s_adc2.h
  • ADC2_CHANNEL_0 : stm8s_adc2.h
  • ADC2_CHANNEL_1 : stm8s_adc2.h
  • ADC2_CHANNEL_10 : stm8s_adc2.h
  • ADC2_CHANNEL_11 : stm8s_adc2.h
  • ADC2_CHANNEL_12 : stm8s_adc2.h
  • ADC2_CHANNEL_13 : stm8s_adc2.h
  • ADC2_CHANNEL_14 : stm8s_adc2.h
  • ADC2_CHANNEL_15 : stm8s_adc2.h
  • ADC2_CHANNEL_2 : stm8s_adc2.h
  • ADC2_CHANNEL_3 : stm8s_adc2.h
  • ADC2_CHANNEL_4 : stm8s_adc2.h
  • ADC2_CHANNEL_5 : stm8s_adc2.h
  • ADC2_CHANNEL_6 : stm8s_adc2.h
  • ADC2_CHANNEL_7 : stm8s_adc2.h
  • ADC2_CHANNEL_8 : stm8s_adc2.h
  • ADC2_CHANNEL_9 : stm8s_adc2.h
  • ADC2_CONVERSIONMODE_CONTINUOUS : stm8s_adc2.h
  • ADC2_CONVERSIONMODE_SINGLE : stm8s_adc2.h
  • ADC2_EXTTRIG_GPIO : stm8s_adc2.h
  • ADC2_EXTTRIG_TIM : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D10 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D12 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D18 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D2 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D3 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D4 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D6 : stm8s_adc2.h
  • ADC2_PRESSEL_FCPU_D8 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_ALL : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL0 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL1 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL10 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL11 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL12 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL13 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL14 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL15 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL2 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL3 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL4 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL5 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL6 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL7 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL8 : stm8s_adc2.h
  • ADC2_SCHMITTTRIG_CHANNEL9 : stm8s_adc2.h
  • AWU_TIMEBASE_128MS : stm8s_awu.h
  • AWU_TIMEBASE_12S : stm8s_awu.h
  • AWU_TIMEBASE_16MS : stm8s_awu.h
  • AWU_TIMEBASE_1MS : stm8s_awu.h
  • AWU_TIMEBASE_1S : stm8s_awu.h
  • AWU_TIMEBASE_250US : stm8s_awu.h
  • AWU_TIMEBASE_256MS : stm8s_awu.h
  • AWU_TIMEBASE_2MS : stm8s_awu.h
  • AWU_TIMEBASE_2S : stm8s_awu.h
  • AWU_TIMEBASE_30S : stm8s_awu.h
  • AWU_TIMEBASE_32MS : stm8s_awu.h
  • AWU_TIMEBASE_4MS : stm8s_awu.h
  • AWU_TIMEBASE_500US : stm8s_awu.h
  • AWU_TIMEBASE_512MS : stm8s_awu.h
  • AWU_TIMEBASE_64MS : stm8s_awu.h
  • AWU_TIMEBASE_8MS : stm8s_awu.h
  • AWU_TIMEBASE_NO_IT : stm8s_awu.h


STM8S/A Standard Peripherals Drivers: Globals

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- b -

  • BEEP_FREQUENCY_1KHZ : stm8s_beep.h
  • BEEP_FREQUENCY_2KHZ : stm8s_beep.h
  • BEEP_FREQUENCY_4KHZ : stm8s_beep.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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- c -

  • CAN_BitSeg1_10TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_11TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_12TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_13TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_14TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_15TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_16TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_1TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_2TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_3TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_4TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_5TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_6TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_7TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_8TimeQuantum : stm8s_can.h
  • CAN_BitSeg1_9TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_1TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_2TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_3TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_4TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_5TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_6TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_7TimeQuantum : stm8s_can.h
  • CAN_BitSeg2_8TimeQuantum : stm8s_can.h
  • CAN_ErrorCode_ACKErr : stm8s_can.h
  • CAN_ErrorCode_BitDominantErr : stm8s_can.h
  • CAN_ErrorCode_BitRecessiveErr : stm8s_can.h
  • CAN_ErrorCode_CRCErr : stm8s_can.h
  • CAN_ErrorCode_FormErr : stm8s_can.h
  • CAN_ErrorCode_NoErr : stm8s_can.h
  • CAN_ErrorCode_SoftwareSetErr : stm8s_can.h
  • CAN_ErrorCode_StuffErr : stm8s_can.h
  • CAN_FilterMode_IdList : stm8s_can.h
  • CAN_FilterMode_IdList_IdMask : stm8s_can.h
  • CAN_FilterMode_IdMask : stm8s_can.h
  • CAN_FilterMode_IdMask_IdList : stm8s_can.h
  • CAN_FilterNumber_0 : stm8s_can.h
  • CAN_FilterNumber_1 : stm8s_can.h
  • CAN_FilterNumber_2 : stm8s_can.h
  • CAN_FilterNumber_3 : stm8s_can.h
  • CAN_FilterNumber_4 : stm8s_can.h
  • CAN_FilterNumber_5 : stm8s_can.h
  • CAN_FilterScale_16_8Bit : stm8s_can.h
  • CAN_FilterScale_16Bit : stm8s_can.h
  • CAN_FilterScale_32Bit : stm8s_can.h
  • CAN_FilterScale_8Bit : stm8s_can.h
  • CAN_FLAG_BOF : stm8s_can.h
  • CAN_FLAG_EPV : stm8s_can.h
  • CAN_FLAG_EWG : stm8s_can.h
  • CAN_FLAG_FF : stm8s_can.h
  • CAN_FLAG_FMP : stm8s_can.h
  • CAN_FLAG_FOV : stm8s_can.h
  • CAN_FLAG_LEC : stm8s_can.h
  • CAN_FLAG_RQCP0 : stm8s_can.h
  • CAN_FLAG_RQCP1 : stm8s_can.h
  • CAN_FLAG_RQCP2 : stm8s_can.h
  • CAN_FLAG_WKU : stm8s_can.h
  • CAN_Id_Extended : stm8s_can.h
  • CAN_Id_Standard : stm8s_can.h
  • CAN_InitStatus_Failed : stm8s_can.h
  • CAN_InitStatus_Success : stm8s_can.h
  • CAN_IT_BOF : stm8s_can.h
  • CAN_IT_EPV : stm8s_can.h
  • CAN_IT_ERR : stm8s_can.h
  • CAN_IT_EWG : stm8s_can.h
  • CAN_IT_FF : stm8s_can.h
  • CAN_IT_FMP : stm8s_can.h
  • CAN_IT_FOV : stm8s_can.h
  • CAN_IT_LEC : stm8s_can.h
  • CAN_IT_TME : stm8s_can.h
  • CAN_IT_WKU : stm8s_can.h
  • CAN_MasterCtrl_AllDisabled : stm8s_can.h
  • CAN_MasterCtrl_AllEnabled : stm8s_can.h
  • CAN_MasterCtrl_AutoBusOffManagement : stm8s_can.h
  • CAN_MasterCtrl_AutoWakeUpMode : stm8s_can.h
  • CAN_MasterCtrl_NoAutoReTx : stm8s_can.h
  • CAN_MasterCtrl_RxFifoLockedMode : stm8s_can.h
  • CAN_MasterCtrl_TimeTriggerCOMMode : stm8s_can.h
  • CAN_MasterCtrl_TxFifoPriority : stm8s_can.h
  • CAN_Mode_LoopBack : stm8s_can.h
  • CAN_Mode_Normal : stm8s_can.h
  • CAN_Mode_Silent : stm8s_can.h
  • CAN_Mode_Silent_LoopBack : stm8s_can.h
  • CAN_ModeStatus_Failed : stm8s_can.h
  • CAN_ModeStatus_Success : stm8s_can.h
  • CAN_NbrPendingMessage_0 : stm8s_can.h
  • CAN_NbrPendingMessage_1 : stm8s_can.h
  • CAN_NbrPendingMessage_2 : stm8s_can.h
  • CAN_NbrPendingMessage_3 : stm8s_can.h
  • CAN_OperatingMode_Initialization : stm8s_can.h
  • CAN_OperatingMode_Normal : stm8s_can.h
  • CAN_OperatingMode_Sleep : stm8s_can.h
  • CAN_Page_Config : stm8s_can.h
  • CAN_Page_Filter01 : stm8s_can.h
  • CAN_Page_Filter23 : stm8s_can.h
  • CAN_Page_Filter45 : stm8s_can.h
  • CAN_Page_RxFifo : stm8s_can.h
  • CAN_Page_TxMailBox0 : stm8s_can.h
  • CAN_Page_TxMailBox1 : stm8s_can.h
  • CAN_Page_TxMailBox2 : stm8s_can.h
  • CAN_RTR_Data : stm8s_can.h
  • CAN_RTR_Remote : stm8s_can.h
  • CAN_Sleep_Failed : stm8s_can.h
  • CAN_Sleep_Ok : stm8s_can.h
  • CAN_ST7Compatibility_Disable : stm8s_can.h
  • CAN_ST7Compatibility_Enable : stm8s_can.h
  • CAN_SynJumpWidth_1TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_2TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_3TimeQuantum : stm8s_can.h
  • CAN_SynJumpWidth_4TimeQuantum : stm8s_can.h
  • CAN_TransmitMailBox_0 : stm8s_can.h
  • CAN_TransmitMailBox_1 : stm8s_can.h
  • CAN_TransmitMailBox_2 : stm8s_can.h
  • CAN_TxStatus_Failed : stm8s_can.h
  • CAN_TxStatus_MailBox0Ok : stm8s_can.h
  • CAN_TxStatus_MailBox1Ok : stm8s_can.h
  • CAN_TxStatus_MailBox2Ok : stm8s_can.h
  • CAN_TxStatus_MailBoxEmpty : stm8s_can.h
  • CAN_TxStatus_NoMailBox : stm8s_can.h
  • CAN_TxStatus_Ok : stm8s_can.h
  • CAN_TxStatus_Pending : stm8s_can.h
  • CAN_WakeUp_Failed : stm8s_can.h
  • CAN_WakeUp_Ok : stm8s_can.h
  • CLK_CSSCONFIG_DISABLE : stm8s_clk.h
  • CLK_CSSCONFIG_ENABLE : stm8s_clk.h
  • CLK_CSSCONFIG_ENABLEWITHIT : stm8s_clk.h
  • CLK_CURRENTCLOCKSTATE_DISABLE : stm8s_clk.h
  • CLK_CURRENTCLOCKSTATE_ENABLE : stm8s_clk.h
  • CLK_FLAG_AUX : stm8s_clk.h
  • CLK_FLAG_CCOBSY : stm8s_clk.h
  • CLK_FLAG_CCORDY : stm8s_clk.h
  • CLK_FLAG_CSSD : stm8s_clk.h
  • CLK_FLAG_HSERDY : stm8s_clk.h
  • CLK_FLAG_HSIRDY : stm8s_clk.h
  • CLK_FLAG_LSIRDY : stm8s_clk.h
  • CLK_FLAG_SWBSY : stm8s_clk.h
  • CLK_FLAG_SWIF : stm8s_clk.h
  • CLK_HSITRIMVALUE_0 : stm8s_clk.h
  • CLK_HSITRIMVALUE_1 : stm8s_clk.h
  • CLK_HSITRIMVALUE_2 : stm8s_clk.h
  • CLK_HSITRIMVALUE_3 : stm8s_clk.h
  • CLK_HSITRIMVALUE_4 : stm8s_clk.h
  • CLK_HSITRIMVALUE_5 : stm8s_clk.h
  • CLK_HSITRIMVALUE_6 : stm8s_clk.h
  • CLK_HSITRIMVALUE_7 : stm8s_clk.h
  • CLK_IT_CSSD : stm8s_clk.h
  • CLK_IT_SWIF : stm8s_clk.h
  • CLK_OUTPUT_CPU : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV16 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV2 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV32 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV4 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV64 : stm8s_clk.h
  • CLK_OUTPUT_CPUDIV8 : stm8s_clk.h
  • CLK_OUTPUT_HSE : stm8s_clk.h
  • CLK_OUTPUT_HSI : stm8s_clk.h
  • CLK_OUTPUT_HSIRC : stm8s_clk.h
  • CLK_OUTPUT_LSI : stm8s_clk.h
  • CLK_OUTPUT_MASTER : stm8s_clk.h
  • CLK_OUTPUT_OTHERS : stm8s_clk.h
  • CLK_PERIPHERAL_ADC : stm8s_clk.h
  • CLK_PERIPHERAL_AWU : stm8s_clk.h
  • CLK_PERIPHERAL_CAN : stm8s_clk.h
  • CLK_PERIPHERAL_I2C : stm8s_clk.h
  • CLK_PERIPHERAL_SPI : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER1 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER2 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER3 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER4 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER5 : stm8s_clk.h
  • CLK_PERIPHERAL_TIMER6 : stm8s_clk.h
  • CLK_PERIPHERAL_UART1 : stm8s_clk.h
  • CLK_PERIPHERAL_UART2 : stm8s_clk.h
  • CLK_PERIPHERAL_UART3 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV1 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV128 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV16 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV2 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV32 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV4 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV64 : stm8s_clk.h
  • CLK_PRESCALER_CPUDIV8 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV1 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV2 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV4 : stm8s_clk.h
  • CLK_PRESCALER_HSIDIV8 : stm8s_clk.h
  • CLK_SOURCE_HSE : stm8s_clk.h
  • CLK_SOURCE_HSI : stm8s_clk.h
  • CLK_SOURCE_LSI : stm8s_clk.h
  • CLK_SWIMDIVIDER_2 : stm8s_clk.h
  • CLK_SWIMDIVIDER_OTHER : stm8s_clk.h
  • CLK_SWITCHMODE_AUTO : stm8s_clk.h
  • CLK_SWITCHMODE_MANUAL : stm8s_clk.h


STM8S/A Standard Peripherals Drivers: Globals

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- d -

  • DISABLE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- e -

  • ENABLE : stm8s.h
  • ERROR : stm8s.h
  • EXTI_PORT_GPIOA : stm8s_exti.h
  • EXTI_PORT_GPIOB : stm8s_exti.h
  • EXTI_PORT_GPIOC : stm8s_exti.h
  • EXTI_PORT_GPIOD : stm8s_exti.h
  • EXTI_PORT_GPIOE : stm8s_exti.h
  • EXTI_SENSITIVITY_FALL_LOW : stm8s_exti.h
  • EXTI_SENSITIVITY_FALL_ONLY : stm8s_exti.h
  • EXTI_SENSITIVITY_RISE_FALL : stm8s_exti.h
  • EXTI_SENSITIVITY_RISE_ONLY : stm8s_exti.h
  • EXTI_TLISENSITIVITY_FALL_ONLY : stm8s_exti.h
  • EXTI_TLISENSITIVITY_RISE_ONLY : stm8s_exti.h


STM8S/A Standard Peripherals Drivers: Globals

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- f -

  • FALSE : stm8s.h
  • FLASH_FLAG_DUL : stm8s_flash.h
  • FLASH_FLAG_EOP : stm8s_flash.h
  • FLASH_FLAG_PUL : stm8s_flash.h
  • FLASH_FLAG_WR_PG_DIS : stm8s_flash.h
  • FLASH_LPMODE_POWERDOWN : stm8s_flash.h
  • FLASH_LPMODE_POWERDOWN_STANDBY : stm8s_flash.h
  • FLASH_LPMODE_STANDBY : stm8s_flash.h
  • FLASH_LPMODE_STANDBY_POWERDOWN : stm8s_flash.h
  • FLASH_MEMTYPE_DATA : stm8s_flash.h
  • FLASH_MEMTYPE_PROG : stm8s_flash.h
  • FLASH_PROGRAMMODE_FAST : stm8s_flash.h
  • FLASH_PROGRAMMODE_STANDARD : stm8s_flash.h
  • FLASH_PROGRAMTIME_STANDARD : stm8s_flash.h
  • FLASH_PROGRAMTIME_TPROG : stm8s_flash.h
  • FLASH_STATUS_SUCCESSFUL_OPERATION : stm8s_flash.h
  • FLASH_STATUS_TIMEOUT : stm8s_flash.h
  • FLASH_STATUS_WRITE_PROTECTION_ERROR : stm8s_flash.h


STM8S/A Standard Peripherals Drivers: Globals

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- g -

  • GPIO_MODE_IN_FL_IT : stm8s_gpio.h
  • GPIO_MODE_IN_FL_NO_IT : stm8s_gpio.h
  • GPIO_MODE_IN_PU_IT : stm8s_gpio.h
  • GPIO_MODE_IN_PU_NO_IT : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_HIZ_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_HIZ_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_LOW_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_OD_LOW_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_HIGH_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_HIGH_SLOW : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_LOW_FAST : stm8s_gpio.h
  • GPIO_MODE_OUT_PP_LOW_SLOW : stm8s_gpio.h
  • GPIO_PIN_0 : stm8s_gpio.h
  • GPIO_PIN_1 : stm8s_gpio.h
  • GPIO_PIN_2 : stm8s_gpio.h
  • GPIO_PIN_3 : stm8s_gpio.h
  • GPIO_PIN_4 : stm8s_gpio.h
  • GPIO_PIN_5 : stm8s_gpio.h
  • GPIO_PIN_6 : stm8s_gpio.h
  • GPIO_PIN_7 : stm8s_gpio.h
  • GPIO_PIN_ALL : stm8s_gpio.h
  • GPIO_PIN_HNIB : stm8s_gpio.h
  • GPIO_PIN_LNIB : stm8s_gpio.h


STM8S/A Standard Peripherals Drivers: Globals

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- i -

  • I2C_ACK_CURR : stm8s_i2c.h
  • I2C_ACK_NEXT : stm8s_i2c.h
  • I2C_ACK_NONE : stm8s_i2c.h
  • I2C_ADDMODE_10BIT : stm8s_i2c.h
  • I2C_ADDMODE_7BIT : stm8s_i2c.h
  • I2C_DIRECTION_RX : stm8s_i2c.h
  • I2C_DIRECTION_TX : stm8s_i2c.h
  • I2C_DUTYCYCLE_16_9 : stm8s_i2c.h
  • I2C_DUTYCYCLE_2 : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_RECEIVED : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : stm8s_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : stm8s_i2c.h
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : stm8s_i2c.h
  • I2C_EVENT_MASTER_MODE_SELECT : stm8s_i2c.h
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : stm8s_i2c.h
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_ACK_FAILURE : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTING : stm8s_i2c.h
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_STOP_DETECTED : stm8s_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : stm8s_i2c.h
  • I2C_FLAG_ACKNOWLEDGEFAILURE : stm8s_i2c.h
  • I2C_FLAG_ADDRESSSENTMATCHED : stm8s_i2c.h
  • I2C_FLAG_ARBITRATIONLOSS : stm8s_i2c.h
  • I2C_FLAG_BUSBUSY : stm8s_i2c.h
  • I2C_FLAG_BUSERROR : stm8s_i2c.h
  • I2C_FLAG_GENERALCALL : stm8s_i2c.h
  • I2C_FLAG_HEADERSENT : stm8s_i2c.h
  • I2C_FLAG_MASTERSLAVE : stm8s_i2c.h
  • I2C_FLAG_OVERRUNUNDERRUN : stm8s_i2c.h
  • I2C_FLAG_RXNOTEMPTY : stm8s_i2c.h
  • I2C_FLAG_STARTDETECTION : stm8s_i2c.h
  • I2C_FLAG_STOPDETECTION : stm8s_i2c.h
  • I2C_FLAG_TRANSFERFINISHED : stm8s_i2c.h
  • I2C_FLAG_TRANSMITTERRECEIVER : stm8s_i2c.h
  • I2C_FLAG_TXEMPTY : stm8s_i2c.h
  • I2C_FLAG_WAKEUPFROMHALT : stm8s_i2c.h
  • I2C_IT_BUF : stm8s_i2c.h
  • I2C_IT_ERR : stm8s_i2c.h
  • I2C_IT_EVT : stm8s_i2c.h
  • I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE : stm8s_i2c.h
  • I2C_ITPENDINGBIT_ADDRESSSENTMATCHED : stm8s_i2c.h
  • I2C_ITPENDINGBIT_ARBITRATIONLOSS : stm8s_i2c.h
  • I2C_ITPENDINGBIT_BUSERROR : stm8s_i2c.h
  • I2C_ITPENDINGBIT_HEADERSENT : stm8s_i2c.h
  • I2C_ITPENDINGBIT_OVERRUNUNDERRUN : stm8s_i2c.h
  • I2C_ITPENDINGBIT_RXNOTEMPTY : stm8s_i2c.h
  • I2C_ITPENDINGBIT_STARTDETECTION : stm8s_i2c.h
  • I2C_ITPENDINGBIT_STOPDETECTION : stm8s_i2c.h
  • I2C_ITPENDINGBIT_TRANSFERFINISHED : stm8s_i2c.h
  • I2C_ITPENDINGBIT_TXEMPTY : stm8s_i2c.h
  • I2C_ITPENDINGBIT_WAKEUPFROMHALT : stm8s_i2c.h
  • ITC_IRQ_AWU : stm8s_itc.h
  • ITC_IRQ_CLK : stm8s_itc.h
  • ITC_IRQ_EEPROM_EEC : stm8s_itc.h
  • ITC_IRQ_I2C : stm8s_itc.h
  • ITC_IRQ_PORTA : stm8s_itc.h
  • ITC_IRQ_PORTB : stm8s_itc.h
  • ITC_IRQ_PORTC : stm8s_itc.h
  • ITC_IRQ_PORTD : stm8s_itc.h
  • ITC_IRQ_PORTE : stm8s_itc.h
  • ITC_IRQ_SPI : stm8s_itc.h
  • ITC_IRQ_TIM1_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM1_OVF : stm8s_itc.h
  • ITC_IRQ_TIM2_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM2_OVF : stm8s_itc.h
  • ITC_IRQ_TIM3_CAPCOM : stm8s_itc.h
  • ITC_IRQ_TIM3_OVF : stm8s_itc.h
  • ITC_IRQ_TIM4_OVF : stm8s_itc.h
  • ITC_IRQ_TLI : stm8s_itc.h
  • ITC_IRQ_UART1_RX : stm8s_itc.h
  • ITC_IRQ_UART1_TX : stm8s_itc.h
  • ITC_PRIORITYLEVEL_0 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_1 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_2 : stm8s_itc.h
  • ITC_PRIORITYLEVEL_3 : stm8s_itc.h
  • IWDG_Prescaler_128 : stm8s_iwdg.h
  • IWDG_Prescaler_16 : stm8s_iwdg.h
  • IWDG_Prescaler_256 : stm8s_iwdg.h
  • IWDG_Prescaler_32 : stm8s_iwdg.h
  • IWDG_Prescaler_4 : stm8s_iwdg.h
  • IWDG_Prescaler_64 : stm8s_iwdg.h
  • IWDG_Prescaler_8 : stm8s_iwdg.h
  • IWDG_WriteAccess_Disable : stm8s_iwdg.h
  • IWDG_WriteAccess_Enable : stm8s_iwdg.h


STM8S/A Standard Peripherals Drivers: Globals

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- r -

  • RESET : stm8s.h
  • RST_FLAG_EMCF : stm8s_rst.h
  • RST_FLAG_ILLOPF : stm8s_rst.h
  • RST_FLAG_IWDGF : stm8s_rst.h
  • RST_FLAG_SWIMF : stm8s_rst.h
  • RST_FLAG_WWDGF : stm8s_rst.h


STM8S/A Standard Peripherals Drivers: Globals

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- s -

  • SET : stm8s.h
  • SPI_BAUDRATEPRESCALER_128 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm8s_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm8s_spi.h
  • SPI_CLOCKPHASE_1EDGE : stm8s_spi.h
  • SPI_CLOCKPHASE_2EDGE : stm8s_spi.h
  • SPI_CLOCKPOLARITY_HIGH : stm8s_spi.h
  • SPI_CLOCKPOLARITY_LOW : stm8s_spi.h
  • SPI_CRC_RX : stm8s_spi.h
  • SPI_CRC_TX : stm8s_spi.h
  • SPI_DATADIRECTION_1LINE_RX : stm8s_spi.h
  • SPI_DATADIRECTION_1LINE_TX : stm8s_spi.h
  • SPI_DATADIRECTION_2LINES_FULLDUPLEX : stm8s_spi.h
  • SPI_DATADIRECTION_2LINES_RXONLY : stm8s_spi.h
  • SPI_DIRECTION_RX : stm8s_spi.h
  • SPI_DIRECTION_TX : stm8s_spi.h
  • SPI_FIRSTBIT_LSB : stm8s_spi.h
  • SPI_FIRSTBIT_MSB : stm8s_spi.h
  • SPI_FLAG_BSY : stm8s_spi.h
  • SPI_FLAG_CRCERR : stm8s_spi.h
  • SPI_FLAG_MODF : stm8s_spi.h
  • SPI_FLAG_OVR : stm8s_spi.h
  • SPI_FLAG_RXNE : stm8s_spi.h
  • SPI_FLAG_TXE : stm8s_spi.h
  • SPI_FLAG_WKUP : stm8s_spi.h
  • SPI_IT_CRCERR : stm8s_spi.h
  • SPI_IT_ERR : stm8s_spi.h
  • SPI_IT_MODF : stm8s_spi.h
  • SPI_IT_OVR : stm8s_spi.h
  • SPI_IT_RXNE : stm8s_spi.h
  • SPI_IT_TXE : stm8s_spi.h
  • SPI_IT_WKUP : stm8s_spi.h
  • SPI_MODE_MASTER : stm8s_spi.h
  • SPI_MODE_SLAVE : stm8s_spi.h
  • SPI_NSS_HARD : stm8s_spi.h
  • SPI_NSS_SOFT : stm8s_spi.h
  • SUCCESS : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

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- t -

  • TIM1_AUTOMATICOUTPUT_DISABLE : stm8s_tim1.h
  • TIM1_AUTOMATICOUTPUT_ENABLE : stm8s_tim1.h
  • TIM1_BREAK_DISABLE : stm8s_tim1.h
  • TIM1_BREAK_ENABLE : stm8s_tim1.h
  • TIM1_BREAKPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_BREAKPOLARITY_LOW : stm8s_tim1.h
  • TIM1_CHANNEL_1 : stm8s_tim1.h
  • TIM1_CHANNEL_2 : stm8s_tim1.h
  • TIM1_CHANNEL_3 : stm8s_tim1.h
  • TIM1_CHANNEL_4 : stm8s_tim1.h
  • TIM1_COUNTERMODE_CENTERALIGNED1 : stm8s_tim1.h
  • TIM1_COUNTERMODE_CENTERALIGNED2 : stm8s_tim1.h
  • TIM1_COUNTERMODE_CENTERALIGNED3 : stm8s_tim1.h
  • TIM1_COUNTERMODE_DOWN : stm8s_tim1.h
  • TIM1_COUNTERMODE_UP : stm8s_tim1.h
  • TIM1_ENCODERMODE_TI1 : stm8s_tim1.h
  • TIM1_ENCODERMODE_TI12 : stm8s_tim1.h
  • TIM1_ENCODERMODE_TI2 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_BREAK : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC1 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC2 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC3 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_CC4 : stm8s_tim1.h
  • TIM1_EVENTSOURCE_COM : stm8s_tim1.h
  • TIM1_EVENTSOURCE_TRIGGER : stm8s_tim1.h
  • TIM1_EVENTSOURCE_UPDATE : stm8s_tim1.h
  • TIM1_EXTTRGPOLARITY_INVERTED : stm8s_tim1.h
  • TIM1_EXTTRGPOLARITY_NONINVERTED : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV2 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV4 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_DIV8 : stm8s_tim1.h
  • TIM1_EXTTRGPSC_OFF : stm8s_tim1.h
  • TIM1_FLAG_BREAK : stm8s_tim1.h
  • TIM1_FLAG_CC1 : stm8s_tim1.h
  • TIM1_FLAG_CC1OF : stm8s_tim1.h
  • TIM1_FLAG_CC2 : stm8s_tim1.h
  • TIM1_FLAG_CC2OF : stm8s_tim1.h
  • TIM1_FLAG_CC3 : stm8s_tim1.h
  • TIM1_FLAG_CC3OF : stm8s_tim1.h
  • TIM1_FLAG_CC4 : stm8s_tim1.h
  • TIM1_FLAG_CC4OF : stm8s_tim1.h
  • TIM1_FLAG_COM : stm8s_tim1.h
  • TIM1_FLAG_TRIGGER : stm8s_tim1.h
  • TIM1_FLAG_UPDATE : stm8s_tim1.h
  • TIM1_FORCEDACTION_ACTIVE : stm8s_tim1.h
  • TIM1_FORCEDACTION_INACTIVE : stm8s_tim1.h
  • TIM1_ICPOLARITY_FALLING : stm8s_tim1.h
  • TIM1_ICPOLARITY_RISING : stm8s_tim1.h
  • TIM1_ICPSC_DIV1 : stm8s_tim1.h
  • TIM1_ICPSC_DIV2 : stm8s_tim1.h
  • TIM1_ICPSC_DIV4 : stm8s_tim1.h
  • TIM1_ICPSC_DIV8 : stm8s_tim1.h
  • TIM1_ICSELECTION_DIRECTTI : stm8s_tim1.h
  • TIM1_ICSELECTION_INDIRECTTI : stm8s_tim1.h
  • TIM1_ICSELECTION_TRGI : stm8s_tim1.h
  • TIM1_IT_BREAK : stm8s_tim1.h
  • TIM1_IT_CC1 : stm8s_tim1.h
  • TIM1_IT_CC2 : stm8s_tim1.h
  • TIM1_IT_CC3 : stm8s_tim1.h
  • TIM1_IT_CC4 : stm8s_tim1.h
  • TIM1_IT_COM : stm8s_tim1.h
  • TIM1_IT_TRIGGER : stm8s_tim1.h
  • TIM1_IT_UPDATE : stm8s_tim1.h
  • TIM1_LOCKLEVEL_1 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_2 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_3 : stm8s_tim1.h
  • TIM1_LOCKLEVEL_OFF : stm8s_tim1.h
  • TIM1_OCIDLESTATE_RESET : stm8s_tim1.h
  • TIM1_OCIDLESTATE_SET : stm8s_tim1.h
  • TIM1_OCMODE_ACTIVE : stm8s_tim1.h
  • TIM1_OCMODE_INACTIVE : stm8s_tim1.h
  • TIM1_OCMODE_PWM1 : stm8s_tim1.h
  • TIM1_OCMODE_PWM2 : stm8s_tim1.h
  • TIM1_OCMODE_TIMING : stm8s_tim1.h
  • TIM1_OCMODE_TOGGLE : stm8s_tim1.h
  • TIM1_OCNIDLESTATE_RESET : stm8s_tim1.h
  • TIM1_OCNIDLESTATE_SET : stm8s_tim1.h
  • TIM1_OCNPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_OCNPOLARITY_LOW : stm8s_tim1.h
  • TIM1_OCPOLARITY_HIGH : stm8s_tim1.h
  • TIM1_OCPOLARITY_LOW : stm8s_tim1.h
  • TIM1_OPMODE_REPETITIVE : stm8s_tim1.h
  • TIM1_OPMODE_SINGLE : stm8s_tim1.h
  • TIM1_OSSISTATE_DISABLE : stm8s_tim1.h
  • TIM1_OSSISTATE_ENABLE : stm8s_tim1.h
  • TIM1_OUTPUTNSTATE_DISABLE : stm8s_tim1.h
  • TIM1_OUTPUTNSTATE_ENABLE : stm8s_tim1.h
  • TIM1_OUTPUTSTATE_DISABLE : stm8s_tim1.h
  • TIM1_OUTPUTSTATE_ENABLE : stm8s_tim1.h
  • TIM1_PSCRELOADMODE_IMMEDIATE : stm8s_tim1.h
  • TIM1_PSCRELOADMODE_UPDATE : stm8s_tim1.h
  • TIM1_SLAVEMODE_EXTERNAL1 : stm8s_tim1.h
  • TIM1_SLAVEMODE_GATED : stm8s_tim1.h
  • TIM1_SLAVEMODE_RESET : stm8s_tim1.h
  • TIM1_SLAVEMODE_TRIGGER : stm8s_tim1.h
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1 : stm8s_tim1.h
  • TIM1_TIXEXTERNALCLK1SOURCE_TI1ED : stm8s_tim1.h
  • TIM1_TIXEXTERNALCLK1SOURCE_TI2 : stm8s_tim1.h
  • TIM1_TRGOSOURCE_ENABLE : stm8s_tim1.h
  • TIM1_TRGOSource_OC1 : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC1REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC2REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_OC3REF : stm8s_tim1.h
  • TIM1_TRGOSOURCE_RESET : stm8s_tim1.h
  • TIM1_TRGOSOURCE_UPDATE : stm8s_tim1.h
  • TIM1_TS_ETRF : stm8s_tim1.h
  • TIM1_TS_TI1F_ED : stm8s_tim1.h
  • TIM1_TS_TI1FP1 : stm8s_tim1.h
  • TIM1_TS_TI2FP2 : stm8s_tim1.h
  • TIM1_TS_TIM5 : stm8s_tim1.h
  • TIM1_TS_TIM6 : stm8s_tim1.h
  • TIM1_UPDATESOURCE_GLOBAL : stm8s_tim1.h
  • TIM1_UPDATESOURCE_REGULAR : stm8s_tim1.h
  • TIM2_CHANNEL_1 : stm8s_tim2.h
  • TIM2_CHANNEL_2 : stm8s_tim2.h
  • TIM2_CHANNEL_3 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_CC1 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_CC2 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_CC3 : stm8s_tim2.h
  • TIM2_EVENTSOURCE_UPDATE : stm8s_tim2.h
  • TIM2_FLAG_CC1 : stm8s_tim2.h
  • TIM2_FLAG_CC1OF : stm8s_tim2.h
  • TIM2_FLAG_CC2 : stm8s_tim2.h
  • TIM2_FLAG_CC2OF : stm8s_tim2.h
  • TIM2_FLAG_CC3 : stm8s_tim2.h
  • TIM2_FLAG_CC3OF : stm8s_tim2.h
  • TIM2_FLAG_UPDATE : stm8s_tim2.h
  • TIM2_FORCEDACTION_ACTIVE : stm8s_tim2.h
  • TIM2_FORCEDACTION_INACTIVE : stm8s_tim2.h
  • TIM2_ICPOLARITY_FALLING : stm8s_tim2.h
  • TIM2_ICPOLARITY_RISING : stm8s_tim2.h
  • TIM2_ICPSC_DIV1 : stm8s_tim2.h
  • TIM2_ICPSC_DIV2 : stm8s_tim2.h
  • TIM2_ICPSC_DIV4 : stm8s_tim2.h
  • TIM2_ICPSC_DIV8 : stm8s_tim2.h
  • TIM2_ICSELECTION_DIRECTTI : stm8s_tim2.h
  • TIM2_ICSELECTION_INDIRECTTI : stm8s_tim2.h
  • TIM2_ICSELECTION_TRGI : stm8s_tim2.h
  • TIM2_IT_CC1 : stm8s_tim2.h
  • TIM2_IT_CC2 : stm8s_tim2.h
  • TIM2_IT_CC3 : stm8s_tim2.h
  • TIM2_IT_UPDATE : stm8s_tim2.h
  • TIM2_OCMODE_ACTIVE : stm8s_tim2.h
  • TIM2_OCMODE_INACTIVE : stm8s_tim2.h
  • TIM2_OCMODE_PWM1 : stm8s_tim2.h
  • TIM2_OCMODE_PWM2 : stm8s_tim2.h
  • TIM2_OCMODE_TIMING : stm8s_tim2.h
  • TIM2_OCMODE_TOGGLE : stm8s_tim2.h
  • TIM2_OCPOLARITY_HIGH : stm8s_tim2.h
  • TIM2_OCPOLARITY_LOW : stm8s_tim2.h
  • TIM2_OPMODE_REPETITIVE : stm8s_tim2.h
  • TIM2_OPMODE_SINGLE : stm8s_tim2.h
  • TIM2_OUTPUTSTATE_DISABLE : stm8s_tim2.h
  • TIM2_OUTPUTSTATE_ENABLE : stm8s_tim2.h
  • TIM2_PRESCALER_1 : stm8s_tim2.h
  • TIM2_PRESCALER_1024 : stm8s_tim2.h
  • TIM2_PRESCALER_128 : stm8s_tim2.h
  • TIM2_PRESCALER_16 : stm8s_tim2.h
  • TIM2_PRESCALER_16384 : stm8s_tim2.h
  • TIM2_PRESCALER_2 : stm8s_tim2.h
  • TIM2_PRESCALER_2048 : stm8s_tim2.h
  • TIM2_PRESCALER_256 : stm8s_tim2.h
  • TIM2_PRESCALER_32 : stm8s_tim2.h
  • TIM2_PRESCALER_32768 : stm8s_tim2.h
  • TIM2_PRESCALER_4 : stm8s_tim2.h
  • TIM2_PRESCALER_4096 : stm8s_tim2.h
  • TIM2_PRESCALER_512 : stm8s_tim2.h
  • TIM2_PRESCALER_64 : stm8s_tim2.h
  • TIM2_PRESCALER_8 : stm8s_tim2.h
  • TIM2_PRESCALER_8192 : stm8s_tim2.h
  • TIM2_PSCRELOADMODE_IMMEDIATE : stm8s_tim2.h
  • TIM2_PSCRELOADMODE_UPDATE : stm8s_tim2.h
  • TIM2_UPDATESOURCE_GLOBAL : stm8s_tim2.h
  • TIM2_UPDATESOURCE_REGULAR : stm8s_tim2.h
  • TIM3_CHANNEL_1 : stm8s_tim3.h
  • TIM3_CHANNEL_2 : stm8s_tim3.h
  • TIM3_EVENTSOURCE_CC1 : stm8s_tim3.h
  • TIM3_EVENTSOURCE_CC2 : stm8s_tim3.h
  • TIM3_EVENTSOURCE_UPDATE : stm8s_tim3.h
  • TIM3_FLAG_CC1 : stm8s_tim3.h
  • TIM3_FLAG_CC1OF : stm8s_tim3.h
  • TIM3_FLAG_CC2 : stm8s_tim3.h
  • TIM3_FLAG_CC2OF : stm8s_tim3.h
  • TIM3_FLAG_UPDATE : stm8s_tim3.h
  • TIM3_FORCEDACTION_ACTIVE : stm8s_tim3.h
  • TIM3_FORCEDACTION_INACTIVE : stm8s_tim3.h
  • TIM3_ICPOLARITY_FALLING : stm8s_tim3.h
  • TIM3_ICPOLARITY_RISING : stm8s_tim3.h
  • TIM3_ICPSC_DIV1 : stm8s_tim3.h
  • TIM3_ICPSC_DIV2 : stm8s_tim3.h
  • TIM3_ICPSC_DIV4 : stm8s_tim3.h
  • TIM3_ICPSC_DIV8 : stm8s_tim3.h
  • TIM3_ICSELECTION_DIRECTTI : stm8s_tim3.h
  • TIM3_ICSELECTION_INDIRECTTI : stm8s_tim3.h
  • TIM3_ICSELECTION_TRGI : stm8s_tim3.h
  • TIM3_IT_CC1 : stm8s_tim3.h
  • TIM3_IT_CC2 : stm8s_tim3.h
  • TIM3_IT_UPDATE : stm8s_tim3.h
  • TIM3_OCMODE_ACTIVE : stm8s_tim3.h
  • TIM3_OCMODE_INACTIVE : stm8s_tim3.h
  • TIM3_OCMODE_PWM1 : stm8s_tim3.h
  • TIM3_OCMODE_PWM2 : stm8s_tim3.h
  • TIM3_OCMODE_TIMING : stm8s_tim3.h
  • TIM3_OCMODE_TOGGLE : stm8s_tim3.h
  • TIM3_OCPOLARITY_HIGH : stm8s_tim3.h
  • TIM3_OCPOLARITY_LOW : stm8s_tim3.h
  • TIM3_OPMODE_REPETITIVE : stm8s_tim3.h
  • TIM3_OPMODE_SINGLE : stm8s_tim3.h
  • TIM3_OUTPUTSTATE_DISABLE : stm8s_tim3.h
  • TIM3_OUTPUTSTATE_ENABLE : stm8s_tim3.h
  • TIM3_PRESCALER_1 : stm8s_tim3.h
  • TIM3_PRESCALER_1024 : stm8s_tim3.h
  • TIM3_PRESCALER_128 : stm8s_tim3.h
  • TIM3_PRESCALER_16 : stm8s_tim3.h
  • TIM3_PRESCALER_16384 : stm8s_tim3.h
  • TIM3_PRESCALER_2 : stm8s_tim3.h
  • TIM3_PRESCALER_2048 : stm8s_tim3.h
  • TIM3_PRESCALER_256 : stm8s_tim3.h
  • TIM3_PRESCALER_32 : stm8s_tim3.h
  • TIM3_PRESCALER_32768 : stm8s_tim3.h
  • TIM3_PRESCALER_4 : stm8s_tim3.h
  • TIM3_PRESCALER_4096 : stm8s_tim3.h
  • TIM3_PRESCALER_512 : stm8s_tim3.h
  • TIM3_PRESCALER_64 : stm8s_tim3.h
  • TIM3_PRESCALER_8 : stm8s_tim3.h
  • TIM3_PRESCALER_8192 : stm8s_tim3.h
  • TIM3_PSCRELOADMODE_IMMEDIATE : stm8s_tim3.h
  • TIM3_PSCRELOADMODE_UPDATE : stm8s_tim3.h
  • TIM3_UPDATESOURCE_GLOBAL : stm8s_tim3.h
  • TIM3_UPDATESOURCE_REGULAR : stm8s_tim3.h
  • TIM4_EVENTSOURCE_UPDATE : stm8s_tim4.h
  • TIM4_FLAG_UPDATE : stm8s_tim4.h
  • TIM4_IT_UPDATE : stm8s_tim4.h
  • TIM4_OPMODE_REPETITIVE : stm8s_tim4.h
  • TIM4_OPMODE_SINGLE : stm8s_tim4.h
  • TIM4_PRESCALER_1 : stm8s_tim4.h
  • TIM4_PRESCALER_128 : stm8s_tim4.h
  • TIM4_PRESCALER_16 : stm8s_tim4.h
  • TIM4_PRESCALER_2 : stm8s_tim4.h
  • TIM4_PRESCALER_32 : stm8s_tim4.h
  • TIM4_PRESCALER_4 : stm8s_tim4.h
  • TIM4_PRESCALER_64 : stm8s_tim4.h
  • TIM4_PRESCALER_8 : stm8s_tim4.h
  • TIM4_PSCRELOADMODE_IMMEDIATE : stm8s_tim4.h
  • TIM4_PSCRELOADMODE_UPDATE : stm8s_tim4.h
  • TIM4_UPDATESOURCE_GLOBAL : stm8s_tim4.h
  • TIM4_UPDATESOURCE_REGULAR : stm8s_tim4.h
  • TIM5_CHANNEL_1 : stm8s_tim5.h
  • TIM5_CHANNEL_2 : stm8s_tim5.h
  • TIM5_CHANNEL_3 : stm8s_tim5.h
  • TIM5_ENCODERMODE_TI1 : stm8s_tim5.h
  • TIM5_ENCODERMODE_TI12 : stm8s_tim5.h
  • TIM5_ENCODERMODE_TI2 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC1 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC2 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_CC3 : stm8s_tim5.h
  • TIM5_EVENTSOURCE_TRIGGER : stm8s_tim5.h
  • TIM5_EVENTSOURCE_UPDATE : stm8s_tim5.h
  • TIM5_EXTTRGPOLARITY_INVERTED : stm8s_tim5.h
  • TIM5_EXTTRGPOLARITY_NONINVERTED : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV2 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV4 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_DIV8 : stm8s_tim5.h
  • TIM5_EXTTRGPSC_OFF : stm8s_tim5.h
  • TIM5_FLAG_CC1 : stm8s_tim5.h
  • TIM5_FLAG_CC1OF : stm8s_tim5.h
  • TIM5_FLAG_CC2 : stm8s_tim5.h
  • TIM5_FLAG_CC2OF : stm8s_tim5.h
  • TIM5_FLAG_CC3 : stm8s_tim5.h
  • TIM5_FLAG_CC3OF : stm8s_tim5.h
  • TIM5_FLAG_TRIGGER : stm8s_tim5.h
  • TIM5_FLAG_UPDATE : stm8s_tim5.h
  • TIM5_FORCEDACTION_ACTIVE : stm8s_tim5.h
  • TIM5_FORCEDACTION_INACTIVE : stm8s_tim5.h
  • TIM5_ICPOLARITY_FALLING : stm8s_tim5.h
  • TIM5_ICPOLARITY_RISING : stm8s_tim5.h
  • TIM5_ICPSC_DIV1 : stm8s_tim5.h
  • TIM5_ICPSC_DIV2 : stm8s_tim5.h
  • TIM5_ICPSC_DIV4 : stm8s_tim5.h
  • TIM5_ICPSC_DIV8 : stm8s_tim5.h
  • TIM5_ICSELECTION_DIRECTTI : stm8s_tim5.h
  • TIM5_ICSELECTION_INDIRECTTI : stm8s_tim5.h
  • TIM5_ICSELECTION_TRGI : stm8s_tim5.h
  • TIM5_IT_CC1 : stm8s_tim5.h
  • TIM5_IT_CC2 : stm8s_tim5.h
  • TIM5_IT_CC3 : stm8s_tim5.h
  • TIM5_IT_TRIGGER : stm8s_tim5.h
  • TIM5_IT_UPDATE : stm8s_tim5.h
  • TIM5_OCMODE_ACTIVE : stm8s_tim5.h
  • TIM5_OCMODE_INACTIVE : stm8s_tim5.h
  • TIM5_OCMODE_PWM1 : stm8s_tim5.h
  • TIM5_OCMODE_PWM2 : stm8s_tim5.h
  • TIM5_OCMODE_TIMING : stm8s_tim5.h
  • TIM5_OCMODE_TOGGLE : stm8s_tim5.h
  • TIM5_OCPOLARITY_HIGH : stm8s_tim5.h
  • TIM5_OCPOLARITY_LOW : stm8s_tim5.h
  • TIM5_OPMODE_REPETITIVE : stm8s_tim5.h
  • TIM5_OPMODE_SINGLE : stm8s_tim5.h
  • TIM5_OUTPUTSTATE_DISABLE : stm8s_tim5.h
  • TIM5_OUTPUTSTATE_ENABLE : stm8s_tim5.h
  • TIM5_PRESCALER_1 : stm8s_tim5.h
  • TIM5_PRESCALER_1024 : stm8s_tim5.h
  • TIM5_PRESCALER_128 : stm8s_tim5.h
  • TIM5_PRESCALER_16 : stm8s_tim5.h
  • TIM5_PRESCALER_16384 : stm8s_tim5.h
  • TIM5_PRESCALER_2 : stm8s_tim5.h
  • TIM5_PRESCALER_2048 : stm8s_tim5.h
  • TIM5_PRESCALER_256 : stm8s_tim5.h
  • TIM5_PRESCALER_32 : stm8s_tim5.h
  • TIM5_PRESCALER_32768 : stm8s_tim5.h
  • TIM5_PRESCALER_4 : stm8s_tim5.h
  • TIM5_PRESCALER_4096 : stm8s_tim5.h
  • TIM5_PRESCALER_512 : stm8s_tim5.h
  • TIM5_PRESCALER_64 : stm8s_tim5.h
  • TIM5_PRESCALER_8 : stm8s_tim5.h
  • TIM5_PRESCALER_8192 : stm8s_tim5.h
  • TIM5_PSCRELOADMODE_IMMEDIATE : stm8s_tim5.h
  • TIM5_PSCRELOADMODE_UPDATE : stm8s_tim5.h
  • TIM5_SLAVEMODE_EXTERNAL1 : stm8s_tim5.h
  • TIM5_SLAVEMODE_GATED : stm8s_tim5.h
  • TIM5_SLAVEMODE_RESET : stm8s_tim5.h
  • TIM5_SLAVEMODE_TRIGGER : stm8s_tim5.h
  • TIM5_TRGOSOURCE_ENABLE : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC1 : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC1REF : stm8s_tim5.h
  • TIM5_TRGOSOURCE_OC2REF : stm8s_tim5.h
  • TIM5_TRGOSOURCE_RESET : stm8s_tim5.h
  • TIM5_TRGOSOURCE_UPDATE : stm8s_tim5.h
  • TIM5_TS_TIM1 : stm8s_tim5.h
  • TIM5_TS_TIM6 : stm8s_tim5.h
  • TIM5_UPDATESOURCE_GLOBAL : stm8s_tim5.h
  • TIM5_UPDATESOURCE_REGULAR : stm8s_tim5.h
  • TIM6_EVENTSOURCE_TRIGGER : stm8s_tim6.h
  • TIM6_EVENTSOURCE_UPDATE : stm8s_tim6.h
  • TIM6_FLAG_TRIGGER : stm8s_tim6.h
  • TIM6_FLAG_UPDATE : stm8s_tim6.h
  • TIM6_IT_TRIGGER : stm8s_tim6.h
  • TIM6_IT_UPDATE : stm8s_tim6.h
  • TIM6_OPMODE_REPETITIVE : stm8s_tim6.h
  • TIM6_OPMODE_SINGLE : stm8s_tim6.h
  • TIM6_PRESCALER_1 : stm8s_tim6.h
  • TIM6_PRESCALER_128 : stm8s_tim6.h
  • TIM6_PRESCALER_16 : stm8s_tim6.h
  • TIM6_PRESCALER_2 : stm8s_tim6.h
  • TIM6_PRESCALER_32 : stm8s_tim6.h
  • TIM6_PRESCALER_4 : stm8s_tim6.h
  • TIM6_PRESCALER_64 : stm8s_tim6.h
  • TIM6_PRESCALER_8 : stm8s_tim6.h
  • TIM6_PSCRELOADMODE_IMMEDIATE : stm8s_tim6.h
  • TIM6_PSCRELOADMODE_UPDATE : stm8s_tim6.h
  • TIM6_SLAVEMODE_DISABLE : stm8s_tim6.h
  • TIM6_SLAVEMODE_EXTERNAL1 : stm8s_tim6.h
  • TIM6_SLAVEMODE_GATED : stm8s_tim6.h
  • TIM6_SLAVEMODE_RESET : stm8s_tim6.h
  • TIM6_SLAVEMODE_TRIGGER : stm8s_tim6.h
  • TIM6_TRGOSOURCE_ENABLE : stm8s_tim6.h
  • TIM6_TRGOSOURCE_RESET : stm8s_tim6.h
  • TIM6_TRGOSOURCE_UPDATE : stm8s_tim6.h
  • TIM6_TS_TIM1 : stm8s_tim6.h
  • TIM6_TS_TIM5 : stm8s_tim6.h
  • TIM6_UPDATESOURCE_GLOBAL : stm8s_tim6.h
  • TIM6_UPDATESOURCE_REGULAR : stm8s_tim6.h
  • TRUE : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • i
  • r
  • s
  • t
  • u

- u -

  • UART1_FLAG_FE : stm8s_uart1.h
  • UART1_FLAG_IDLE : stm8s_uart1.h
  • UART1_FLAG_LBDF : stm8s_uart1.h
  • UART1_FLAG_NF : stm8s_uart1.h
  • UART1_FLAG_OR : stm8s_uart1.h
  • UART1_FLAG_PE : stm8s_uart1.h
  • UART1_FLAG_RXNE : stm8s_uart1.h
  • UART1_FLAG_SBK : stm8s_uart1.h
  • UART1_FLAG_TC : stm8s_uart1.h
  • UART1_FLAG_TXE : stm8s_uart1.h
  • UART1_IRDAMODE_LOWPOWER : stm8s_uart1.h
  • UART1_IRDAMODE_NORMAL : stm8s_uart1.h
  • UART1_IT_IDLE : stm8s_uart1.h
  • UART1_IT_LBDF : stm8s_uart1.h
  • UART1_IT_OR : stm8s_uart1.h
  • UART1_IT_PE : stm8s_uart1.h
  • UART1_IT_RXNE : stm8s_uart1.h
  • UART1_IT_RXNE_OR : stm8s_uart1.h
  • UART1_IT_TC : stm8s_uart1.h
  • UART1_IT_TXE : stm8s_uart1.h
  • UART1_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart1.h
  • UART1_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart1.h
  • UART1_MODE_RX_DISABLE : stm8s_uart1.h
  • UART1_MODE_RX_ENABLE : stm8s_uart1.h
  • UART1_MODE_TX_DISABLE : stm8s_uart1.h
  • UART1_MODE_TX_ENABLE : stm8s_uart1.h
  • UART1_MODE_TXRX_ENABLE : stm8s_uart1.h
  • UART1_PARITY_EVEN : stm8s_uart1.h
  • UART1_PARITY_NO : stm8s_uart1.h
  • UART1_PARITY_ODD : stm8s_uart1.h
  • UART1_STOPBITS_0_5 : stm8s_uart1.h
  • UART1_STOPBITS_1 : stm8s_uart1.h
  • UART1_STOPBITS_1_5 : stm8s_uart1.h
  • UART1_STOPBITS_2 : stm8s_uart1.h
  • UART1_SYNCMODE_CLOCK_DISABLE : stm8s_uart1.h
  • UART1_SYNCMODE_CLOCK_ENABLE : stm8s_uart1.h
  • UART1_SYNCMODE_CPHA_BEGINING : stm8s_uart1.h
  • UART1_SYNCMODE_CPHA_MIDDLE : stm8s_uart1.h
  • UART1_SYNCMODE_CPOL_HIGH : stm8s_uart1.h
  • UART1_SYNCMODE_CPOL_LOW : stm8s_uart1.h
  • UART1_SYNCMODE_LASTBIT_DISABLE : stm8s_uart1.h
  • UART1_SYNCMODE_LASTBIT_ENABLE : stm8s_uart1.h
  • UART1_WAKEUP_ADDRESSMARK : stm8s_uart1.h
  • UART1_WAKEUP_IDLELINE : stm8s_uart1.h
  • UART1_WORDLENGTH_8D : stm8s_uart1.h
  • UART1_WORDLENGTH_9D : stm8s_uart1.h
  • UART2_FLAG_FE : stm8s_uart2.h
  • UART2_FLAG_IDLE : stm8s_uart2.h
  • UART2_FLAG_LBDF : stm8s_uart2.h
  • UART2_FLAG_LHDF : stm8s_uart2.h
  • UART2_FLAG_LSF : stm8s_uart2.h
  • UART2_FLAG_NF : stm8s_uart2.h
  • UART2_FLAG_OR_LHE : stm8s_uart2.h
  • UART2_FLAG_PE : stm8s_uart2.h
  • UART2_FLAG_RXNE : stm8s_uart2.h
  • UART2_FLAG_SBK : stm8s_uart2.h
  • UART2_FLAG_TC : stm8s_uart2.h
  • UART2_FLAG_TXE : stm8s_uart2.h
  • UART2_IRDAMODE_LOWPOWER : stm8s_uart2.h
  • UART2_IRDAMODE_NORMAL : stm8s_uart2.h
  • UART2_IT_IDLE : stm8s_uart2.h
  • UART2_IT_LBDF : stm8s_uart2.h
  • UART2_IT_LHDF : stm8s_uart2.h
  • UART2_IT_OR : stm8s_uart2.h
  • UART2_IT_PE : stm8s_uart2.h
  • UART2_IT_RXNE : stm8s_uart2.h
  • UART2_IT_RXNE_OR : stm8s_uart2.h
  • UART2_IT_TC : stm8s_uart2.h
  • UART2_IT_TXE : stm8s_uart2.h
  • UART2_LIN_AUTOSYNC_DISABLE : stm8s_uart2.h
  • UART2_LIN_AUTOSYNC_ENABLE : stm8s_uart2.h
  • UART2_LIN_DIVUP_LBRR1 : stm8s_uart2.h
  • UART2_LIN_DIVUP_NEXTRXNE : stm8s_uart2.h
  • UART2_LIN_MODE_MASTER : stm8s_uart2.h
  • UART2_LIN_MODE_SLAVE : stm8s_uart2.h
  • UART2_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart2.h
  • UART2_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart2.h
  • UART2_MODE_RX_DISABLE : stm8s_uart2.h
  • UART2_MODE_RX_ENABLE : stm8s_uart2.h
  • UART2_MODE_TX_DISABLE : stm8s_uart2.h
  • UART2_MODE_TX_ENABLE : stm8s_uart2.h
  • UART2_MODE_TXRX_ENABLE : stm8s_uart2.h
  • UART2_PARITY_EVEN : stm8s_uart2.h
  • UART2_PARITY_NO : stm8s_uart2.h
  • UART2_PARITY_ODD : stm8s_uart2.h
  • UART2_STOPBITS_0_5 : stm8s_uart2.h
  • UART2_STOPBITS_1 : stm8s_uart2.h
  • UART2_STOPBITS_1_5 : stm8s_uart2.h
  • UART2_STOPBITS_2 : stm8s_uart2.h
  • UART2_SYNCMODE_CLOCK_DISABLE : stm8s_uart2.h
  • UART2_SYNCMODE_CLOCK_ENABLE : stm8s_uart2.h
  • UART2_SYNCMODE_CPHA_BEGINING : stm8s_uart2.h
  • UART2_SYNCMODE_CPHA_MIDDLE : stm8s_uart2.h
  • UART2_SYNCMODE_CPOL_HIGH : stm8s_uart2.h
  • UART2_SYNCMODE_CPOL_LOW : stm8s_uart2.h
  • UART2_SYNCMODE_LASTBIT_DISABLE : stm8s_uart2.h
  • UART2_SYNCMODE_LASTBIT_ENABLE : stm8s_uart2.h
  • UART2_WAKEUP_ADDRESSMARK : stm8s_uart2.h
  • UART2_WAKEUP_IDLELINE : stm8s_uart2.h
  • UART2_WORDLENGTH_8D : stm8s_uart2.h
  • UART2_WORDLENGTH_9D : stm8s_uart2.h
  • UART3_FLAG_FE : stm8s_uart3.h
  • UART3_FLAG_IDLE : stm8s_uart3.h
  • UART3_FLAG_LBDF : stm8s_uart3.h
  • UART3_FLAG_LHDF : stm8s_uart3.h
  • UART3_FLAG_LSF : stm8s_uart3.h
  • UART3_FLAG_NF : stm8s_uart3.h
  • UART3_FLAG_OR_LHE : stm8s_uart3.h
  • UART3_FLAG_PE : stm8s_uart3.h
  • UART3_FLAG_RXNE : stm8s_uart3.h
  • UART3_FLAG_SBK : stm8s_uart3.h
  • UART3_FLAG_TC : stm8s_uart3.h
  • UART3_FLAG_TXE : stm8s_uart3.h
  • UART3_IT_IDLE : stm8s_uart3.h
  • UART3_IT_LBDF : stm8s_uart3.h
  • UART3_IT_LHDF : stm8s_uart3.h
  • UART3_IT_OR : stm8s_uart3.h
  • UART3_IT_PE : stm8s_uart3.h
  • UART3_IT_RXNE : stm8s_uart3.h
  • UART3_IT_RXNE_OR : stm8s_uart3.h
  • UART3_IT_TC : stm8s_uart3.h
  • UART3_IT_TXE : stm8s_uart3.h
  • UART3_LIN_AUTOSYNC_DISABLE : stm8s_uart3.h
  • UART3_LIN_AUTOSYNC_ENABLE : stm8s_uart3.h
  • UART3_LIN_DIVUP_LBRR1 : stm8s_uart3.h
  • UART3_LIN_DIVUP_NEXTRXNE : stm8s_uart3.h
  • UART3_LIN_MODE_MASTER : stm8s_uart3.h
  • UART3_LIN_MODE_SLAVE : stm8s_uart3.h
  • UART3_LINBREAKDETECTIONLENGTH_10BITS : stm8s_uart3.h
  • UART3_LINBREAKDETECTIONLENGTH_11BITS : stm8s_uart3.h
  • UART3_MODE_RX_DISABLE : stm8s_uart3.h
  • UART3_MODE_RX_ENABLE : stm8s_uart3.h
  • UART3_MODE_TX_DISABLE : stm8s_uart3.h
  • UART3_MODE_TX_ENABLE : stm8s_uart3.h
  • UART3_MODE_TXRX_ENABLE : stm8s_uart3.h
  • UART3_PARITY_EVEN : stm8s_uart3.h
  • UART3_PARITY_NO : stm8s_uart3.h
  • UART3_PARITY_ODD : stm8s_uart3.h
  • UART3_STOPBITS_1 : stm8s_uart3.h
  • UART3_STOPBITS_2 : stm8s_uart3.h
  • UART3_WAKEUP_ADDRESSMARK : stm8s_uart3.h
  • UART3_WAKEUP_IDLELINE : stm8s_uart3.h
  • UART3_WORDLENGTH_8D : stm8s_uart3.h
  • UART3_WORDLENGTH_9D : stm8s_uart3.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • e
  • f
  • g
  • i
  • r
  • s
  • t
  • u
  • w

- a -

  • ADC1_AWDChannelConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ClearFlag() : stm8s_adc1.c , stm8s_adc1.h
  • ADC1_ClearITPendingBit() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_Cmd() : stm8s_adc1.c , stm8s_adc1.h
  • ADC1_ConversionConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_DataBufferCmd() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_DeInit() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ExternalTriggerConfig() : stm8s_adc1.c , stm8s_adc1.h
  • ADC1_GetAWDChannelStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetBufferValue() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetConversionValue() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetFlagStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_GetITStatus() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_Init() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_ITConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_PrescalerConfig() : stm8s_adc1.c , stm8s_adc1.h
  • ADC1_ScanModeCmd() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SchmittTriggerConfig() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SetHighThreshold() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_SetLowThreshold() : stm8s_adc1.h , stm8s_adc1.c
  • ADC1_StartConversion() : stm8s_adc1.h , stm8s_adc1.c
  • ADC2_ClearFlag() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_ClearITPendingBit() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_Cmd() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_ConversionConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_DeInit() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_ExternalTriggerConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_GetConversionValue() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_GetFlagStatus() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_GetITStatus() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_Init() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_ITConfig() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_PrescalerConfig() : stm8s_adc2.h , stm8s_adc2.c
  • ADC2_SchmittTriggerConfig() : stm8s_adc2.c , stm8s_adc2.h
  • ADC2_StartConversion() : stm8s_adc2.h , stm8s_adc2.c
  • AWU_Cmd() : stm8s_awu.c , stm8s_awu.h
  • AWU_DeInit() : stm8s_awu.h , stm8s_awu.c
  • AWU_GetFlagStatus() : stm8s_awu.h , stm8s_awu.c
  • AWU_IdleModeEnable() : stm8s_awu.h , stm8s_awu.c
  • AWU_Init() : stm8s_awu.h , stm8s_awu.c
  • AWU_LSICalibrationConfig() : stm8s_awu.h , stm8s_awu.c


STM8S/A Standard Peripherals Drivers: Globals

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- b -

  • BEEP_Cmd() : stm8s_beep.h , stm8s_beep.c
  • BEEP_DeInit() : stm8s_beep.c , stm8s_beep.h
  • BEEP_Init() : stm8s_beep.h , stm8s_beep.c
  • BEEP_LSICalibrationConfig() : stm8s_beep.c , stm8s_beep.h


STM8S/A Standard Peripherals Drivers: Globals

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- c -

  • CAN_CancelTransmit() : stm8s_can.h , stm8s_can.c
  • CAN_ClearFlag() : stm8s_can.c , stm8s_can.h
  • CAN_ClearITPendingBit() : stm8s_can.h , stm8s_can.c
  • CAN_DeInit() : stm8s_can.c , stm8s_can.h
  • CAN_FIFORelease() : stm8s_can.h , stm8s_can.c
  • CAN_FilterInit() : stm8s_can.h , stm8s_can.c
  • CAN_GetFlagStatus() : stm8s_can.h , stm8s_can.c
  • CAN_GetITStatus() : stm8s_can.c , stm8s_can.h
  • CAN_GetLastErrorCode() : stm8s_can.h , stm8s_can.c
  • CAN_GetMessageTimeStamp() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedData() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedDLC() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedFMI() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedId() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedIDE() : stm8s_can.h , stm8s_can.c
  • CAN_GetReceivedRTR() : stm8s_can.c , stm8s_can.h
  • CAN_GetSelectedPage() : stm8s_can.h , stm8s_can.c
  • CAN_Init() : stm8s_can.h , stm8s_can.c
  • CAN_ITConfig() : stm8s_can.h , stm8s_can.c
  • CAN_MessagePending() : stm8s_can.h , stm8s_can.c
  • CAN_OperatingModeRequest() : stm8s_can.h , stm8s_can.c
  • CAN_Receive() : stm8s_can.h , stm8s_can.c
  • CAN_SelectPage() : stm8s_can.h , stm8s_can.c
  • CAN_Sleep() : stm8s_can.h , stm8s_can.c
  • CAN_ST7CompatibilityCmd() : stm8s_can.h , stm8s_can.c
  • CAN_Transmit() : stm8s_can.h , stm8s_can.c
  • CAN_TransmitStatus() : stm8s_can.h , stm8s_can.c
  • CAN_TTComModeCmd() : stm8s_can.h , stm8s_can.c
  • CAN_WakeUp() : stm8s_can.h , stm8s_can.c
  • CheckITStatus() : stm8s_can.c
  • CLK_AdjustHSICalibrationValue() : stm8s_clk.h , stm8s_clk.c
  • CLK_CCOCmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_CCOConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClearITPendingBit() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSecuritySystemEnable() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSwitchCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_ClockSwitchConfig() : stm8s_clk.c , stm8s_clk.h
  • CLK_DeInit() : stm8s_clk.h , stm8s_clk.c
  • CLK_FastHaltWakeUpCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetClockFreq() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetFlagStatus() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetITStatus() : stm8s_clk.h , stm8s_clk.c
  • CLK_GetSYSCLKSource() : stm8s_clk.h , stm8s_clk.c
  • CLK_HSECmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_HSICmd() : stm8s_clk.c , stm8s_clk.h
  • CLK_HSIPrescalerConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_ITConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_LSICmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_PeripheralClockConfig() : stm8s_clk.c , stm8s_clk.h
  • CLK_SlowActiveHaltWakeUpCmd() : stm8s_clk.h , stm8s_clk.c
  • CLK_SWIMConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_SYSCLKConfig() : stm8s_clk.h , stm8s_clk.c
  • CLK_SYSCLKEmergencyClear() : stm8s_clk.h , stm8s_clk.c


STM8S/A Standard Peripherals Drivers: Globals

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- e -

  • EXTI_DeInit() : stm8s_exti.h , stm8s_exti.c
  • EXTI_GetExtIntSensitivity() : stm8s_exti.c , stm8s_exti.h
  • EXTI_GetTLISensitivity() : stm8s_exti.h , stm8s_exti.c
  • EXTI_SetExtIntSensitivity() : stm8s_exti.h , stm8s_exti.c
  • EXTI_SetTLISensitivity() : stm8s_exti.c , stm8s_exti.h


STM8S/A Standard Peripherals Drivers: Globals

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- f -

  • FLASH_DeInit() : stm8s_flash.h , stm8s_flash.c
  • FLASH_EraseByte() : stm8s_flash.c , stm8s_flash.h
  • FLASH_EraseOptionByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetBootSize() : stm8s_flash.c , stm8s_flash.h
  • FLASH_GetFlagStatus() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetLowPowerMode() : stm8s_flash.h , stm8s_flash.c
  • FLASH_GetProgrammingTime() : stm8s_flash.h , stm8s_flash.c
  • FLASH_ITConfig() : stm8s_flash.c , stm8s_flash.h
  • FLASH_Lock() : stm8s_flash.h , stm8s_flash.c
  • FLASH_ProgramByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_ProgramOptionByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_ProgramWord() : stm8s_flash.c , stm8s_flash.h
  • FLASH_ReadByte() : stm8s_flash.h , stm8s_flash.c
  • FLASH_ReadOptionByte() : stm8s_flash.c , stm8s_flash.h
  • FLASH_SetLowPowerMode() : stm8s_flash.h , stm8s_flash.c
  • FLASH_SetProgrammingTime() : stm8s_flash.c , stm8s_flash.h
  • FLASH_Unlock() : stm8s_flash.c , stm8s_flash.h


STM8S/A Standard Peripherals Drivers: Globals

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- g -

  • GPIO_DeInit() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ExternalPullUpConfig() : stm8s_gpio.c , stm8s_gpio.h
  • GPIO_Init() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ReadInputData() : stm8s_gpio.c , stm8s_gpio.h
  • GPIO_ReadInputPin() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_ReadOutputData() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_Write() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_WriteHigh() : stm8s_gpio.h , stm8s_gpio.c
  • GPIO_WriteLow() : stm8s_gpio.c , stm8s_gpio.h
  • GPIO_WriteReverse() : stm8s_gpio.c , stm8s_gpio.h


STM8S/A Standard Peripherals Drivers: Globals

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- i -

  • I2C_AcknowledgeConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_CheckEvent() : stm8s_i2c.c , stm8s_i2c.h
  • I2C_ClearFlag() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ClearITPendingBit() : stm8s_i2c.c , stm8s_i2c.h
  • I2C_Cmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_DeInit() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_FastModeDutyCycleConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GeneralCallCmd() : stm8s_i2c.c , stm8s_i2c.h
  • I2C_GenerateSTART() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GenerateSTOP() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetFlagStatus() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetITStatus() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_GetLastEvent() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_Init() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ITConfig() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_ReceiveData() : stm8s_i2c.c , stm8s_i2c.h
  • I2C_Send7bitAddress() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_SendData() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_SoftwareResetCmd() : stm8s_i2c.h , stm8s_i2c.c
  • I2C_StretchClockCmd() : stm8s_i2c.c , stm8s_i2c.h
  • IN_RAM() : stm8s_flash.h
  • ITC_DeInit() : stm8s_itc.c , stm8s_itc.h
  • ITC_GetCPUCC() : stm8s_itc.c , stm8s_itc.h
  • ITC_GetSoftIntStatus() : stm8s_itc.c , stm8s_itc.h
  • ITC_GetSoftwarePriority() : stm8s_itc.h , stm8s_itc.c
  • ITC_SetSoftwarePriority() : stm8s_itc.h , stm8s_itc.c
  • IWDG_Enable() : stm8s_iwdg.c , stm8s_iwdg.h
  • IWDG_ReloadCounter() : stm8s_iwdg.c , stm8s_iwdg.h
  • IWDG_SetPrescaler() : stm8s_iwdg.c , stm8s_iwdg.h
  • IWDG_SetReload() : stm8s_iwdg.h , stm8s_iwdg.c
  • IWDG_WriteAccessCmd() : stm8s_iwdg.h , stm8s_iwdg.c


STM8S/A Standard Peripherals Drivers: Globals

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- r -

  • RST_ClearFlag() : stm8s_rst.h , stm8s_rst.c
  • RST_GetFlagStatus() : stm8s_rst.h , stm8s_rst.c


STM8S/A Standard Peripherals Drivers: Globals

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- s -

  • SPI_BiDirectionalLineConfig() : stm8s_spi.h , stm8s_spi.c
  • SPI_CalculateCRCCmd() : stm8s_spi.c , stm8s_spi.h
  • SPI_ClearFlag() : stm8s_spi.h , stm8s_spi.c
  • SPI_ClearITPendingBit() : stm8s_spi.c , stm8s_spi.h
  • SPI_Cmd() : stm8s_spi.h , stm8s_spi.c
  • SPI_DeInit() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetCRC() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetCRCPolynomial() : stm8s_spi.c , stm8s_spi.h
  • SPI_GetFlagStatus() : stm8s_spi.h , stm8s_spi.c
  • SPI_GetITStatus() : stm8s_spi.h , stm8s_spi.c
  • SPI_Init() : stm8s_spi.h , stm8s_spi.c
  • SPI_ITConfig() : stm8s_spi.c , stm8s_spi.h
  • SPI_NSSInternalSoftwareCmd() : stm8s_spi.h , stm8s_spi.c
  • SPI_ReceiveData() : stm8s_spi.c , stm8s_spi.h
  • SPI_ResetCRC() : stm8s_spi.h , stm8s_spi.c
  • SPI_SendData() : stm8s_spi.c , stm8s_spi.h
  • SPI_TransmitCRC() : stm8s_spi.c , stm8s_spi.h


STM8S/A Standard Peripherals Drivers: Globals

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- t -

  • TI1_Config() : stm8s_tim1.c , stm8s_tim2.c , stm8s_tim5.c , stm8s_tim3.c
  • TI2_Config() : stm8s_tim5.c , stm8s_tim1.c , stm8s_tim2.c , stm8s_tim3.c
  • TI3_Config() : stm8s_tim1.c , stm8s_tim2.c , stm8s_tim5.c
  • TI4_Config() : stm8s_tim1.c
  • TIM1_ARRPreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_BDTRConfig() : stm8s_tim1.c , stm8s_tim1.h
  • TIM1_CCPreloadControl() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CCxCmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CCxNCmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ClearFlag() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ClearITPendingBit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_Cmd() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CounterModeConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_CtrlPWMOutputs() : stm8s_tim1.c , stm8s_tim1.h
  • TIM1_DeInit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_EncoderInterfaceConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ETRClockMode1Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ETRClockMode2Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ETRConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC1Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC2Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC3Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ForcedOC4Config() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GenerateEvent() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture1() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture2() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture3() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCapture4() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetCounter() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetFlagStatus() : stm8s_tim1.c , stm8s_tim1.h
  • TIM1_GetITStatus() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_GetPrescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ICInit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_InternalClockConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_ITConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC1PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC2PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3NPolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC3PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4FastConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4Init() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4PolarityConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_OC4PreloadConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_PrescalerConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_PWMIConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectCOM() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectHallSensor() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectInputTrigger() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectMasterSlaveMode() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectOCxM() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectOnePulseMode() : stm8s_tim1.c , stm8s_tim1.h
  • TIM1_SelectOutputTrigger() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SelectSlaveMode() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetAutoreload() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare1() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare2() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare3() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCompare4() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetCounter() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC1Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC2Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC3Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_SetIC4Prescaler() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_TimeBaseInit() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_TIxExternalClockConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_UpdateDisableConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM1_UpdateRequestConfig() : stm8s_tim1.h , stm8s_tim1.c
  • TIM2_ARRPreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_CCPreloadControl() : stm8s_tim2.h
  • TIM2_CCxCmd() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ClearFlag() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ClearITPendingBit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_Cmd() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_DeInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ForcedOC1Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ForcedOC2Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ForcedOC3Config() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GenerateEvent() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture1() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture2() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCapture3() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetCounter() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetFlagStatus() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetITStatus() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_GetPrescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_ICInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_InternalClockConfig() : stm8s_tim2.h
  • TIM2_ITConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC1PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC2PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3Init() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3PolarityConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_OC3PreloadConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_PrescalerConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_PWMIConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SelectOCxM() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SelectOnePulseMode() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetAutoreload() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare1() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare2() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCompare3() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetCounter() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC1Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC2Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_SetIC3Prescaler() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_TimeBaseInit() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_UpdateDisableConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM2_UpdateRequestConfig() : stm8s_tim2.h , stm8s_tim2.c
  • TIM3_ARRPreloadConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_CCPreloadControl() : stm8s_tim3.h
  • TIM3_CCxCmd() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ClearFlag() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_ClearITPendingBit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_Cmd() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_DeInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ForcedOC1Config() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ForcedOC2Config() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GenerateEvent() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetCapture1() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetCapture2() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetCounter() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetFlagStatus() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetITStatus() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_GetPrescaler() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_ICInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_InternalClockConfig() : stm8s_tim3.h
  • TIM3_ITConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_OC1Init() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC1PolarityConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_OC1PreloadConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2Init() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2PolarityConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_OC2PreloadConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_PrescalerConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_PWMIConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_SelectOCxM() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SelectOnePulseMode() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_SetAutoreload() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetCompare1() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetCompare2() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetCounter() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_SetIC1Prescaler() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_SetIC2Prescaler() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_TimeBaseInit() : stm8s_tim3.h , stm8s_tim3.c
  • TIM3_UpdateDisableConfig() : stm8s_tim3.c , stm8s_tim3.h
  • TIM3_UpdateRequestConfig() : stm8s_tim3.h , stm8s_tim3.c
  • TIM4_ARRPreloadConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_ClearFlag() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_ClearITPendingBit() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_Cmd() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_DeInit() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_GenerateEvent() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_GetCounter() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_GetFlagStatus() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_GetITStatus() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_GetPrescaler() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_ITConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_PrescalerConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_SelectOnePulseMode() : stm8s_tim4.c , stm8s_tim4.h
  • TIM4_SetAutoreload() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_SetCounter() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_TimeBaseInit() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_UpdateDisableConfig() : stm8s_tim4.h , stm8s_tim4.c
  • TIM4_UpdateRequestConfig() : stm8s_tim4.c , stm8s_tim4.h
  • TIM5_ARRPreloadConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_CCPreloadControl() : stm8s_tim5.h
  • TIM5_CCxCmd() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ClearFlag() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ClearITPendingBit() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_Cmd() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_DeInit() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_EncoderInterfaceConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ForcedOC1Config() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_ForcedOC2Config() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ForcedOC3Config() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GenerateEvent() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetCapture1() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_GetCapture2() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetCapture3() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetCounter() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_GetFlagStatus() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetITStatus() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_GetPrescaler() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_ICInit() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_InternalClockConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_ITConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1Init() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1PolarityConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC1PreloadConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC2Init() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_OC2PolarityConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC2PreloadConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_OC3Init() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_OC3PolarityConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_OC3PreloadConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_PrescalerConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_PWMIConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectInputTrigger() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectOCxM() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectOnePulseMode() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectOutputTrigger() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SelectSlaveMode() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetAutoreload() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetCompare1() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCompare2() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetCompare3() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetCounter() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_SetIC1Prescaler() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetIC2Prescaler() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_SetIC3Prescaler() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_TimeBaseInit() : stm8s_tim5.c , stm8s_tim5.h
  • TIM5_UpdateDisableConfig() : stm8s_tim5.h , stm8s_tim5.c
  • TIM5_UpdateRequestConfig() : stm8s_tim5.c , stm8s_tim5.h
  • TIM6_ARRPreloadConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_ClearFlag() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_ClearITPendingBit() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_Cmd() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_DeInit() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GenerateEvent() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_GetCounter() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GetFlagStatus() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GetITStatus() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_GetPrescaler() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_InternalClockConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_ITConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_PrescalerConfig() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectInputTrigger() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_SelectMasterSlaveMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectOnePulseMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectOutputTrigger() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SelectSlaveMode() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_SetAutoreload() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_SetCounter() : stm8s_tim6.h , stm8s_tim6.c
  • TIM6_TimeBaseInit() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_UpdateDisableConfig() : stm8s_tim6.c , stm8s_tim6.h
  • TIM6_UpdateRequestConfig() : stm8s_tim6.c , stm8s_tim6.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • e
  • f
  • g
  • i
  • r
  • s
  • t
  • u
  • w

- u -

  • UART1_ClearFlag() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ClearITPendingBit() : stm8s_uart1.c , stm8s_uart1.h
  • UART1_Cmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_DeInit() : stm8s_uart1.c , stm8s_uart1.h
  • UART1_GetFlagStatus() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_GetITStatus() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_HalfDuplexCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_Init() : stm8s_uart1.c , stm8s_uart1.h
  • UART1_IrDACmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_IrDAConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ITConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_LINBreakDetectionConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_LINCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ReceiveData8() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ReceiveData9() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_ReceiverWakeUpCmd() : stm8s_uart1.c , stm8s_uart1.h
  • UART1_SendBreak() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SendData8() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SendData9() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetAddress() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetGuardTime() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SetPrescaler() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SmartCardCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_SmartCardNACKCmd() : stm8s_uart1.h , stm8s_uart1.c
  • UART1_WakeUpConfig() : stm8s_uart1.h , stm8s_uart1.c
  • UART2_ClearFlag() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ClearITPendingBit() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_Cmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_DeInit() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_GetFlagStatus() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_GetITStatus() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_HalfDuplexCmd() : stm8s_uart2.h
  • UART2_Init() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_IrDACmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_IrDAConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ITConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LINBreakDetectionConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_LINCmd() : stm8s_uart2.c , stm8s_uart2.h
  • UART2_LINConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ReceiveData8() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ReceiveData9() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_ReceiverWakeUpCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SendBreak() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SendData8() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SendData9() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetAddress() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetGuardTime() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SetPrescaler() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SmartCardCmd() : stm8s_uart2.h , stm8s_uart2.c
  • UART2_SmartCardNACKCmd() : stm8s_uart2.c , stm8s_uart2.h
  • UART2_WakeUpConfig() : stm8s_uart2.h , stm8s_uart2.c
  • UART3_ClearFlag() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_ClearITPendingBit() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_Cmd() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_DeInit() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_GetFlagStatus() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_GetITStatus() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_Init() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_ITConfig() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_LINBreakDetectionConfig() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_LINCmd() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_LINConfig() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_ReceiveData8() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_ReceiveData9() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_ReceiverWakeUpCmd() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_SendBreak() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SendData8() : stm8s_uart3.h , stm8s_uart3.c
  • UART3_SendData9() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_SetAddress() : stm8s_uart3.c , stm8s_uart3.h
  • UART3_WakeUpConfig() : stm8s_uart3.h , stm8s_uart3.c


STM8S/A Standard Peripherals Drivers: Globals

  • File List
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  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • a
  • b
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  • e
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  • g
  • i
  • r
  • s
  • t
  • u
  • w

- w -

  • WWDG_GetCounter() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_Init() : stm8s_wwdg.c , stm8s_wwdg.h
  • WWDG_SetCounter() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_SetWindowValue() : stm8s_wwdg.h , stm8s_wwdg.c
  • WWDG_SWReset() : stm8s_wwdg.c , stm8s_wwdg.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • a
  • b
  • c
  • e
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  • g
  • i
  • o
  • r
  • s
  • t
  • u
  • w

- a -

  • AWU_TypeDef : stm8s.h

- b -

  • BEEP_TypeDef : stm8s.h
  • BitAction : stm8s.h
  • BitStatus : stm8s.h

- c -

  • CFG_TypeDef : stm8s.h
  • CLK_TypeDef : stm8s.h

- e -

  • EXTI_TypeDef : stm8s.h

- f -

  • FLASH_TypeDef : stm8s.h

- g -

  • GPIO_TypeDef : stm8s.h

- i -

  • I2C_TypeDef : stm8s.h
  • int16_t : stm8s.h
  • int32_t : stm8s.h
  • int8_t : stm8s.h
  • ITC_TypeDef : stm8s.h
  • ITStatus : stm8s.h
  • IWDG_TypeDef : stm8s.h

- o -

  • OPT_TypeDef : stm8s.h

- r -

  • RST_TypeDef : stm8s.h

- s -

  • s16 : stm8s.h
  • s32 : stm8s.h
  • s8 : stm8s.h
  • SPI_TypeDef : stm8s.h

- t -

  • TIM1_TypeDef : stm8s.h
  • TIM2_TypeDef : stm8s.h
  • TIM3_TypeDef : stm8s.h
  • TIM4_TypeDef : stm8s.h
  • TIM5_TypeDef : stm8s.h
  • TIM6_TypeDef : stm8s.h

- u -

  • u16 : stm8s.h
  • u32 : stm8s.h
  • u8 : stm8s.h
  • UART1_TypeDef : stm8s.h
  • UART2_TypeDef : stm8s.h
  • UART3_TypeDef : stm8s.h
  • uint16_t : stm8s.h
  • uint32_t : stm8s.h
  • uint8_t : stm8s.h

- w -

  • WWDG_TypeDef : stm8s.h


STM8S/A Standard Peripherals Drivers: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _Data : stm8s_can.c
  • _DLC : stm8s_can.c
  • _FMI : stm8s_can.c
  • _Id : stm8s_can.c
  • _IDE : stm8s_can.c
  • _RTR : stm8s_can.c
  • APR_Array : stm8s_awu.c
  • CLKPrescTable : stm8s_clk.c
  • HSIDivFactor : stm8s_clk.c
  • TBR_Array : stm8s_awu.c


STM8S/A Standard Peripherals Library: Supported devices and toolchains

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STM8S/A Standard Peripherals Library

Supported devices and toolchains

Copyright 2011 STMicroelectronics

STM8S/A devices peripherals Overview

The following table presents the available peripherals set for each STM8S/A devices.
Glossary
  • High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory density ranges between 32 to 128 Kbytes
  • Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68, STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory density ranges between 8 to 32 Kbytes
  • High-Density STM8S devices are the STM8S207xx, STM8S007x and STM8S208xx microcontrollers where the Flash memory density ranges between 32 to 128 Kbytes.
  • Medium-Density STM8S devices are the STM8S105x and STM8S005x microcontrollers where the Flash memory density ranges between 16 to 32-Kbytes.
  • Low-Density STM8S devices are the STM8S103x, STM8S003x and STM8S903xx microcontrollers where the Flash density is 8 Kbytes.

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Supported STM8S/A devices

The Standard Peripherals Library supports all STM8S and STM8A family products devices. By using this library it becomes straightforward to move the application firmware from one STM8S/A device to another.

User has only to select which device he will use by controlling preprocessor define declared in stm8s.h file (No selected device by default) then the library will be configured accordingly:

stm8s.h

...

/* Uncomment the line below according to the target STM8S or STM8A device used in your
application. */

/* #define STM8S208 */ /*!< STM8S High density devices with CAN */
/* #define STM8S207 */ /*!< STM8S High density devices without CAN */
 /* #define STM8S007 */ /*!< STM8S Value Line High density devices without CAN */
/* #define STM8AF52Ax */ /*!< STM8A High density devices with CAN */
/* #define STM8AF62Ax */ /*!< STM8A High density devices without CAN */
/* #define STM8S105 */ /*!< STM8S Medium density devices */
 /* #define STM8S005 */ /*!< STM8S Value Line Medium density devices */
/* #define STM8AF626x */ /*!< STM8A Medium density devices */
/* #define STM8S103 */ /*!< STM8S Low density devices */
 /* #define STM8S003 */ /*!< STM8S Value Line Low density devices */
/* #define STM8S903 */ /*!< STM8S Low density devices */

/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.

...

In the provided template projects within the Standard Peripherals Library package, the appropriate device is preconfigured and defined in the toolchain compiler preprocessor.

This define will control the declaration of the following part of the Standard Peripherals library:

IRQ channel definition

Peripheral memory mapping and physical registers address definition

Peripheral pointer declaration and driver header file inclusion

Product miscellaneous configuration: external quartz (HSE) value…

Peripheral with Features w/ different/incompatible implementation across the family

Notes: These defines impact essentially the following files:

FLASH driver (stm8s_flash.c/.h files) and ITC driver (stm8s_itc.c/.h files)

stm8s_it.c/.h files as the Interrupt sources are device dependent.

stm8s_conf.h: this file allows library configuration with the appropriate peripheral drivers inclusion according to the selected device.

Per default and in the given file template, headers for all peripheral drivers are uncommented and conditionned by the appropriate device define

Howvever user may choose to don't use some periheral drivers in his application, he only has to comment its related header in the stm8s_conf.h file.

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Supported toolchains

The Standard Peripherals Library supports the following toolchains:

ST Visual Develop STVD
 Embedded Workbench for STM8 EWSTM8

Raisonance Integrated Development Environment RIDE

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STM8S/A Standard Peripherals Library: Peripheral’s Drivers Description

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STM8S/A Standard Peripherals Library

Peripheral’s Drivers Description

Copyright 2011 STMicroelectronics

STM8S/A Standard Peripheral's Library Architecture

The following figure provides a global view of the STM8S/A Standard Peripherals Library usage and interaction with other firmware conponents.

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Description of the STM8S/A Standard Peripheral's Drivers files

The Standard Peripherals library file inclusions relationship is shown in the following figure:

Each peripheral has a source code file stm8s_ppp.c and a header file stm8s_ppp.h. The stm8s_ppp.c file contains all the firmware functions required to use the PPP peripheral.
A single memory mapping file, stm8s.h, is supplied for all peripherals. It contains all the register declarations and bits definition. This is the only file that needs to be included in the user application to interface with the library.
The stm8s_conf.h file is used to specify the set of parameters to interface with the library drivers before running any application.

The table bellow lists and describes the different files used by the Standard Peripherals library:

File name | Description
stm8s_conf.h | Peripheral’s drivers configuration file The user can enable or disable peripheral header file inclusion by using the template This file can also be used to enable or disable the Library run-time failure detection before compiling the firmware library drivers, through the preprocessor define USE_FULL_ASSERT
stm8s_ppp.h | Header file of PPP peripheral This file includes the PPP peripheral function and variable definitions used within these functions.
stm8s_ppp.c | Driver source code file of PPP peripheral written in C language
stm8s_it.h | Header file including all interrupt handlers prototypes
stm8s_it.c | Template source file containing the interrupt service routine (ISR) for CortexM3 exceptions. User can add additional ISR(s) for the used peripheral(s) (for the available peripheral interrupt handler's name, please refer to the startup file startup_stm8s_md.s).

stm8s.h

STM8S/A devices peripheral access layer header file.

The file is the unique include file that the application programmer is using in the C source code, usually in main.c. This file contains:

  • configuration section that allows to select:

- the device used in the target application

- to use or not the peripheral’s drivers in application code (i.e. code will be based on direct
access to peripheral’s registers rather than drivers API) , this option is controlled by the
#define USE_STDPERIPH_DRIVER
- to change few application-specific parameters such as the HSE crystal frequency

  • data structures and the address mapping for all peripherals
  • peripheral's registers declarations and bits definition
  • macros to access peripheral’s registers hardware

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STM8S/A Standard Peripherals Drivers MISRA-C 2004 Compliance

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STM8S/A Standard Peripherals Drivers MISRA-C 2004 Compliance

Copyright 2011 STMicroelectronics

The C programming language is growing in importance and use for embedded systems, but when it comes to developing code for safety-critical systems, the language has many drawbacks. There are several unspecified, implementation-defined, and undefined aspects of the C language that make it unsuited for use when developing safety-critical systems.
The Motor Industry Software Reliability Association’s Guidelines for the use of the C language in critical systems MISRA-C 2004 [1] describe a subset of C, suited for use when developing safety-critical systems.
The STM8S/A Standard Peripherals Drivers (STM8S_StdPeriph_Driver) has been developed to be MISRA-C 2004 compliant.

The following section details how the StdPeriph_Driver complies with MISRA-C 2004 (as described in section 4.4 Claiming compliance of the standard [1]):

  • A compliance matrix has been completed to shows how compliance has been enforced.
  • All the STM8S_StdPeriph_Driver C code is compliant with the rules of MISRA-C 2004 or subject documented deviations.
  • A list of all instances of rules not being followed is being maintained, and for each instance there is an appropriately signed-off deviation.
  • All issues listed in the section "4.2 The programming language and coding context of the standard" [1], that has to be checked during the phase of the firmware development process, have been addressed during the development of the STM8S/A Standard Peripherals Drivers and appropriate measures have been taken.

Contents

  1. STM8S/A Standard Peripherals Drivers Compliance
  2. How to check your code for MISRA-C 2004 Compliance?

STM8S/A Standard Peripherals Drivers Compliance

The STM8S/A Standard Peripherals Drivers (STM8S_StdPeriph_Driver) has been checked for MISRA-C 2004 compliance using the IAR C/C++ Compiler for STM8. MISRA compliancy applies only to STM8S/A Standard Peripherals Drivers source file, examples and project files are not MISRA compliant.

For the checking tool two options are available:

  • The compiler: IAR C/C++ Compiler for STM8
  • Manual Checking (code review)

The following table lists the MISRA-C 2004 rules that are violated frequently in the code.

MISRA-C 2004 Rule No | Required/Advisory | Summary | Reason
1.1 | Required | Compiler is configured to allow extensions - all code shall conform to ISO 9899 standard C, with no extensions permitted | IAR compiler extensions are enabled.
5.1 | Required | Identifiers (internal and external) shall not rely on significance of more than 31 characters | Some long parameters names are defined for code readability.
5.4 | Required | Enumerated type mixed with another type - the use of a tag shall agree with its declaration. |
10.1 | Required | The value of an expression of integer type shall not be implicitly converted to a different underlying type. | Complexity
10.6 | Required | A 'U' suffix shall be applied to all constants of 'unsigned' type | The "stdint.h" defined types are used to be compatible w/ STM32.
11.2 | Required | Conversions shall not be performed between a pointer to object and any type other than an integral type, another pointer to object type or a pointer to void. | Needed when addressing memory mapped registers
11.3 | Advisory | A cast should not be performed between a pointer type and an integral type. | Needed when addressing memory mapped registers
11.4 | Advisory | A cast should not be performed between a pointer to object type and a different pointer to object type, | Avoid complexity in Flash driver
16.7 | Advisory | A pointer parameter in a function prototype should be declared as pointer to const if the pointer is not used to modify the addressed object. | Avoid complexity in Flash driver
17.4 | Required | Array indexing shall be the only allowed form of pointer arithmetic | Avoid complexity in Flash driver
19.1 | Advisory | #include statements in a file shall only be preceded by other preprocessor directives or comments | This rule was violated to be inline with STM32.
19.13 | Advisory | # and ## preprosso operators shouldn't be used | Needed for EWSTM8 macro interrupt routine definition

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How to check your code for MISRA-C 2004 Compliance?

The default IAR project template provided with the STM8S/A Standard Peripherals Library is already pre-configured for MISRA-C 2004 Compliance. Then, user has to enable the MISRA-C 2004 checker if needed.

To enable the IAR MISRA-C 2004 Checker, go to Project->Options (ALT+F7) and then in "General Options" Category select the "MISRA-C:2004" tab and check the "Enable MISRA-C" box. With the default EWSTM8 project template, all violated rules described above are unchecked.

To check your code for MISRA-C 2004 compliance using the IAR MISRA-C Checker, please follow the following steps

Enable the IAR MISRA-C 2004 Checker

Uncomment the "USE_FULL_ASSERT" inside the stm8s_conf.h file

Note: Only the STM8S/A Standard Peripherals Drivers are MISRA-C 2004 Compliant.

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[1] MISRA-C 2004 Guidelines for the use of the C language in critical systems, Motor Industry Software Reliability Association, October 2004


STM8S/A Standard Peripherals Library: Overview

Copyright 2011 STMicroelectronics

The STM8S/A Standard Peripherals library covers 3 abstraction levels, and includes:

A complete register address mapping with all bits, bit fields and registers declared in C. This avoids a cumbersome task and more important, it brings the benefits of a bug free reference mapping file, speeding up the early project phase.

A collection of routines and data structures which covers all peripheral functions (drivers with common API). It can directly be used as a reference framework, since it also includes macros for supporting core-related intrinsic features and common constants and data types definition.

A set of examples covering all available peripherals with template projects for the most common development toolchains. With the appropriate hardware evaluation board, this allows to get started with a brand new micro within few hours.

Each driver consists of a set of functions covering all peripheral functionalities. The development of each driver is driven by a common API (application programming interface) which standardizes the driver structure, the functions and the parameter names.
The driver source code is developed in ‘Strict ANSI-C’ (relaxed ANSI-C for projects and example files). It is fully documented and is MISRA-C 2004 compliant (the compliancy matrix is available upon request). Writing the whole library in ‘Strict ANSI-C’ makes it independent from the software toolchain. Only the start-up files depend on the toolchain.

The Standard Peripherals Library implements run-time failure detection by checking the input values for all library functions. Such dynamic checking contributes towards enhancing the robustness of the software. Run-time detection is suitable for user application development and debugging. It adds an overhead which can be removed from the final application code to minimize code size and execution speed. For more details refer to Section Run-time checking.

Since the Standard Peripherals Library is generic and covers all peripheral functionalities, the size and/or execution speed of the application code may not be optimized. For many applications, the library may be used as is. However, for applications having tough constraints in terms of code size and/or execution speed, the library drivers should be used as a reference on how to configure the peripheral and tailor them to specific application requirements.

Note: The performance of application code, in terms of size and/or speed, depends also from the C compiler optimization settings. To help make the application code smaller, faster or balanced between size and speed you should consider fine-tuning the optimizations according to your application needs. For more information please refer to your C compiler documentation.

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STM8S/A Standard Peripherals Library: Coding rules and conventions

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STM8S/A Standard Peripherals Library: Coding rules and conventions

Copyright © 2011 STMicroelectronics

The Standard Peripherals Library uses rules and conventions described in the sections below.

Acronyms

The Table below describes the acronyms used in the Standard Peripherals Library.

Acronym | Peripheral/unit
ADC | Analog to digital converter
BEEP | Beeper
CLK | Clock controller
CAN | CAN
EXTI | External interrupt/event controller
FLASH | Flash memory
GPIO | General purpose I/O
I2C | Inter-integrated circuit
ITC | Interrupt controller
IWDG | Independent watchdog
RST | Reset controller
SPI | Serial peripheral interface
TIM1 | 16-bit advanced control timer
TIM2, TIM3, TIM5, TIM6 | 16-bit general purpose timers
TIM4 | 8-bit basic timer
UART | Universal asynchronous receiver transmitter
WWDG | Window watchdog

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Naming conventions

The Standard Peripherals Library uses the following naming conventions:

  • PPP refers to any peripheral acronym, for example TIM2 and TIM3.
  • System and source/header file names are preceded by the prefix ‘stm8s_’.
  • Constants used in one file are defined within this file. A constant used in more than one file is defined in a header file. All constants are written in upper case.
  • Registers are considered as constants. Their names are in upper case. In most cases, the same acronyms as in the product reference manual document are used.
  • Names of peripheral functions are preceded by the corresponding peripheral acronym in upper case followed by an underscore. The first letter in each word is in upper case, for example SPI_SendData. Only one underscore is allowed in a function name to separate the peripheral acronym from the rest of the function name.
  • Functions used to initialize the PPP peripheral according to parameters specified in the header file are named PPP_Init, for example TIM2_Init.
  • Functions used to reset the PPP peripheral registers to their default values are named PPP_DeInit, for example TIM2_DeInit.
  • Functions used to enable or disable the specified PPP peripheral are named PPP_Cmd, for example SPI_Cmd.
  • Functions used to enable or disable an interrupt source of the specified PPP peripheral are named PPP_ITConfig, for example SPI_ITConfig.
  • Functions used to configure a peripheral function always end with the string ‘Config’, for example TIM2_ETRConfig
  • Functions used to check whether the specified PPP flag is set or reset are named PPP_GetFlagStatus, for example I2C_GetFlagStatus.
  • Functions used to clear a PPP flag are named PPP_ClearFlag, for example I2C_ClearFlag.
  • Functions used to check whether the specified PPP interrupt has occurred or not are named PPP_GetITStatus, for example TIM2_GetITStatus.
  • Functions used to clear a PPP interrupt pending bit are named PPP_ClearITPendingBit, for example TIM2_ClearITPendingBit.

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Coding rules

This section describes the coding rules used in the Standard Peripherals Library.

Variable types

Specific variable types are already defined with a fixed type and size. These types are defined in the file stm8s.h

#define
    __I     volatile
    const
    /*!< defines 'read only' permissions      */
#define     __O
    volatile
    /*!< defines 'write only' permissions     */
#define     __IO
    volatile
    /*!< defines 'read / write' permissions   */

/*!< Constant qualifier */
#ifdef _COSMIC_
#define __CONST  const
#else /* _RAISONANCE_*/
#define __CONST  code
#endif /*_COSMIC_*/

/*!< Signed integer types  */
typedef   signed char     int8_t;
typedef   signed short    int16_t;
typedef   signed long     int32_t;

/*!< Unsigned integer types  */
typedef unsigned char     uint8_t;
typedef unsigned short    uint16_t;
typedef unsigned long     uint32_t;

typedef enum {FALSE = 0, TRUE = !FALSE} bool;

typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;

typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;

typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;

Peripheral registers

Peripheral registers are accessed through a pointer of structure. Each peripheral has its own structure and pointer. All the structures and declarations are defined in the stm8s.h file.

Registers structure
The example below illustrates the Serial Peripheral Interface (SPI) registers structure declaration:

typedef struct SPI_struct
{
    __IO uint8_t CR1;    /*!< SPI control register 1 */
    __IO uint8_t CR2;    /*!< SPI control register 2 */
    __IO uint8_t CR3;    /*!< SPI DMA and interrupt control register */
    __IO uint8_t SR;     /*!< SPI status register */
    __IO uint8_t DR;     /*!< SPI data I/O register */
    __IO uint8_t CRCPR;  /*!< SPI CRC polynomial register */
    __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */
    __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */
}
SPI_TypeDef;

Register names are the register acronyms written in upper case for each peripheral.
RESERVEDi indicates a reserved field (i being an integer that indexes the reserved field).

Peripheral declaration
The following example shows the declaration of the SPI peripheral:

#define SPI1_BaseAddress      (uint16_t)0x5200
...
#define SPI1 ((SPI_TypeDef *) SPI1_BaseAddress)

The peripheral registers are accessed as follows:

SPI1->CR1 = 0x01;

Each peripheral has several dedicated registers which contain different flags. Registers are defined within a dedicated structure for each peripheral. Flags are defined as acronyms written in upper case and preceded by ‘PPP_FLAG_’. Flag definition is adapted to each peripheral case and defined in stm8l15x_ppp.h file.

Registers reset values
The reset values of all peripheral registers are defined as constants in the stm8s.h file. They are defined as acronyms written in upper-case into the form:

PPP_<register_name>_RESET_VALUE

Example:

#define SPI_CR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 1 reset value */
#define SPI_CR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 2 reset value */
#define SPI_CR3_RESET_VALUE    ((uint8_t)0x00) /*!< DMA and Interrupt Control Register reset value */
#define SPI_SR_RESET_VALUE     ((uint8_t)0x02) /*!< Status Register reset value */
#define SPI_DR_RESET_VALUE     ((uint8_t)0x00) /*!< Data Register reset value */
#define SPI_CRCPR_RESET_VALUE  ((uint8_t)0x07) /*!< Polynomial Register reset value */
#define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */
#define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */

Registers bits
All the peripheral registers bits are defined as constants in the stm8s.h file. They are defined as acronyms written in upper-case into the form:

PPP_<register_name>_<bit_name>

Example:

#define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */
#define SPI_CR1_SPE      ((uint8_t)0x40) /*!< Enable bits mask */
#define SPI_CR1_BR       ((uint8_t)0x38) /*!< Baud rate control mask */
#define SPI_CR1_MSTR     ((uint8_t)0x04) /*!< Master Selection mask */
#define SPI_CR1_CPOL     ((uint8_t)0x02) /*!< Clock Polarity mask */
#define SPI_CR1_CPHA     ((uint8_t)0x01) /*!< Clock Phase mask */

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Run-time checking

The Standard Peripherals Library implements run-time failure detection by checking the input values of all library functions. The run-time checking is achieved by using an assert_param macro. This macro is used in all library functions which have at least an input parameter. It allows the user to check that the input value lies within the defined parameter values.

BEEP_Init function example

stm8s_beep.c
void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency)
{
 /* Check parameter */
  assert_param(IS_BEEP_FREQUENCY(BEEP_Frequency));
...
}

stm8s_beep.h
#define IS_BEEP_FREQUENCY(FREQ) \
  (((FREQ) == BEEP_Frequency_1KHz) || \
   ((FREQ) == BEEP_Frequency_2KHz) || \
   ((FREQ) == BEEP_Frequency_4KHz))

If the expression passed to the assert_param macro is false, the assert_failed function is called, otherwise nothing happens.

Two implementation of assert_failed function are provided, depending on FULL_ASSERT define (declared in stm8l15x_conf.h file).

  • #define FULL_ASSERT (1) line is uncommented, if the expression passed to the assert_param macro is false, the assert_failed function will have as input the name of the source file and the source line number of the call that failed.
  • #define FULL_ASSERT (1) line is commented, if the expression passed to the assert_param macro is true, the assert_failed function will have takes no does not returns the name of the source file and the source line number of the call that failed.

The assert_param macro is implemented in stm8l15x_conf.h as follows:

#ifdef  USE_FULL_ASSERT

/**
  * @brief  The assert_param macro is used for function's parameters check.
  * @param expr: If expr is false, it calls assert_failed function
  *   which reports the name of the source file and the source
  *   line number of the call that failed.
  *   If expr is true, it returns no value.
  * @retval : None
  */
  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
  void assert_failed(uint8_t* file, uint32_t line);
#else
  #define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */

The assert_failed function is implemented in the main.c file or in any other user C files and can be modified by the user in order to take action when an error occurs.

#ifdef  USE_FULL_ASSERT

/**
  * @brief  Reports the name of the source file and the source line number
  *   where the assert_param error has occurred.
  * @param file: pointer to the source file name
  * @param line: assert_param error line source number
  * @retval : None
  */
void assert_failed(uint8_t* file, uint32_t line)
{
  /* User can add his own implementation to report the file name and line number,
     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */

  /* Infinite loop */
  while (1)
  {
  }
}
#endif

It is recommended to use run-time checking during application code development and debugging, and to remove it from the final application to improve code size and speed (because of the overhead it introduces).
However if the user wants to keep this functionality in his final application, he can re-use the assert_param macro defined within the library to test the parameter values before calling the library functions.

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STM8S/A Standard Peripherals Drivers: main_page.txt File Reference

  • File List
  • Globals

main_page.txt File Reference

STM8 Standard Peripherals Library: Footer

For complete documentation on STM8 8-bit Microcontrollers platform visit www.st.com


STM8S/A Standard Peripherals Drivers: Modules

Modules

Here is a list of all modules:
  • STM8S_StdPeriph_Driver
    • I2C_Private_Defines
    • Exported_types
    • MAP_FILE_Exported_Types_and_Constants
      • GPIO_Registers_Reset_Value
    • IWDG_Private_Define
    • IWDG_Private_Macros
    • IWDG_Exported_Types
    • IWDG_Exported_Functions
    • RST_Exported_Types
    • RST_Private_Macros
    • RST_Exported_functions
    • SPI_Exported_Types
    • SPI_Private_Macros
    • SPI_Exported_Functions
    • TIM1_Exported_Types
    • TIM1_Exported_Functions
    • TIM3_Exported_Types
    • TIM3_Exported_Functions
    • TIM4_Exported_Types
    • TIM4_Exported_Functions
    • TIM6_Exported_Types
    • TIM6_Private_Macros
    • TIM6_Exported_Functions
    • UART1_Exported_Types
    • UART1_Private_Macros
    • UART1_Exported_Functions
    • UART2_Exported_Types
    • UART2_Private_Macros
    • UART2_Exported_Functions
    • UART3_Exported_Types
    • UART3_Private_Macros
    • UART3_Exported_Functions
    • WWDG_Private_Macros
    • WWDG_Exported_Functions
    • ADC1_Public_Functions
    • ADC2_Public_Functions
    • AWU_Public_Functions
    • BEEP_Public_Functions
    • CAN_Public_Functions
    • CLK_Private_Constants
    • CLK_Public_Functions
    • EXTI_Public_Functions
    • FLASH_Public_functions
    • GPIO_Public_Functions
    • I2C_Public_Functions
    • ITC_Private_Functions
    • ITC_Public_Functions
    • RST_Public_Functions
    • SPI_Public_Functions
    • TIM1_Public_Functions
    • TIM2_Public_Functions
    • TIM3_Public_Functions
    • TIM4_Public_Functions
    • TIM5_Public_Functions
    • TIM6_Public_Functions
    • WWDG_Public_Functions
  • AWU_Registers_Reset_Value
  • AWU_Registers_Bits_Definition
  • BEEP_Registers_Reset_Value
  • BEEP_Registers_Bits_Definition
  • CLK_Registers_Reset_Value
  • CLK_Registers_Bits_Definition
  • TIM1_Registers_Reset_Value
  • TIM1_Registers_Bits_Definition
  • TIM2_Registers_Reset_Value
  • TIM2_Registers_Bits_Definition
  • TIM3_Registers_Reset_Value
  • TIM3_Registers_Bits_Definition
  • TIM4_Registers_Reset_Value
  • TIM4_Registers_Bits_Definition
  • TIM5_Registers_Reset_Value
  • TIM5_Registers_Bits_Definition
  • TIM6_Registers_Reset_Value
  • TIM6_Registers_Bits_Definition
  • I2C_Registers_Reset_Value
  • I2C_Registers_Bits_Definition
  • ITC_Registers_Reset_Value
  • CPU_Registers_Bits_Definition
  • EXTI_Registers_Reset_Value
  • EXTI_Registers_Bits_Definition
  • FLASH_Registers_Reset_Value
  • FLASH_Registers_Bits_Definition
  • IWDG_Registers_Reset_Value
  • WWDG_Registers_Reset_Value
  • WWDG_Registers_Bits_Definition
  • RST_Registers_Bits_Definition
  • SPI_Registers_Reset_Value
  • SPI_Registers_Bits_Definition
  • UART1_Registers_Reset_Value
  • UART1_Registers_Bits_Definition
  • UART2_Registers_Reset_Value
  • UART2_Registers_Bits_Definition
  • UART3_Registers_Reset_Value
  • UART3_Registers_Bits_Definition
  • CAN_Registers_Bits_Definition
  • CAN_Registers_Reset_Value
  • CFG_Registers_Reset_Value
  • CFG_Registers_Bits_Definition
  • MAP_FILE_Base_Addresses
  • ADC1_Exported_Types
  • ADC1_Private_Macros
  • ADC1_Exported_Functions
  • ADC2_Exported_Types
  • ADC2_Private_Macros
  • ADC2_Exported_Functions
  • AWU_Exported_Types
  • AWU_Exported_Constants
  • AWU_Private_Macros
  • AWU_Exported_Functions
  • BEEP_Exported_Types
  • BEEP_Exported_Constants
  • BEEP_Private_Macros
  • BEEP_Exported_Functions
  • CAN_Exported_Types
  • CAN_Private_Macros
  • CAN_Exported_Functions
  • CLK_Exported_Types
  • CLK_Exported_Constants
  • CLK_Private_Macros
  • CLK_Exported_functions
  • EXTI_Exported_Types
  • EXTI_Private_Macros
  • EXTI_Exported_Functions
  • FLASH_Exported_Constants
  • FLASH_Exported_Types
  • FLASH_Private_Macros
  • FLASH_Exported_Functions
  • GPIO_Exported_Types
  • GPIO_Private_Macros
  • GPIO_Exported_Functions
  • I2C_Exported_Types
  • I2C_Exported_Constants
  • I2C_Private_Macros
  • I2C_Exported_Functions
  • ITC_Exported_Types
  • ITC_Exported_Constants
  • ITC_Private_Macros
  • ITC_Exported_Functions
  • TIM2_Exported_Functions
  • TIM5_Exported_Functions
  • IWDG_Public_Functions
  • UART1_Public_Functions
  • UART2_Public_Functions
  • UART3_Public_Functions


STM8S/A Standard Peripherals Drivers: Related Pages

Related Pages

Here is a list of all related documentation pages:
  • STM8S/A Standard Peripheral's Drivers


Release Notes for STM8S/A Standard Peripherals Library Drivers

Release Notes for STM8S/A Standard Peripherals Library Drivers (StdPeriph_Driver)

Copyright © 2011 STMicroelectronics

Contents

  1. STM8S/A Standard Peripherals Library Drivers update history
  2. License

STM8S/A Standard Peripherals Library Drivers update history

V2.1.0 / 18-November-2011

Main Changes

  • Peripheral drivers updated to support the STM8S Value Line product family devices
    • Impacted drivers are CLK, FLASH, I2C and ITC
  • stm8s.h
    • Add definition of STM8S Value Line product family devices
    • Replace #include <intrist7.h> by #include <intrins.h> in the interrupt macro for raisonance compiler
    • Replace __wait_for_interrup() by __wait_for_interrupt() in the wfi macro definition with EWSTM8 toolchain

V2.0.0 / 25-February-2011

Main Changes

  • Overall peripheral drivers updated to support STM8A product family devices
  • stm8s.h
    • Add definition of STM8A product family devices
    • Add "error" directive to force device family choice
    • Updated to support IAR Embedded Workbench for STM8 (EWSTM8) toolchain specific declarations
    • Add HSE_Value definition depending on device choice
    • Add definition of Device on-chip RC oscillator frequencies HSI_VALUE and LSI_VALUE
    • Add EEPROM definition in compiler defines (COSMIC, RAISONANCE, IAR)
    • Add MEMCPY definition per devices family in RAISONANCE compiler defines
    • Add RAM_EXECUTION define to allow handling functions execution from RAM
    • Add IN_RAM macro to manage functions execution from RAM
    • Remove "stm8s_type.h" inclusion and replace it by the file content
    • Remove AWU_CSR_MR bit definition
    • Remove CANCCR register from CLK controller registers
    • Remove CLK_CANCCR_RESET_VALUE definition
    • Remove CLK_CANCCR_CANDIV definition
    • Remove SWIM_struct definition
    • Remove CAN_BTR2_CLKS bit definition
    • Remove SWIM_BaseAddress definition
    • INTERRUPT_HANDLER" macro added to manage interrupt vector declarations for all supported toochains.
  • stm8s_adc1.c/.h
    • Add the support of analog channel 12
    • Update ADC1_SetHighThreshold() and ADC1_SetLowThreshold() functions
  • stm8s_awu.c/.h
    • Remove AWU_ReInitCounter() function
    • Change "const" by "CONST" in the APR_Array and TBR_Array declarations
    • Change LSI_FREQUENCY_MIN value to 110000 instead of 100000
    • Change LSI_FREQUENCY_MAX value to 150000 instead of 200000
  • stm8s_beep.c/.h
    • Change LSI_FREQUENCY_MIN value to 110000 instead of 100000
    • Change LSI_FREQUENCY_MAX value to 150000 instead of 200000
  • stm8s_can.c/.h
    • Remove CAN_SelectClock() function
    • Update CAN_Init() function
    • Update CAN_Transmit() function
  • stm8s_clk.c/.h
    • Replace uc8 by CONST uint8_t in HSIDivFactor and CLKPrescTable declaration
    • Remove CLK_CANDivider_TypeDef
    • Remove CLK_CANConfig(CLK_CANDivider_TypeDef CLK_CANDivider) function
  • stm8s_flash.c/.h
    • Update FLASH_Lock() function by using the new definition of FLASH_MemType_TypeDef enum variables
    • Update FLASH_ProgramOptionByte() and FLASH_EraseOptionByte() functions to handle the case of ROP option byte and to check on EOP flag instead of HVOFF
    • Change OPERATION_TIMEOUT value to 0xFFFFF
    • Update FLASH_EraseBlock() function to use new definition of PointerAttr
    • Update FLASH_ProgramBlock() function to use new definition of PointerAttr
    • Add detailed description of execution from RAM using functions provided by this driver and with the different supported toolchains. For more information, refer to stm8s_flash.h and stm8s_flash.c files.
  • stm8s_gpio.c/.h
    • Update GPIO_Mode_TypeDef enum variables by hexadecimal definition
  • stm8s_I2c.c/.h
    • Update I2C_Flag_TypeDef definition enum variable
    • Update IS_I2C_CLEAR_FLAG_OK macro definition
    • Update I2C_Event_TypeDef definition and naming:
      • I2C_EVENT_MASTER_START_SENT changed to I2C_EVENT_MASTER_MODE_SELECT
      • I2C_EVENT_MASTER_ADDRESS_ACKED removed and replaced by I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED and I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
      • I2C_EVENT_MASTER_HEADER_ACKED changed to I2C_EVENT_MASTER_MODE_ADDRESS10
      • I2C_EVENT_SLAVE_ADDRESS_MATCHED removed and replaced by I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED and
        I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED and I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED
      • I2C_EVENT_SLAVE_BYTE_TRANSMITTING event added
    • Update I2C_ITPendingBit_TypeDef enum variabale definition
    • Update I2C_GetITStatus() function to check on the interrupt configuration bits
    • Add defines for REGISTER_Mask, REGISTER_SR1_Index, REGISTER_SR2_Index, FLAG_Mask and ITEN_Mask
    • Update I2C_ClearFlag() function to clear only the flags that are cleared by writing 0
    • Add IS_I2C_CLEAR_ITPENDINGBIT_OK macro
    • Update I2C_ClearITPendingBit() function to clear only the flags that are cleared by writing 0
    • Update I2C_GetFlagStatus() function
    • Add new function I2C_GetLastEvent()
    • Update I2C_CheckEvent() function
    • Add detailed description of I2C events and how to manage them using the functions provided by this driver. For more information, refer to stm8s_i2c.h and stm8s_i2c.c files
  • stm8s_itc.c /.h
    • Update ITC_GetCPUCC() function to support EWSTM8 toolchain
  • stm8s_spi.c/.h
    • Update SPI_CalculateCRCCmd() function by removing the the disable of SPI (should be done outside the function)
  • stm8s_uartx.c/.h
    • Remove CLK driver inclusion

V1.1.1 / 06-05-2009

Main Changes

  • General
    • Project template updated for both STVD and RIDE toolchains
    • Almost peripheral examples reviewed and validated with both Cosmic and Raisonance compilers
  • Library
    • stm8s.h:
      • __CONST definition added for Cosmic and Raisonance compilers
      • TINY definition added for Cosmic and Raisonance compilers
      • NEAR definition added for Raisonance compilers
      • CAN registers declaration updated
      • ADC1 registers declaration updated
    • stm8s_adc1.h:
      • IS_ADC1_BUFFER_OK macro definition updated
    • stm8s_beep.c:
      • BEEP_Init function updated: BEEP->CSR |= BEEP_CSR_BEEPEN; removed from init function
    • stm8s_can.c/.h:
      • Private variables declaration changed to volatile
      • CAN_DeInit function updated
      • CAN_Receive function updated
      • CAN_FilterInit funtion updated
      • CAN_Transmit function updated
      • CAN_IT_TypeDef enum updated: CAN_IT_ERR and CAN_IT_LEC definition updated to avoid ANSI check error with Cosmic
    • stm8s_clk.h:
      • CLK_Peripheral_TypeDef enum updated:
        - CLK_PERIPHERAL_UART1 definition updated and conditioned by the device to use
    • stm8s_gpio.h:
      • The GPIO_Mode_TypeDef enum element definition updated:
        - GPIO_MODE_OUT_OD_LOW_FAST
        - GPIO_MODE_OUT_PP_LOW_FAST
        - GPIO_MODE_OUT_OD_LOW_SLOW
        - GPIO_MODE_OUT_PP_LOW_SLOW
        - GPIO_MODE_OUT_OD_HIZ_FAST
        - GPIO_MODE_OUT_PP_HIGH_FAST
        - GPIO_MODE_OUT_OD_HIZ_SLOW
        - GPIO_MODE_OUT_PP_HIGH_SLOW
    • stm8s_tim3.h:
      • IS_TIM3_CLEAR_FLAG_OK macro definition updated
      • TIM3_GetITStatus and TIM3_GetFlagStatus functions updated: Local varaiables changed to volatile
    • stm8s_usart1.h:
      • UART1_IT_TypeDef enum description updated to give more details on the element values convention.
    • stm8s_usart2.h:
      • UART2_IT_TypeDef enum description updated to give more details on the element values convention.
    • stm8s_usart3.h:
      • UART3_IT_TypeDef enum description updated to give more details on the element values convention.
    • stm8s_gpio.c:
      • GPIO_ReadInputPin function updated
    • stm8s_i2c.c:
      • I2C_ClearFlag function description and code updated
      • I2C_ClearITPendingBit function description and code updated
    • stm8s_itc.c:
      • The private function ITC_GetCPUCC definition updated for Raisonance
    • stm8s_tim1.c:
      • TIM1_GetITStatus and TIM1_GetFlagStatus functions updated: Local varaiables changed to volatile
    • stm8s_tim2.c:
      • TIM2_GetITStatus and TIM2_GetFlagStatus functions updated:Local varaiables changed to volatile
    • stm8s_tim5.c:
      • TIM5_GetITStatus and TIM5_GetFlagStatus functions updated:Local varaiables changed to volatile
    • stm8s_tim6.c:
      • TIM6_GetITStatus and TIM6_GetFlagStatus functions updated: Local varaiables changed to volatile
  • Examples
    • Almost examples were updated with both Cosmic and Raisonance compilers using STVD toolchain.
      • Exception is made for the following FLASH examples:
        - FLASH_EraseBlockOnFlashProgramMemory
        - FLASH_WriteEraseBlockOnDataEepromMemory
        - FLASH_BlockOperationOnFlashProgramMemory
        --> Dependency related to linkerfile edition
    • All examples readme.txt files were updated :
      • @par Directory contents section updated
      • @par Hardware and Software environment section updated
      • @par How to use it ? section updated
    • Mono LCD driver updated: mono_lcd.c
      • LCD_SendByte function updated by adding a delay (LCD_Delay(80);) after sending the last byte
    • Micro Sd driver updated : micro_sd.c
      • MSD_WriteByte function updated to support 2G SD card (type: kingston)
    • AWU example updated
      • AWU_AutoLSICalibration private function removed and replaced by u32 LSIMeasurment to measure LSI w/ either TIM1 or TIM3 depending on the used device
    • BEEP example updated
      • BEEP_AutoLSICalibration private function removed and replaced by u32 LSIMeasurment to measure LSI w/ either TIM1 or TIM3 depending on the used device
      • Add BEEP_Cmd function call in the example due to BEEP_Init function update.
    • CLK example
      • CLK_ClockSelection updated
    • SPI example
      • SPI_FastCommunication example renamed to SPI_FastCommunicationMicroSD
  • Projects
    • Project templates updated for STVD and RIDE toolchain
      • asm_functions.asm file removed from both projects STVD with Raisonance and RIDE7
      • stm8s_it.c file updated to support both Cosmic and Raisonance compiler
      • stm8_interrupt_vector.c and stm8s_it.h files were updated to use @far instead of @near
      • Optimization option updated for STVD with Raisonance project
      • SCINAME(STM8) linker option added for STVD with Raisonance project
      • STM8_OB.asm file added within RIDE7 project to configure option bytes

V1.1.0 / 02-27-2009

Main Changes

  • General
    • The STM8S Firmware library supports now STM8S Performance line (STM8S208 and STM8S207 sub-families), Access line (STM8S105 and STM8S103 sub-families) and STM8S903.
    • RN0022 "STM8S firmware library Release note" document merged in "stm8s_fwlib_um.chm" user manual.
    • "stm8s_fwlib_um.chm" user manual: structure and content enhanced to provide complete information about the library and how it can be used.
    • List of peripheral examples reviewed: redundant examples were removed (same example provided for two or more peripherals) and others were added
  • Library
    • stm8_map.h renamed to stm8.h and the following modification were performed:
      • add the library configuration section
      • add definition of the used compiler
      • add definition of the library supported devices
      • add definition of the standard peripheral driver use
      • add definition of pointer declaration for FLASH routines
      • Update peripheral registers and bit definition to support STM8S103 & STM8S903 devices: TIM5 & TIM6 registers and structures added
      • OPT base address updated
      • Peripheral declaration conditioned by supported devices
      • add macros added for interrupts and bits handling (content of legacy stm8s_macro.h file)
    • stm8s_macro.h file removed and its content is copied to stm8s.h file
    • stm8s_conf.h:
      • Include stm8.h file instead of stm8s_type.h and stm8s_macro.h files
      • #define DEBUG removed
      • Cosmic section definition removed
      • HSE value definition conditioned by supported devices
      • CAN definition added
      • TIM5 & TIM6 definition added
      • Peripheral definition conditioned by supported devices
      • add section for peripheral header file inclusion (content of legacy stm8s_lib.h file)
    • stm8s_lib.h file removed and its content is copied to stm8s_conf.h file
    • All peripheral drivers (tm8s_ppp.c)
      • '#include "stm8s_map.h"' replaced by '#include "stm8s.h"'
      • Cosmic sections removed, except from stm8s_falsh.c
    • stm8s_awu.h/.c:
      • AWU_AutoLSICalibration function removed and added in AWU example
    • stm8s_beep.h/.c:
      • BEEP_AutoLSICalibration function removed and added in BEEP example
    • stm8s_can.h/.c:
      • CAN driver added
    • stm8s_clk.h:
      • CLK_Peripheral_TypeDef enum updated :
        • CLK_PERIPHERAL_USART replaced by CLK_PERIPHERAL_UART1
        • CLK_PERIPHERAL_LINUART replaced by CLK_PERIPHERAL_UART2
        • CLK_PERIPHERAL_UART3, CLK_PERIPHERAL_TIMER6 and CLK_PERIPHERAL_TIMER5 added
      • IS_CLK_PERIPHERAL_OK macro updated
    • stm8s_flash.h/.c:
      • FLASH_ProgramWord function updated to write data in big endian format
      • Only FLASH_EraseBlock() & FLASH_ProgramBlock() functions can be executed from RAM
      • FLASH_EraseBlock()function is updated to support the lower memory size devices
      • Add a check on the HVOFF flag in the FLASH_EraseBlock and FLASH_ProgramBlock functions before coming back to fetch from flash
      • Parameter FLASH_STATUS_END_HIGH_VOLTAGE added in the FLASH_Status_TypeDef enumeration
    • stm8s_i2c.h :
      • IS_I2C_INPUT_CLOCK_FREQ_OK macro updated
    • stm8s_itc.h/c:
      • ITC_Irq_TypeDef updated: thefollowing parameters removed:
        - ITC_IRQ_USART_TX
        - ITC_IRQ_USART_RX
        - ITC_IRQ_LINUART_TX
        - ITC_IRQ_LINUART_RX
        - ITC_IRQ_ADC , and the following parameters added :
        - ITC_IRQ_UART2_RX
        - ITC_IRQ_UART2_TX
        - ITC_IRQ_UART3_TX
        - ITC_IRQ_UART3_RX
        - ITC_IRQ_ADC2
        - ITC_IRQ_ADC1
        - ITC_IRQ_TIM6_OVFTRI
        - ITC_IRQ_PORTF
      • ITC_SetSoftwarePriority() function updated
  • Examples
    • All examples readme.txt files were updated :
      • @par Directory contents section updated
      • @par Hardware and Software environment section updated
      • @par How to use it ? section updated
    • Micro SD driver
      • microsd.c file: MSD_WriteBlock function updated to support buffer size lower than block size for the MicroSD memory card
    • ADC1 examples removed (equivalent examples are available for ADC2)
    • AWU example updated
      • AWU_AutoLSICalibration private function added to calibrate LSI w/ TIM3
    • BEEP example updated
      • BEEP_AutoLSICalibration private function added to calibrate LSI w/ TIM3
    • CAN example added
    • CLK examples
      • ManualClcokSwitch example removed
    • FLASH examples updated to support STM8S105, STM8S103 and STM8S903
      • Rename and update the example " FLASH_WriteErase" by "FLASH_WriteEraseBlockOnDataEepromMemory"
      • Rename and update the example " FLASH_EraseBlock" by "FLASH_EraseBlockOnFlashProgramMemory"
      • FLASH_BlockOperationOnFlashProgramMemory example added to show the possibility to continue execution from RAM while program operation on FLASH Program is on going
    • I2C_EEPROMRandomRead, I2C_EEPROMReadWrite and I2C_EEPROMSequentialRead examples merged in one single example: I2C_EEPROM
      • add driver for I2C EEPROM: i2c_ee.c/.h
    • TIM3 examples removed (equivalent examples are available for TIM1 and TIM2)
    • TIM5 example added
    • UART2 & UART3 examples removed (equivalent examples are available for UART1)
  • Projects
    • Project templates updated for STVD and RIDE toolchain
      • project.stw: one Workspace file including five projects related to the FW Lib STM8S supported devices
        - stm8s103.stp Project file for STM8S103 product
        - stm8s105.stp Project file for STM8S105 product
        - stm8s207.stp Project file for STM8S207 product
        - stm8s208.stp Project file for STM8S208 product
        - stm8s903.stp Project file for STM8S903 product (not available on RIDE)

V1.0.1 - 09/22/2008

Main Changes

  • I2C driver Update
    • stm8s_i2c.c: I2C_ClearFlag, I2C_GetITStatus and I2C_ClearITPendingBit functions updated
    • stm8s_i2c.h: I2C_IT_TypeDef enumeration updated & new I2C_ITPendingBit_TypeDef enumeration added
  • I2C IAP, SPI IAP, UART3 Lin & TIM3 OCActiveMode examples removed from the package.
  • TIMx_GetCapturex functions updated on TIM1, TIM2 and TIM3
  • CLK driver updated (CLK_AdjustHSICalibrationValue function optimized)
  • Projects template updated
  • stm8s_map.h file updated (CAN registers structure added)
  • User manual updated: new section added (Usage of STM8S Firmware Library Examples)

V1.0.0 - 08/15/2008

Main Changes

  • Created

    License

    The enclosed firmware and all the related documentation are not covered by a License Agreement, if you need such License you can contact your local STMicroelectronics office.

    THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

    For complete documentation on STMicroelectronics Microcontrollers visit www.st.com


STM8S/A Standard Peripherals Drivers: stdperiphlib_drivers.txt File Reference

  • File List
  • Globals

stdperiphlib_drivers.txt File Reference

STM8 Standard Peripherals Library: Footer

For complete documentation on STM8 8-bit Microcontrollers platform visit www.st.com


STM8S/A Standard Peripherals Drivers: stm8s.h Source File

  • File List
  • Globals
  • STM8S_StdPeriph_Driver
  • inc

stm8s.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm8s.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all HW registers definitions and memory mapping.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_H
00024 #define __STM8S_H
00025
00026 /** @addtogroup STM8S_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /* Uncomment the line below according to the target STM8S or STM8A device used in your
00031    application. */
00032
00033  /* #define STM8S208 */      /*!< STM8S High density devices with CAN */
00034  /* #define STM8S207 */      /*!< STM8S High density devices without CAN */
00035  /* #define STM8S007 */      /*!< STM8S Value Line High density devices */
00036  /* #define STM8AF52Ax */    /*!< STM8A High density devices with CAN */
00037  /* #define STM8AF62Ax */    /*!< STM8A High density devices without CAN */
00038  /* #define STM8S105 */      /*!< STM8S Medium density devices */
00039  /* #define STM8S005 */      /*!< STM8S Value Line Medium density devices */
00040  /* #define STM8AF626x */    /*!< STM8A Medium density devices */
00041  /* #define STM8S103 */      /*!< STM8S Low density devices */
00042  /* #define STM8S003 */      /*!< STM8S Value Line Low density devices */
00043  /* #define STM8S903 */      /*!< STM8S Low density devices */
00044
00045 /*   Tip: To avoid modifying this file each time you need to switch between these
00046         devices, you can define the device in your toolchain compiler preprocessor.
00047
00048   - High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,
00049     STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory
00050     density ranges between 32 to 128 Kbytes
00051   - Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68,
00052     STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory
00053     density ranges between 8 to 32 Kbytes
00054   - High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx microcontrollers
00055     where the Flash memory density ranges between 32 to 128 Kbytes.
00056   - Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers
00057     where the Flash memory density ranges between 16 to 32-Kbytes.
00058   - Low-Density STM8S devices are the STM8S103xx, STM8S003 and STM8S903xx microcontrollers
00059     where the Flash density is 8 Kbytes. */
00060
00061 #if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \
00062     !defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \
00063     !defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \
00064     !defined (STM8S003)&& !defined (STM8S005)
00065  #error "Please select first the target STM8S/A device used in your application (in stm8s.h file)"
00066 #endif
00067
00068 /******************************************************************************/
00069 /*                   Library configuration section                            */
00070 /******************************************************************************/
00071 /* Check the used compiler */
00072 #if defined(__CSMC__)
00073  #define _COSMIC_
00074 #elif defined(__RCST7__)
00075  #define _RAISONANCE_
00076 #elif defined(__ICCSTM8__)
00077  #define _IAR_
00078 #else
00079  #error "Unsupported Compiler!"          /* Compiler defines not found */
00080 #endif
00081
00082 #if !defined  USE_STDPERIPH_DRIVER
00083 /* Comment the line below if you will not use the peripherals drivers.
00084    In this case, these drivers will not be included and the application code will be
00085    based on direct access to peripherals registers */
00086  #define USE_STDPERIPH_DRIVER
00087 #endif
00088
00089 /**
00090   * @brief  In the following line adjust the value of External High Speed oscillator (HSE)
00091    used in your application
00092
00093    Tip: To avoid modifying this file each time you need to use different HSE, you
00094         can define the HSE value in your toolchain compiler preprocessor.
00095   */
00096 #if !defined  HSE_Value
00097  #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
00098      defined (STM8AF62Ax)
00099   #define HSE_VALUE ((u32)24000000) /* Value of the External oscillator in Hz*/
00100  #else
00101   #define HSE_VALUE ((u32)16000000) /* Value of the External oscillator in Hz*/
00102  #endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax */
00103 #endif /* HSE_Value */
00104
00105 /**
00106   * @brief  Definition of Device on-chip RC oscillator frequencies
00107   */
00108 #define HSI_VALUE   ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */
00109 #define LSI_VALUE   ((uint32_t)128000)   /*!< Typical Value of the LSI in Hz */
00110
00111 #ifdef _COSMIC_
00112  #define FAR  @far
00113  #define NEAR @near
00114  #define TINY @tiny
00115  #define EEPROM @eeprom
00116  #define CONST  const
00117 #elif defined (_RAISONANCE_) /* __RCST7__ */
00118  #define FAR  far
00119  #define NEAR data
00120  #define TINY page0
00121  #define EEPROM eeprom
00122  #define CONST  code
00123  #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
00124      defined (STM8AF62Ax)
00125    /*!< Used with memory Models for code higher than 64K */
00126   #define MEMCPY fmemcpy
00127  #else /* STM8S903, STM8S103, STM8S003, STM8S105, STM8AF626x */
00128   /*!< Used with memory Models for code less than 64K */
00129   #define MEMCPY memcpy
00130  #endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */
00131 #else /*_IAR_*/
00132  #define FAR  __far
00133  #define NEAR __near
00134  #define TINY __tiny
00135  #define EEPROM __eeprom
00136  #define CONST  const
00137 #endif /* __CSMC__ */
00138
00139 /* For FLASH routines, select whether pointer will be declared as near (2 bytes,
00140    to handle code smaller than 64KB) or far (3 bytes, to handle code larger
00141    than 64K) */
00142
00143 #if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined (STM8S003) || \
00144     defined (STM8S903) || defined (STM8AF626x)
00145 /*!< Used with memory Models for code smaller than 64K */
00146  #define PointerAttr NEAR
00147 #else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */
00148 /*!< Used with memory Models for code higher than 64K */
00149  #define PointerAttr FAR
00150 #endif /* STM8S105 or STM8S103 or STM8S003 or STM8S903 or STM8AF626x */
00151
00152 /* Uncomment the line below to enable the FLASH functions execution from RAM */
00153 #if !defined (RAM_EXECUTION)
00154 /* #define RAM_EXECUTION  (1) */
00155 #endif /* RAM_EXECUTION */
00156
00157 #ifdef RAM_EXECUTION
00158  #ifdef _COSMIC_
00159    #define IN_RAM(a) a
00160  #elif defined (_RAISONANCE_) /* __RCST7__ */
00161    #define IN_RAM(a) a inram
00162  #else /*_IAR_*/
00163   #define IN_RAM(a) __ramfunc a
00164  #endif /* _COSMIC_ */
00165 #else
00166   #define IN_RAM(a) a
00167 #endif /* RAM_EXECUTION */
00168
00169 /*!< [31:16] STM8S Standard Peripheral Library main version V2.1.0*/
00170 #define __STM8S_STDPERIPH_VERSION_MAIN   ((uint8_t)0x02) /*!< [31:24] main version */
00171 #define __STM8S_STDPERIPH_VERSION_SUB1   ((uint8_t)0x01) /*!< [23:16] sub1 version */
00172 #define __STM8S_STDPERIPH_VERSION_SUB2   ((uint8_t)0x00) /*!< [15:8]  sub2 version */
00173 #define __STM8S_STDPERIPH_VERSION_RC     ((uint8_t)0x00) /*!< [7:0]  release candidate */
00174 #define __STM8S_STDPERIPH_VERSION       ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\
00175                                           |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\
00176                                           |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\
00177                                           |(__STM8S_STDPERIPH_VERSION_RC))
00178
00179 /******************************************************************************/
00180
00181 /* Includes ------------------------------------------------------------------*/
00182
00183 /* Exported types and constants ----------------------------------------------*/
00184
00185 /** @addtogroup Exported_types
00186   * @{
00187   */
00188
00189 /**
00190  * IO definitions
00191  *
00192  * define access restrictions to peripheral registers
00193  */
00194 #define     __I     volatile const   /*!< defines 'read only' permissions     */
00195 #define     __O     volatile         /*!< defines 'write only' permissions    */
00196 #define     __IO    volatile         /*!< defines 'read / write' permissions  */
00197
00198 /*!< Signed integer types  */
00199 typedef   signed char     int8_t;
00200 typedef   signed short    int16_t;
00201 typedef   signed long     int32_t;
00202
00203 /*!< Unsigned integer types  */
00204 typedef unsigned char     uint8_t;
00205 typedef unsigned short    uint16_t;
00206 typedef unsigned long     uint32_t;
00207
00208 /*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */
00209
00210 typedef int32_t  s32;
00211 typedef int16_t s16;
00212 typedef int8_t  s8;
00213
00214 typedef uint32_t  u32;
00215 typedef uint16_t u16;
00216 typedef uint8_t  u8;
00217
00218
00219 typedef enum {FALSE = 0, TRUE = !FALSE} bool;
00220
00221 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
00222
00223 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
00224 #define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
00225
00226 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
00227
00228 #define U8_MAX     (255)
00229 #define S8_MAX     (127)
00230 #define S8_MIN     (-128)
00231 #define U16_MAX    (65535u)
00232 #define S16_MAX    (32767)
00233 #define S16_MIN    (-32768)
00234 #define U32_MAX    (4294967295uL)
00235 #define S32_MAX    (2147483647)
00236 #define S32_MIN    (-2147483648uL)
00237
00238 /**
00239   * @}
00240   */
00241
00242 /** @addtogroup MAP_FILE_Exported_Types_and_Constants
00243   * @{
00244   */
00245
00246 /******************************************************************************/
00247 /*                          IP registers structures                           */
00248 /******************************************************************************/
00249
00250 /**
00251   * @brief  General Purpose I/Os (GPIO)
00252   */
00253 typedef struct GPIO_struct
00254 {
00255   __IO uint8_t ODR; /*!< Output Data Register */
00256   __IO uint8_t IDR; /*!< Input Data Register */
00257   __IO uint8_t DDR; /*!< Data Direction Register */
00258   __IO uint8_t CR1; /*!< Configuration Register 1 */
00259   __IO uint8_t CR2; /*!< Configuration Register 2 */
00260 }
00261 GPIO_TypeDef;
00262
00263 /** @addtogroup GPIO_Registers_Reset_Value
00264   * @{
00265   */
00266
00267 #define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)
00268 #define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
00269 #define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
00270 #define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
00271
00272 /**
00273   * @}
00274   */
00275
00276 /*----------------------------------------------------------------------------*/
00277 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
00278     defined(STM8S903) || defined(STM8AF626x)
00279 /**
00280   * @brief  Analog to Digital Converter (ADC1)
00281   */
00282  typedef struct ADC1_struct
00283  {
00284   __IO uint8_t DB0RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00285   __IO uint8_t DB0RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00286   __IO uint8_t DB1RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00287   __IO uint8_t DB1RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00288   __IO uint8_t DB2RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00289   __IO uint8_t DB2RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00290   __IO uint8_t DB3RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00291   __IO uint8_t DB3RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00292   __IO uint8_t DB4RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00293   __IO uint8_t DB4RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00294   __IO uint8_t DB5RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00295   __IO uint8_t DB5RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00296   __IO uint8_t DB6RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00297   __IO uint8_t DB6RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00298   __IO uint8_t DB7RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00299   __IO uint8_t DB7RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00300   __IO uint8_t DB8RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00301   __IO uint8_t DB8RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00302   __IO uint8_t DB9RH;         /*!< ADC1 Data Buffer Register (MSB)  */
00303   __IO uint8_t DB9RL;         /*!< ADC1 Data Buffer Register (LSB)  */
00304   uint8_t RESERVED[12];       /*!< Reserved byte */
00305   __IO uint8_t CSR;           /*!< ADC1 control status register */
00306   __IO uint8_t CR1;           /*!< ADC1 configuration register 1 */
00307   __IO uint8_t CR2;           /*!< ADC1 configuration register 2 */
00308   __IO uint8_t CR3;           /*!< ADC1 configuration register 3  */
00309   __IO uint8_t DRH;           /*!< ADC1 Data high */
00310   __IO uint8_t DRL;           /*!< ADC1 Data low */
00311   __IO uint8_t TDRH;          /*!< ADC1 Schmitt trigger disable register high */
00312   __IO uint8_t TDRL;          /*!< ADC1 Schmitt trigger disable register low */
00313   __IO uint8_t HTRH;          /*!< ADC1 high threshold register High*/
00314   __IO uint8_t HTRL;          /*!< ADC1 high threshold register Low*/
00315   __IO uint8_t LTRH;          /*!< ADC1 low threshold register high */
00316   __IO uint8_t LTRL;          /*!< ADC1 low threshold register low */
00317   __IO uint8_t AWSRH;         /*!< ADC1 watchdog status register high */
00318   __IO uint8_t AWSRL;         /*!< ADC1 watchdog status register low */
00319   __IO uint8_t AWCRH;         /*!< ADC1 watchdog control register high */
00320   __IO uint8_t AWCRL;         /*!< ADC1 watchdog control register low */
00321  }
00322  ADC1_TypeDef;
00323
00324 /** @addtogroup ADC1_Registers_Reset_Value
00325   * @{
00326   */
00327  #define  ADC1_CSR_RESET_VALUE    ((uint8_t)0x00)
00328  #define  ADC1_CR1_RESET_VALUE    ((uint8_t)0x00)
00329  #define  ADC1_CR2_RESET_VALUE    ((uint8_t)0x00)
00330  #define  ADC1_CR3_RESET_VALUE    ((uint8_t)0x00)
00331  #define  ADC1_TDRL_RESET_VALUE   ((uint8_t)0x00)
00332  #define  ADC1_TDRH_RESET_VALUE   ((uint8_t)0x00)
00333  #define  ADC1_HTRL_RESET_VALUE   ((uint8_t)0x03)
00334  #define  ADC1_HTRH_RESET_VALUE   ((uint8_t)0xFF)
00335  #define  ADC1_LTRH_RESET_VALUE   ((uint8_t)0x00)
00336  #define  ADC1_LTRL_RESET_VALUE   ((uint8_t)0x00)
00337  #define  ADC1_AWCRH_RESET_VALUE  ((uint8_t)0x00)
00338  #define  ADC1_AWCRL_RESET_VALUE  ((uint8_t)0x00)
00339 /**
00340   * @}
00341   */
00342
00343 /** @addtogroup ADC1_Registers_Bits_Definition
00344   * @{
00345   */
00346  #define ADC1_CSR_EOC     ((uint8_t)0x80) /*!< End of Conversion mask */
00347  #define ADC1_CSR_AWD     ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */
00348  #define ADC1_CSR_EOCIE   ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
00349  #define ADC1_CSR_AWDIE   ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable mask */
00350  #define ADC1_CSR_CH      ((uint8_t)0x0F) /*!< Channel selection bits mask */
00351
00352  #define ADC1_CR1_SPSEL   ((uint8_t)0x70) /*!< Prescaler selection mask */
00353  #define ADC1_CR1_CONT    ((uint8_t)0x02) /*!< Continuous conversion mask */
00354  #define ADC1_CR1_ADON    ((uint8_t)0x01) /*!< A/D Converter on/off mask */
00355
00356  #define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
00357  #define ADC1_CR2_EXTSEL  ((uint8_t)0x30) /*!< External event selection mask */
00358  #define ADC1_CR2_ALIGN   ((uint8_t)0x08) /*!< Data Alignment mask */
00359  #define ADC1_CR2_SCAN    ((uint8_t)0x02) /*!< Scan mode mask */
00360
00361  #define ADC1_CR3_DBUF    ((uint8_t)0x80) /*!< Data Buffer Enable mask */
00362  #define ADC1_CR3_OVR     ((uint8_t)0x40) /*!< Overrun Status Flag mask */
00363
00364 #endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */
00365 /**
00366   * @}
00367   */
00368
00369 /*----------------------------------------------------------------------------*/
00370 /**
00371   * @brief  Analog to Digital Converter (ADC2)
00372   */
00373 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
00374  typedef struct ADC2_struct
00375  {
00376   __IO uint8_t CSR;        /*!< ADC2 control status register */
00377   __IO uint8_t CR1;        /*!< ADC2 configuration register 1 */
00378   __IO uint8_t CR2;        /*!< ADC2 configuration register 2 */
00379   uint8_t RESERVED;        /*!< Reserved byte */
00380   __IO uint8_t DRH;        /*!< ADC2 Data high */
00381   __IO uint8_t DRL;        /*!< ADC2 Data low */
00382   __IO uint8_t TDRH;       /*!< ADC2 Schmitt trigger disable register high  */
00383   __IO uint8_t TDRL;       /*!< ADC2 Schmitt trigger disable register low */
00384  }
00385  ADC2_TypeDef;
00386
00387 /** @addtogroup ADC2_Registers_Reset_Value
00388   * @{
00389   */
00390  #define  ADC2_CSR_RESET_VALUE  ((uint8_t)0x00)
00391  #define  ADC2_CR1_RESET_VALUE  ((uint8_t)0x00)
00392  #define  ADC2_CR2_RESET_VALUE  ((uint8_t)0x00)
00393  #define  ADC2_TDRL_RESET_VALUE ((uint8_t)0x00)
00394  #define  ADC2_TDRH_RESET_VALUE ((uint8_t)0x00)
00395 /**
00396   * @}
00397   */
00398
00399 /** @addtogroup ADC2_Registers_Bits_Definition
00400   * @{
00401   */
00402  #define ADC2_CSR_EOC     ((uint8_t)0x80) /*!< End of Conversion mask */
00403  #define ADC2_CSR_EOCIE   ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
00404  #define ADC2_CSR_CH      ((uint8_t)0x0F) /*!< Channel selection bits mask */
00405
00406  #define ADC2_CR1_SPSEL   ((uint8_t)0x70) /*!< Prescaler selection mask */
00407  #define ADC2_CR1_CONT    ((uint8_t)0x02) /*!< Continuous conversion mask */
00408  #define ADC2_CR1_ADON    ((uint8_t)0x01) /*!< A/D Converter on/off mask */
00409
00410  #define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
00411  #define ADC2_CR2_EXTSEL  ((uint8_t)0x30) /*!< External event selection mask */
00412  #define ADC2_CR2_ALIGN   ((uint8_t)0x08) /*!< Data Alignment mask */
00413
00414 #endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) || (STM8AF52Ax) */
00415 /**
00416   * @}
00417   */
00418
00419 /*----------------------------------------------------------------------------*/
00420
00421 /**
00422   * @brief  Auto Wake Up (AWU) peripheral registers.
00423   */
00424 typedef struct AWU_struct
00425 {
00426   __IO uint8_t CSR; /*!< AWU Control status register */
00427   __IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */
00428   __IO uint8_t TBR; /*!< AWU Time base selection register */
00429 }
00430 AWU_TypeDef;
00431
00432 /** @addtogroup AWU_Registers_Reset_Value
00433   * @{
00434   */
00435 #define AWU_CSR_RESET_VALUE ((uint8_t)0x00)
00436 #define AWU_APR_RESET_VALUE ((uint8_t)0x3F)
00437 #define AWU_TBR_RESET_VALUE ((uint8_t)0x00)
00438
00439 /**
00440   * @}
00441   */
00442
00443 /** @addtogroup AWU_Registers_Bits_Definition
00444   * @{
00445   */
00446
00447 #define AWU_CSR_AWUF    ((uint8_t)0x20) /*!< Interrupt flag mask */
00448 #define AWU_CSR_AWUEN   ((uint8_t)0x10) /*!< Auto Wake-up enable mask */
00449 #define AWU_CSR_MSR     ((uint8_t)0x01) /*!< LSI Measurement enable mask */
00450
00451 #define AWU_APR_APR     ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */
00452
00453 #define AWU_TBR_AWUTB   ((uint8_t)0x0F) /*!< Timebase selection mask */
00454
00455 /**
00456   * @}
00457   */
00458
00459 /*----------------------------------------------------------------------------*/
00460 /**
00461   * @brief  Beeper (BEEP) peripheral registers.
00462   */
00463
00464 typedef struct BEEP_struct
00465 {
00466   __IO uint8_t CSR; /*!< BEEP Control status register */
00467 }
00468 BEEP_TypeDef;
00469
00470 /** @addtogroup BEEP_Registers_Reset_Value
00471   * @{
00472   */
00473 #define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)
00474 /**
00475   * @}
00476   */
00477
00478 /** @addtogroup BEEP_Registers_Bits_Definition
00479   * @{
00480   */
00481 #define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */
00482 #define BEEP_CSR_BEEPEN  ((uint8_t)0x20) /*!< Beeper enable mask */
00483 #define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */
00484 /**
00485   * @}
00486   */
00487
00488 /*----------------------------------------------------------------------------*/
00489 /**
00490   * @brief  Clock Controller (CLK)
00491   */
00492 typedef struct CLK_struct
00493 {
00494   __IO uint8_t ICKR;     /*!< Internal Clocks Control Register */
00495   __IO uint8_t ECKR;     /*!< External Clocks Control Register */
00496   uint8_t RESERVED;      /*!< Reserved byte */
00497   __IO uint8_t CMSR;     /*!< Clock Master Status Register */
00498   __IO uint8_t SWR;      /*!< Clock Master Switch Register */
00499   __IO uint8_t SWCR;     /*!< Switch Control Register */
00500   __IO uint8_t CKDIVR;   /*!< Clock Divider Register */
00501   __IO uint8_t PCKENR1;  /*!< Peripheral Clock Gating Register 1 */
00502   __IO uint8_t CSSR;     /*!< Clock Security System Register */
00503   __IO uint8_t CCOR;     /*!< Configurable Clock Output Register */
00504   __IO uint8_t PCKENR2;  /*!< Peripheral Clock Gating Register 2 */
00505   uint8_t RESERVED1;     /*!< Reserved byte */
00506   __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */
00507   __IO uint8_t SWIMCCR;  /*!< SWIM clock control register */
00508 }
00509 CLK_TypeDef;
00510
00511 /** @addtogroup CLK_Registers_Reset_Value
00512   * @{
00513   */
00514
00515 #define CLK_ICKR_RESET_VALUE     ((uint8_t)0x01)
00516 #define CLK_ECKR_RESET_VALUE     ((uint8_t)0x00)
00517 #define CLK_CMSR_RESET_VALUE     ((uint8_t)0xE1)
00518 #define CLK_SWR_RESET_VALUE      ((uint8_t)0xE1)
00519 #define CLK_SWCR_RESET_VALUE     ((uint8_t)0x00)
00520 #define CLK_CKDIVR_RESET_VALUE   ((uint8_t)0x18)
00521 #define CLK_PCKENR1_RESET_VALUE  ((uint8_t)0xFF)
00522 #define CLK_PCKENR2_RESET_VALUE  ((uint8_t)0xFF)
00523 #define CLK_CSSR_RESET_VALUE     ((uint8_t)0x00)
00524 #define CLK_CCOR_RESET_VALUE     ((uint8_t)0x00)
00525 #define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
00526 #define CLK_SWIMCCR_RESET_VALUE  ((uint8_t)0x00)
00527
00528 /**
00529   * @}
00530   */
00531
00532 /** @addtogroup CLK_Registers_Bits_Definition
00533   * @{
00534   */
00535 #define CLK_ICKR_SWUAH       ((uint8_t)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */
00536 #define CLK_ICKR_LSIRDY      ((uint8_t)0x10) /*!< Low speed internal oscillator ready */
00537 #define CLK_ICKR_LSIEN       ((uint8_t)0x08) /*!< Low speed internal RC oscillator enable */
00538 #define CLK_ICKR_FHWU        ((uint8_t)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */
00539 #define CLK_ICKR_HSIRDY      ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */
00540 #define CLK_ICKR_HSIEN       ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */
00541
00542 #define CLK_ECKR_HSERDY      ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */
00543 #define CLK_ECKR_HSEEN       ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */
00544
00545 #define CLK_CMSR_CKM         ((uint8_t)0xFF) /*!< Clock master status bits */
00546
00547 #define CLK_SWR_SWI          ((uint8_t)0xFF) /*!< Clock master selection bits */
00548
00549 #define CLK_SWCR_SWIF        ((uint8_t)0x08) /*!< Clock switch interrupt flag */
00550 #define CLK_SWCR_SWIEN       ((uint8_t)0x04) /*!< Clock switch interrupt enable */
00551 #define CLK_SWCR_SWEN        ((uint8_t)0x02) /*!< Switch start/stop */
00552 #define CLK_SWCR_SWBSY       ((uint8_t)0x01) /*!< Switch busy flag*/
00553
00554 #define CLK_CKDIVR_HSIDIV    ((uint8_t)0x18) /*!< High speed internal clock prescaler */
00555 #define CLK_CKDIVR_CPUDIV    ((uint8_t)0x07) /*!< CPU clock prescaler */
00556
00557 #define CLK_PCKENR1_TIM1     ((uint8_t)0x80) /*!< Timer 1 clock enable */
00558 #define CLK_PCKENR1_TIM3     ((uint8_t)0x40) /*!< Timer 3 clock enable */
00559 #define CLK_PCKENR1_TIM2     ((uint8_t)0x20) /*!< Timer 2 clock enable */
00560 #define CLK_PCKENR1_TIM5     ((uint8_t)0x20) /*!< Timer 5 clock enable */
00561 #define CLK_PCKENR1_TIM4     ((uint8_t)0x10) /*!< Timer 4 clock enable */
00562 #define CLK_PCKENR1_TIM6     ((uint8_t)0x10) /*!< Timer 6 clock enable */
00563 #define CLK_PCKENR1_UART3    ((uint8_t)0x08) /*!< UART3 clock enable */
00564 #define CLK_PCKENR1_UART2    ((uint8_t)0x08) /*!< UART2 clock enable */
00565 #define CLK_PCKENR1_UART1    ((uint8_t)0x04) /*!< UART1 clock enable */
00566 #define CLK_PCKENR1_SPI      ((uint8_t)0x02) /*!< SPI clock enable */
00567 #define CLK_PCKENR1_I2C      ((uint8_t)0x01) /*!< I2C clock enable */
00568
00569 #define CLK_PCKENR2_CAN      ((uint8_t)0x80) /*!< CAN clock enable */
00570 #define CLK_PCKENR2_ADC      ((uint8_t)0x08) /*!< ADC clock enable */
00571 #define CLK_PCKENR2_AWU      ((uint8_t)0x04) /*!< AWU clock enable */
00572
00573 #define CLK_CSSR_CSSD        ((uint8_t)0x08) /*!< Clock security system detection */
00574 #define CLK_CSSR_CSSDIE      ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */
00575 #define CLK_CSSR_AUX         ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */
00576 #define CLK_CSSR_CSSEN       ((uint8_t)0x01) /*!< Clock security system enable */
00577
00578 #define CLK_CCOR_CCOBSY      ((uint8_t)0x40) /*!< Configurable clock output busy */
00579 #define CLK_CCOR_CCORDY      ((uint8_t)0x20) /*!< Configurable clock output ready */
00580 #define CLK_CCOR_CCOSEL      ((uint8_t)0x1E) /*!< Configurable clock output selection */
00581 #define CLK_CCOR_CCOEN       ((uint8_t)0x01) /*!< Configurable clock output enable */
00582
00583 #define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator trimmer */
00584
00585 #define CLK_SWIMCCR_SWIMDIV  ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */
00586
00587 /**
00588   * @}
00589   */
00590
00591 /*----------------------------------------------------------------------------*/
00592 /**
00593   * @brief  16-bit timer with complementary PWM outputs (TIM1)
00594   */
00595
00596 typedef struct TIM1_struct
00597 {
00598   __IO uint8_t CR1;   /*!< control register 1 */
00599   __IO uint8_t CR2;   /*!< control register 2 */
00600   __IO uint8_t SMCR;  /*!< Synchro mode control register */
00601   __IO uint8_t ETR;   /*!< external trigger register */
00602   __IO uint8_t IER;   /*!< interrupt enable register*/
00603   __IO uint8_t SR1;   /*!< status register 1 */
00604   __IO uint8_t SR2;   /*!< status register 2 */
00605   __IO uint8_t EGR;   /*!< event generation register */
00606   __IO uint8_t CCMR1; /*!< CC mode register 1 */
00607   __IO uint8_t CCMR2; /*!< CC mode register 2 */
00608   __IO uint8_t CCMR3; /*!< CC mode register 3 */
00609   __IO uint8_t CCMR4; /*!< CC mode register 4 */
00610   __IO uint8_t CCER1; /*!< CC enable register 1 */
00611   __IO uint8_t CCER2; /*!< CC enable register 2 */
00612   __IO uint8_t CNTRH; /*!< counter high */
00613   __IO uint8_t CNTRL; /*!< counter low */
00614   __IO uint8_t PSCRH; /*!< prescaler high */
00615   __IO uint8_t PSCRL; /*!< prescaler low */
00616   __IO uint8_t ARRH;  /*!< auto-reload register high */
00617   __IO uint8_t ARRL;  /*!< auto-reload register low */
00618   __IO uint8_t RCR;   /*!< Repetition Counter register */
00619   __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
00620   __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
00621   __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
00622   __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
00623   __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
00624   __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
00625   __IO uint8_t CCR4H; /*!< capture/compare register 3 high */
00626   __IO uint8_t CCR4L; /*!< capture/compare register 3 low */
00627   __IO uint8_t BKR;   /*!< Break Register */
00628   __IO uint8_t DTR;   /*!< dead-time register */
00629   __IO uint8_t OISR;  /*!< Output idle register */
00630 }
00631 TIM1_TypeDef;
00632
00633 /** @addtogroup TIM1_Registers_Reset_Value
00634   * @{
00635   */
00636
00637 #define TIM1_CR1_RESET_VALUE   ((uint8_t)0x00)
00638 #define TIM1_CR2_RESET_VALUE   ((uint8_t)0x00)
00639 #define TIM1_SMCR_RESET_VALUE  ((uint8_t)0x00)
00640 #define TIM1_ETR_RESET_VALUE   ((uint8_t)0x00)
00641 #define TIM1_IER_RESET_VALUE   ((uint8_t)0x00)
00642 #define TIM1_SR1_RESET_VALUE   ((uint8_t)0x00)
00643 #define TIM1_SR2_RESET_VALUE   ((uint8_t)0x00)
00644 #define TIM1_EGR_RESET_VALUE   ((uint8_t)0x00)
00645 #define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
00646 #define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
00647 #define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
00648 #define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
00649 #define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
00650 #define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
00651 #define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
00652 #define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
00653 #define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
00654 #define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
00655 #define TIM1_ARRH_RESET_VALUE  ((uint8_t)0xFF)
00656 #define TIM1_ARRL_RESET_VALUE  ((uint8_t)0xFF)
00657 #define TIM1_RCR_RESET_VALUE   ((uint8_t)0x00)
00658 #define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
00659 #define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
00660 #define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
00661 #define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
00662 #define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
00663 #define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
00664 #define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
00665 #define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
00666 #define TIM1_BKR_RESET_VALUE   ((uint8_t)0x00)
00667 #define TIM1_DTR_RESET_VALUE   ((uint8_t)0x00)
00668 #define TIM1_OISR_RESET_VALUE  ((uint8_t)0x00)
00669
00670 /**
00671   * @}
00672   */
00673
00674 /** @addtogroup TIM1_Registers_Bits_Definition
00675   * @{
00676   */
00677 /* CR1*/
00678 #define TIM1_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
00679 #define TIM1_CR1_CMS     ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */
00680 #define TIM1_CR1_DIR     ((uint8_t)0x10) /*!< Direction mask. */
00681 #define TIM1_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
00682 #define TIM1_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
00683 #define TIM1_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
00684 #define TIM1_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
00685 /* CR2*/
00686 #define TIM1_CR2_TI1S    ((uint8_t)0x80) /*!< TI1S Selection mask. */
00687 #define TIM1_CR2_MMS     ((uint8_t)0x70) /*!< MMS Selection mask. */
00688 #define TIM1_CR2_COMS    ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */
00689 #define TIM1_CR2_CCPC    ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */
00690 /* SMCR*/
00691 #define TIM1_SMCR_MSM    ((uint8_t)0x80) /*!< Master/Slave Mode mask. */
00692 #define TIM1_SMCR_TS     ((uint8_t)0x70) /*!< Trigger Selection mask. */
00693 #define TIM1_SMCR_SMS    ((uint8_t)0x07) /*!< Slave Mode Selection mask. */
00694 /*ETR*/
00695 #define TIM1_ETR_ETP     ((uint8_t)0x80) /*!< External Trigger Polarity mask. */
00696 #define TIM1_ETR_ECE     ((uint8_t)0x40)/*!< External Clock mask. */
00697 #define TIM1_ETR_ETPS    ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */
00698 #define TIM1_ETR_ETF     ((uint8_t)0x0F) /*!< External Trigger Filter mask. */
00699 /*IER*/
00700 #define TIM1_IER_BIE     ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */
00701 #define TIM1_IER_TIE     ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
00702 #define TIM1_IER_COMIE   ((uint8_t)0x20) /*!<  Commutation Interrupt Enable mask.*/
00703 #define TIM1_IER_CC4IE   ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */
00704 #define TIM1_IER_CC3IE   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
00705 #define TIM1_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
00706 #define TIM1_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
00707 #define TIM1_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
00708 /*SR1*/
00709 #define TIM1_SR1_BIF     ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */
00710 #define TIM1_SR1_TIF     ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
00711 #define TIM1_SR1_COMIF   ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */
00712 #define TIM1_SR1_CC4IF   ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */
00713 #define TIM1_SR1_CC3IF   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
00714 #define TIM1_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
00715 #define TIM1_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
00716 #define TIM1_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
00717 /*SR2*/
00718 #define TIM1_SR2_CC4OF   ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */
00719 #define TIM1_SR2_CC3OF   ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
00720 #define TIM1_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
00721 #define TIM1_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
00722 /*EGR*/
00723 #define TIM1_EGR_BG      ((uint8_t)0x80) /*!< Break Generation mask. */
00724 #define TIM1_EGR_TG      ((uint8_t)0x40) /*!< Trigger Generation mask. */
00725 #define TIM1_EGR_COMG    ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */
00726 #define TIM1_EGR_CC4G    ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */
00727 #define TIM1_EGR_CC3G    ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
00728 #define TIM1_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
00729 #define TIM1_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
00730 #define TIM1_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
00731 /*CCMR*/
00732 #define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
00733 #define TIM1_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
00734 #define TIM1_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
00735 #define TIM1_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
00736 #define TIM1_CCMR_OCxFE  ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */
00737 #define TIM1_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
00738
00739 #define CCMR_TIxDirect_Set ((uint8_t)0x01)
00740 /*CCER1*/
00741 #define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */
00742 #define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */
00743 #define TIM1_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
00744 #define TIM1_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
00745 #define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */
00746 #define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */
00747 #define TIM1_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
00748 #define TIM1_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
00749 /*CCER2*/
00750 #define TIM1_CCER2_CC4P  ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity mask. */
00751 #define TIM1_CCER2_CC4E  ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask. */
00752 #define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */
00753 #define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */
00754 #define TIM1_CCER2_CC3P  ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
00755 #define TIM1_CCER2_CC3E  ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
00756 /*CNTRH*/
00757 #define TIM1_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
00758 /*CNTRL*/
00759 #define TIM1_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
00760 /*PSCH*/
00761 #define TIM1_PSCH_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
00762 /*PSCL*/
00763 #define TIM1_PSCL_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */
00764 /*ARR*/
00765 #define TIM1_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
00766 #define TIM1_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
00767 /*RCR*/
00768 #define TIM1_RCR_REP     ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */
00769 /*CCR1*/
00770 #define TIM1_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
00771 #define TIM1_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
00772 /*CCR2*/
00773 #define TIM1_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
00774 #define TIM1_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
00775 /*CCR3*/
00776 #define TIM1_CCR3H_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
00777 #define TIM1_CCR3L_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
00778 /*CCR4*/
00779 #define TIM1_CCR4H_CCR4  ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */
00780 #define TIM1_CCR4L_CCR4  ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */
00781 /*BKR*/
00782 #define TIM1_BKR_MOE     ((uint8_t)0x80) /*!< Main Output Enable mask. */
00783 #define TIM1_BKR_AOE     ((uint8_t)0x40) /*!< Automatic Output Enable mask. */
00784 #define TIM1_BKR_BKP     ((uint8_t)0x20) /*!< Break Polarity mask. */
00785 #define TIM1_BKR_BKE     ((uint8_t)0x10) /*!< Break Enable mask. */
00786 #define TIM1_BKR_OSSR    ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */
00787 #define TIM1_BKR_OSSI    ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */
00788 #define TIM1_BKR_LOCK    ((uint8_t)0x03) /*!< Lock Configuration mask. */
00789 /*DTR*/
00790 #define TIM1_DTR_DTG     ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */
00791 /*OISR*/
00792 #define TIM1_OISR_OIS4   ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output) mask. */
00793 #define TIM1_OISR_OIS3N  ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */
00794 #define TIM1_OISR_OIS3   ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */
00795 #define TIM1_OISR_OIS2N  ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */
00796 #define TIM1_OISR_OIS2   ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */
00797 #define TIM1_OISR_OIS1N  ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */
00798 #define TIM1_OISR_OIS1   ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */
00799 /**
00800   * @}
00801   */
00802
00803 /*----------------------------------------------------------------------------*/
00804 /**
00805   * @brief  16-bit timer (TIM2)
00806   */
00807
00808 typedef struct TIM2_struct
00809 {
00810   __IO uint8_t CR1;   /*!< control register 1 */
00811 #if defined(STM8S103) || defined(STM8S003)
00812         uint8_t RESERVED1; /*!< Reserved register */
00813         uint8_t RESERVED2; /*!< Reserved register */
00814 #endif
00815   __IO uint8_t IER;   /*!< interrupt enable register */
00816   __IO uint8_t SR1;   /*!< status register 1 */
00817   __IO uint8_t SR2;   /*!< status register 2 */
00818   __IO uint8_t EGR;   /*!< event generation register */
00819   __IO uint8_t CCMR1; /*!< CC mode register 1 */
00820   __IO uint8_t CCMR2; /*!< CC mode register 2 */
00821   __IO uint8_t CCMR3; /*!< CC mode register 3 */
00822   __IO uint8_t CCER1; /*!< CC enable register 1 */
00823   __IO uint8_t CCER2; /*!< CC enable register 2 */
00824   __IO uint8_t CNTRH; /*!< counter high */
00825   __IO uint8_t CNTRL; /*!< counter low */
00826   __IO uint8_t PSCR;  /*!< prescaler register */
00827   __IO uint8_t ARRH;  /*!< auto-reload register high */
00828   __IO uint8_t ARRL;  /*!< auto-reload register low */
00829   __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
00830   __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
00831   __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
00832   __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
00833   __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
00834   __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
00835 }
00836 TIM2_TypeDef;
00837
00838 /** @addtogroup TIM2_Registers_Reset_Value
00839   * @{
00840   */
00841
00842 #define TIM2_CR1_RESET_VALUE   ((uint8_t)0x00)
00843 #define TIM2_IER_RESET_VALUE   ((uint8_t)0x00)
00844 #define TIM2_SR1_RESET_VALUE   ((uint8_t)0x00)
00845 #define TIM2_SR2_RESET_VALUE   ((uint8_t)0x00)
00846 #define TIM2_EGR_RESET_VALUE   ((uint8_t)0x00)
00847 #define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)
00848 #define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)
00849 #define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)
00850 #define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)
00851 #define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)
00852 #define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)
00853 #define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)
00854 #define TIM2_PSCR_RESET_VALUE  ((uint8_t)0x00)
00855 #define TIM2_ARRH_RESET_VALUE  ((uint8_t)0xFF)
00856 #define TIM2_ARRL_RESET_VALUE  ((uint8_t)0xFF)
00857 #define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)
00858 #define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)
00859 #define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)
00860 #define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)
00861 #define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)
00862 #define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)
00863
00864 /**
00865   * @}
00866   */
00867
00868 /** @addtogroup TIM2_Registers_Bits_Definition
00869   * @{
00870   */
00871 /*CR1*/
00872 #define TIM2_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
00873 #define TIM2_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
00874 #define TIM2_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
00875 #define TIM2_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
00876 #define TIM2_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
00877 /*IER*/
00878 #define TIM2_IER_CC3IE   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
00879 #define TIM2_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
00880 #define TIM2_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
00881 #define TIM2_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
00882 /*SR1*/
00883 #define TIM2_SR1_CC3IF   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
00884 #define TIM2_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
00885 #define TIM2_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
00886 #define TIM2_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
00887 /*SR2*/
00888 #define TIM2_SR2_CC3OF   ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
00889 #define TIM2_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
00890 #define TIM2_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
00891 /*EGR*/
00892 #define TIM2_EGR_CC3G    ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
00893 #define TIM2_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
00894 #define TIM2_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
00895 #define TIM2_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
00896 /*CCMR*/
00897 #define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
00898 #define TIM2_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
00899 #define TIM2_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
00900 #define TIM2_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
00901 #define TIM2_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
00902 /*CCER1*/
00903 #define TIM2_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
00904 #define TIM2_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
00905 #define TIM2_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
00906 #define TIM2_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
00907 /*CCER2*/
00908 #define TIM2_CCER2_CC3P  ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
00909 #define TIM2_CCER2_CC3E  ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
00910 /*CNTR*/
00911 #define TIM2_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
00912 #define TIM2_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
00913 /*PSCR*/
00914 #define TIM2_PSCR_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
00915 /*ARR*/
00916 #define TIM2_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
00917 #define TIM2_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
00918 /*CCR1*/
00919 #define TIM2_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
00920 #define TIM2_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
00921 /*CCR2*/
00922 #define TIM2_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
00923 #define TIM2_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
00924 /*CCR3*/
00925 #define TIM2_CCR3H_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
00926 #define TIM2_CCR3L_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
00927
00928 /**
00929   * @}
00930   */
00931
00932 /*----------------------------------------------------------------------------*/
00933 /**
00934   * @brief  16-bit timer (TIM3)
00935   */
00936 typedef struct TIM3_struct
00937 {
00938   __IO uint8_t CR1;   /*!< control register 1 */
00939   __IO uint8_t IER;   /*!< interrupt enable register */
00940   __IO uint8_t SR1;   /*!< status register 1 */
00941   __IO uint8_t SR2;   /*!< status register 2 */
00942   __IO uint8_t EGR;   /*!< event generation register */
00943   __IO uint8_t CCMR1; /*!< CC mode register 1 */
00944   __IO uint8_t CCMR2; /*!< CC mode register 2 */
00945   __IO uint8_t CCER1; /*!< CC enable register 1 */
00946   __IO uint8_t CNTRH; /*!< counter high */
00947   __IO uint8_t CNTRL; /*!< counter low */
00948   __IO uint8_t PSCR;  /*!< prescaler register */
00949   __IO uint8_t ARRH;  /*!< auto-reload register high */
00950   __IO uint8_t ARRL;  /*!< auto-reload register low */
00951   __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
00952   __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
00953   __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
00954   __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
00955 }
00956 TIM3_TypeDef;
00957
00958 /** @addtogroup TIM3_Registers_Reset_Value
00959   * @{
00960   */
00961
00962 #define TIM3_CR1_RESET_VALUE   ((uint8_t)0x00)
00963 #define TIM3_IER_RESET_VALUE   ((uint8_t)0x00)
00964 #define TIM3_SR1_RESET_VALUE   ((uint8_t)0x00)
00965 #define TIM3_SR2_RESET_VALUE   ((uint8_t)0x00)
00966 #define TIM3_EGR_RESET_VALUE   ((uint8_t)0x00)
00967 #define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)
00968 #define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)
00969 #define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)
00970 #define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)
00971 #define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)
00972 #define TIM3_PSCR_RESET_VALUE  ((uint8_t)0x00)
00973 #define TIM3_ARRH_RESET_VALUE  ((uint8_t)0xFF)
00974 #define TIM3_ARRL_RESET_VALUE  ((uint8_t)0xFF)
00975 #define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)
00976 #define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)
00977 #define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)
00978 #define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)
00979
00980 /**
00981   * @}
00982   */
00983
00984 /** @addtogroup TIM3_Registers_Bits_Definition
00985   * @{
00986   */
00987 /*CR1*/
00988 #define TIM3_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
00989 #define TIM3_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
00990 #define TIM3_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
00991 #define TIM3_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
00992 #define TIM3_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
00993 /*IER*/
00994 #define TIM3_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
00995 #define TIM3_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
00996 #define TIM3_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
00997 /*SR1*/
00998 #define TIM3_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
00999 #define TIM3_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
01000 #define TIM3_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
01001 /*SR2*/
01002 #define TIM3_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
01003 #define TIM3_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
01004 /*EGR*/
01005 #define TIM3_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
01006 #define TIM3_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
01007 #define TIM3_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
01008 /*CCMR*/
01009 #define TIM3_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
01010 #define TIM3_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
01011 #define TIM3_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
01012 #define TIM3_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
01013 #define TIM3_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
01014 /*CCER1*/
01015 #define TIM3_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
01016 #define TIM3_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
01017 #define TIM3_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
01018 #define TIM3_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
01019 /*CNTR*/
01020 #define TIM3_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
01021 #define TIM3_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
01022 /*PSCR*/
01023 #define TIM3_PSCR_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
01024 /*ARR*/
01025 #define TIM3_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
01026 #define TIM3_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
01027 /*CCR1*/
01028 #define TIM3_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
01029 #define TIM3_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
01030 /*CCR2*/
01031 #define TIM3_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
01032 #define TIM3_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
01033 /**
01034   * @}
01035   */
01036
01037 /*----------------------------------------------------------------------------*/
01038 /**
01039   * @brief  8-bit system timer (TIM4)
01040   */
01041
01042 typedef struct TIM4_struct
01043 {
01044   __IO uint8_t CR1;  /*!< control register 1 */
01045 #if defined(STM8S103) || defined(STM8S003)
01046         uint8_t RESERVED1; /*!< Reserved register */
01047         uint8_t RESERVED2; /*!< Reserved register */
01048 #endif
01049   __IO uint8_t IER;  /*!< interrupt enable register */
01050   __IO uint8_t SR1;  /*!< status register 1 */
01051   __IO uint8_t EGR;  /*!< event generation register */
01052   __IO uint8_t CNTR; /*!< counter register */
01053   __IO uint8_t PSCR; /*!< prescaler register */
01054   __IO uint8_t ARR;  /*!< auto-reload register */
01055 }
01056 TIM4_TypeDef;
01057
01058 /** @addtogroup TIM4_Registers_Reset_Value
01059   * @{
01060   */
01061
01062 #define TIM4_CR1_RESET_VALUE  ((uint8_t)0x00)
01063 #define TIM4_IER_RESET_VALUE  ((uint8_t)0x00)
01064 #define TIM4_SR1_RESET_VALUE  ((uint8_t)0x00)
01065 #define TIM4_EGR_RESET_VALUE  ((uint8_t)0x00)
01066 #define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)
01067 #define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)
01068 #define TIM4_ARR_RESET_VALUE  ((uint8_t)0xFF)
01069
01070 /**
01071   * @}
01072   */
01073
01074 /** @addtogroup TIM4_Registers_Bits_Definition
01075   * @{
01076   */
01077 /*CR1*/
01078 #define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
01079 #define TIM4_CR1_OPM  ((uint8_t)0x08) /*!< One Pulse Mode mask. */
01080 #define TIM4_CR1_URS  ((uint8_t)0x04) /*!< Update Request Source mask. */
01081 #define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
01082 #define TIM4_CR1_CEN  ((uint8_t)0x01) /*!< Counter Enable mask. */
01083 /*IER*/
01084 #define TIM4_IER_UIE  ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
01085 /*SR1*/
01086 #define TIM4_SR1_UIF  ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
01087 /*EGR*/
01088 #define TIM4_EGR_UG   ((uint8_t)0x01) /*!< Update Generation mask. */
01089 /*CNTR*/
01090 #define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
01091 /*PSCR*/
01092 #define TIM4_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value  mask. */
01093 /*ARR*/
01094 #define TIM4_ARR_ARR  ((uint8_t)0xFF) /*!< Autoreload Value mask. */
01095
01096 /**
01097   * @}
01098   */
01099
01100 /*----------------------------------------------------------------------------*/
01101 /**
01102   * @brief  16-bit timer with synchro module (TIM5)
01103   */
01104
01105 typedef struct TIM5_struct
01106 {
01107   __IO uint8_t CR1;       /*!<TIM5 Control Register 1                */
01108   __IO uint8_t CR2;       /*!<TIM5 Control Register 2                */
01109   __IO uint8_t SMCR;      /*!<TIM5 Slave Mode Control Register       */
01110   __IO uint8_t IER;       /*!<TIM5 Interrupt Enable Register         */
01111   __IO uint8_t SR1;       /*!<TIM5 Status Register 1                 */
01112   __IO uint8_t SR2;       /*!<TIM5 Status Register 2                 */
01113   __IO uint8_t EGR;       /*!<TIM5 Event Generation Register         */
01114   __IO uint8_t CCMR1;     /*!<TIM5 Capture/Compare Mode Register 1   */
01115   __IO uint8_t CCMR2;     /*!<TIM5 Capture/Compare Mode Register 2   */
01116   __IO uint8_t CCMR3;     /*!<TIM5 Capture/Compare Mode Register 3   */
01117   __IO uint8_t CCER1;     /*!<TIM5 Capture/Compare Enable Register 1 */
01118   __IO uint8_t CCER2;     /*!<TIM5 Capture/Compare Enable Register 2 */
01119   __IO uint8_t CNTRH;     /*!<TIM5 Counter High                      */
01120   __IO uint8_t CNTRL;     /*!<TIM5 Counter Low                       */
01121   __IO uint8_t PSCR;      /*!<TIM5 Prescaler Register                */
01122   __IO uint8_t ARRH;      /*!<TIM5 Auto-Reload Register High         */
01123   __IO uint8_t ARRL;      /*!<TIM5 Auto-Reload Register Low          */
01124   __IO uint8_t CCR1H;     /*!<TIM5 Capture/Compare Register 1 High   */
01125   __IO uint8_t CCR1L;     /*!<TIM5 Capture/Compare Register 1 Low    */
01126   __IO uint8_t CCR2H;     /*!<TIM5 Capture/Compare Register 2 High   */
01127   __IO uint8_t CCR2L;     /*!<TIM5 Capture/Compare Register 2 Low    */
01128   __IO uint8_t CCR3H;     /*!<TIM5 Capture/Compare Register 3 High   */
01129   __IO uint8_t CCR3L;     /*!<TIM5 Capture/Compare Register 3 Low    */
01130 }TIM5_TypeDef;
01131
01132 /** @addtogroup TIM5_Registers_Reset_Value
01133   * @{
01134   */
01135
01136 #define TIM5_CR1_RESET_VALUE   ((uint8_t)0x00)
01137 #define TIM5_CR2_RESET_VALUE     ((uint8_t)0x00)
01138 #define TIM5_SMCR_RESET_VALUE    ((uint8_t)0x00)
01139 #define TIM5_IER_RESET_VALUE   ((uint8_t)0x00)
01140 #define TIM5_SR1_RESET_VALUE   ((uint8_t)0x00)
01141 #define TIM5_SR2_RESET_VALUE   ((uint8_t)0x00)
01142 #define TIM5_EGR_RESET_VALUE   ((uint8_t)0x00)
01143 #define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)
01144 #define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)
01145 #define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)
01146 #define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)
01147 #define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)
01148 #define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)
01149 #define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)
01150 #define TIM5_PSCR_RESET_VALUE  ((uint8_t)0x00)
01151 #define TIM5_ARRH_RESET_VALUE  ((uint8_t)0xFF)
01152 #define TIM5_ARRL_RESET_VALUE  ((uint8_t)0xFF)
01153 #define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)
01154 #define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)
01155 #define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)
01156 #define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)
01157 #define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)
01158 #define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)
01159
01160 /**
01161   * @}
01162   */
01163
01164 /** @addtogroup TIM5_Registers_Bits_Definition
01165   * @{
01166   */
01167 /* CR1*/
01168 #define TIM5_CR1_ARPE           ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
01169 #define TIM5_CR1_OPM            ((uint8_t)0x08) /*!< One Pulse Mode mask. */
01170 #define TIM5_CR1_URS            ((uint8_t)0x04) /*!< Update Request Source mask. */
01171 #define TIM5_CR1_UDIS           ((uint8_t)0x02) /*!< Update DIsable mask. */
01172 #define TIM5_CR1_CEN            ((uint8_t)0x01) /*!< Counter Enable mask. */
01173 /* CR2*/
01174 #define TIM5_CR2_TI1S           ((uint8_t)0x80) /*!< TI1S Selection Mask. */
01175 #define TIM5_CR2_MMS              ((uint8_t)0x70) /*!< MMS Selection Mask. */
01176 /* SMCR*/
01177 #define TIM5_SMCR_MSM           ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
01178 #define TIM5_SMCR_TS            ((uint8_t)0x70) /*!< Trigger Selection Mask. */
01179 #define TIM5_SMCR_SMS           ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
01180 /*IER*/
01181 #define TIM5_IER_TIE            ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
01182 #define TIM5_IER_CC3IE          ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
01183 #define TIM5_IER_CC2IE          ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
01184 #define TIM5_IER_CC1IE          ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
01185 #define TIM5_IER_UIE            ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
01186 /*SR1*/
01187 #define TIM5_SR1_TIF            ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
01188 #define TIM5_SR1_CC3IF          ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
01189 #define TIM5_SR1_CC2IF          ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
01190 #define TIM5_SR1_CC1IF          ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
01191 #define TIM5_SR1_UIF            ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
01192 /*SR2*/
01193 #define TIM5_SR2_CC3OF          ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
01194 #define TIM5_SR2_CC2OF          ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
01195 #define TIM5_SR2_CC1OF          ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
01196 /*EGR*/
01197 #define TIM5_EGR_TG             ((uint8_t)0x40) /*!< Trigger Generation mask. */
01198 #define TIM5_EGR_CC3G           ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
01199 #define TIM5_EGR_CC2G           ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
01200 #define TIM5_EGR_CC1G           ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
01201 #define TIM5_EGR_UG             ((uint8_t)0x01) /*!< Update Generation mask. */
01202 /*CCMR*/
01203 #define TIM5_CCMR_ICxPSC        ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
01204 #define TIM5_CCMR_ICxF          ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
01205 #define TIM5_CCMR_OCM           ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
01206 #define TIM5_CCMR_OCxPE         ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
01207 #define TIM5_CCMR_CCxS          ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
01208 /*CCER1*/
01209 #define TIM5_CCER1_CC2P         ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
01210 #define TIM5_CCER1_CC2E         ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
01211 #define TIM5_CCER1_CC1P         ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
01212 #define TIM5_CCER1_CC1E         ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
01213 /*CCER2*/
01214 #define TIM5_CCER2_CC3P         ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
01215 #define TIM5_CCER2_CC3E         ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
01216 /*CNTR*/
01217 #define TIM5_CNTRH_CNT          ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
01218 #define TIM5_CNTRL_CNT          ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
01219 /*PSCR*/
01220 #define TIM5_PSCR_PSC           ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
01221 /*ARR*/
01222 #define TIM5_ARRH_ARR           ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
01223 #define TIM5_ARRL_ARR           ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
01224 /*CCR1*/
01225 #define TIM5_CCR1H_CCR1         ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
01226 #define TIM5_CCR1L_CCR1         ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
01227 /*CCR2*/
01228 #define TIM5_CCR2H_CCR2         ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
01229 #define TIM5_CCR2L_CCR2         ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
01230 /*CCR3*/
01231 #define TIM5_CCR3H_CCR3         ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
01232 #define TIM5_CCR3L_CCR3         ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
01233 /*CCMR*/
01234 #define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)
01235 /**
01236   * @}
01237   */
01238
01239 /*----------------------------------------------------------------------------*/
01240 /**
01241   * @brief  8-bit system timer  with synchro module(TIM6)
01242   */
01243
01244 typedef struct TIM6_struct
01245 {
01246     __IO uint8_t CR1;   /*!< control register 1 */
01247     __IO uint8_t CR2;   /*!< control register 2 */
01248     __IO uint8_t SMCR;  /*!< Synchro mode control register */
01249     __IO uint8_t IER;   /*!< interrupt enable register  */
01250     __IO uint8_t SR1;   /*!< status register 1    */
01251     __IO uint8_t EGR;   /*!< event generation register */
01252     __IO uint8_t CNTR;  /*!< counter register  */
01253     __IO uint8_t PSCR;  /*!< prescaler register */
01254     __IO uint8_t ARR;   /*!< auto-reload register */
01255 }
01256 TIM6_TypeDef;
01257 /** @addtogroup TIM6_Registers_Reset_Value
01258   * @{
01259   */
01260 #define TIM6_CR1_RESET_VALUE    ((uint8_t)0x00)
01261 #define TIM6_CR2_RESET_VALUE    ((uint8_t)0x00)
01262 #define TIM6_SMCR_RESET_VALUE   ((uint8_t)0x00)
01263 #define TIM6_IER_RESET_VALUE    ((uint8_t)0x00)
01264 #define TIM6_SR1_RESET_VALUE    ((uint8_t)0x00)
01265 #define TIM6_EGR_RESET_VALUE    ((uint8_t)0x00)
01266 #define TIM6_CNTR_RESET_VALUE   ((uint8_t)0x00)
01267 #define TIM6_PSCR_RESET_VALUE   ((uint8_t)0x00)
01268 #define TIM6_ARR_RESET_VALUE    ((uint8_t)0xFF)
01269
01270 /**
01271 * @}
01272 */
01273
01274 /** @addtogroup TIM6_Registers_Bits_Definition
01275   * @{
01276   */
01277 /* CR1*/
01278 #define TIM6_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */
01279 #define TIM6_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode Mask. */
01280 #define TIM6_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source Mask. */
01281 #define TIM6_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable Mask. */
01282 #define TIM6_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable Mask. */
01283 /* CR2*/
01284 #define TIM6_CR2_MMS       ((uint8_t)0x70) /*!< MMS Selection Mask. */
01285 /* SMCR*/
01286 #define TIM6_SMCR_MSM    ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
01287 #define TIM6_SMCR_TS     ((uint8_t)0x70) /*!< Trigger Selection Mask. */
01288 #define TIM6_SMCR_SMS    ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
01289 /* IER*/
01290 #define TIM6_IER_TIE     ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */
01291 #define TIM6_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */
01292 /* SR1*/
01293 #define TIM6_SR1_TIF     ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
01294 #define TIM6_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */
01295 /* EGR*/
01296 #define TIM6_EGR_TG      ((uint8_t)0x40) /*!< Trigger Generation mask. */
01297 #define TIM6_EGR_UG      ((uint8_t)0x01) /*!< Update Generation Mask. */
01298 /* CNTR*/
01299 #define TIM6_CNTR_CNT    ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */
01300 /* PSCR*/
01301 #define TIM6_PSCR_PSC    ((uint8_t)0x07) /*!<Prescaler Value  Mask. */
01302
01303 #define TIM6_ARR_ARR       ((uint8_t)0xFF) /*!<Autoreload Value Mask. */
01304 /**
01305   * @}
01306   */
01307 /*----------------------------------------------------------------------------*/
01308 /**
01309   * @brief  Inter-Integrated Circuit (I2C)
01310   */
01311
01312 typedef struct I2C_struct
01313 {
01314   __IO uint8_t CR1;       /*!< I2C control register 1 */
01315   __IO uint8_t CR2;       /*!< I2C control register 2 */
01316   __IO uint8_t FREQR;     /*!< I2C frequency register */
01317   __IO uint8_t OARL;      /*!< I2C own address register LSB */
01318   __IO uint8_t OARH;      /*!< I2C own address register MSB */
01319   uint8_t RESERVED1;      /*!< Reserved byte */
01320   __IO uint8_t DR;        /*!< I2C data register */
01321   __IO uint8_t SR1;       /*!< I2C status register 1 */
01322   __IO uint8_t SR2;       /*!< I2C status register 2 */
01323   __IO uint8_t SR3;       /*!< I2C status register 3 */
01324   __IO uint8_t ITR;       /*!< I2C interrupt register */
01325   __IO uint8_t CCRL;      /*!< I2C clock control register low */
01326   __IO uint8_t CCRH;      /*!< I2C clock control register high */
01327   __IO uint8_t TRISER;    /*!< I2C maximum rise time register */
01328   uint8_t RESERVED2;      /*!< Reserved byte */
01329 }
01330 I2C_TypeDef;
01331
01332 /** @addtogroup I2C_Registers_Reset_Value
01333   * @{
01334   */
01335
01336 #define I2C_CR1_RESET_VALUE    ((uint8_t)0x00)
01337 #define I2C_CR2_RESET_VALUE    ((uint8_t)0x00)
01338 #define I2C_FREQR_RESET_VALUE  ((uint8_t)0x00)
01339 #define I2C_OARL_RESET_VALUE   ((uint8_t)0x00)
01340 #define I2C_OARH_RESET_VALUE   ((uint8_t)0x00)
01341 #define I2C_DR_RESET_VALUE     ((uint8_t)0x00)
01342 #define I2C_SR1_RESET_VALUE    ((uint8_t)0x00)
01343 #define I2C_SR2_RESET_VALUE    ((uint8_t)0x00)
01344 #define I2C_SR3_RESET_VALUE    ((uint8_t)0x00)
01345 #define I2C_ITR_RESET_VALUE    ((uint8_t)0x00)
01346 #define I2C_CCRL_RESET_VALUE   ((uint8_t)0x00)
01347 #define I2C_CCRH_RESET_VALUE   ((uint8_t)0x00)
01348 #define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
01349
01350 /**
01351   * @}
01352   */
01353
01354 /** @addtogroup I2C_Registers_Bits_Definition
01355   * @{
01356   */
01357
01358 #define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */
01359 #define I2C_CR1_ENGC      ((uint8_t)0x40) /*!< General Call Enable */
01360 #define I2C_CR1_PE        ((uint8_t)0x01) /*!< Peripheral Enable */
01361
01362 #define I2C_CR2_SWRST ((uint8_t)0x80)     /*!< Software Reset */
01363 #define I2C_CR2_POS   ((uint8_t)0x08)     /*!< Acknowledge */
01364 #define I2C_CR2_ACK   ((uint8_t)0x04)     /*!< Acknowledge Enable */
01365 #define I2C_CR2_STOP  ((uint8_t)0x02)     /*!< Stop Generation */
01366 #define I2C_CR2_START ((uint8_t)0x01)     /*!< Start Generation */
01367
01368 #define I2C_FREQR_FREQ ((uint8_t)0x3F)    /*!< Peripheral Clock Frequency */
01369
01370 #define I2C_OARL_ADD  ((uint8_t)0xFE)     /*!< Interface Address bits [7..1] */
01371 #define I2C_OARL_ADD0 ((uint8_t)0x01)     /*!< Interface Address bit0 */
01372
01373 #define I2C_OARH_ADDMODE ((uint8_t)0x80)  /*!< Addressing Mode (Slave mode) */
01374 #define I2C_OARH_ADDCONF ((uint8_t)0x40)  /*!< Address Mode Configuration */
01375 #define I2C_OARH_ADD     ((uint8_t)0x06)  /*!< Interface Address bits [9..8] */
01376
01377 #define I2C_DR_DR        ((uint8_t)0xFF)  /*!< Data Register */
01378
01379 #define I2C_SR1_TXE      ((uint8_t)0x80)  /*!< Data Register Empty (transmitters) */
01380 #define I2C_SR1_RXNE     ((uint8_t)0x40)  /*!< Data Register not Empty (receivers) */
01381 #define I2C_SR1_STOPF    ((uint8_t)0x10)  /*!< Stop detection (Slave mode) */
01382 #define I2C_SR1_ADD10    ((uint8_t)0x08)  /*!< 10-bit header sent (Master mode) */
01383 #define I2C_SR1_BTF      ((uint8_t)0x04)  /*!< Byte Transfer Finished */
01384 #define I2C_SR1_ADDR     ((uint8_t)0x02)  /*!< Address sent (master mode)/matched (slave mode) */
01385 #define I2C_SR1_SB       ((uint8_t)0x01)  /*!< Start Bit (Master mode) */
01386
01387 #define I2C_SR2_WUFH     ((uint8_t)0x20)  /*!< Wake-up from Halt */
01388 #define I2C_SR2_OVR      ((uint8_t)0x08)  /*!< Overrun/Underrun */
01389 #define I2C_SR2_AF       ((uint8_t)0x04)  /*!< Acknowledge Failure */
01390 #define I2C_SR2_ARLO     ((uint8_t)0x02)  /*!< Arbitration Lost (master mode) */
01391 #define I2C_SR2_BERR     ((uint8_t)0x01)  /*!< Bus Error */
01392
01393 #define I2C_SR3_GENCALL  ((uint8_t)0x10)  /*!< General Call Header (Slave mode) */
01394 #define I2C_SR3_TRA      ((uint8_t)0x04)  /*!< Transmitter/Receiver */
01395 #define I2C_SR3_BUSY     ((uint8_t)0x02)  /*!< Bus Busy */
01396 #define I2C_SR3_MSL      ((uint8_t)0x01)  /*!< Master/Slave */
01397
01398 #define I2C_ITR_ITBUFEN  ((uint8_t)0x04)  /*!< Buffer Interrupt Enable */
01399 #define I2C_ITR_ITEVTEN  ((uint8_t)0x02)  /*!< Event Interrupt Enable */
01400 #define I2C_ITR_ITERREN  ((uint8_t)0x01)  /*!< Error Interrupt Enable */
01401
01402 #define I2C_CCRL_CCR     ((uint8_t)0xFF)  /*!< Clock Control Register (Master mode) */
01403
01404 #define I2C_CCRH_FS      ((uint8_t)0x80)  /*!< Master Mode Selection */
01405 #define I2C_CCRH_DUTY    ((uint8_t)0x40)  /*!< Fast Mode Duty Cycle */
01406 #define I2C_CCRH_CCR     ((uint8_t)0x0F)  /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */
01407
01408 #define I2C_TRISER_TRISE ((uint8_t)0x3F)  /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
01409
01410 /**
01411   * @}
01412   */
01413
01414 /*----------------------------------------------------------------------------*/
01415 /**
01416   * @brief  Interrupt Controller (ITC)
01417   */
01418
01419 typedef struct ITC_struct
01420 {
01421   __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */
01422   __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */
01423   __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */
01424   __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */
01425   __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */
01426   __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */
01427   __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */
01428   __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */
01429 }
01430 ITC_TypeDef;
01431
01432 /** @addtogroup ITC_Registers_Reset_Value
01433   * @{
01434   */
01435
01436 #define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers */
01437
01438 /**
01439   * @}
01440   */
01441
01442 /** @addtogroup CPU_Registers_Bits_Definition
01443   * @{
01444   */
01445
01446 #define CPU_CC_I1I0 ((uint8_t)0x28) /*!< Condition Code register, I1 and I0 bits mask */
01447
01448 /**
01449   * @}
01450   */
01451
01452 /*----------------------------------------------------------------------------*/
01453 /**
01454   * @brief  External Interrupt Controller (EXTI)
01455   */
01456
01457 typedef struct EXTI_struct
01458 {
01459   __IO uint8_t CR1; /*!< External Interrupt Control Register for PORTA to PORTD */
01460   __IO uint8_t CR2; /*!< External Interrupt Control Register for PORTE and TLI */
01461 }
01462 EXTI_TypeDef;
01463
01464 /** @addtogroup EXTI_Registers_Reset_Value
01465   * @{
01466   */
01467
01468 #define EXTI_CR1_RESET_VALUE ((uint8_t)0x00)
01469 #define EXTI_CR2_RESET_VALUE ((uint8_t)0x00)
01470
01471 /**
01472   * @}
01473   */
01474
01475 /** @addtogroup EXTI_Registers_Bits_Definition
01476   * @{
01477   */
01478
01479 #define EXTI_CR1_PDIS ((uint8_t)0xC0) /*!< PORTD external interrupt sensitivity bits mask */
01480 #define EXTI_CR1_PCIS ((uint8_t)0x30) /*!< PORTC external interrupt sensitivity bits mask */
01481 #define EXTI_CR1_PBIS ((uint8_t)0x0C) /*!< PORTB external interrupt sensitivity bits mask */
01482 #define EXTI_CR1_PAIS ((uint8_t)0x03) /*!< PORTA external interrupt sensitivity bits mask */
01483
01484 #define EXTI_CR2_TLIS ((uint8_t)0x04) /*!< Top level interrupt sensitivity bit mask */
01485 #define EXTI_CR2_PEIS ((uint8_t)0x03) /*!< PORTE external interrupt sensitivity bits mask */
01486
01487 /**
01488   * @}
01489   */
01490
01491
01492
01493 /*----------------------------------------------------------------------------*/
01494 /**
01495   * @brief  FLASH program and Data memory (FLASH)
01496   */
01497
01498 typedef struct FLASH_struct
01499 {
01500   __IO uint8_t CR1;       /*!< Flash control register 1 */
01501   __IO uint8_t CR2;       /*!< Flash control register 2 */
01502   __IO uint8_t NCR2;      /*!< Flash complementary control register 2 */
01503   __IO uint8_t FPR;       /*!< Flash protection register */
01504   __IO uint8_t NFPR;      /*!< Flash complementary protection register */
01505   __IO uint8_t IAPSR;     /*!< Flash in-application programming status register */
01506   uint8_t RESERVED1;      /*!< Reserved byte */
01507   uint8_t RESERVED2;      /*!< Reserved byte */
01508   __IO uint8_t PUKR;      /*!< Flash program memory unprotection register */
01509   uint8_t RESERVED3;      /*!< Reserved byte */
01510   __IO uint8_t DUKR;      /*!< Data EEPROM unprotection register */
01511 }
01512 FLASH_TypeDef;
01513
01514 /** @addtogroup FLASH_Registers_Reset_Value
01515   * @{
01516   */
01517
01518 #define FLASH_CR1_RESET_VALUE   ((uint8_t)0x00)
01519 #define FLASH_CR2_RESET_VALUE   ((uint8_t)0x00)
01520 #define FLASH_NCR2_RESET_VALUE  ((uint8_t)0xFF)
01521 #define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)
01522 #define FLASH_PUKR_RESET_VALUE  ((uint8_t)0x00)
01523 #define FLASH_DUKR_RESET_VALUE  ((uint8_t)0x00)
01524
01525 /**
01526   * @}
01527   */
01528
01529 /** @addtogroup FLASH_Registers_Bits_Definition
01530   * @{
01531   */
01532
01533 #define FLASH_CR1_HALT        ((uint8_t)0x08) /*!< Standby in Halt mode mask */
01534 #define FLASH_CR1_AHALT       ((uint8_t)0x04) /*!< Standby in Active Halt mode mask */
01535 #define FLASH_CR1_IE          ((uint8_t)0x02) /*!< Flash Interrupt enable mask */
01536 #define FLASH_CR1_FIX         ((uint8_t)0x01) /*!< Fix programming time mask */
01537
01538 #define FLASH_CR2_OPT         ((uint8_t)0x80) /*!< Select option byte mask */
01539 #define FLASH_CR2_WPRG        ((uint8_t)0x40) /*!< Word Programming mask */
01540 #define FLASH_CR2_ERASE       ((uint8_t)0x20) /*!< Erase block mask */
01541 #define FLASH_CR2_FPRG        ((uint8_t)0x10) /*!< Fast programming mode mask */
01542 #define FLASH_CR2_PRG         ((uint8_t)0x01) /*!< Program block mask */
01543
01544 #define FLASH_NCR2_NOPT       ((uint8_t)0x80) /*!< Select option byte mask */
01545 #define FLASH_NCR2_NWPRG      ((uint8_t)0x40) /*!< Word Programming mask */
01546 #define FLASH_NCR2_NERASE     ((uint8_t)0x20) /*!< Erase block mask */
01547 #define FLASH_NCR2_NFPRG      ((uint8_t)0x10) /*!< Fast programming mode mask */
01548 #define FLASH_NCR2_NPRG       ((uint8_t)0x01) /*!< Program block mask */
01549
01550 #define FLASH_IAPSR_HVOFF     ((uint8_t)0x40) /*!< End of high voltage flag mask */
01551 #define FLASH_IAPSR_DUL       ((uint8_t)0x08) /*!< Data EEPROM unlocked flag mask */
01552 #define FLASH_IAPSR_EOP       ((uint8_t)0x04) /*!< End of operation flag mask */
01553 #define FLASH_IAPSR_PUL       ((uint8_t)0x02) /*!< Flash Program memory unlocked flag mask */
01554 #define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page mask */
01555
01556 #define FLASH_PUKR_PUK        ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */
01557
01558 #define FLASH_DUKR_DUK        ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */
01559
01560 /**
01561   * @}
01562   */
01563
01564 /*----------------------------------------------------------------------------*/
01565 /**
01566   * @brief  Option Bytes (OPT)
01567   */
01568 typedef struct OPT_struct
01569 {
01570   __IO uint8_t OPT0;  /*!< Option byte 0: Read-out protection (not accessible in IAP mode) */
01571   __IO uint8_t OPT1;  /*!< Option byte 1: User boot code */
01572   __IO uint8_t NOPT1; /*!< Complementary Option byte 1 */
01573   __IO uint8_t OPT2;  /*!< Option byte 2: Alternate function remapping */
01574   __IO uint8_t NOPT2; /*!< Complementary Option byte 2 */
01575   __IO uint8_t OPT3;  /*!< Option byte 3: Watchdog option */
01576   __IO uint8_t NOPT3; /*!< Complementary Option byte 3 */
01577   __IO uint8_t OPT4;  /*!< Option byte 4: Clock option */
01578   __IO uint8_t NOPT4; /*!< Complementary Option byte 4 */
01579   __IO uint8_t OPT5;  /*!< Option byte 5: HSE clock startup */
01580   __IO uint8_t NOPT5; /*!< Complementary Option byte 5 */
01581   uint8_t RESERVED1;  /*!< Reserved Option byte*/
01582   uint8_t RESERVED2; /*!< Reserved Option byte*/
01583   __IO uint8_t OPT7;  /*!< Option byte 7: flash wait states */
01584   __IO uint8_t NOPT7; /*!< Complementary Option byte 7 */
01585 }
01586 OPT_TypeDef;
01587
01588 /*----------------------------------------------------------------------------*/
01589 /**
01590   * @brief  Independent Watchdog (IWDG)
01591   */
01592
01593 typedef struct IWDG_struct
01594 {
01595   __IO uint8_t KR;  /*!< Key Register */
01596   __IO uint8_t PR;  /*!< Prescaler Register */
01597   __IO uint8_t RLR; /*!< Reload Register */
01598 }
01599 IWDG_TypeDef;
01600
01601 /** @addtogroup IWDG_Registers_Reset_Value
01602   * @{
01603   */
01604
01605 #define IWDG_PR_RESET_VALUE  ((uint8_t)0x00)
01606 #define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)
01607
01608 /**
01609   * @}
01610   */
01611
01612 /*----------------------------------------------------------------------------*/
01613 /**
01614   * @brief  Window Watchdog (WWDG)
01615   */
01616
01617 typedef struct WWDG_struct
01618 {
01619   __IO uint8_t CR; /*!< Control Register */
01620   __IO uint8_t WR; /*!< Window Register */
01621 }
01622 WWDG_TypeDef;
01623
01624 /** @addtogroup WWDG_Registers_Reset_Value
01625   * @{
01626   */
01627
01628 #define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
01629 #define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)
01630
01631 /**
01632   * @}
01633   */
01634
01635 /** @addtogroup WWDG_Registers_Bits_Definition
01636   * @{
01637   */
01638
01639 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */
01640 #define WWDG_CR_T6   ((uint8_t)0x40) /*!< T6 bit mask */
01641 #define WWDG_CR_T    ((uint8_t)0x7F) /*!< T bits mask */
01642
01643 #define WWDG_WR_MSB  ((uint8_t)0x80) /*!< MSB bit mask */
01644 #define WWDG_WR_W    ((uint8_t)0x7F) /*!< W bits mask */
01645
01646 /**
01647   * @}
01648   */
01649
01650 /*----------------------------------------------------------------------------*/
01651 /**
01652   * @brief  Reset Controller (RST)
01653   */
01654
01655 typedef struct RST_struct
01656 {
01657   __IO uint8_t SR; /*!< Reset status register */
01658 }
01659 RST_TypeDef;
01660
01661 /** @addtogroup RST_Registers_Bits_Definition
01662   * @{
01663   */
01664
01665 #define RST_SR_EMCF   ((uint8_t)0x10) /*!< EMC reset flag bit mask */
01666 #define RST_SR_SWIMF  ((uint8_t)0x08) /*!< SWIM reset flag bit mask */
01667 #define RST_SR_ILLOPF ((uint8_t)0x04) /*!< Illegal opcode reset flag bit mask */
01668 #define RST_SR_IWDGF  ((uint8_t)0x02) /*!< IWDG reset flag bit mask */
01669 #define RST_SR_WWDGF  ((uint8_t)0x01) /*!< WWDG reset flag bit mask */
01670
01671 /**
01672   * @}
01673   */
01674
01675 /*----------------------------------------------------------------------------*/
01676 /**
01677   * @brief  Serial Peripheral Interface (SPI)
01678   */
01679
01680 typedef struct SPI_struct
01681 {
01682   __IO uint8_t CR1;    /*!< SPI control register 1 */
01683   __IO uint8_t CR2;    /*!< SPI control register 2 */
01684   __IO uint8_t ICR;    /*!< SPI interrupt control register */
01685   __IO uint8_t SR;     /*!< SPI status register */
01686   __IO uint8_t DR;     /*!< SPI data I/O register */
01687   __IO uint8_t CRCPR;  /*!< SPI CRC polynomial register */
01688   __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */
01689   __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */
01690 }
01691 SPI_TypeDef;
01692
01693 /** @addtogroup SPI_Registers_Reset_Value
01694   * @{
01695   */
01696
01697 #define SPI_CR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 1 reset value */
01698 #define SPI_CR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 2 reset value */
01699 #define SPI_ICR_RESET_VALUE    ((uint8_t)0x00) /*!< Interrupt Control Register reset value */
01700 #define SPI_SR_RESET_VALUE     ((uint8_t)0x02) /*!< Status Register reset value */
01701 #define SPI_DR_RESET_VALUE     ((uint8_t)0x00) /*!< Data Register reset value */
01702 #define SPI_CRCPR_RESET_VALUE  ((uint8_t)0x07) /*!< Polynomial Register reset value */
01703 #define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */
01704 #define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */
01705
01706 /**
01707   * @}
01708   */
01709
01710 /** @addtogroup SPI_Registers_Bits_Definition
01711   * @{
01712   */
01713
01714 #define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */
01715 #define SPI_CR1_SPE      ((uint8_t)0x40) /*!< Enable bits mask */
01716 #define SPI_CR1_BR       ((uint8_t)0x38) /*!< Baud rate control mask */
01717 #define SPI_CR1_MSTR     ((uint8_t)0x04) /*!< Master Selection mask */
01718 #define SPI_CR1_CPOL     ((uint8_t)0x02) /*!< Clock Polarity mask */
01719 #define SPI_CR1_CPHA     ((uint8_t)0x01) /*!< Clock Phase mask */
01720
01721 #define SPI_CR2_BDM      ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */
01722 #define SPI_CR2_BDOE     ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */
01723 #define SPI_CR2_CRCEN    ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */
01724 #define SPI_CR2_CRCNEXT  ((uint8_t)0x10) /*!< Transmit CRC next mask */
01725 #define SPI_CR2_RXONLY   ((uint8_t)0x04) /*!< Receive only mask */
01726 #define SPI_CR2_SSM      ((uint8_t)0x02) /*!< Software slave management mask */
01727 #define SPI_CR2_SSI      ((uint8_t)0x01) /*!< Internal slave select mask */
01728
01729 #define SPI_ICR_TXEI     ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */
01730 #define SPI_ICR_RXEI     ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */
01731 #define SPI_ICR_ERRIE    ((uint8_t)0x20) /*!< Error interrupt enable mask */
01732 #define SPI_ICR_WKIE     ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */
01733
01734 #define SPI_SR_BSY       ((uint8_t)0x80) /*!< Busy flag */
01735 #define SPI_SR_OVR       ((uint8_t)0x40) /*!< Overrun flag */
01736 #define SPI_SR_MODF      ((uint8_t)0x20) /*!< Mode fault */
01737 #define SPI_SR_CRCERR    ((uint8_t)0x10) /*!< CRC error flag */
01738 #define SPI_SR_WKUP      ((uint8_t)0x08) /*!< Wake-Up flag */
01739 #define SPI_SR_TXE       ((uint8_t)0x02) /*!< Transmit buffer empty */
01740 #define SPI_SR_RXNE      ((uint8_t)0x01) /*!< Receive buffer not empty */
01741
01742 /**
01743   * @}
01744   */
01745
01746 /*----------------------------------------------------------------------------*/
01747 /**
01748   * @brief  Universal Synchronous Asynchronous Receiver Transmitter (UART1)
01749   */
01750
01751 typedef struct UART1_struct
01752 {
01753   __IO uint8_t SR;   /*!< UART1 status register */
01754   __IO uint8_t DR;   /*!< UART1 data register */
01755   __IO uint8_t BRR1; /*!< UART1 baud rate register */
01756   __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
01757   __IO uint8_t CR1;  /*!< UART1 control register 1 */
01758   __IO uint8_t CR2;  /*!< UART1 control register 2 */
01759   __IO uint8_t CR3;  /*!< UART1 control register 3 */
01760   __IO uint8_t CR4;  /*!< UART1 control register 4 */
01761   __IO uint8_t CR5;  /*!< UART1 control register 5 */
01762   __IO uint8_t GTR;  /*!< UART1 guard time register */
01763   __IO uint8_t PSCR; /*!< UART1 prescaler register */
01764 }
01765 UART1_TypeDef;
01766
01767 /** @addtogroup UART1_Registers_Reset_Value
01768   * @{
01769   */
01770
01771 #define UART1_SR_RESET_VALUE   ((uint8_t)0xC0)
01772 #define UART1_BRR1_RESET_VALUE ((uint8_t)0x00)
01773 #define UART1_BRR2_RESET_VALUE ((uint8_t)0x00)
01774 #define UART1_CR1_RESET_VALUE  ((uint8_t)0x00)
01775 #define UART1_CR2_RESET_VALUE  ((uint8_t)0x00)
01776 #define UART1_CR3_RESET_VALUE  ((uint8_t)0x00)
01777 #define UART1_CR4_RESET_VALUE  ((uint8_t)0x00)
01778 #define UART1_CR5_RESET_VALUE  ((uint8_t)0x00)
01779 #define UART1_GTR_RESET_VALUE  ((uint8_t)0x00)
01780 #define UART1_PSCR_RESET_VALUE ((uint8_t)0x00)
01781
01782 /**
01783   * @}
01784   */
01785
01786 /** @addtogroup UART1_Registers_Bits_Definition
01787   * @{
01788   */
01789
01790 #define UART1_SR_TXE   ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
01791 #define UART1_SR_TC    ((uint8_t)0x40) /*!< Transmission Complete mask */
01792 #define UART1_SR_RXNE  ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
01793 #define UART1_SR_IDLE  ((uint8_t)0x10) /*!< IDLE line detected mask */
01794 #define UART1_SR_OR   ((uint8_t)0x08) /*!< OverRun error mask */
01795 #define UART1_SR_NF    ((uint8_t)0x04) /*!< Noise Flag mask */
01796 #define UART1_SR_FE    ((uint8_t)0x02) /*!< Framing Error mask */
01797 #define UART1_SR_PE    ((uint8_t)0x01) /*!< Parity Error mask */
01798
01799 #define UART1_BRR1_DIVM  ((uint8_t)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask */
01800
01801 #define UART1_BRR2_DIVM  ((uint8_t)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask */
01802 #define UART1_BRR2_DIVF  ((uint8_t)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask */
01803
01804 #define UART1_CR1_R8      ((uint8_t)0x80) /*!< Receive Data bit 8 */
01805 #define UART1_CR1_T8      ((uint8_t)0x40) /*!< Transmit data bit 8 */
01806 #define UART1_CR1_UARTD   ((uint8_t)0x20) /*!< UART1 Disable (for low power consumption) */
01807 #define UART1_CR1_M       ((uint8_t)0x10) /*!< Word length mask */
01808 #define UART1_CR1_WAKE    ((uint8_t)0x08) /*!< Wake-up method mask */
01809 #define UART1_CR1_PCEN    ((uint8_t)0x04) /*!< Parity Control Enable mask */
01810 #define UART1_CR1_PS      ((uint8_t)0x02) /*!< UART1 Parity Selection */
01811 #define UART1_CR1_PIEN    ((uint8_t)0x01) /*!< UART1 Parity Interrupt Enable mask */
01812
01813 #define UART1_CR2_TIEN    ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
01814 #define UART1_CR2_TCIEN   ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
01815 #define UART1_CR2_RIEN    ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
01816 #define UART1_CR2_ILIEN   ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
01817 #define UART1_CR2_TEN     ((uint8_t)0x08) /*!< Transmitter Enable mask */
01818 #define UART1_CR2_REN     ((uint8_t)0x04) /*!< Receiver Enable mask */
01819 #define UART1_CR2_RWU     ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
01820 #define UART1_CR2_SBK     ((uint8_t)0x01) /*!< Send Break mask */
01821
01822 #define UART1_CR3_LINEN   ((uint8_t)0x40) /*!< Alternate Function output mask */
01823 #define UART1_CR3_STOP    ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
01824 #define UART1_CR3_CKEN    ((uint8_t)0x08) /*!< Clock Enable mask */
01825 #define UART1_CR3_CPOL    ((uint8_t)0x04) /*!< Clock Polarity mask */
01826 #define UART1_CR3_CPHA    ((uint8_t)0x02) /*!< Clock Phase mask */
01827 #define UART1_CR3_LBCL    ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
01828
01829 #define UART1_CR4_LBDIEN  ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
01830 #define UART1_CR4_LBDL    ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
01831 #define UART1_CR4_LBDF    ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
01832 #define UART1_CR4_ADD     ((uint8_t)0x0F) /*!< Address of the UART1 node mask */
01833
01834 #define UART1_CR5_SCEN    ((uint8_t)0x20) /*!< Smart Card Enable mask */
01835 #define UART1_CR5_NACK    ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
01836 #define UART1_CR5_HDSEL   ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
01837 #define UART1_CR5_IRLP    ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
01838 #define UART1_CR5_IREN    ((uint8_t)0x02) /*!< Irda Enable mask */
01839
01840 /**
01841   * @}
01842   */
01843
01844 /*----------------------------------------------------------------------------*/
01845 /**
01846   * @brief  Universal Synchronous Asynchronous Receiver Transmitter (UART2)
01847   */
01848
01849 typedef struct UART2_struct
01850 {
01851   __IO uint8_t SR;   /*!< UART1 status register */
01852   __IO uint8_t DR;   /*!< UART1 data register */
01853   __IO uint8_t BRR1; /*!< UART1 baud rate register */
01854   __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
01855   __IO uint8_t CR1;  /*!< UART1 control register 1 */
01856   __IO uint8_t CR2;  /*!< UART1 control register 2 */
01857   __IO uint8_t CR3;  /*!< UART1 control register 3 */
01858   __IO uint8_t CR4;  /*!< UART1 control register 4 */
01859   __IO uint8_t CR5;  /*!< UART1 control register 5 */
01860         __IO uint8_t CR6;  /*!< UART1 control register 6 */
01861   __IO uint8_t GTR;  /*!< UART1 guard time register */
01862   __IO uint8_t PSCR; /*!< UART1 prescaler register */
01863 }
01864 UART2_TypeDef;
01865
01866 /** @addtogroup UART2_Registers_Reset_Value
01867   * @{
01868   */
01869
01870 #define UART2_SR_RESET_VALUE   ((uint8_t)0xC0)
01871 #define UART2_BRR1_RESET_VALUE ((uint8_t)0x00)
01872 #define UART2_BRR2_RESET_VALUE ((uint8_t)0x00)
01873 #define UART2_CR1_RESET_VALUE  ((uint8_t)0x00)
01874 #define UART2_CR2_RESET_VALUE  ((uint8_t)0x00)
01875 #define UART2_CR3_RESET_VALUE  ((uint8_t)0x00)
01876 #define UART2_CR4_RESET_VALUE  ((uint8_t)0x00)
01877 #define UART2_CR5_RESET_VALUE  ((uint8_t)0x00)
01878 #define UART2_CR6_RESET_VALUE  ((uint8_t)0x00)
01879 #define UART2_GTR_RESET_VALUE  ((uint8_t)0x00)
01880 #define UART2_PSCR_RESET_VALUE ((uint8_t)0x00)
01881
01882 /**
01883   * @}
01884   */
01885
01886 /** @addtogroup UART2_Registers_Bits_Definition
01887   * @{
01888   */
01889
01890 #define UART2_SR_TXE   ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
01891 #define UART2_SR_TC    ((uint8_t)0x40) /*!< Transmission Complete mask */
01892 #define UART2_SR_RXNE  ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
01893 #define UART2_SR_IDLE  ((uint8_t)0x10) /*!< IDLE line detected mask */
01894 #define UART2_SR_OR   ((uint8_t)0x08) /*!< OverRun error mask */
01895 #define UART2_SR_NF    ((uint8_t)0x04) /*!< Noise Flag mask */
01896 #define UART2_SR_FE    ((uint8_t)0x02) /*!< Framing Error mask */
01897 #define UART2_SR_PE    ((uint8_t)0x01) /*!< Parity Error mask */
01898
01899 #define UART2_BRR1_DIVM  ((uint8_t)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask */
01900
01901 #define UART2_BRR2_DIVM  ((uint8_t)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask */
01902 #define UART2_BRR2_DIVF  ((uint8_t)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask */
01903
01904 #define UART2_CR1_R8      ((uint8_t)0x80) /*!< Receive Data bit 8 */
01905 #define UART2_CR1_T8      ((uint8_t)0x40) /*!< Transmit data bit 8 */
01906 #define UART2_CR1_UARTD   ((uint8_t)0x20) /*!< UART2 Disable (for low power consumption) */
01907 #define UART2_CR1_M       ((uint8_t)0x10) /*!< Word length mask */
01908 #define UART2_CR1_WAKE    ((uint8_t)0x08) /*!< Wake-up method mask */
01909 #define UART2_CR1_PCEN    ((uint8_t)0x04) /*!< Parity Control Enable mask */
01910 #define UART2_CR1_PS      ((uint8_t)0x02) /*!< UART2 Parity Selection */
01911 #define UART2_CR1_PIEN    ((uint8_t)0x01) /*!< UART2 Parity Interrupt Enable mask */
01912
01913 #define UART2_CR2_TIEN    ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
01914 #define UART2_CR2_TCIEN   ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
01915 #define UART2_CR2_RIEN    ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
01916 #define UART2_CR2_ILIEN   ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
01917 #define UART2_CR2_TEN     ((uint8_t)0x08) /*!< Transmitter Enable mask */
01918 #define UART2_CR2_REN     ((uint8_t)0x04) /*!< Receiver Enable mask */
01919 #define UART2_CR2_RWU     ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
01920 #define UART2_CR2_SBK     ((uint8_t)0x01) /*!< Send Break mask */
01921
01922 #define UART2_CR3_LINEN   ((uint8_t)0x40) /*!< Alternate Function output mask */
01923 #define UART2_CR3_STOP    ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
01924 #define UART2_CR3_CKEN    ((uint8_t)0x08) /*!< Clock Enable mask */
01925 #define UART2_CR3_CPOL    ((uint8_t)0x04) /*!< Clock Polarity mask */
01926 #define UART2_CR3_CPHA    ((uint8_t)0x02) /*!< Clock Phase mask */
01927 #define UART2_CR3_LBCL    ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
01928
01929 #define UART2_CR4_LBDIEN  ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
01930 #define UART2_CR4_LBDL    ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
01931 #define UART2_CR4_LBDF    ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
01932 #define UART2_CR4_ADD     ((uint8_t)0x0F) /*!< Address of the UART2 node mask */
01933
01934 #define UART2_CR5_SCEN    ((uint8_t)0x20) /*!< Smart Card Enable mask */
01935 #define UART2_CR5_NACK    ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
01936 #define UART2_CR5_HDSEL   ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
01937 #define UART2_CR5_IRLP    ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
01938 #define UART2_CR5_IREN    ((uint8_t)0x02) /*!< Irda Enable mask */
01939
01940 #define UART2_CR6_LDUM    ((uint8_t)0x80) /*!< LIN Divider Update Method */
01941 #define UART2_CR6_LSLV    ((uint8_t)0x20) /*!< LIN Slave Enable */
01942 #define UART2_CR6_LASE    ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
01943 #define UART2_CR6_LHDIEN  ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */
01944 #define UART2_CR6_LHDF    ((uint8_t)0x02) /*!< LIN Header Detection Flag */
01945 #define UART2_CR6_LSF     ((uint8_t)0x01) /*!< LIN Synch Field */
01946
01947 /**
01948   * @}
01949   */
01950
01951
01952 /*----------------------------------------------------------------------------*/
01953 /**
01954   * @brief  LIN Universal Asynchronous Receiver Transmitter (UART3)
01955   */
01956
01957 typedef struct UART3_struct
01958 {
01959   __IO uint8_t SR;       /*!< status register */
01960   __IO uint8_t DR;       /*!< data register */
01961   __IO uint8_t BRR1;     /*!< baud rate register */
01962   __IO uint8_t BRR2;     /*!< DIV mantissa[11:8] SCIDIV fraction */
01963   __IO uint8_t CR1;      /*!< control register 1 */
01964   __IO uint8_t CR2;      /*!< control register 2 */
01965   __IO uint8_t CR3;      /*!< control register 3 */
01966   __IO uint8_t CR4;      /*!< control register 4 */
01967   uint8_t RESERVED; /*!< Reserved byte */
01968   __IO uint8_t CR6;      /*!< control register 5 */
01969 }
01970 UART3_TypeDef;
01971
01972 /** @addtogroup UART3_Registers_Reset_Value
01973   * @{
01974   */
01975
01976 #define UART3_SR_RESET_VALUE   ((uint8_t)0xC0)
01977 #define UART3_BRR1_RESET_VALUE ((uint8_t)0x00)
01978 #define UART3_BRR2_RESET_VALUE ((uint8_t)0x00)
01979 #define UART3_CR1_RESET_VALUE  ((uint8_t)0x00)
01980 #define UART3_CR2_RESET_VALUE  ((uint8_t)0x00)
01981 #define UART3_CR3_RESET_VALUE  ((uint8_t)0x00)
01982 #define UART3_CR4_RESET_VALUE  ((uint8_t)0x00)
01983 #define UART3_CR6_RESET_VALUE  ((uint8_t)0x00)
01984
01985 /**
01986   * @}
01987   */
01988
01989 /** @addtogroup UART3_Registers_Bits_Definition
01990   * @{
01991   */
01992
01993 #define UART3_SR_TXE      ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
01994 #define UART3_SR_TC       ((uint8_t)0x40) /*!< Transmission Complete mask */
01995 #define UART3_SR_RXNE     ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
01996 #define UART3_SR_IDLE     ((uint8_t)0x10) /*!< IDLE line detected mask */
01997 #define UART3_SR_OR       ((uint8_t)0x08) /*!< OverRun error mask */
01998 #define UART3_SR_NF       ((uint8_t)0x04) /*!< Noise Flag mask */
01999 #define UART3_SR_FE       ((uint8_t)0x02) /*!< Framing Error mask */
02000 #define UART3_SR_PE       ((uint8_t)0x01) /*!< Parity Error mask */
02001
02002 #define UART3_BRR1_DIVM   ((uint8_t)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask */
02003
02004 #define UART3_BRR2_DIVM   ((uint8_t)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask */
02005 #define UART3_BRR2_DIVF   ((uint8_t)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask */
02006
02007 #define UART3_CR1_R8      ((uint8_t)0x80) /*!< Receive Data bit 8 */
02008 #define UART3_CR1_T8      ((uint8_t)0x40) /*!< Transmit data bit 8 */
02009 #define UART3_CR1_UARTD   ((uint8_t)0x20) /*!< UART Disable (for low power consumption) */
02010 #define UART3_CR1_M       ((uint8_t)0x10) /*!< Word length mask */
02011 #define UART3_CR1_WAKE    ((uint8_t)0x08) /*!< Wake-up method mask */
02012 #define UART3_CR1_PCEN    ((uint8_t)0x04) /*!< Parity control enable mask */
02013 #define UART3_CR1_PS      ((uint8_t)0x02) /*!< Parity selection bit mask */
02014 #define UART3_CR1_PIEN    ((uint8_t)0x01) /*!< Parity interrupt enable bit mask */
02015
02016 #define UART3_CR2_TIEN    ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
02017 #define UART3_CR2_TCIEN   ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
02018 #define UART3_CR2_RIEN    ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
02019 #define UART3_CR2_ILIEN   ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
02020 #define UART3_CR2_TEN     ((uint8_t)0x08) /*!< Transmitter Enable mask */
02021 #define UART3_CR2_REN     ((uint8_t)0x04) /*!< Receiver Enable mask */
02022 #define UART3_CR2_RWU     ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
02023 #define UART3_CR2_SBK     ((uint8_t)0x01) /*!< Send Break mask */
02024
02025 #define UART3_CR3_LINEN   ((uint8_t)0x40) /*!< Alternate Function output mask */
02026 #define UART3_CR3_STOP    ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
02027
02028 #define UART3_CR4_LBDIEN  ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
02029 #define UART3_CR4_LBDL    ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
02030 #define UART3_CR4_LBDF    ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
02031 #define UART3_CR4_ADD     ((uint8_t)0x0F) /*!< Address of the UART3 node mask */
02032
02033 #define UART3_CR6_LDUM    ((uint8_t)0x80) /*!< LIN Divider Update Method */
02034 #define UART3_CR6_LSLV    ((uint8_t)0x20) /*!< LIN Slave Enable */
02035 #define UART3_CR6_LASE    ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
02036 #define UART3_CR6_LHDIEN  ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */
02037 #define UART3_CR6_LHDF    ((uint8_t)0x02) /*!< LIN Header Detection Flag */
02038 #define UART3_CR6_LSF     ((uint8_t)0x01) /*!< LIN Synch Field */
02039
02040 /**
02041   * @}
02042   */
02043
02044
02045 /*----------------------------------------------------------------------------*/
02046 /**
02047   * @brief  Controller Area Network  (CAN)
02048   */
02049
02050 typedef struct
02051 {
02052   __IO uint8_t MCR;    /*!< CAN master control register */
02053   __IO uint8_t MSR;    /*!< CAN master status register */
02054   __IO uint8_t TSR;    /*!< CAN transmit status register */
02055   __IO uint8_t TPR;    /*!< CAN transmit priority register */
02056   __IO uint8_t RFR;    /*!< CAN receive FIFO register */
02057   __IO uint8_t IER;    /*!< CAN interrupt enable register */
02058   __IO uint8_t DGR;    /*!< CAN diagnosis register */
02059   __IO uint8_t PSR;    /*!< CAN page selection register */
02060
02061   union
02062   {
02063     struct
02064     {
02065       __IO uint8_t MCSR;
02066       __IO uint8_t MDLCR;
02067       __IO uint8_t MIDR1;
02068       __IO uint8_t MIDR2;
02069       __IO uint8_t MIDR3;
02070       __IO uint8_t MIDR4;
02071       __IO uint8_t MDAR1;
02072       __IO uint8_t MDAR2;
02073       __IO uint8_t MDAR3;
02074       __IO uint8_t MDAR4;
02075       __IO uint8_t MDAR5;
02076       __IO uint8_t MDAR6;
02077       __IO uint8_t MDAR7;
02078       __IO uint8_t MDAR8;
02079       __IO uint8_t MTSRL;
02080       __IO uint8_t MTSRH;
02081     }
02082           TxMailbox;
02083
02084         struct
02085     {
02086       __IO uint8_t FR01;
02087       __IO uint8_t FR02;
02088       __IO uint8_t FR03;
02089       __IO uint8_t FR04;
02090       __IO uint8_t FR05;
02091       __IO uint8_t FR06;
02092       __IO uint8_t FR07;
02093       __IO uint8_t FR08;
02094
02095       __IO uint8_t FR09;
02096       __IO uint8_t FR10;
02097       __IO uint8_t FR11;
02098       __IO uint8_t FR12;
02099       __IO uint8_t FR13;
02100       __IO uint8_t FR14;
02101       __IO uint8_t FR15;
02102       __IO uint8_t FR16;
02103     }
02104         Filter;
02105
02106
02107     struct
02108     {
02109       __IO uint8_t F0R1;
02110       __IO uint8_t F0R2;
02111       __IO uint8_t F0R3;
02112       __IO uint8_t F0R4;
02113       __IO uint8_t F0R5;
02114       __IO uint8_t F0R6;
02115       __IO uint8_t F0R7;
02116       __IO uint8_t F0R8;
02117
02118       __IO uint8_t F1R1;
02119       __IO uint8_t F1R2;
02120       __IO uint8_t F1R3;
02121       __IO uint8_t F1R4;
02122       __IO uint8_t F1R5;
02123       __IO uint8_t F1R6;
02124       __IO uint8_t F1R7;
02125           __IO uint8_t F1R8;
02126     }
02127           Filter01;
02128
02129     struct
02130     {
02131       __IO uint8_t F2R1;
02132       __IO uint8_t F2R2;
02133       __IO uint8_t F2R3;
02134       __IO uint8_t F2R4;
02135       __IO uint8_t F2R5;
02136       __IO uint8_t F2R6;
02137       __IO uint8_t F2R7;
02138       __IO uint8_t F2R8;
02139
02140       __IO uint8_t F3R1;
02141       __IO uint8_t F3R2;
02142       __IO uint8_t F3R3;
02143       __IO uint8_t F3R4;
02144       __IO uint8_t F3R5;
02145       __IO uint8_t F3R6;
02146       __IO uint8_t F3R7;
02147       __IO uint8_t F3R8;
02148     }
02149           Filter23;
02150
02151     struct
02152     {
02153       __IO uint8_t F4R1;
02154       __IO uint8_t F4R2;
02155       __IO uint8_t F4R3;
02156       __IO uint8_t F4R4;
02157       __IO uint8_t F4R5;
02158       __IO uint8_t F4R6;
02159       __IO uint8_t F4R7;
02160       __IO uint8_t F4R8;
02161
02162       __IO uint8_t F5R1;
02163       __IO uint8_t F5R2;
02164       __IO uint8_t F5R3;
02165       __IO uint8_t F5R4;
02166       __IO uint8_t F5R5;
02167       __IO uint8_t F5R6;
02168       __IO uint8_t F5R7;
02169       __IO uint8_t F5R8;
02170     }
02171           Filter45;
02172
02173     struct
02174     {
02175       __IO uint8_t ESR;
02176       __IO uint8_t EIER;
02177       __IO uint8_t TECR;
02178       __IO uint8_t RECR;
02179       __IO uint8_t BTR1;
02180       __IO uint8_t BTR2;
02181       u8 Reserved1[2];
02182       __IO uint8_t FMR1;
02183       __IO uint8_t FMR2;
02184       __IO uint8_t FCR1;
02185       __IO uint8_t FCR2;
02186       __IO uint8_t FCR3;
02187       u8 Reserved2[3];
02188     }
02189                 Config;
02190
02191     struct
02192     {
02193       __IO uint8_t MFMI;
02194       __IO uint8_t MDLCR;
02195       __IO uint8_t MIDR1;
02196       __IO uint8_t MIDR2;
02197       __IO uint8_t MIDR3;
02198       __IO uint8_t MIDR4;
02199       __IO uint8_t MDAR1;
02200       __IO uint8_t MDAR2;
02201       __IO uint8_t MDAR3;
02202       __IO uint8_t MDAR4;
02203       __IO uint8_t MDAR5;
02204       __IO uint8_t MDAR6;
02205       __IO uint8_t MDAR7;
02206       __IO uint8_t MDAR8;
02207       __IO uint8_t MTSRL;
02208       __IO uint8_t MTSRH;
02209     }
02210           RxFIFO;
02211   }Page;
02212 } CAN_TypeDef;
02213 /** @addtogroup CAN_Registers_Bits_Definition
02214   * @{
02215   */
02216 /*******************************Common****************************************/
02217 /* CAN Master Control Register bits */
02218 #define CAN_MCR_INRQ     ((uint8_t)0x01)
02219 #define CAN_MCR_SLEEP    ((uint8_t)0x02)
02220 #define CAN_MCR_TXFP     ((uint8_t)0x04)
02221 #define CAN_MCR_RFLM     ((uint8_t)0x08)
02222 #define CAN_MCR_NART     ((uint8_t)0x10)
02223 #define CAN_MCR_AWUM     ((uint8_t)0x20)
02224 #define CAN_MCR_ABOM     ((uint8_t)0x40)
02225 #define CAN_MCR_TTCM     ((uint8_t)0x80)
02226
02227 /* CAN Master Status Register bits */
02228 #define CAN_MSR_INAK     ((uint8_t)0x01)
02229 #define CAN_MSR_SLAK     ((uint8_t)0x02)
02230 #define CAN_MSR_ERRI     ((uint8_t)0x04)
02231 #define CAN_MSR_WKUI     ((uint8_t)0x08)
02232 #define CAN_MSR_TX       ((uint8_t)0x10)
02233 #define CAN_MSR_RX       ((uint8_t)0x20)
02234
02235 /* CAN Transmit Status Register bits */
02236 #define CAN_TSR_RQCP0    ((uint8_t)0x01)
02237 #define CAN_TSR_RQCP1    ((uint8_t)0x02)
02238 #define CAN_TSR_RQCP2    ((uint8_t)0x04)
02239 #define CAN_TSR_RQCP012  ((uint8_t)0x07)
02240 #define CAN_TSR_TXOK0    ((uint8_t)0x10)
02241 #define CAN_TSR_TXOK1    ((uint8_t)0x20)
02242 #define CAN_TSR_TXOK2    ((uint8_t)0x40)
02243
02244 #define CAN_TPR_CODE0    ((uint8_t)0x01)
02245 #define CAN_TPR_TME0     ((uint8_t)0x04)
02246 #define CAN_TPR_TME1     ((uint8_t)0x08)
02247 #define CAN_TPR_TME2     ((uint8_t)0x10)
02248 #define CAN_TPR_LOW0     ((uint8_t)0x20)
02249 #define CAN_TPR_LOW1     ((uint8_t)0x40)
02250 #define CAN_TPR_LOW2     ((uint8_t)0x80)
02251 /* CAN Receive FIFO Register bits */
02252 #define CAN_RFR_FMP01  ((uint8_t)0x03)
02253 #define CAN_RFR_FULL   ((uint8_t)0x08)
02254 #define CAN_RFR_FOVR   ((uint8_t)0x10)
02255 #define CAN_RFR_RFOM   ((uint8_t)0x20)
02256
02257 /* CAN Interrupt Register bits */
02258 #define CAN_IER_TMEIE  ((uint8_t)0x01)
02259 #define CAN_IER_FMPIE  ((uint8_t)0x02)
02260 #define CAN_IER_FFIE   ((uint8_t)0x04)
02261 #define CAN_IER_FOVIE  ((uint8_t)0x08)
02262 #define CAN_IER_WKUIE  ((uint8_t)0x80)
02263
02264
02265 /* CAN diagnostic Register bits */
02266 #define CAN_DGR_LBKM  ((uint8_t)0x01)
02267 #define CAN_DGR_SLIM  ((uint8_t)0x02)
02268 #define CAN_DGR_SAMP  ((uint8_t)0x04)
02269 #define CAN_DGR_RX    ((uint8_t)0x08)
02270 #define CAN_DGR_TXM2E ((uint8_t)0x10)
02271
02272
02273 /* CAN page select Register bits */
02274 #define CAN_PSR_PS0  ((uint8_t)0x01)
02275 #define CAN_PSR_PS1  ((uint8_t)0x02)
02276 #define CAN_PSR_PS2  ((uint8_t)0x04)
02277
02278 /*********************Tx MailBox & Fifo Page common bits***********************/
02279 #define CAN_MCSR_TXRQ    ((uint8_t)0x01)
02280 #define CAN_MCSR_ABRQ    ((uint8_t)0x02)
02281 #define CAN_MCSR_RQCP    ((uint8_t)0x04)
02282 #define CAN_MCSR_TXOK    ((uint8_t)0x08)
02283 #define CAN_MCSR_ALST    ((uint8_t)0x10)
02284 #define CAN_MCSR_TERR    ((uint8_t)0x20)
02285
02286 #define CAN_MDLCR_DLC    ((uint8_t)0x0F)
02287 #define CAN_MDLCR_TGT    ((uint8_t)0x80)
02288
02289 #define CAN_MIDR1_RTR    ((uint8_t)0x20)
02290 #define CAN_MIDR1_IDE    ((uint8_t)0x40)
02291
02292
02293 /*************************Filter Page******************************************/
02294
02295 /* CAN Error Status Register bits */
02296 #define CAN_ESR_EWGF     ((uint8_t)0x01)
02297 #define CAN_ESR_EPVF     ((uint8_t)0x02)
02298 #define CAN_ESR_BOFF     ((uint8_t)0x04)
02299 #define CAN_ESR_LEC0     ((uint8_t)0x10)
02300 #define CAN_ESR_LEC1     ((uint8_t)0x20)
02301 #define CAN_ESR_LEC2     ((uint8_t)0x40)
02302 #define CAN_ESR_LEC      ((uint8_t)0x70)
02303
02304 /* CAN Error Status Register bits */
02305 #define CAN_EIER_EWGIE    ((uint8_t)0x01)
02306 #define CAN_EIER_EPVIE    ((uint8_t)0x02)
02307 #define CAN_EIER_BOFIE    ((uint8_t)0x04)
02308 #define CAN_EIER_LECIE    ((uint8_t)0x10)
02309 #define CAN_EIER_ERRIE    ((uint8_t)0x80)
02310
02311 /* CAN transmit error counter Register bits(CAN_TECR) */
02312 #define CAN_TECR_TEC0     ((uint8_t)0x01)
02313 #define CAN_TECR_TEC1     ((uint8_t)0x02)
02314 #define CAN_TECR_TEC2     ((uint8_t)0x04)
02315 #define CAN_TECR_TEC3     ((uint8_t)0x08)
02316 #define CAN_TECR_TEC4     ((uint8_t)0x10)
02317 #define CAN_TECR_TEC5     ((uint8_t)0x20)
02318 #define CAN_TECR_TEC6     ((uint8_t)0x40)
02319 #define CAN_TECR_TEC7     ((uint8_t)0x80)
02320
02321 /* CAN RECEIVE error counter Register bits(CAN_TECR) */
02322 #define CAN_RECR_REC0     ((uint8_t)0x01)
02323 #define CAN_RECR_REC1     ((uint8_t)0x02)
02324 #define CAN_RECR_REC2     ((uint8_t)0x04)
02325 #define CAN_RECR_REC3     ((uint8_t)0x08)
02326 #define CAN_RECR_REC4     ((uint8_t)0x10)
02327 #define CAN_RECR_REC5     ((uint8_t)0x20)
02328 #define CAN_RECR_REC6     ((uint8_t)0x40)
02329 #define CAN_RECR_REC7     ((uint8_t)0x80)
02330
02331 /* CAN filter mode register bits (CAN_FMR) */
02332 #define CAN_FMR1_FML0     ((uint8_t)0x01)
02333 #define CAN_FMR1_FMH0     ((uint8_t)0x02)
02334 #define CAN_FMR1_FML1     ((uint8_t)0x04)
02335 #define CAN_FMR1_FMH1     ((uint8_t)0x08)
02336 #define CAN_FMR1_FML2     ((uint8_t)0x10)
02337 #define CAN_FMR1_FMH2     ((uint8_t)0x20)
02338 #define CAN_FMR1_FML3     ((uint8_t)0x40)
02339 #define CAN_FMR1_FMH3     ((uint8_t)0x80)
02340
02341 #define CAN_FMR2_FML4     ((uint8_t)0x01)
02342 #define CAN_FMR2_FMH4     ((uint8_t)0x02)
02343 #define CAN_FMR2_FML5     ((uint8_t)0x04)
02344 #define CAN_FMR2_FMH5     ((uint8_t)0x08)
02345
02346 /* CAN filter Config register bits (CAN_FCR) */
02347 #define CAN_FCR1_FACT0     ((uint8_t)0x01)
02348 #define CAN_FCR1_FACT1     ((uint8_t)0x10)
02349 #define CAN_FCR2_FACT2     ((uint8_t)0x01)
02350 #define CAN_FCR2_FACT3     ((uint8_t)0x10)
02351 #define CAN_FCR3_FACT4     ((uint8_t)0x01)
02352 #define CAN_FCR3_FACT5     ((uint8_t)0x10)
02353
02354 #define CAN_FCR1_FSC00    ((uint8_t)0x02)
02355 #define CAN_FCR1_FSC01    ((uint8_t)0x04)
02356 #define CAN_FCR1_FSC10    ((uint8_t)0x20)
02357 #define CAN_FCR1_FSC11    ((uint8_t)0x40)
02358 #define CAN_FCR2_FSC20    ((uint8_t)0x02)
02359 #define CAN_FCR2_FSC21    ((uint8_t)0x04)
02360 #define CAN_FCR2_FSC30    ((uint8_t)0x20)
02361 #define CAN_FCR2_FSC31    ((uint8_t)0x40)
02362 #define CAN_FCR3_FSC40    ((uint8_t)0x02)
02363 #define CAN_FCR3_FSC41    ((uint8_t)0x04)
02364 #define CAN_FCR3_FSC50    ((uint8_t)0x20)
02365 #define CAN_FCR3_FSC51    ((uint8_t)0x40)
02366
02367
02368
02369 /**
02370   * @}
02371   */
02372
02373 /** @addtogroup CAN_Registers_Reset_Value
02374   * @{
02375   */
02376
02377 #define         CAN_MCR_RESET_VALUE                     ((uint8_t)0x02)
02378 #define         CAN_MSR_RESET_VALUE                     ((uint8_t)0x02)
02379 #define         CAN_TSR_RESET_VALUE                     ((uint8_t)0x00)
02380 #define         CAN_TPR_RESET_VALUE                     ((uint8_t)0x0C)
02381 #define         CAN_RFR_RESET_VALUE                     ((uint8_t)0x00)
02382 #define         CAN_IER_RESET_VALUE                     ((uint8_t)0x00)
02383 #define         CAN_DGR_RESET_VALUE                     ((uint8_t)0x0C)
02384 #define         CAN_PSR_RESET_VALUE                     ((uint8_t)0x00)
02385
02386 #define         CAN_ESR_RESET_VALUE                     ((uint8_t)0x00)
02387 #define         CAN_EIER_RESET_VALUE            ((uint8_t)0x00)
02388 #define         CAN_TECR_RESET_VALUE            ((uint8_t)0x00)
02389 #define         CAN_RECR_RESET_VALUE            ((uint8_t)0x00)
02390 #define         CAN_BTR1_RESET_VALUE            ((uint8_t)0x40)
02391 #define         CAN_BTR2_RESET_VALUE            ((uint8_t)0x23)
02392 #define         CAN_FMR1_RESET_VALUE            ((uint8_t)0x00)
02393 #define         CAN_FMR2_RESET_VALUE            ((uint8_t)0x00)
02394 #define         CAN_FCR_RESET_VALUE                     ((uint8_t)0x00)
02395
02396 #define         CAN_MFMI_RESET_VALUE                    ((uint8_t)0x00)
02397 #define         CAN_MDLC_RESET_VALUE                    ((uint8_t)0x00)
02398 #define         CAN_MCSR_RESET_VALUE                    ((uint8_t)0x00)
02399
02400 /**
02401   * @}
02402   */
02403
02404 /**
02405   * @brief  Configuration Registers (CFG)
02406   */
02407
02408 typedef struct CFG_struct
02409 {
02410   __IO uint8_t GCR; /*!< Global Configuration register */
02411 }
02412 CFG_TypeDef;
02413
02414 /** @addtogroup CFG_Registers_Reset_Value
02415   * @{
02416   */
02417
02418 #define CFG_GCR_RESET_VALUE ((uint8_t)0x00)
02419
02420 /**
02421   * @}
02422   */
02423
02424 /** @addtogroup CFG_Registers_Bits_Definition
02425   * @{
02426   */
02427
02428 #define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */
02429 #define CFG_GCR_AL  ((uint8_t)0x02) /*!< Activation Level bit mask */
02430
02431 /**
02432   * @}
02433   */
02434
02435 /**
02436   * @}
02437   */
02438
02439 /******************************************************************************/
02440 /*                          Peripherals Base Address                          */
02441 /******************************************************************************/
02442
02443 /** @addtogroup MAP_FILE_Base_Addresses
02444   * @{
02445   */
02446 #define OPT_BaseAddress         0x4800
02447 #define GPIOA_BaseAddress       0x5000
02448 #define GPIOB_BaseAddress       0x5005
02449 #define GPIOC_BaseAddress       0x500A
02450 #define GPIOD_BaseAddress       0x500F
02451 #define GPIOE_BaseAddress       0x5014
02452 #define GPIOF_BaseAddress       0x5019
02453 #define GPIOG_BaseAddress       0x501E
02454 #define GPIOH_BaseAddress       0x5023
02455 #define GPIOI_BaseAddress       0x5028
02456 #define FLASH_BaseAddress       0x505A
02457 #define EXTI_BaseAddress        0x50A0
02458 #define RST_BaseAddress         0x50B3
02459 #define CLK_BaseAddress         0x50C0
02460 #define WWDG_BaseAddress        0x50D1
02461 #define IWDG_BaseAddress        0x50E0
02462 #define AWU_BaseAddress         0x50F0
02463 #define BEEP_BaseAddress        0x50F3
02464 #define SPI_BaseAddress         0x5200
02465 #define I2C_BaseAddress         0x5210
02466 #define UART1_BaseAddress       0x5230
02467 #define UART2_BaseAddress       0x5240
02468 #define UART3_BaseAddress       0x5240
02469 #define TIM1_BaseAddress        0x5250
02470 #define TIM2_BaseAddress        0x5300
02471 #define TIM3_BaseAddress        0x5320
02472 #define TIM4_BaseAddress        0x5340
02473 #define TIM5_BaseAddress        0x5300
02474 #define TIM6_BaseAddress        0x5340
02475 #define ADC1_BaseAddress        0x53E0
02476 #define ADC2_BaseAddress        0x5400
02477 #define CAN_BaseAddress         0x5420
02478 #define CFG_BaseAddress         0x7F60
02479 #define ITC_BaseAddress         0x7F70
02480 #define DM_BaseAddress          0x7F90
02481
02482 /**
02483   * @}
02484   */
02485
02486 /******************************************************************************/
02487 /*                          Peripherals declarations                          */
02488 /******************************************************************************/
02489
02490 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
02491     defined(STM8S903) || defined(STM8AF626x)
02492  #define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)
02493 #endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */
02494
02495 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
02496     defined (STM8AF62Ax)
02497 #define ADC2 ((ADC2_TypeDef *) ADC2_BaseAddress)
02498 #endif /* (STM8S208) ||(STM8S207) || (STM8S007) || (STM8AF52Ax) || (STM8AF62Ax) */
02499
02500 #define AWU ((AWU_TypeDef *) AWU_BaseAddress)
02501
02502 #define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
02503
02504 #if defined (STM8S208) || defined (STM8AF52Ax)
02505  #define CAN ((CAN_TypeDef *) CAN_BaseAddress)
02506 #endif /* (STM8S208) || (STM8AF52Ax) */
02507
02508 #define CLK ((CLK_TypeDef *) CLK_BaseAddress)
02509
02510 #define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)
02511
02512 #define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
02513
02514 #define OPT ((OPT_TypeDef *) OPT_BaseAddress)
02515
02516 #define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
02517
02518 #define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
02519
02520 #define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
02521
02522 #define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
02523
02524 #define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
02525
02526 #define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
02527
02528 #if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined(STM8S105) || \
02529     defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)
02530  #define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress)
02531 #endif /* (STM8S208) ||(STM8S207)  || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x) */
02532
02533 #if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || \
02534     defined (STM8AF62Ax)
02535  #define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress)
02536  #define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress)
02537 #endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
02538
02539 #define RST ((RST_TypeDef *) RST_BaseAddress)
02540
02541 #define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
02542 #define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
02543
02544 #define SPI ((SPI_TypeDef *) SPI_BaseAddress)
02545 #define I2C ((I2C_TypeDef *) I2C_BaseAddress)
02546
02547 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
02548     defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
02549  #define UART1 ((UART1_TypeDef *) UART1_BaseAddress)
02550 #endif /* (STM8S208) ||(STM8S207)  || (STM8S103) || (STM8S903) || (STM8AF52Ax) || (STM8AF62Ax) */
02551
02552 #if defined (STM8S105) || defined (STM8S005) || defined (STM8AF626x)
02553  #define UART2 ((UART2_TypeDef *) UART2_BaseAddress)
02554 #endif /* STM8S105 || STM8S005 || STM8AF626x */
02555
02556 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
02557     defined (STM8AF62Ax)
02558  #define UART3 ((UART3_TypeDef *) UART3_BaseAddress)
02559 #endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
02560
02561 #define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
02562
02563 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
02564     defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \
02565     defined (STM8AF62Ax) || defined (STM8AF626x)
02566  #define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)
02567 #endif /* (STM8S208) ||(STM8S207)  || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/
02568
02569 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S105) || \
02570     defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)
02571  #define TIM3 ((TIM3_TypeDef *) TIM3_BaseAddress)
02572 #endif /* (STM8S208) ||(STM8S207)  || (STM8S105) || (STM8AF62Ax) || (STM8AF52Ax) || (STM8AF626x)*/
02573
02574 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
02575     defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \
02576     defined (STM8AF62Ax) || defined (STM8AF626x)
02577  #define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)
02578 #endif /* (STM8S208) ||(STM8S207)  || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/
02579
02580 #ifdef STM8S903
02581  #define TIM5 ((TIM5_TypeDef *) TIM5_BaseAddress)
02582  #define TIM6 ((TIM6_TypeDef *) TIM6_BaseAddress)
02583 #endif /* STM8S903 */
02584
02585 #define ITC ((ITC_TypeDef *) ITC_BaseAddress)
02586
02587 #define CFG ((CFG_TypeDef *) CFG_BaseAddress)
02588
02589 #define DM ((DM_TypeDef *) DM_BaseAddress)
02590
02591
02592 #ifdef USE_STDPERIPH_DRIVER
02593  #include "stm8s_conf.h"
02594 #endif
02595
02596 /* Exported macro --------------------------------------------------------------*/
02597
02598 /*============================== Interrupts ====================================*/
02599 #ifdef _RAISONANCE_
02600  #include <intrins.h>
02601  #define enableInterrupts()    _rim_()  /* enable interrupts */
02602  #define disableInterrupts()   _sim_()  /* disable interrupts */
02603  #define rim()                 _rim_()  /* enable interrupts */
02604  #define sim()                 _sim_()  /* disable interrupts */
02605  #define nop()                 _nop_()  /* No Operation */
02606  #define trap()                _trap_() /* Trap (soft IT) */
02607  #define wfi()                 _wfi_()  /* Wait For Interrupt */
02608  #define halt()                _halt_() /* Halt */
02609 #elif defined(_COSMIC_)
02610  #define enableInterrupts()    {_asm("rim\n");}  /* enable interrupts */
02611  #define disableInterrupts()   {_asm("sim\n");}  /* disable interrupts */
02612  #define rim()                 {_asm("rim\n");}  /* enable interrupts */
02613  #define sim()                 {_asm("sim\n");}  /* disable interrupts */
02614  #define nop()                 {_asm("nop\n");}  /* No Operation */
02615  #define trap()                {_asm("trap\n");} /* Trap (soft IT) */
02616  #define wfi()                 {_asm("wfi\n");}  /* Wait For Interrupt */
02617  #define halt()                {_asm("halt\n");} /* Halt */
02618 #else /*_IAR_*/
02619  #include <intrinsics.h>
02620  #define enableInterrupts()    __enable_interrupt()   /* enable interrupts */
02621  #define disableInterrupts()   __disable_interrupt()  /* disable interrupts */
02622  #define rim()                 __enable_interrupt()   /* enable interrupts */
02623  #define sim()                 __disable_interrupt()  /* disable interrupts */
02624  #define nop()                 __no_operation()       /* No Operation */
02625  #define trap()                __trap()               /* Trap (soft IT) */
02626  #define wfi()                 __wait_for_interrupt() /* Wait For Interrupt */
02627  #define halt()                __halt()               /* Halt */
02628 #endif /*_RAISONANCE_*/
02629
02630 /*============================== Interrupt vector Handling ========================*/
02631
02632 #ifdef _COSMIC_
02633  #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void)
02634  #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void)
02635 #endif /* _COSMIC_ */
02636
02637 #ifdef _RAISONANCE_
02638  #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b
02639  #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap
02640 #endif /* _RAISONANCE_ */
02641
02642 #ifdef _IAR_
02643  #define STRINGVECTOR(x) #x
02644  #define VECTOR_ID(x) STRINGVECTOR( vector = (x) )
02645  #define INTERRUPT_HANDLER( a, b )  \
02646  _Pragma( VECTOR_ID( (b)+2 ) )        \
02647  __interrupt void (a)( void )
02648  #define INTERRUPT_HANDLER_TRAP(a) \
02649  _Pragma( VECTOR_ID( 1 ) ) \
02650  __interrupt void (a) (void)
02651 #endif /* _IAR_ */
02652
02653 /*============================== Interrupt Handler declaration ========================*/
02654 #ifdef _COSMIC_
02655  #define INTERRUPT @far @interrupt
02656 #elif defined(_IAR_)
02657  #define INTERRUPT __interrupt
02658 #endif /* _COSMIC_ */
02659
02660 /*============================== Handling bits ====================================*/
02661 /*-----------------------------------------------------------------------------
02662 Method : I
02663 Description : Handle the bit from the character variables.
02664 Comments :    The different parameters of commands are
02665               - VAR : Name of the character variable where the bit is located.
02666               - Place : Bit position in the variable (7 6 5 4 3 2 1 0)
02667               - Value : Can be 0 (reset bit) or not 0 (set bit)
02668               The "MskBit" command allows to select some bits in a source
02669               variables and copy it in a destination var (return the value).
02670               The "ValBit" command returns the value of a bit in a char
02671               variable: the bit is reset if it returns 0 else the bit is set.
02672               This method generates not an optimised code yet.
02673 -----------------------------------------------------------------------------*/
02674 #define SetBit(VAR,Place)         ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
02675 #define ClrBit(VAR,Place)         ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
02676
02677 #define ChgBit(VAR,Place)         ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
02678 #define AffBit(VAR,Place,Value)   ((Value) ? \
02679                                    ((VAR) |= ((uint8_t)1<<(Place))) : \
02680                                    ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))
02681 #define MskBit(Dest,Msk,Src)      ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )
02682
02683 #define ValBit(VAR,Place)         ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))
02684
02685 #define BYTE_0(n)                 ((uint8_t)((n) & (uint8_t)0xFF))        /*!< Returns the low byte of the 32-bit value */
02686 #define BYTE_1(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))  /*!< Returns the second byte of the 32-bit value */
02687 #define BYTE_2(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */
02688 #define BYTE_3(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */
02689
02690 /*============================== Assert Macros ====================================*/
02691 #define IS_STATE_VALUE_OK(SensitivityValue) \
02692   (((SensitivityValue) == ENABLE) || \
02693    ((SensitivityValue) == DISABLE))
02694
02695 /*-----------------------------------------------------------------------------
02696 Method : II
02697 Description : Handle directly the bit.
02698 Comments :    The idea is to handle directly with the bit name. For that, it is
02699               necessary to have RAM area descriptions (example: HW register...)
02700               and the following command line for each area.
02701               This method generates the most optimized code.
02702 -----------------------------------------------------------------------------*/
02703
02704 #define AREA 0x00     /* The area of bits begins at address 0x10. */
02705
02706 #define BitClr(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
02707 #define BitSet(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
02708 #define BitVal(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
02709
02710 /* Exported functions ------------------------------------------------------- */
02711
02712 #endif /* __STM8S_H */
02713
02714 /**
02715   * @}
02716   */
02717
02718 /**
02719   * @}
02720   */
02721 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_adc1.c Source File

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stm8s_adc1.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_adc1.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions/macros for the ADC1 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_adc1.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034
00035 /* Public functions ----------------------------------------------------------*/
00036
00037 /**
00038   * @addtogroup ADC1_Public_Functions
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  Deinitializes the ADC1 peripheral registers to their default reset
00044   * values.
00045   * @param  None
00046   * @retval None
00047   */
00048 void ADC1_DeInit(void)
00049 {
00050     ADC1->CSR  = ADC1_CSR_RESET_VALUE;
00051     ADC1->CR1  = ADC1_CR1_RESET_VALUE;
00052     ADC1->CR2  = ADC1_CR2_RESET_VALUE;
00053     ADC1->CR3  = ADC1_CR3_RESET_VALUE;
00054     ADC1->TDRH = ADC1_TDRH_RESET_VALUE;
00055     ADC1->TDRL = ADC1_TDRL_RESET_VALUE;
00056     ADC1->HTRH = ADC1_HTRH_RESET_VALUE;
00057     ADC1->HTRL = ADC1_HTRL_RESET_VALUE;
00058     ADC1->LTRH = ADC1_LTRH_RESET_VALUE;
00059     ADC1->LTRL = ADC1_LTRL_RESET_VALUE;
00060     ADC1->AWCRH = ADC1_AWCRH_RESET_VALUE;
00061     ADC1->AWCRL = ADC1_AWCRL_RESET_VALUE;
00062 }
00063
00064
00065 /**
00066   * @brief  Initializes the ADC1 peripheral according to the specified parameters
00067   * @param   ADC1_ConversionMode: specifies the conversion mode
00068   * can be one of the values of @ref ADC1_ConvMode_TypeDef.
00069   * @param   ADC1_Channel: specifies the channel to convert
00070   * can be one of the values of @ref ADC1_Channel_TypeDef.
00071   * @param   ADC1_PrescalerSelection: specifies the ADC1 prescaler
00072   * can be one of the values of @ref ADC1_PresSel_TypeDef.
00073   * @param   ADC1_ExtTrigger: specifies the external trigger
00074   * can be one of the values of @ref ADC1_ExtTrig_TypeDef.
00075   * @param   ADC1_ExtTriggerState: specifies the external trigger new state
00076   * can be one of the values of @ref FunctionalState.
00077   * @param   ADC1_Align: specifies the converted data alignment
00078   * can be one of the values of @ref ADC1_Align_TypeDef.
00079   * @param   ADC1_SchmittTriggerChannel: specifies the schmitt trigger channel
00080   * can be one of the values of @ref ADC1_SchmittTrigg_TypeDef.
00081   * @param   ADC1_SchmittTriggerState: specifies the schmitt trigger state
00082   * can be one of the values of @ref FunctionalState.
00083   * @retval None
00084   */
00085 void ADC1_Init(ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)
00086 {
00087
00088     /* Check the parameters */
00089     assert_param(IS_ADC1_CONVERSIONMODE_OK(ADC1_ConversionMode));
00090     assert_param(IS_ADC1_CHANNEL_OK(ADC1_Channel));
00091     assert_param(IS_ADC1_PRESSEL_OK(ADC1_PrescalerSelection));
00092     assert_param(IS_ADC1_EXTTRIG_OK(ADC1_ExtTrigger));
00093     assert_param(IS_FUNCTIONALSTATE_OK(((ADC1_ExtTriggerState))));
00094     assert_param(IS_ADC1_ALIGN_OK(ADC1_Align));
00095     assert_param(IS_ADC1_SCHMITTTRIG_OK(ADC1_SchmittTriggerChannel));
00096     assert_param(IS_FUNCTIONALSTATE_OK(ADC1_SchmittTriggerState));
00097
00098     /*-----------------CR1 & CSR configuration --------------------*/
00099     /* Configure the conversion mode and the channel to convert
00100     respectively according to ADC1_ConversionMode & ADC1_Channel values  &  ADC1_Align values */
00101     ADC1_ConversionConfig(ADC1_ConversionMode, ADC1_Channel, ADC1_Align);
00102     /* Select the prescaler division factor according to ADC1_PrescalerSelection values */
00103     ADC1_PrescalerConfig(ADC1_PrescalerSelection);
00104
00105     /*-----------------CR2 configuration --------------------*/
00106     /* Configure the external trigger state and event respectively
00107     according to NewState, ADC1_ExtTrigger */
00108     ADC1_ExternalTriggerConfig(ADC1_ExtTrigger, ADC1_ExtTriggerState);
00109
00110     /*------------------TDR configuration ---------------------------*/
00111     /* Configure the schmitt trigger channel and state respectively
00112     according to ADC1_SchmittTriggerChannel & ADC1_SchmittTriggerNewState  values */
00113     ADC1_SchmittTriggerConfig(ADC1_SchmittTriggerChannel, ADC1_SchmittTriggerState);
00114
00115     /* Enable the ADC1 peripheral */
00116     ADC1->CR1 |= ADC1_CR1_ADON;
00117
00118 }
00119
00120
00121 /**
00122   * @brief  Enables or Disables the ADC1 peripheral.
00123   * @param   NewState: specifies the peripheral enabled or disabled state.
00124   * @retval None
00125   */
00126 void ADC1_Cmd(FunctionalState NewState)
00127 {
00128
00129     /* Check the parameters */
00130     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00131
00132     if (NewState != DISABLE)
00133     {
00134         ADC1->CR1 |= ADC1_CR1_ADON;
00135     }
00136     else /* NewState == DISABLE */
00137     {
00138         ADC1->CR1 &= (uint8_t)(~ADC1_CR1_ADON);
00139     }
00140
00141 }
00142
00143 /**
00144   * @brief  Enables or Disables the ADC1 scan mode.
00145   * @param   NewState: specifies the selected mode enabled or disabled state.
00146   * @retval None
00147   */
00148 void ADC1_ScanModeCmd(FunctionalState NewState)
00149 {
00150
00151     /* Check the parameters */
00152     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00153
00154     if (NewState != DISABLE)
00155     {
00156         ADC1->CR2 |= ADC1_CR2_SCAN;
00157     }
00158     else /* NewState == DISABLE */
00159     {
00160         ADC1->CR2 &= (uint8_t)(~ADC1_CR2_SCAN);
00161     }
00162
00163 }
00164
00165 /**
00166   * @brief  Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register
00167   * @param   NewState: specifies the selected mode enabled or disabled state.
00168   * @retval None
00169   */
00170 void ADC1_DataBufferCmd(FunctionalState NewState)
00171 {
00172
00173     /* Check the parameters */
00174     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00175
00176     if (NewState != DISABLE)
00177     {
00178         ADC1->CR3 |= ADC1_CR3_DBUF;
00179     }
00180     else /* NewState == DISABLE */
00181     {
00182         ADC1->CR3 &= (uint8_t)(~ADC1_CR3_DBUF);
00183     }
00184
00185 }
00186
00187 /**
00188   * @brief  Enables or disables the ADC1 interrupt.
00189   * @param   ADC1_IT specifies the name of the interrupt to enable or disable.
00190   * This parameter can be one of the following values:
00191   *    - ADC1_IT_AWDITEN : Analog WDG interrupt enable
00192   *    - ADC1_IT_EOCITEN  : EOC iterrupt enable
00193   * @param   NewState specifies the state of the interrupt to apply.
00194   * @retval None
00195   */
00196 void ADC1_ITConfig(ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)
00197 {
00198
00199     /* Check the parameters */
00200     assert_param(IS_ADC1_IT_OK(ADC1_IT));
00201     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00202
00203     if (NewState != DISABLE)
00204     {
00205         /* Enable the ADC1 interrupts */
00206         ADC1->CSR |= (uint8_t)ADC1_IT;
00207     }
00208     else  /* NewState == DISABLE */
00209     {
00210         /* Disable the ADC1 interrupts */
00211         ADC1->CSR &= (uint8_t)((uint16_t)~(uint16_t)ADC1_IT);
00212     }
00213
00214 }
00215
00216 /**
00217   * @brief  Configure the ADC1 prescaler division factor.
00218   * @param   ADC1_Prescaler: the selected precaler.
00219   * It can be one of the values of @ref ADC1_PresSel_TypeDef.
00220   * @retval None
00221   */
00222 void ADC1_PrescalerConfig(ADC1_PresSel_TypeDef ADC1_Prescaler)
00223 {
00224
00225     /* Check the parameter */
00226     assert_param(IS_ADC1_PRESSEL_OK(ADC1_Prescaler));
00227
00228     /* Clear the SPSEL bits */
00229     ADC1->CR1 &= (uint8_t)(~ADC1_CR1_SPSEL);
00230     /* Select the prescaler division factor according to ADC1_PrescalerSelection values */
00231     ADC1->CR1 |= (uint8_t)(ADC1_Prescaler);
00232
00233 }
00234
00235
00236 /**
00237   * @brief  Enables or disables the ADC1 Schmitt Trigger on a selected channel.
00238   * @param   ADC1_SchmittTriggerChannel specifies the desired Channel.
00239   * It can be set of the values of @ref ADC1_SchmittTrigg_TypeDef.
00240   * @param   NewState specifies Channel new status.
00241   * can have one of the values of @ref FunctionalState.
00242   * @retval None
00243   */
00244 void ADC1_SchmittTriggerConfig(ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)
00245 {
00246
00247     /* Check the parameters */
00248     assert_param(IS_ADC1_SCHMITTTRIG_OK(ADC1_SchmittTriggerChannel));
00249     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00250
00251     if (ADC1_SchmittTriggerChannel == ADC1_SCHMITTTRIG_ALL)
00252     {
00253         if (NewState != DISABLE)
00254         {
00255             ADC1->TDRL &= (uint8_t)0x0;
00256             ADC1->TDRH &= (uint8_t)0x0;
00257         }
00258         else /* NewState == DISABLE */
00259         {
00260             ADC1->TDRL |= (uint8_t)0xFF;
00261             ADC1->TDRH |= (uint8_t)0xFF;
00262         }
00263     }
00264     else if (ADC1_SchmittTriggerChannel < ADC1_SCHMITTTRIG_CHANNEL8)
00265     {
00266         if (NewState != DISABLE)
00267         {
00268             ADC1->TDRL &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << (uint8_t)ADC1_SchmittTriggerChannel));
00269         }
00270         else /* NewState == DISABLE */
00271         {
00272             ADC1->TDRL |= (uint8_t)((uint8_t)0x01 << (uint8_t)ADC1_SchmittTriggerChannel);
00273         }
00274     }
00275     else /* ADC1_SchmittTriggerChannel >= ADC1_SCHMITTTRIG_CHANNEL8 */
00276     {
00277         if (NewState != DISABLE)
00278         {
00279             ADC1->TDRH &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << ((uint8_t)ADC1_SchmittTriggerChannel - (uint8_t)8)));
00280         }
00281         else /* NewState == DISABLE */
00282         {
00283             ADC1->TDRH |= (uint8_t)((uint8_t)0x01 << ((uint8_t)ADC1_SchmittTriggerChannel - (uint8_t)8));
00284         }
00285     }
00286
00287 }
00288
00289
00290 /**
00291   * @brief  Configure the ADC1 conversion on selected channel.
00292   * @param   ADC1_ConversionMode Specifies the conversion type.
00293   * It can be set of the values of @ref ADC1_ConvMode_TypeDef
00294   * @param   ADC1_Channel specifies the ADC1 Channel.
00295   * It can be set of the values of @ref ADC1_Channel_TypeDef
00296   * @param   ADC1_Align specifies the conerted data alignment.
00297   * It can be set of the values of @ref ADC1_Align_TypeDef
00298   * @retval None
00299   */
00300 void ADC1_ConversionConfig(ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)
00301 {
00302
00303     /* Check the parameters */
00304     assert_param(IS_ADC1_CONVERSIONMODE_OK(ADC1_ConversionMode));
00305     assert_param(IS_ADC1_CHANNEL_OK(ADC1_Channel));
00306     assert_param(IS_ADC1_ALIGN_OK(ADC1_Align));
00307
00308     /* Clear the align bit */
00309     ADC1->CR2 &= (uint8_t)(~ADC1_CR2_ALIGN);
00310     /* Configure the data alignment */
00311     ADC1->CR2 |= (uint8_t)(ADC1_Align);
00312
00313     if (ADC1_ConversionMode == ADC1_CONVERSIONMODE_CONTINUOUS)
00314     {
00315         /* Set the continuous coversion mode */
00316         ADC1->CR1 |= ADC1_CR1_CONT;
00317     }
00318     else /* ADC1_ConversionMode == ADC1_CONVERSIONMODE_SINGLE */
00319     {
00320         /* Set the single conversion mode */
00321         ADC1->CR1 &= (uint8_t)(~ADC1_CR1_CONT);
00322     }
00323
00324     /* Clear the ADC1 channels */
00325     ADC1->CSR &= (uint8_t)(~ADC1_CSR_CH);
00326     /* Select the ADC1 channel */
00327     ADC1->CSR |= (uint8_t)(ADC1_Channel);
00328
00329 }
00330
00331
00332 /**
00333   * @brief  Configure the ADC1 conversion on external trigger event.
00334   * @par Full description:
00335   * The selected external trigger evant can be enabled or disabled.
00336   * @param   ADC1_ExtTrigger to select the External trigger event.
00337   * can have one of the values of @ref ADC1_ExtTrig_TypeDef.
00338   * @param   NewState to enable/disable the selected external trigger
00339   * can have one of the values of @ref FunctionalState.
00340   * @retval None
00341   */
00342 void ADC1_ExternalTriggerConfig(ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
00343 {
00344
00345     /* Check the parameters */
00346     assert_param(IS_ADC1_EXTTRIG_OK(ADC1_ExtTrigger));
00347     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00348
00349     /* Clear the external trigger selection bits */
00350     ADC1->CR2 &= (uint8_t)(~ADC1_CR2_EXTSEL);
00351
00352     if (NewState != DISABLE)
00353     {
00354         /* Enable the selected external Trigger */
00355         ADC1->CR2 |= (uint8_t)(ADC1_CR2_EXTTRIG);
00356     }
00357     else /* NewState == DISABLE */
00358     {
00359         /* Disable the selected external trigger */
00360         ADC1->CR2 &= (uint8_t)(~ADC1_CR2_EXTTRIG);
00361     }
00362
00363     /* Set the selected external trigger */
00364     ADC1->CR2 |= (uint8_t)(ADC1_ExtTrigger);
00365
00366 }
00367
00368
00369 /**
00370   * @brief  Start ADC1 conversion
00371   * @par Full description:
00372   * This function  triggers the start of conversion, after ADC1 configuration.
00373   * @param  None
00374   * @retval None
00375   * @par Required preconditions:
00376   * Enable the ADC1 peripheral before calling this function
00377   */
00378 void ADC1_StartConversion(void)
00379 {
00380     ADC1->CR1 |= ADC1_CR1_ADON;
00381 }
00382
00383 /**
00384   * @brief  Get one sample of measured signal.
00385   * @param  None
00386   * @retval ConversionValue:  value of the measured signal.
00387   * @par Required preconditions:
00388   * ADC1 conversion finished.
00389   */
00390 uint16_t ADC1_GetConversionValue(void)
00391 {
00392
00393     uint16_t temph = 0;
00394     uint8_t templ = 0;
00395
00396     if ((ADC1->CR2 & ADC1_CR2_ALIGN) != 0) /* Right alignment */
00397     {
00398         /* Read LSB first */
00399         templ = ADC1->DRL;
00400         /* Then read MSB */
00401         temph = ADC1->DRH;
00402
00403         temph = (uint16_t)(templ | (uint16_t)(temph << (uint8_t)8));
00404     }
00405     else /* Left alignment */
00406     {
00407         /* Read MSB firts*/
00408         temph = ADC1->DRH;
00409         /* Then read LSB */
00410         templ = ADC1->DRL;
00411
00412         temph = (uint16_t)((uint16_t)((uint16_t)templ << 6) | (uint16_t)((uint16_t)temph << 8));
00413     }
00414
00415     return ((uint16_t)temph);
00416
00417 }
00418
00419 /**
00420   * @brief  Enables or disables the analog watchdog for the given channel.
00421   * @param   Channel specifies the desired Channel.
00422   * It can be set of the values of @ref ADC1_Channel_TypeDef.
00423   * @param   NewState specifies the analog watchdog new state.
00424   * can have one of the values of @ref FunctionalState.
00425   * @retval None
00426   */
00427 void ADC1_AWDChannelConfig(ADC1_Channel_TypeDef Channel, FunctionalState NewState)
00428 {
00429     /* Check the parameters */
00430     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00431     assert_param(IS_ADC1_CHANNEL_OK(Channel));
00432
00433     if (Channel < (uint8_t)8)
00434     {
00435         if (NewState != DISABLE)
00436         {
00437             ADC1->AWCRL |= (uint8_t)((uint8_t)1 << Channel);
00438         }
00439         else /* NewState == DISABLE */
00440         {
00441             ADC1->AWCRL &= (uint8_t)~(uint8_t)((uint8_t)1 << Channel);
00442         }
00443     }
00444     else
00445     {
00446         if (NewState != DISABLE)
00447         {
00448             ADC1->AWCRH |= (uint8_t)((uint8_t)1 << (Channel - (uint8_t)8));
00449         }
00450         else /* NewState == DISABLE */
00451         {
00452             ADC1->AWCRH &= (uint8_t)~(uint8_t)((uint8_t)1 << (uint8_t)(Channel - (uint8_t)8));
00453         }
00454     }
00455 }
00456
00457 /**
00458   * @brief  Sets the high threshold of the analog watchdog.
00459   * @param   Threshold specifies the high threshold value.
00460   * this value depends on the reference voltage range.
00461   * @retval None
00462   */
00463 void ADC1_SetHighThreshold(uint16_t Threshold)
00464 {
00465     ADC1->HTRH = (uint8_t)(Threshold >> (uint8_t)2);
00466     ADC1->HTRL = (uint8_t)Threshold;
00467 }
00468
00469 /**
00470   * @brief  Sets the low threshold of the analog watchdog.
00471   * @param   Threshold specifies the low threshold value.
00472   * this value depends on the reference voltage range.
00473   * @retval None
00474   */
00475 void ADC1_SetLowThreshold(uint16_t Threshold)
00476 {
00477     ADC1->LTRL = (uint8_t)Threshold;
00478     ADC1->LTRH = (uint8_t)(Threshold >> (uint8_t)2);
00479 }
00480
00481 /**
00482   * @brief  Get one sample of measured signal.
00483   * @param   Buffer specifies the buffer to read.
00484   * @retval BufferValue:  value read from the given buffer.
00485   * @par Required preconditions:
00486   * ADC1 conversion finished.
00487   */
00488 uint16_t ADC1_GetBufferValue(uint8_t Buffer)
00489 {
00490
00491     uint16_t temph = 0;
00492     uint8_t templ = 0;
00493
00494     /* Check the parameters */
00495     assert_param(IS_ADC1_BUFFER_OK(Buffer));
00496
00497     if ((ADC1->CR2 & ADC1_CR2_ALIGN) != 0) /* Right alignment */
00498     {
00499         /* Read LSB first */
00500         templ = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1) + 1);
00501         /* Then read MSB */
00502         temph = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1));
00503
00504         temph = (uint16_t)(templ | (uint16_t)(temph << (uint8_t)8));
00505     }
00506     else /* Left alignment */
00507     {
00508         /* Read MSB firts*/
00509         temph = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1));
00510         /* Then read LSB */
00511         templ = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1) + 1);
00512
00513         temph = (uint16_t)((uint16_t)((uint16_t)templ << 6) | (uint16_t)(temph << 8));
00514     }
00515
00516     return ((uint16_t)temph);
00517
00518 }
00519
00520 /**
00521   * @brief  Checks the specified analog watchdog channel status.
00522   * @param   Channel: specify the channel of which to check the analog watchdog
00523   * can be one of the values of @ref ADC1_Channel_TypeDef.
00524   * @retval FlagStatus Status of the analog watchdog.
00525   */
00526 FlagStatus ADC1_GetAWDChannelStatus(ADC1_Channel_TypeDef Channel)
00527 {
00528     uint8_t status = 0;
00529
00530     /* Check the parameters */
00531     assert_param(IS_ADC1_CHANNEL_OK(Channel));
00532
00533     if (Channel < (uint8_t)8)
00534     {
00535         status = (uint8_t)(ADC1->AWSRL & (uint8_t)((uint8_t)1 << Channel));
00536     }
00537     else /* Channel = 8 | 9 */
00538     {
00539         status = (uint8_t)(ADC1->AWSRH & (uint8_t)((uint8_t)1 << (Channel - (uint8_t)8)));
00540     }
00541
00542     return ((FlagStatus)status);
00543 }
00544
00545 /**
00546   * @brief  Checks the specified ADC1 flag status.
00547   * @param   Flag: ADC1 flag.
00548   * can be one of the values of @ref ADC1_Flag_TypeDef.
00549   * @retval FlagStatus Status of the ADC1 flag.
00550   */
00551 FlagStatus ADC1_GetFlagStatus(ADC1_Flag_TypeDef Flag)
00552 {
00553     uint8_t flagstatus = 0;
00554     uint8_t temp = 0;
00555
00556     /* Check the parameters */
00557     assert_param(IS_ADC1_FLAG_OK(Flag));
00558
00559     if ((Flag & 0x0F) == 0x01)
00560     {
00561         /* Get OVR flag status */
00562         flagstatus = (uint8_t)(ADC1->CR3 & ADC1_CR3_OVR);
00563     }
00564     else if ((Flag & 0xF0) == 0x10)
00565     {
00566         /* Get analog watchdog channel status */
00567         temp = (uint8_t)(Flag & (uint8_t)0x0F);
00568         if (temp < 8)
00569         {
00570             flagstatus = (uint8_t)(ADC1->AWSRL & (uint8_t)((uint8_t)1 << temp));
00571         }
00572         else
00573         {
00574             flagstatus = (uint8_t)(ADC1->AWSRH & (uint8_t)((uint8_t)1 << (temp - 8)));
00575         }
00576     }
00577     else  /* Get EOC | AWD flag status */
00578     {
00579         flagstatus = (uint8_t)(ADC1->CSR & Flag);
00580     }
00581     return ((FlagStatus)flagstatus);
00582
00583 }
00584
00585 /**
00586   * @brief  Clear the specified ADC1 Flag.
00587   * @param   Flag: ADC1 flag.
00588   * can be one of the values of @ref ADC1_Flag_TypeDef.
00589   * @retval None
00590   */
00591 void ADC1_ClearFlag(ADC1_Flag_TypeDef Flag)
00592 {
00593     uint8_t temp = 0;
00594
00595     /* Check the parameters */
00596     assert_param(IS_ADC1_FLAG_OK(Flag));
00597
00598     if ((Flag & 0x0F) == 0x01)
00599     {
00600         /* Clear OVR flag status */
00601         ADC1->CR3 &= (uint8_t)(~ADC1_CR3_OVR);
00602     }
00603     else if ((Flag & 0xF0) == 0x10)
00604     {
00605         /* Clear analog watchdog channel status */
00606         temp = (uint8_t)(Flag & (uint8_t)0x0F);
00607         if (temp < 8)
00608         {
00609             ADC1->AWSRL &= (uint8_t)~(uint8_t)((uint8_t)1 << temp);
00610         }
00611         else
00612         {
00613             ADC1->AWSRH &= (uint8_t)~(uint8_t)((uint8_t)1 << (temp - 8));
00614         }
00615     }
00616     else  /* Clear EOC | AWD flag status */
00617     {
00618         ADC1->CSR &= (uint8_t) (~Flag);
00619     }
00620 }
00621
00622 /**
00623   * @brief  Returns the specified pending bit status
00624   * @param   ITPendingBit : the IT pending bit to check.
00625   * This parameter can be one of the following values:
00626   *    - ADC1_IT_AWD   : Analog WDG IT status
00627   *    - ADC1_IT_AWS0 : Analog channel 0 IT status
00628   *    - ADC1_IT_AWS1 : Analog channel 1 IT status
00629   *    - ADC1_IT_AWS2 : Analog channel 2 IT status
00630   *    - ADC1_IT_AWS3 : Analog channel 3 IT status
00631   *    - ADC1_IT_AWS4 : Analog channel 4 IT status
00632   *    - ADC1_IT_AWS5 : Analog channel 5 IT status
00633   *    - ADC1_IT_AWS6 : Analog channel 6 IT status
00634   *    - ADC1_IT_AWS7 : Analog channel 7 IT status
00635   *    - ADC1_IT_AWS8 : Analog channel 8 IT status
00636   *    - ADC1_IT_AWS9 : Analog channel 9 IT status
00637   *    - ADC1_IT_EOC    : EOC pending bit
00638   * @retval ITStatus: status of the specified pending bit.
00639   */
00640 ITStatus ADC1_GetITStatus(ADC1_IT_TypeDef ITPendingBit)
00641 {
00642     ITStatus itstatus = RESET;
00643     uint8_t temp = 0;
00644
00645     /* Check the parameters */
00646     assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));
00647
00648     if (((uint16_t)ITPendingBit & 0xF0) == 0x10)
00649     {
00650         /* Get analog watchdog channel status */
00651         temp = (uint8_t)((uint16_t)ITPendingBit & 0x0F);
00652         if (temp < 8)
00653         {
00654             itstatus = (ITStatus)(ADC1->AWSRL & (uint8_t)((uint8_t)1 << temp));
00655         }
00656         else
00657         {
00658             itstatus = (ITStatus)(ADC1->AWSRH & (uint8_t)((uint8_t)1 << (temp - 8)));
00659         }
00660     }
00661     else  /* Get EOC | AWD flag status */
00662     {
00663         itstatus = (ITStatus)(ADC1->CSR & (uint8_t)ITPendingBit);
00664     }
00665     return ((ITStatus)itstatus);
00666
00667 }
00668
00669 /**
00670   * @brief  Clear the ADC1 End of Conversion pending bit.
00671   * @param   ITPendingBit : the IT pending bit to clear.
00672   * This parameter can be one of the following values:
00673   *    - ADC1_IT_AWD   : Analog WDG IT status
00674   *    - ADC1_IT_AWS0 : Analog channel 0 IT status
00675   *    - ADC1_IT_AWS1 : Analog channel 1 IT status
00676   *    - ADC1_IT_AWS2 : Analog channel 2 IT status
00677   *    - ADC1_IT_AWS3 : Analog channel 3 IT status
00678   *    - ADC1_IT_AWS4 : Analog channel 4 IT status
00679   *    - ADC1_IT_AWS5 : Analog channel 5 IT status
00680   *    - ADC1_IT_AWS6 : Analog channel 6 IT status
00681   *    - ADC1_IT_AWS7 : Analog channel 7 IT status
00682   *    - ADC1_IT_AWS8 : Analog channel 8 IT status
00683   *    - ADC1_IT_AWS9 : Analog channel 9 IT status
00684   *    - ADC1_IT_EOC  : EOC pending bit
00685   * @retval None
00686   */
00687 void ADC1_ClearITPendingBit(ADC1_IT_TypeDef ITPendingBit)
00688 {
00689     uint8_t temp = 0;
00690
00691     /* Check the parameters */
00692     assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));
00693
00694     if (((uint16_t)ITPendingBit & 0xF0) == 0x10)
00695     {
00696         /* Clear analog watchdog channel status */
00697         temp = (uint8_t)((uint16_t)ITPendingBit & 0x0F);
00698         if (temp < 8)
00699         {
00700             ADC1->AWSRL &= (uint8_t)~(uint8_t)((uint8_t)1 << temp);
00701         }
00702         else
00703         {
00704             ADC1->AWSRH &= (uint8_t)~(uint8_t)((uint8_t)1 << (temp - 8));
00705         }
00706     }
00707     else  /* Clear EOC | AWD flag status */
00708     {
00709         ADC1->CSR &= (uint8_t)((uint16_t)~(uint16_t)ITPendingBit);
00710     }
00711 }
00712
00713 /**
00714   * @}
00715   */
00716
00717 /**
00718   * @}
00719   */
00720
00721 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_adc1.h Source File

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stm8s_adc1.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_adc1.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the prototypes/macros for the ADC1 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021 /* Define to prevent recursive inclusion -------------------------------------*/
00022 #ifndef __STM8S_ADC1_H
00023 #define __STM8S_ADC1_H
00024
00025 /* Includes ------------------------------------------------------------------*/
00026 #include "stm8s.h"
00027
00028 /* Exported types ------------------------------------------------------------*/
00029
00030 /** @addtogroup ADC1_Exported_Types
00031   * @{
00032   */
00033
00034 /**
00035   * @brief  ADC1 clock prescaler selection
00036   */
00037
00038 typedef enum
00039 {
00040   ADC1_PRESSEL_FCPU_D2  = (uint8_t)0x00, /**< Prescaler selection fADC1 = fcpu/2 */
00041   ADC1_PRESSEL_FCPU_D3  = (uint8_t)0x10, /**< Prescaler selection fADC1 = fcpu/3 */
00042   ADC1_PRESSEL_FCPU_D4  = (uint8_t)0x20, /**< Prescaler selection fADC1 = fcpu/4 */
00043   ADC1_PRESSEL_FCPU_D6  = (uint8_t)0x30, /**< Prescaler selection fADC1 = fcpu/6 */
00044   ADC1_PRESSEL_FCPU_D8  = (uint8_t)0x40, /**< Prescaler selection fADC1 = fcpu/8 */
00045   ADC1_PRESSEL_FCPU_D10 = (uint8_t)0x50, /**< Prescaler selection fADC1 = fcpu/10 */
00046   ADC1_PRESSEL_FCPU_D12 = (uint8_t)0x60, /**< Prescaler selection fADC1 = fcpu/12 */
00047   ADC1_PRESSEL_FCPU_D18 = (uint8_t)0x70  /**< Prescaler selection fADC1 = fcpu/18 */
00048 } ADC1_PresSel_TypeDef;
00049
00050 /**
00051   * @brief   ADC1 External conversion trigger event selection
00052   */
00053 typedef enum
00054 {
00055   ADC1_EXTTRIG_TIM   = (uint8_t)0x00, /**< Conversion from Internal TIM1 TRGO event */
00056   ADC1_EXTTRIG_GPIO  = (uint8_t)0x10  /**< Conversion from External interrupt on ADC_ETR pin*/
00057 } ADC1_ExtTrig_TypeDef;
00058
00059 /**
00060   * @brief  ADC1 data alignment
00061   */
00062 typedef enum
00063 {
00064   ADC1_ALIGN_LEFT  = (uint8_t)0x00, /**< Data alignment left */
00065   ADC1_ALIGN_RIGHT = (uint8_t)0x08  /**< Data alignment right */
00066 } ADC1_Align_TypeDef;
00067
00068 /**
00069   * @brief  ADC1 Interrupt source
00070   */
00071 typedef enum
00072 {
00073   ADC1_IT_AWDIE = (uint16_t)0x010, /**< Analog WDG interrupt enable */
00074   ADC1_IT_EOCIE = (uint16_t)0x020, /**< EOC interrupt enable */
00075   ADC1_IT_AWD   = (uint16_t)0x140, /**< Analog WDG status */
00076   ADC1_IT_AWS0  = (uint16_t)0x110, /**< Analog channel 0 status */
00077   ADC1_IT_AWS1  = (uint16_t)0x111, /**< Analog channel 1 status */
00078   ADC1_IT_AWS2  = (uint16_t)0x112, /**< Analog channel 2 status */
00079   ADC1_IT_AWS3  = (uint16_t)0x113, /**< Analog channel 3 status */
00080   ADC1_IT_AWS4  = (uint16_t)0x114, /**< Analog channel 4 status */
00081   ADC1_IT_AWS5  = (uint16_t)0x115, /**< Analog channel 5 status */
00082   ADC1_IT_AWS6  = (uint16_t)0x116, /**< Analog channel 6 status */
00083   ADC1_IT_AWS7  = (uint16_t)0x117, /**< Analog channel 7 status */
00084   ADC1_IT_AWS8  = (uint16_t)0x118, /**< Analog channel 8 status */
00085   ADC1_IT_AWS9  = (uint16_t)0x119, /**< Analog channel 9 status */
00086   ADC1_IT_AWS12 = (uint16_t)0x11C, /**< Analog channel 12 status */
00087                                    /* refer to product datasheet for channel 12 availability */
00088   ADC1_IT_EOC   = (uint16_t)0x080  /**< EOC pending bit */
00089
00090 } ADC1_IT_TypeDef;
00091
00092 /**
00093   * @brief  ADC1 Flags
00094   */
00095 typedef enum
00096 {
00097   ADC1_FLAG_OVR   = (uint8_t)0x41, /**< Overrun status flag */
00098   ADC1_FLAG_AWD   = (uint8_t)0x40, /**< Analog WDG status */
00099   ADC1_FLAG_AWS0  = (uint8_t)0x10, /**< Analog channel 0 status */
00100   ADC1_FLAG_AWS1  = (uint8_t)0x11, /**< Analog channel 1 status */
00101   ADC1_FLAG_AWS2  = (uint8_t)0x12, /**< Analog channel 2 status */
00102   ADC1_FLAG_AWS3  = (uint8_t)0x13, /**< Analog channel 3 status */
00103   ADC1_FLAG_AWS4  = (uint8_t)0x14, /**< Analog channel 4 status */
00104   ADC1_FLAG_AWS5  = (uint8_t)0x15, /**< Analog channel 5 status */
00105   ADC1_FLAG_AWS6  = (uint8_t)0x16, /**< Analog channel 6 status */
00106   ADC1_FLAG_AWS7  = (uint8_t)0x17, /**< Analog channel 7 status */
00107   ADC1_FLAG_AWS8  = (uint8_t)0x18, /**< Analog channel 8  status*/
00108   ADC1_FLAG_AWS9  = (uint8_t)0x19, /**< Analog channel 9 status */
00109   ADC1_FLAG_AWS12 = (uint8_t)0x1C, /**< Analog channel 12 status */
00110                                   /* refer to product datasheet for channel 12 availability */
00111   ADC1_FLAG_EOC   = (uint8_t)0x80  /**< EOC falg */
00112 }ADC1_Flag_TypeDef;
00113
00114
00115 /**
00116   * @brief  ADC1 schmitt Trigger
00117   */
00118 typedef enum
00119 {
00120   ADC1_SCHMITTTRIG_CHANNEL0  = (uint8_t)0x00, /**< Schmitt trigger disable on AIN0 */
00121   ADC1_SCHMITTTRIG_CHANNEL1  = (uint8_t)0x01, /**< Schmitt trigger disable on AIN1 */
00122   ADC1_SCHMITTTRIG_CHANNEL2  = (uint8_t)0x02, /**< Schmitt trigger disable on AIN2 */
00123   ADC1_SCHMITTTRIG_CHANNEL3  = (uint8_t)0x03, /**< Schmitt trigger disable on AIN3 */
00124   ADC1_SCHMITTTRIG_CHANNEL4  = (uint8_t)0x04, /**< Schmitt trigger disable on AIN4 */
00125   ADC1_SCHMITTTRIG_CHANNEL5  = (uint8_t)0x05, /**< Schmitt trigger disable on AIN5 */
00126   ADC1_SCHMITTTRIG_CHANNEL6  = (uint8_t)0x06, /**< Schmitt trigger disable on AIN6 */
00127   ADC1_SCHMITTTRIG_CHANNEL7  = (uint8_t)0x07, /**< Schmitt trigger disable on AIN7 */
00128   ADC1_SCHMITTTRIG_CHANNEL8  = (uint8_t)0x08, /**< Schmitt trigger disable on AIN8 */
00129   ADC1_SCHMITTTRIG_CHANNEL9  = (uint8_t)0x09, /**< Schmitt trigger disable on AIN9 */
00130   ADC1_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, /**< Schmitt trigger disable on AIN12 */
00131                                               /* refer to product datasheet for channel 12 availability */
00132   ADC1_SCHMITTTRIG_ALL       = (uint8_t)0xFF /**< Schmitt trigger disable on All channels */
00133 } ADC1_SchmittTrigg_TypeDef;
00134
00135 /**
00136   * @brief  ADC1 conversion mode selection
00137   */
00138
00139 typedef enum
00140 {
00141   ADC1_CONVERSIONMODE_SINGLE     = (uint8_t)0x00, /**< Single conversion mode */
00142   ADC1_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01  /**< Continuous conversion mode */
00143 } ADC1_ConvMode_TypeDef;
00144
00145 /**
00146   * @brief  ADC1 analog channel selection
00147   */
00148
00149 typedef enum
00150 {
00151   ADC1_CHANNEL_0  = (uint8_t)0x00, /**< Analog channel 0 */
00152   ADC1_CHANNEL_1  = (uint8_t)0x01, /**< Analog channel 1 */
00153   ADC1_CHANNEL_2  = (uint8_t)0x02, /**< Analog channel 2 */
00154   ADC1_CHANNEL_3  = (uint8_t)0x03, /**< Analog channel 3 */
00155   ADC1_CHANNEL_4  = (uint8_t)0x04, /**< Analog channel 4 */
00156   ADC1_CHANNEL_5  = (uint8_t)0x05, /**< Analog channel 5 */
00157   ADC1_CHANNEL_6  = (uint8_t)0x06, /**< Analog channel 6 */
00158   ADC1_CHANNEL_7  = (uint8_t)0x07, /**< Analog channel 7 */
00159   ADC1_CHANNEL_8  = (uint8_t)0x08, /**< Analog channel 8 */
00160   ADC1_CHANNEL_9  = (uint8_t)0x09, /**< Analog channel 9 */
00161   ADC1_CHANNEL_12 = (uint8_t)0x0C /**< Analog channel 12 */
00162                  /* refer to product datasheet for channel 12 availability */
00163 } ADC1_Channel_TypeDef;
00164
00165 /**
00166   * @}
00167   */
00168
00169 /* Exported constants --------------------------------------------------------*/
00170
00171 /* Exported macros ------------------------------------------------------------*/
00172
00173 /* Private macros ------------------------------------------------------------*/
00174
00175 /** @addtogroup ADC1_Private_Macros
00176   * @brief  Macros used by the assert function to check the different functions parameters.
00177   * @{
00178   */
00179
00180 /**
00181   * @brief  Macro used by the assert function to check the different prescaler's values.
00182   */
00183 #define IS_ADC1_PRESSEL_OK(PRESCALER) (((PRESCALER) == ADC1_PRESSEL_FCPU_D2) || \
00184                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D3) || \
00185                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D4) || \
00186                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D6) || \
00187                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D8) || \
00188                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D10) || \
00189                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D12) || \
00190                                       ((PRESCALER) == ADC1_PRESSEL_FCPU_D18))
00191
00192 /**
00193   * @brief  Macro used by the assert function to check the different external trigger values.
00194   */
00195 #define IS_ADC1_EXTTRIG_OK(EXTRIG) (((EXTRIG) == ADC1_EXTTRIG_TIM) || \
00196                                    ((EXTRIG) == ADC1_EXTTRIG_GPIO))
00197
00198 /**
00199   * @brief  Macro used by the assert function to check the different alignment modes.
00200   */
00201 #define IS_ADC1_ALIGN_OK(ALIGN) (((ALIGN) == ADC1_ALIGN_LEFT) || \
00202                                 ((ALIGN) == ADC1_ALIGN_RIGHT))
00203
00204 /**
00205   * @brief  Macro used by the assert function to check the Interrupt source.
00206   */
00207 #define IS_ADC1_IT_OK(IT) (((IT) == ADC1_IT_EOCIE) || \
00208                           ((IT) == ADC1_IT_AWDIE))
00209
00210 /**
00211   * @brief  Macro used by the assert function to check the ADC1 Flag.
00212   */
00213 #define IS_ADC1_FLAG_OK(FLAG) (((FLAG) == ADC1_FLAG_EOC)|| \
00214                               ((FLAG) == ADC1_FLAG_OVR) || \
00215                               ((FLAG) == ADC1_FLAG_AWD) || \
00216                               ((FLAG) == ADC1_FLAG_AWS0) || \
00217                               ((FLAG) == ADC1_FLAG_AWS1) || \
00218                               ((FLAG) == ADC1_FLAG_AWS2) || \
00219                               ((FLAG) == ADC1_FLAG_AWS3) || \
00220                               ((FLAG) == ADC1_FLAG_AWS4) || \
00221                               ((FLAG) == ADC1_FLAG_AWS5) || \
00222                               ((FLAG) == ADC1_FLAG_AWS6) || \
00223                               ((FLAG) == ADC1_FLAG_AWS7) || \
00224                               ((FLAG) == ADC1_FLAG_AWS8) || \
00225                               ((FLAG) == ADC1_FLAG_AWS9))
00226
00227 /**
00228   * @brief  Macro used by the assert function to check the ADC1 pending bits.
00229   */
00230 #define IS_ADC1_ITPENDINGBIT_OK(ITPENDINGBIT) (((ITPENDINGBIT) == ADC1_IT_EOC) || \
00231     ((ITPENDINGBIT) == ADC1_IT_AWD) || \
00232     ((ITPENDINGBIT) == ADC1_IT_AWS0) || \
00233     ((ITPENDINGBIT) == ADC1_IT_AWS1) || \
00234     ((ITPENDINGBIT) == ADC1_IT_AWS2) || \
00235     ((ITPENDINGBIT) == ADC1_IT_AWS3) || \
00236     ((ITPENDINGBIT) == ADC1_IT_AWS4) || \
00237     ((ITPENDINGBIT) == ADC1_IT_AWS5) || \
00238     ((ITPENDINGBIT) == ADC1_IT_AWS6) || \
00239     ((ITPENDINGBIT) == ADC1_IT_AWS7) || \
00240     ((ITPENDINGBIT) == ADC1_IT_AWS8) || \
00241     ((ITPENDINGBIT) == ADC1_IT_AWS12) || \
00242     ((ITPENDINGBIT) == ADC1_IT_AWS9))
00243
00244 /**
00245   * @brief  Macro used by the assert function to check the different schmitt trigger values.
00246   */
00247 #define IS_ADC1_SCHMITTTRIG_OK(SCHMITTTRIG) (((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL0) || \
00248     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL1) || \
00249     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL2) || \
00250     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL3) || \
00251     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL4) || \
00252     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL5) || \
00253     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL6) || \
00254     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL7) || \
00255     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL8) || \
00256     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL12) || \
00257     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_ALL) || \
00258     ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL9))
00259
00260 /**
00261   * @brief  Macro used by the assert function to check the different conversion modes.
00262   */
00263 #define IS_ADC1_CONVERSIONMODE_OK(MODE) (((MODE) == ADC1_CONVERSIONMODE_SINGLE) || \
00264                                         ((MODE) == ADC1_CONVERSIONMODE_CONTINUOUS))
00265
00266 /**
00267   * @brief  Macro used by the assert function to check the different channels values.
00268   */
00269 #define IS_ADC1_CHANNEL_OK(CHANNEL) (((CHANNEL) == ADC1_CHANNEL_0) || \
00270                                     ((CHANNEL) == ADC1_CHANNEL_1) || \
00271                                     ((CHANNEL) == ADC1_CHANNEL_2) || \
00272                                     ((CHANNEL) == ADC1_CHANNEL_3) || \
00273                                     ((CHANNEL) == ADC1_CHANNEL_4) || \
00274                                     ((CHANNEL) == ADC1_CHANNEL_5) || \
00275                                     ((CHANNEL) == ADC1_CHANNEL_6) || \
00276                                     ((CHANNEL) == ADC1_CHANNEL_7) || \
00277                                     ((CHANNEL) == ADC1_CHANNEL_8) || \
00278                                     ((CHANNEL) == ADC1_CHANNEL_12) || \
00279                                     ((CHANNEL) == ADC1_CHANNEL_9))
00280
00281 /**
00282   * @brief  Macro used by the assert function to check the possible buffer values.
00283   */
00284 #define IS_ADC1_BUFFER_OK(BUFFER) ((BUFFER) <= (uint8_t)0x09)
00285
00286 /**
00287   * @}
00288   */
00289
00290 /* Exported functions ------------------------------------------------------- */
00291
00292 /** @addtogroup ADC1_Exported_Functions
00293   * @{
00294   */
00295 void ADC1_DeInit(void);
00296 void ADC1_Init(ADC1_ConvMode_TypeDef ADC1_ConversionMode,
00297                ADC1_Channel_TypeDef ADC1_Channel,
00298                ADC1_PresSel_TypeDef ADC1_PrescalerSelection,
00299                ADC1_ExtTrig_TypeDef ADC1_ExtTrigger,
00300                FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align,
00301                ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel,
00302                FunctionalState ADC1_SchmittTriggerState);
00303 void ADC1_Cmd(FunctionalState NewState);
00304 void ADC1_ScanModeCmd(FunctionalState NewState);
00305 void ADC1_DataBufferCmd(FunctionalState NewState);
00306 void ADC1_ITConfig(ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState);
00307 void ADC1_PrescalerConfig(ADC1_PresSel_TypeDef ADC1_Prescaler);
00308 void ADC1_SchmittTriggerConfig(ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel,
00309                               FunctionalState NewState);
00310 void ADC1_ConversionConfig(ADC1_ConvMode_TypeDef ADC1_ConversionMode,
00311                            ADC1_Channel_TypeDef ADC1_Channel,
00312                            ADC1_Align_TypeDef ADC1_Align);
00313 void ADC1_ExternalTriggerConfig(ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState);
00314 void ADC1_AWDChannelConfig(ADC1_Channel_TypeDef Channel, FunctionalState NewState);
00315 void ADC1_StartConversion(void);
00316 uint16_t ADC1_GetConversionValue(void);
00317 void ADC1_SetHighThreshold(uint16_t Threshold);
00318 void ADC1_SetLowThreshold(uint16_t Threshold);
00319 uint16_t ADC1_GetBufferValue(uint8_t Buffer);
00320 FlagStatus ADC1_GetAWDChannelStatus(ADC1_Channel_TypeDef Channel);
00321 FlagStatus ADC1_GetFlagStatus(ADC1_Flag_TypeDef Flag);
00322 void ADC1_ClearFlag(ADC1_Flag_TypeDef Flag);
00323 ITStatus ADC1_GetITStatus(ADC1_IT_TypeDef ITPendingBit);
00324 void ADC1_ClearITPendingBit(ADC1_IT_TypeDef ITPendingBit);
00325 /**
00326   * @}
00327   */
00328
00329 #endif /* __STM8S_ADC1_H */
00330
00331 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_adc2.c Source File

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  • STM8S_StdPeriph_Driver
  • src

stm8s_adc2.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_adc2.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions/macros for the ADC2 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_adc2.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034
00035 /* Public functions ----------------------------------------------------------*/
00036
00037 /**
00038   * @addtogroup ADC2_Public_Functions
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  Deinitializes the ADC2 peripheral registers to their default reset
00044   * values.
00045   * @param  None
00046   * @retval None
00047   */
00048 void ADC2_DeInit(void)
00049 {
00050     ADC2->CSR  = ADC2_CSR_RESET_VALUE;
00051     ADC2->CR1  = ADC2_CR1_RESET_VALUE;
00052     ADC2->CR2  = ADC2_CR2_RESET_VALUE;
00053     ADC2->TDRH = ADC2_TDRH_RESET_VALUE;
00054     ADC2->TDRL = ADC2_TDRL_RESET_VALUE;
00055 }
00056
00057 /**
00058   * @brief  Initializes the ADC2 peripheral according to the specified parameters
00059   * @param   ADC2_ConversionMode: specifies the conversion mode
00060   * can be one of the values of @ref ADC2_ConvMode_TypeDef.
00061   * @param   ADC2_Channel: specifies the channel to convert
00062   * can be one of the values of @ref ADC2_Channel_TypeDef.
00063   * @param   ADC2_PrescalerSelection: specifies the ADC2 prescaler
00064   * can be one of the values of @ref ADC2_PresSel_TypeDef.
00065   * @param   ADC2_ExtTrigger: specifies the external trigger
00066   * can be one of the values of @ref ADC2_ExtTrig_TypeDef.
00067   * @param   ADC2_ExtTriggerState: specifies the external trigger new state
00068   * can be one of the values of @ref FunctionalState.
00069   * @param   ADC2_Align: specifies the converted data alignment
00070   * can be one of the values of @ref ADC2_Align_TypeDef.
00071   * @param   ADC2_SchmittTriggerChannel: specifies the schmitt trigger channel
00072   * can be one of the values of @ref ADC2_SchmittTrigg_TypeDef.
00073   * @param   ADC2_SchmittTriggerState: specifies the schmitt trigger state
00074   * can be one of the values of @ref FunctionalState.
00075   * @retval None
00076   */
00077 void ADC2_Init(ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)
00078 {
00079
00080     /* Check the parameters */
00081     assert_param(IS_ADC2_CONVERSIONMODE_OK(ADC2_ConversionMode));
00082     assert_param(IS_ADC2_CHANNEL_OK(ADC2_Channel));
00083     assert_param(IS_ADC2_PRESSEL_OK(ADC2_PrescalerSelection));
00084     assert_param(IS_ADC2_EXTTRIG_OK(ADC2_ExtTrigger));
00085     assert_param(IS_FUNCTIONALSTATE_OK(((ADC2_ExtTriggerState))));
00086     assert_param(IS_ADC2_ALIGN_OK(ADC2_Align));
00087     assert_param(IS_ADC2_SCHMITTTRIG_OK(ADC2_SchmittTriggerChannel));
00088     assert_param(IS_FUNCTIONALSTATE_OK(ADC2_SchmittTriggerState));
00089
00090     /*-----------------CR1 & CSR configuration --------------------*/
00091     /* Configure the conversion mode and the channel to convert
00092     respectively according to ADC2_ConversionMode & ADC2_Channel values  &  ADC2_Align values */
00093     ADC2_ConversionConfig(ADC2_ConversionMode, ADC2_Channel, ADC2_Align);
00094     /* Select the prescaler division factor according to ADC2_PrescalerSelection values */
00095     ADC2_PrescalerConfig(ADC2_PrescalerSelection);
00096
00097     /*-----------------CR2 configuration --------------------*/
00098     /* Configure the external trigger state and event respectively
00099     according to ADC2_ExtTrigStatus, ADC2_ExtTrigger */
00100     ADC2_ExternalTriggerConfig(ADC2_ExtTrigger, ADC2_ExtTriggerState);
00101
00102     /*------------------TDR configuration ---------------------------*/
00103     /* Configure the schmitt trigger channel and state respectively
00104     according to ADC2_SchmittTriggerChannel & ADC2_SchmittTriggerNewState  values */
00105     ADC2_SchmittTriggerConfig(ADC2_SchmittTriggerChannel, ADC2_SchmittTriggerState);
00106
00107     /* Enable the ADC2 peripheral */
00108     ADC2->CR1 |= ADC2_CR1_ADON;
00109
00110 }
00111
00112
00113 /**
00114   * @brief  Enables or Disables the ADC2 peripheral.
00115   * @param   NewState: specifies the peripheral enabled or disabled state.
00116   * @retval None
00117   */
00118 void ADC2_Cmd(FunctionalState NewState)
00119 {
00120
00121     /* Check the parameters */
00122     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00123
00124     if (NewState != DISABLE)
00125     {
00126         ADC2->CR1 |= ADC2_CR1_ADON;
00127     }
00128     else /* NewState == DISABLE */
00129     {
00130         ADC2->CR1 &= (uint8_t)(~ADC2_CR1_ADON);
00131     }
00132
00133 }
00134
00135 /**
00136   * @brief  Enables or disables the ADC2 interrupt.
00137   * @param   NewState specifies the state of ADC2 interrupt.
00138   * @retval None
00139   */
00140 void ADC2_ITConfig(FunctionalState NewState)
00141 {
00142
00143     /* Check the parameters */
00144     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00145
00146     if (NewState != DISABLE)
00147     {
00148         /* Enable the ADC2 interrupts */
00149         ADC2->CSR |= (uint8_t)ADC2_CSR_EOCIE;
00150     }
00151     else  /*NewState == DISABLE */
00152     {
00153         /* Disable the ADC2 interrupts */
00154         ADC2->CSR &= (uint8_t)(~ADC2_CSR_EOCIE);
00155     }
00156
00157 }
00158
00159 /**
00160   * @brief  Configure the ADC2 prescaler division factor.
00161   * @param   ADC2_Prescaler: the selected prescaler.
00162   * It can be one of the values of @ref ADC2_PresSel_TypeDef.
00163   * @retval None
00164   */
00165 void ADC2_PrescalerConfig(ADC2_PresSel_TypeDef ADC2_Prescaler)
00166 {
00167
00168     /* Check the parameter */
00169     assert_param(IS_ADC2_PRESSEL_OK(ADC2_Prescaler));
00170
00171     /* Clear the SPSEL bits */
00172     ADC2->CR1 &= (uint8_t)(~ADC2_CR1_SPSEL);
00173     /* Select the prescaler division factor according to ADC2_PrescalerSelection values */
00174     ADC2->CR1 |= (uint8_t)(ADC2_Prescaler);
00175
00176 }
00177
00178
00179 /**
00180   * @brief  Enables or disables the ADC2 Schmitt Trigger on a selected channel.
00181   * @param   ADC2_SchmittTriggerChannel specifies the desired Channel.
00182   * It can be set of the values of @ref ADC2_SchmittTrigg_TypeDef.
00183   * @param   NewState specifies the Channel  ADC2 Schmitt Trigger new status.
00184   * can have one of the values of @ref FunctionalState.
00185   * @retval None
00186   */
00187 void ADC2_SchmittTriggerConfig(ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)
00188 {
00189
00190     /* Check the parameters */
00191     assert_param(IS_ADC2_SCHMITTTRIG_OK(ADC2_SchmittTriggerChannel));
00192     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00193
00194     if (ADC2_SchmittTriggerChannel == ADC2_SCHMITTTRIG_ALL)
00195     {
00196         if (NewState != DISABLE)
00197         {
00198             ADC2->TDRL &= (uint8_t)0x0;
00199             ADC2->TDRH &= (uint8_t)0x0;
00200         }
00201         else /* NewState == DISABLE */
00202         {
00203             ADC2->TDRL |= (uint8_t)0xFF;
00204             ADC2->TDRH |= (uint8_t)0xFF;
00205         }
00206     }
00207     else if (ADC2_SchmittTriggerChannel < ADC2_SCHMITTTRIG_CHANNEL8)
00208     {
00209         if (NewState != DISABLE)
00210         {
00211             ADC2->TDRL &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << (uint8_t)ADC2_SchmittTriggerChannel));
00212         }
00213         else /* NewState == DISABLE */
00214         {
00215             ADC2->TDRL |= (uint8_t)((uint8_t)0x01 << (uint8_t)ADC2_SchmittTriggerChannel);
00216         }
00217     }
00218     else /* ADC2_SchmittTriggerChannel >= ADC2_SCHMITTTRIG_CHANNEL8 */
00219     {
00220         if (NewState != DISABLE)
00221         {
00222             ADC2->TDRH &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << ((uint8_t)ADC2_SchmittTriggerChannel - (uint8_t)8)));
00223         }
00224         else /* NewState == DISABLE */
00225         {
00226             ADC2->TDRH |= (uint8_t)((uint8_t)0x01 << ((uint8_t)ADC2_SchmittTriggerChannel - (uint8_t)8));
00227         }
00228     }
00229
00230 }
00231
00232 /**
00233   * @brief  Configure the ADC2 conversion on selected channel.
00234   * @param   ADC2_ConversionMode Specifies the conversion type.
00235   * It can be set of the values of @ref ADC2_ConvMode_TypeDef
00236   * @param   ADC2_Channel specifies the ADC2 Channel.
00237   * It can be set of the values of @ref ADC2_Channel_TypeDef
00238   * @param   ADC2_Align specifies the converted data alignment.
00239   * It can be set of the values of @ref ADC2_Align_TypeDef
00240   * @retval None
00241   */
00242 void ADC2_ConversionConfig(ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)
00243 {
00244
00245     /* Check the parameters */
00246     assert_param(IS_ADC2_CONVERSIONMODE_OK(ADC2_ConversionMode));
00247     assert_param(IS_ADC2_CHANNEL_OK(ADC2_Channel));
00248     assert_param(IS_ADC2_ALIGN_OK(ADC2_Align));
00249
00250     /* Clear the align bit */
00251     ADC2->CR2 &= (uint8_t)(~ADC2_CR2_ALIGN);
00252     /* Configure the data alignment */
00253     ADC2->CR2 |= (uint8_t)(ADC2_Align);
00254
00255     if (ADC2_ConversionMode == ADC2_CONVERSIONMODE_CONTINUOUS)
00256     {
00257         /* Set the continuous conversion mode */
00258         ADC2->CR1 |= ADC2_CR1_CONT;
00259     }
00260     else /* ADC2_ConversionMode == ADC2_CONVERSIONMODE_SINGLE */
00261     {
00262         /* Set the single conversion mode */
00263         ADC2->CR1 &= (uint8_t)(~ADC2_CR1_CONT);
00264     }
00265
00266     /* Clear the ADC2 channels */
00267     ADC2->CSR &= (uint8_t)(~ADC2_CSR_CH);
00268     /* Select the ADC2 channel */
00269     ADC2->CSR |= (uint8_t)(ADC2_Channel);
00270
00271 }
00272
00273
00274 /**
00275   * @brief  Configure the ADC2 conversion on external trigger event.
00276   * @par Full description:
00277   * The selected external trigger event can be enabled or disabled.
00278   * @param   ADC2_ExtTrigger to select the External trigger event.
00279   * can have one of the values of @ref ADC2_ExtTrig_TypeDef.
00280   * @param   NewState to enable/disable the selected external trigger
00281   * can have one of the values of @ref FunctionalState.
00282   * @retval None
00283   */
00284 void ADC2_ExternalTriggerConfig(ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)
00285 {
00286
00287     /* Check the parameters */
00288     assert_param(IS_ADC2_EXTTRIG_OK(ADC2_ExtTrigger));
00289     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00290
00291     /* Clear the external trigger selection bits */
00292     ADC2->CR2 &= (uint8_t)(~ADC2_CR2_EXTSEL);
00293
00294     if (NewState != DISABLE)
00295     {
00296         /* Enable the selected external Trigger */
00297         ADC2->CR2 |= (uint8_t)(ADC2_CR2_EXTTRIG);
00298     }
00299     else /* NewState == DISABLE */
00300     {
00301         /* Disable the selected external trigger */
00302         ADC2->CR2 &= (uint8_t)(~ADC2_CR2_EXTTRIG);
00303     }
00304
00305     /* Set the slected external trigger */
00306     ADC2->CR2 |= (uint8_t)(ADC2_ExtTrigger);
00307
00308 }
00309
00310
00311 /**
00312   * @brief  Start ADC2 conversion
00313   * @par Full description:
00314   * This function  triggers the start of conversion, after ADC2 configuration.
00315   * @param  None
00316   * @retval None
00317   * @par Required preconditions:
00318   * Enable the ADC2 peripheral before calling this function
00319   */
00320 void ADC2_StartConversion(void)
00321 {
00322     ADC2->CR1 |= ADC2_CR1_ADON;
00323 }
00324
00325 /**
00326   * @brief  Get one sample of measured signal.
00327   * @param  None
00328   * @retval ConversionValue:  value of the measured signal.
00329   * @par Required preconditions:
00330   * ADC2 conversion finished.
00331   */
00332 uint16_t ADC2_GetConversionValue(void)
00333 {
00334
00335     uint16_t temph = 0;
00336     uint8_t templ = 0;
00337
00338     if ((ADC2->CR2 & ADC2_CR2_ALIGN) != 0) /* Right alignment */
00339     {
00340         /* Read LSB first */
00341         templ = ADC2->DRL;
00342         /* Then read MSB */
00343         temph = ADC2->DRH;
00344
00345         temph = (uint16_t)(templ | (uint16_t)(temph << (uint8_t)8));
00346     }
00347     else /* Left alignment */
00348     {
00349         /* Read MSB firts*/
00350         temph = ADC2->DRH;
00351         /* Then read LSB */
00352         templ = ADC2->DRL;
00353
00354         temph = (uint16_t)((uint16_t)((uint16_t)templ << 6) | (uint16_t)((uint16_t)temph << 8));
00355     }
00356
00357     return ((uint16_t)temph);
00358
00359 }
00360
00361 /**
00362   * @brief  Checks the ADC2 EOC flag status.
00363   * @param  None
00364   * @retval FlagStatus Status of the ADC2 EOC flag.
00365   */
00366 FlagStatus ADC2_GetFlagStatus(void)
00367 {
00368     /* Get EOC  flag status */
00369     return (FlagStatus)(ADC2->CSR & ADC2_CSR_EOC);
00370
00371 }
00372
00373 /**
00374   * @brief  Clear the ADC2 EOC Flag.
00375   * @param  None
00376   * @retval None
00377   */
00378 void ADC2_ClearFlag(void)
00379 {
00380     ADC2->CSR &= (uint8_t)(~ADC2_CSR_EOC);
00381 }
00382
00383 /**
00384   * @brief  Returns the EOC  pending bit status
00385  * @par Parameters:
00386   * None
00387   * @retval FlagStatus: status of the EOC pending bit.
00388   */
00389 ITStatus ADC2_GetITStatus(void)
00390 {
00391     return (ITStatus)(ADC2->CSR & ADC2_CSR_EOC);
00392 }
00393
00394 /**
00395   * @brief  Clear the ADC2 End of Conversion pending bit.
00396   * @param  None
00397   * @retval None
00398   */
00399 void ADC2_ClearITPendingBit(void)
00400 {
00401     ADC2->CSR &= (uint8_t)(~ADC2_CSR_EOC);
00402 }
00403
00404 /**
00405   * @}
00406   */
00407
00408 /**
00409   * @}
00410   */
00411
00412 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_adc2.h Source File

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  • inc

stm8s_adc2.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_adc2.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the prototypes/macros for the ADC2 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM8S_ADC2_H
00025 #define __STM8S_ADC2_H
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm8s.h"
00029
00030 /* Exported types ------------------------------------------------------------*/
00031
00032 /** @addtogroup ADC2_Exported_Types
00033   * @{
00034   */
00035
00036 /**
00037   * @brief  ADC2 clock prescaler selection
00038   */
00039
00040 typedef enum {
00041   ADC2_PRESSEL_FCPU_D2  = (uint8_t)0x00, /**< Prescaler selection fADC2 = fcpu/2 */
00042   ADC2_PRESSEL_FCPU_D3  = (uint8_t)0x10, /**< Prescaler selection fADC2 = fcpu/3 */
00043   ADC2_PRESSEL_FCPU_D4  = (uint8_t)0x20, /**< Prescaler selection fADC2 = fcpu/4 */
00044   ADC2_PRESSEL_FCPU_D6  = (uint8_t)0x30, /**< Prescaler selection fADC2 = fcpu/6 */
00045   ADC2_PRESSEL_FCPU_D8  = (uint8_t)0x40, /**< Prescaler selection fADC2 = fcpu/8 */
00046   ADC2_PRESSEL_FCPU_D10 = (uint8_t)0x50, /**< Prescaler selection fADC2 = fcpu/10 */
00047   ADC2_PRESSEL_FCPU_D12 = (uint8_t)0x60, /**< Prescaler selection fADC2 = fcpu/12 */
00048   ADC2_PRESSEL_FCPU_D18 = (uint8_t)0x70  /**< Prescaler selection fADC2 = fcpu/18 */
00049 } ADC2_PresSel_TypeDef;
00050
00051 /**
00052   * @brief   ADC2 External conversion trigger event selection
00053   */
00054 typedef enum {
00055   ADC2_EXTTRIG_TIM   = (uint8_t)0x00, /**< Conversion from Internal TIM TRGO event */
00056   ADC2_EXTTRIG_GPIO  = (uint8_t)0x01  /**< Conversion from External interrupt on ADC_ETR pin*/
00057 } ADC2_ExtTrig_TypeDef;
00058
00059 /**
00060   * @brief  ADC2 data alignment
00061   */
00062 typedef enum {
00063   ADC2_ALIGN_LEFT  = (uint8_t)0x00, /**< Data alignment left */
00064   ADC2_ALIGN_RIGHT = (uint8_t)0x08  /**< Data alignment right */
00065 } ADC2_Align_TypeDef;
00066
00067 /**
00068   * @brief  ADC2 schmitt Trigger
00069   */
00070 typedef enum {
00071   ADC2_SCHMITTTRIG_CHANNEL0  = (uint8_t)0x00, /**< Schmitt trigger disable on AIN0 */
00072   ADC2_SCHMITTTRIG_CHANNEL1  = (uint8_t)0x01, /**< Schmitt trigger disable on AIN1 */
00073   ADC2_SCHMITTTRIG_CHANNEL2  = (uint8_t)0x02, /**< Schmitt trigger disable on AIN2 */
00074   ADC2_SCHMITTTRIG_CHANNEL3  = (uint8_t)0x03, /**< Schmitt trigger disable on AIN3 */
00075   ADC2_SCHMITTTRIG_CHANNEL4  = (uint8_t)0x04, /**< Schmitt trigger disable on AIN4 */
00076   ADC2_SCHMITTTRIG_CHANNEL5  = (uint8_t)0x05, /**< Schmitt trigger disable on AIN5 */
00077   ADC2_SCHMITTTRIG_CHANNEL6  = (uint8_t)0x06, /**< Schmitt trigger disable on AIN6 */
00078   ADC2_SCHMITTTRIG_CHANNEL7  = (uint8_t)0x07, /**< Schmitt trigger disable on AIN7 */
00079   ADC2_SCHMITTTRIG_CHANNEL8  = (uint8_t)0x08, /**< Schmitt trigger disable on AIN8 */
00080   ADC2_SCHMITTTRIG_CHANNEL9  = (uint8_t)0x09, /**< Schmitt trigger disable on AIN9 */
00081   ADC2_SCHMITTTRIG_CHANNEL10 = (uint8_t)0x0A, /**< Schmitt trigger disable on AIN10 */
00082   ADC2_SCHMITTTRIG_CHANNEL11 = (uint8_t)0x0B, /**< Schmitt trigger disable on AIN11 */
00083   ADC2_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, /**< Schmitt trigger disable on AIN12 */
00084   ADC2_SCHMITTTRIG_CHANNEL13 = (uint8_t)0x0D, /**< Schmitt trigger disable on AIN13 */
00085   ADC2_SCHMITTTRIG_CHANNEL14 = (uint8_t)0x0E, /**< Schmitt trigger disable on AIN14 */
00086   ADC2_SCHMITTTRIG_CHANNEL15 = (uint8_t)0x0F, /**< Schmitt trigger disable on AIN15 */
00087   ADC2_SCHMITTTRIG_ALL       = (uint8_t)0x1F /**< Schmitt trigger disable on all channels */
00088
00089 } ADC2_SchmittTrigg_TypeDef;
00090
00091 /**
00092   * @brief  ADC2 conversion mode selection
00093   */
00094
00095 typedef enum {
00096   ADC2_CONVERSIONMODE_SINGLE     = (uint8_t)0x00, /**< Single conversion mode */
00097   ADC2_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01  /**< Continuous conversion mode */
00098 } ADC2_ConvMode_TypeDef;
00099
00100 /**
00101   * @brief  ADC2 analog channel selection
00102   */
00103
00104 typedef enum {
00105   ADC2_CHANNEL_0  = (uint8_t)0x00, /**< Analog channel 0 */
00106   ADC2_CHANNEL_1  = (uint8_t)0x01, /**< Analog channel 1 */
00107   ADC2_CHANNEL_2  = (uint8_t)0x02, /**< Analog channel 2 */
00108   ADC2_CHANNEL_3  = (uint8_t)0x03, /**< Analog channel 3 */
00109   ADC2_CHANNEL_4  = (uint8_t)0x04, /**< Analog channel 4 */
00110   ADC2_CHANNEL_5  = (uint8_t)0x05, /**< Analog channel 5 */
00111   ADC2_CHANNEL_6  = (uint8_t)0x06, /**< Analog channel 6 */
00112   ADC2_CHANNEL_7  = (uint8_t)0x07, /**< Analog channel 7 */
00113   ADC2_CHANNEL_8  = (uint8_t)0x08, /**< Analog channel 8 */
00114   ADC2_CHANNEL_9  = (uint8_t)0x09, /**< Analog channel 9 */
00115   ADC2_CHANNEL_10 = (uint8_t)0x0A, /**< Analog channel 10 */
00116   ADC2_CHANNEL_11 = (uint8_t)0x0B, /**< Analog channel 11 */
00117   ADC2_CHANNEL_12 = (uint8_t)0x0C, /**< Analog channel 12 */
00118   ADC2_CHANNEL_13 = (uint8_t)0x0D, /**< Analog channel 13 */
00119   ADC2_CHANNEL_14 = (uint8_t)0x0E, /**< Analog channel 14 */
00120   ADC2_CHANNEL_15 = (uint8_t)0x0F  /**< Analog channel 15 */
00121 } ADC2_Channel_TypeDef;
00122
00123 /**
00124   * @}
00125   */
00126
00127 /* Exported constants --------------------------------------------------------*/
00128
00129 /* Exported macros ------------------------------------------------------------*/
00130
00131 /* Private macros ------------------------------------------------------------*/
00132
00133 /** @addtogroup ADC2_Private_Macros
00134   * @brief  Macros used by the assert function to check the different functions parameters.
00135   * @{
00136   */
00137
00138 /**
00139   * @brief  Macro used by the assert function to check the different prescaler's values.
00140   */
00141 #define IS_ADC2_PRESSEL_OK(PRESCALER) (((PRESCALER) == ADC2_PRESSEL_FCPU_D2) || \
00142                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D3) || \
00143                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D4) || \
00144                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D6) || \
00145                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D8) || \
00146                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D10) || \
00147                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D12) || \
00148                                       ((PRESCALER) == ADC2_PRESSEL_FCPU_D18))
00149
00150 /**
00151   * @brief  Macro used by the assert function to check the different external trigger values.
00152   */
00153 #define IS_ADC2_EXTTRIG_OK(EXTRIG) (((EXTRIG) == ADC2_EXTTRIG_TIM) || \
00154                                                                    ((EXTRIG) == ADC2_EXTTRIG_GPIO))
00155
00156 /**
00157   * @brief  Macro used by the assert function to check the different alignement modes.
00158   */
00159 #define IS_ADC2_ALIGN_OK(ALIGN) (((ALIGN) == ADC2_ALIGN_LEFT) || \
00160                                 ((ALIGN) == ADC2_ALIGN_RIGHT))
00161
00162
00163 /**
00164   * @brief  Macro used by the assert function to check the different schmitt trigger values.
00165   */
00166 #define IS_ADC2_SCHMITTTRIG_OK(SCHMITTTRIG) (((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL0) || \
00167     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL1) || \
00168     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL2) || \
00169     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL3) || \
00170     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL4) || \
00171     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL5) || \
00172     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL6) || \
00173     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL7) || \
00174     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL8) || \
00175     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL9) || \
00176     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL10) || \
00177     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL11) || \
00178     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL12) || \
00179     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL13) || \
00180     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL14) || \
00181     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL15) || \
00182     ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_ALL))
00183
00184 /**
00185   * @brief  Macro used by the assert function to check the different conversion modes.
00186   */
00187 #define IS_ADC2_CONVERSIONMODE_OK(MODE) (((MODE) == ADC2_CONVERSIONMODE_SINGLE) || \
00188                                         ((MODE) == ADC2_CONVERSIONMODE_CONTINUOUS))
00189
00190 /**
00191   * @brief  Macro used by the assert function to check the different channels values.
00192   */
00193 #define IS_ADC2_CHANNEL_OK(CHANNEL) (((CHANNEL) == ADC2_CHANNEL_0) || \
00194                                     ((CHANNEL) == ADC2_CHANNEL_1) || \
00195                                     ((CHANNEL) == ADC2_CHANNEL_2) || \
00196                                     ((CHANNEL) == ADC2_CHANNEL_3) || \
00197                                     ((CHANNEL) == ADC2_CHANNEL_4) || \
00198                                     ((CHANNEL) == ADC2_CHANNEL_5) || \
00199                                     ((CHANNEL) == ADC2_CHANNEL_6) || \
00200                                     ((CHANNEL) == ADC2_CHANNEL_7) || \
00201                                     ((CHANNEL) == ADC2_CHANNEL_8) || \
00202                                     ((CHANNEL) == ADC2_CHANNEL_9) || \
00203                                     ((CHANNEL) == ADC2_CHANNEL_10) || \
00204                                     ((CHANNEL) == ADC2_CHANNEL_11) || \
00205                                     ((CHANNEL) == ADC2_CHANNEL_12) || \
00206                                     ((CHANNEL) == ADC2_CHANNEL_13) || \
00207                                     ((CHANNEL) == ADC2_CHANNEL_14) || \
00208                                     ((CHANNEL) == ADC2_CHANNEL_15))
00209
00210 /**
00211   * @}
00212   */
00213
00214 /* Exported functions ------------------------------------------------------- */
00215
00216 /** @addtogroup ADC2_Exported_Functions
00217   * @{
00218   */
00219 void ADC2_DeInit(void);
00220 void ADC2_Init(ADC2_ConvMode_TypeDef ADC2_ConversionMode,
00221                ADC2_Channel_TypeDef ADC2_Channel,
00222                ADC2_PresSel_TypeDef ADC2_PrescalerSelection,
00223                ADC2_ExtTrig_TypeDef ADC2_ExtTrigger,
00224                FunctionalState ADC2_ExtTriggerState,
00225                ADC2_Align_TypeDef ADC2_Align,
00226                ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel,
00227                FunctionalState ADC2_SchmittTriggerState);
00228 void ADC2_Cmd(FunctionalState NewState);
00229 void ADC2_ITConfig(FunctionalState NewState);
00230 void ADC2_PrescalerConfig(ADC2_PresSel_TypeDef ADC2_Prescaler);
00231 void ADC2_SchmittTriggerConfig(ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel,
00232                               FunctionalState NewState);
00233 void ADC2_ConversionConfig(ADC2_ConvMode_TypeDef ADC2_ConversionMode,
00234                            ADC2_Channel_TypeDef ADC2_Channel,
00235                            ADC2_Align_TypeDef ADC2_Align);
00236 void ADC2_ExternalTriggerConfig(ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState);
00237 void ADC2_StartConversion(void);
00238 uint16_t ADC2_GetConversionValue(void);
00239 FlagStatus ADC2_GetFlagStatus(void);
00240 void ADC2_ClearFlag(void);
00241 ITStatus ADC2_GetITStatus(void);
00242 void ADC2_ClearITPendingBit(void);
00243 /**
00244   * @}
00245   */
00246
00247 #endif /* __STM8S_ADC2_H */
00248
00249 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_awu.c Source File

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  • STM8S_StdPeriph_Driver
  • src

stm8s_awu.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_awu.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the AWU peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_awu.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034
00035 /* See also AWU_Timebase_TypeDef structure in stm8s_awu.h file :
00036                           N   2   5   1   2   4   8   1   3   6   1   2   5   1   2   1   3
00037                           O   5   0   m   m   m   m   6   2   4   2   5   1   s   s   2   0
00038                           I   0   0   s   s   s   s   m   m   m   8   6   2           s   s
00039                           T   u   u                   s   s   s   m   m   m
00040                               s   s                               s   s   s
00041 */
00042 /** Contains the different values to write in the APR register (used by AWU_Init function) */
00043 CONST uint8_t APR_Array[17] =
00044     {
00045         0, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 61, 23, 23, 62
00046     };
00047
00048 /** Contains the different values to write in the TBR register (used by AWU_Init function) */
00049 CONST uint8_t TBR_Array[17] =
00050     {
00051         0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 12, 14, 15, 15
00052     };
00053
00054 /* Public functions ----------------------------------------------------------*/
00055
00056 /**
00057   * @addtogroup AWU_Public_Functions
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  Deinitializes the AWU peripheral registers to their default reset
00063   * values.
00064   * @param  None
00065   * @retval None
00066   */
00067 void AWU_DeInit(void)
00068 {
00069     AWU->CSR = AWU_CSR_RESET_VALUE;
00070     AWU->APR = AWU_APR_RESET_VALUE;
00071     AWU->TBR = AWU_TBR_RESET_VALUE;
00072 }
00073
00074 /**
00075   * @brief  Initializes the AWU peripheral according to the specified parameters.
00076   * @param   AWU_TimeBase : Time base selection (interval between AWU interrupts).
00077   * can be one of the values of @ref AWU_Timebase_TypeDef.
00078   * @retval None
00079   * @par Required preconditions:
00080   * The LS RC calibration must be performed before calling this function.
00081   */
00082 void AWU_Init(AWU_Timebase_TypeDef AWU_TimeBase)
00083 {
00084
00085     /* Check parameter */
00086     assert_param(IS_AWU_TIMEBASE_OK(AWU_TimeBase));
00087
00088     /* Enable the AWU peripheral */
00089     AWU->CSR |= AWU_CSR_AWUEN;
00090
00091     /* Set the TimeBase */
00092     AWU->TBR &= (uint8_t)(~AWU_TBR_AWUTB);
00093     AWU->TBR |= TBR_Array[(uint8_t)AWU_TimeBase];
00094
00095     /* Set the APR divider */
00096     AWU->APR &= (uint8_t)(~AWU_APR_APR);
00097     AWU->APR |= APR_Array[(uint8_t)AWU_TimeBase];
00098
00099 }
00100
00101 /**
00102   * @brief  Enable or disable the AWU peripheral.
00103   * @param   NewState Indicates the new state of the AWU peripheral.
00104   * @retval None
00105   * @par Required preconditions:
00106   * Initialisation of AWU and LS RC calibration must be done before.
00107   */
00108 void AWU_Cmd(FunctionalState NewState)
00109 {
00110     if (NewState != DISABLE)
00111     {
00112         /* Enable the AWU peripheral */
00113         AWU->CSR |= AWU_CSR_AWUEN;
00114     }
00115     else
00116     {
00117         /* Disable the AWU peripheral */
00118         AWU->CSR &= (uint8_t)(~AWU_CSR_AWUEN);
00119     }
00120 }
00121
00122 /**
00123   * @brief  Update APR register with the measured LSI frequency.
00124   * @par Note on the APR calculation:
00125   * A is the integer part of lsifreqkhz/4 and x the decimal part.
00126   * x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1]
00127   * but we know that A + x = lsifreqkhz/4 ==> 4x = lsifreqkhz-4A
00128   * so [F1] can be written :
00129   * 4A >= (lsifreqkhz-4A)(1+2A)
00130   * @param   LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
00131   * @retval None
00132   * @par Required preconditions:
00133   * - AWU must be disabled to avoid unwanted interrupts.
00134   */
00135 void AWU_LSICalibrationConfig(uint32_t LSIFreqHz)
00136 {
00137
00138     uint16_t lsifreqkhz = 0x0;
00139     uint16_t A = 0x0;
00140
00141     /* Check parameter */
00142     assert_param(IS_LSI_FREQUENCY_OK(LSIFreqHz));
00143
00144     lsifreqkhz = (uint16_t)(LSIFreqHz / 1000); /* Converts value in kHz */
00145
00146     /* Calculation of AWU calibration value */
00147
00148     A = (uint16_t)(lsifreqkhz >> 2U); /* Division by 4, keep integer part only */
00149
00150     if ((4U * A) >= ((lsifreqkhz - (4U * A)) * (1U + (2U * A))))
00151     {
00152         AWU->APR = (uint8_t)(A - 2U);
00153     }
00154     else
00155     {
00156         AWU->APR = (uint8_t)(A - 1U);
00157     }
00158 }
00159
00160 /**
00161   * @brief  Configures AWU in Idle mode to reduce power consumption.
00162   * @param  None
00163   * @retval None
00164   */
00165 void AWU_IdleModeEnable(void)
00166 {
00167     /* Disable AWU peripheral */
00168     AWU->CSR &= (uint8_t)(~AWU_CSR_AWUEN);
00169
00170     /* No AWU timebase */
00171     AWU->TBR = (uint8_t)(~AWU_TBR_AWUTB);
00172 }
00173
00174 /**
00175   * @brief  Returns status of the AWU peripheral flag.
00176   * @param  None
00177   * @retval FlagStatus : Status of the AWU flag.
00178   * This parameter can be any of the @ref FlagStatus enumeration.
00179   */
00180 FlagStatus AWU_GetFlagStatus(void)
00181 {
00182     return((FlagStatus)(((uint8_t)(AWU->CSR & AWU_CSR_AWUF) == (uint8_t)0x00) ? RESET : SET));
00183 }
00184
00185
00186 /**
00187   * @}
00188   */
00189
00190 /**
00191   * @}
00192   */
00193
00194 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_awu.h Source File

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  • Globals
  • STM8S_StdPeriph_Driver
  • inc

stm8s_awu.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_awu.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the AWU peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_AWU_H
00024 #define __STM8S_AWU_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030
00031 /** @addtogroup AWU_Exported_Types
00032   * @{
00033   */
00034
00035 /**
00036   * @brief  AWU TimeBase selection
00037   */
00038
00039 typedef enum
00040 {
00041   AWU_TIMEBASE_NO_IT  = (uint8_t)0,    /*!< No AWU interrupt selected */
00042   AWU_TIMEBASE_250US  = (uint8_t)1,    /*!< AWU Timebase equals 0.25 ms */
00043   AWU_TIMEBASE_500US  = (uint8_t)2,    /*!< AWU Timebase equals 0.5 ms */
00044   AWU_TIMEBASE_1MS    = (uint8_t)3,    /*!< AWU Timebase equals 1 ms */
00045   AWU_TIMEBASE_2MS    = (uint8_t)4,    /*!< AWU Timebase equals 2 ms */
00046   AWU_TIMEBASE_4MS    = (uint8_t)5,    /*!< AWU Timebase equals 4 ms */
00047   AWU_TIMEBASE_8MS    = (uint8_t)6,    /*!< AWU Timebase equals 8 ms */
00048   AWU_TIMEBASE_16MS   = (uint8_t)7,    /*!< AWU Timebase equals 16 ms */
00049   AWU_TIMEBASE_32MS   = (uint8_t)8,    /*!< AWU Timebase equals 32 ms */
00050   AWU_TIMEBASE_64MS   = (uint8_t)9,    /*!< AWU Timebase equals 64 ms */
00051   AWU_TIMEBASE_128MS  = (uint8_t)10,   /*!< AWU Timebase equals 128 ms */
00052   AWU_TIMEBASE_256MS  = (uint8_t)11,   /*!< AWU Timebase equals 256 ms */
00053   AWU_TIMEBASE_512MS  = (uint8_t)12,   /*!< AWU Timebase equals 512 ms */
00054   AWU_TIMEBASE_1S     = (uint8_t)13,   /*!< AWU Timebase equals 1 s */
00055   AWU_TIMEBASE_2S     = (uint8_t)14,   /*!< AWU Timebase equals 2 s */
00056   AWU_TIMEBASE_12S    = (uint8_t)15,   /*!< AWU Timebase equals 12 s */
00057   AWU_TIMEBASE_30S    = (uint8_t)16    /*!< AWU Timebase equals 30 s */
00058 } AWU_Timebase_TypeDef;
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Exported constants --------------------------------------------------------*/
00065
00066 /** @addtogroup AWU_Exported_Constants
00067   * @{
00068   */
00069
00070 #define LSI_FREQUENCY_MIN ((uint32_t)110000) /*!< LSI minimum value in Hertz */
00071 #define LSI_FREQUENCY_MAX ((uint32_t)150000) /*!< LSI maximum value in Hertz */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported macros ------------------------------------------------------------*/
00078
00079 /* Private macros ------------------------------------------------------------*/
00080
00081 /** @addtogroup AWU_Private_Macros
00082   * @{
00083   */
00084
00085 /**
00086   * @brief  Macro used by the assert function to check the different functions parameters.
00087   */
00088
00089 /**
00090   * @brief   Macro used by the assert function to check the AWU timebases
00091   */
00092 #define IS_AWU_TIMEBASE_OK(TB) \
00093   (((TB) == AWU_TIMEBASE_NO_IT) || \
00094    ((TB) == AWU_TIMEBASE_250US) || \
00095    ((TB) == AWU_TIMEBASE_500US) || \
00096    ((TB) == AWU_TIMEBASE_1MS)   || \
00097    ((TB) == AWU_TIMEBASE_2MS)   || \
00098    ((TB) == AWU_TIMEBASE_4MS)   || \
00099    ((TB) == AWU_TIMEBASE_8MS)   || \
00100    ((TB) == AWU_TIMEBASE_16MS)  || \
00101    ((TB) == AWU_TIMEBASE_32MS)  || \
00102    ((TB) == AWU_TIMEBASE_64MS)  || \
00103    ((TB) == AWU_TIMEBASE_128MS) || \
00104    ((TB) == AWU_TIMEBASE_256MS) || \
00105    ((TB) == AWU_TIMEBASE_512MS) || \
00106    ((TB) == AWU_TIMEBASE_1S)    || \
00107    ((TB) == AWU_TIMEBASE_2S)    || \
00108    ((TB) == AWU_TIMEBASE_12S)   || \
00109    ((TB) == AWU_TIMEBASE_30S))
00110
00111 /**
00112   * @brief    Macro used by the assert function to check the LSI frequency (in Hz)
00113   */
00114 #define IS_LSI_FREQUENCY_OK(FREQ) \
00115   (((FREQ) >= LSI_FREQUENCY_MIN) && \
00116    ((FREQ) <= LSI_FREQUENCY_MAX))
00117
00118 /**
00119   * @}
00120   */
00121
00122 /* Exported functions ------------------------------------------------------- */
00123
00124 /** @addtogroup AWU_Exported_Functions
00125   * @{
00126   */
00127 void AWU_DeInit(void);
00128 void AWU_Init(AWU_Timebase_TypeDef AWU_TimeBase);
00129 void AWU_Cmd(FunctionalState NewState);
00130 void AWU_LSICalibrationConfig(uint32_t LSIFreqHz);
00131 void AWU_IdleModeEnable(void);
00132 FlagStatus AWU_GetFlagStatus(void);
00133
00134 /**
00135   * @}
00136   */
00137
00138 #endif /* __STM8S_AWU_H */
00139
00140 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_beep.c Source File

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  • STM8S_StdPeriph_Driver
  • src

stm8s_beep.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_beep.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the BEEP peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_beep.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034
00035 /* Public functions ----------------------------------------------------------*/
00036
00037 /**
00038   * @addtogroup BEEP_Public_Functions
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  Deinitializes the BEEP peripheral registers to their default reset
00044   * values.
00045   * @param  None
00046   * @retval None
00047   */
00048 void BEEP_DeInit(void)
00049 {
00050     BEEP->CSR = BEEP_CSR_RESET_VALUE;
00051 }
00052
00053 /**
00054   * @brief  Initializes the BEEP function according to the specified parameters.
00055   * @param   BEEP_Frequency Frequency selection.
00056   * can be one of the values of @ref BEEP_Frequency_TypeDef.
00057   * @retval None
00058   * @par Required preconditions:
00059   * The LS RC calibration must be performed before calling this function.
00060   */
00061 void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency)
00062 {
00063
00064     /* Check parameter */
00065     assert_param(IS_BEEP_FREQUENCY_OK(BEEP_Frequency));
00066
00067     /* Set a default calibration value if no calibration is done */
00068     if ((BEEP->CSR & BEEP_CSR_BEEPDIV) == BEEP_CSR_BEEPDIV)
00069     {
00070         BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPDIV); /* Clear bits */
00071         BEEP->CSR |= BEEP_CALIBRATION_DEFAULT;
00072     }
00073
00074     /* Select the output frequency */
00075     BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPSEL);
00076     BEEP->CSR |= (uint8_t)(BEEP_Frequency);
00077
00078 }
00079
00080 /**
00081   * @brief  Enable or disable the BEEP function.
00082   * @param   NewState Indicates the new state of the BEEP function.
00083   * @retval None
00084   * @par Required preconditions:
00085   * Initialisation of BEEP and LS RC calibration must be done before.
00086   */
00087 void BEEP_Cmd(FunctionalState NewState)
00088 {
00089     if (NewState != DISABLE)
00090     {
00091         /* Enable the BEEP peripheral */
00092         BEEP->CSR |= BEEP_CSR_BEEPEN;
00093     }
00094     else
00095     {
00096         /* Disable the BEEP peripheral */
00097         BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPEN);
00098     }
00099 }
00100
00101 /**
00102   * @brief  Update CSR register with the measured LSI frequency.
00103   * @par Note on the APR calculation:
00104   * A is the integer part of LSIFreqkHz/4 and x the decimal part.
00105   * x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1]
00106   * but we know that A + x = LSIFreqkHz/4 ==> 4x = LSIFreqkHz-4A
00107   * so [F1] can be written :
00108   * 4A >= (LSIFreqkHz-4A)(1+2A)
00109   * @param   LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
00110   * @retval None
00111   * @par Required preconditions:
00112   * - BEEP must be disabled to avoid unwanted interrupts.
00113   */
00114 void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz)
00115 {
00116
00117     uint16_t lsifreqkhz;
00118     uint16_t A;
00119
00120     /* Check parameter */
00121     assert_param(IS_LSI_FREQUENCY_OK(LSIFreqHz));
00122
00123     lsifreqkhz = (uint16_t)(LSIFreqHz / 1000); /* Converts value in kHz */
00124
00125     /* Calculation of BEEPER calibration value */
00126
00127     BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPDIV); /* Clear bits */
00128
00129     A = (uint16_t)(lsifreqkhz >> 3U); /* Division by 8, keep integer part only */
00130
00131     if ((8U * A) >= ((lsifreqkhz - (8U * A)) * (1U + (2U * A))))
00132     {
00133         BEEP->CSR |= (uint8_t)(A - 2U);
00134     }
00135     else
00136     {
00137         BEEP->CSR |= (uint8_t)(A - 1U);
00138     }
00139 }
00140
00141 /**
00142   * @}
00143   */
00144
00145 /**
00146   * @}
00147   */
00148
00149 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_beep.h Source File

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  • STM8S_StdPeriph_Driver
  • inc

stm8s_beep.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_beep.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the BEEP peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM8S_BEEP_H
00025 #define __STM8S_BEEP_H
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm8s.h"
00029
00030 /* Exported types ------------------------------------------------------------*/
00031
00032 /** @addtogroup BEEP_Exported_Types
00033   * @{
00034   */
00035
00036 /**
00037   * @brief  BEEP Frequency selection
00038   */
00039 typedef enum {
00040   BEEP_FREQUENCY_1KHZ = (uint8_t)0x00,  /*!< Beep signal output frequency equals to 1 KHz */
00041   BEEP_FREQUENCY_2KHZ = (uint8_t)0x40,  /*!< Beep signal output frequency equals to 2 KHz */
00042   BEEP_FREQUENCY_4KHZ = (uint8_t)0x80   /*!< Beep signal output frequency equals to 4 KHz */
00043 } BEEP_Frequency_TypeDef;
00044
00045 /**
00046   * @}
00047   */
00048
00049 /* Exported constants --------------------------------------------------------*/
00050
00051 /** @addtogroup BEEP_Exported_Constants
00052   * @{
00053   */
00054
00055 #define BEEP_CALIBRATION_DEFAULT ((uint8_t)0x0B) /*!< Default value when calibration is not done */
00056
00057 #define LSI_FREQUENCY_MIN ((uint32_t)110000) /*!< LSI minimum value in Hertz */
00058 #define LSI_FREQUENCY_MAX ((uint32_t)150000) /*!< LSI maximum value in Hertz */
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Exported macros -----------------------------------------------------------*/
00065 /* Private macros ------------------------------------------------------------*/
00066
00067 /** @addtogroup BEEP_Private_Macros
00068   * @{
00069   */
00070
00071 /**
00072   * @brief  Macro used by the assert function to check the different functions parameters.
00073   */
00074
00075 /**
00076   * @brief  Macro used by the assert function to check the BEEP frequencies.
00077   */
00078 #define IS_BEEP_FREQUENCY_OK(FREQ) \
00079   (((FREQ) == BEEP_FREQUENCY_1KHZ) || \
00080    ((FREQ) == BEEP_FREQUENCY_2KHZ) || \
00081    ((FREQ) == BEEP_FREQUENCY_4KHZ))
00082
00083 /**
00084   * @brief   Macro used by the assert function to check the LSI frequency (in Hz).
00085   */
00086 #define IS_LSI_FREQUENCY_OK(FREQ) \
00087   (((FREQ) >= LSI_FREQUENCY_MIN) && \
00088    ((FREQ) <= LSI_FREQUENCY_MAX))
00089
00090 /**
00091   * @}
00092   */
00093
00094 /* Exported functions ------------------------------------------------------- */
00095
00096 /** @addtogroup BEEP_Exported_Functions
00097   * @{
00098   */
00099
00100 void BEEP_DeInit(void);
00101 void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency);
00102 void BEEP_Cmd(FunctionalState NewState);
00103 void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz);
00104
00105
00106 /**
00107   * @}
00108   */
00109
00110 #endif /* __STM8S_BEEP_H */
00111
00112 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_can.c Source File

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  • STM8S_StdPeriph_Driver
  • src

stm8s_can.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_can.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the CAN peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_can.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 #define CAN_IDLIST_IDMASK_MASK ((uint8_t) 0x55)
00031 #define CAN_IDMASK_IDLIST_MASK ((uint8_t) 0xAA)
00032 #define CAN_MODE_MASK ((uint8_t) 0x03)
00033 #define CAN_ACKNOWLEDGE_TIMEOUT ((uint16_t)0xFFFF)
00034 /* Private macro -------------------------------------------------------------*/
00035 /* Private variables ---------------------------------------------------------*/
00036 __IO uint32_t _Id = 0;
00037 __IO uint8_t _IDE = 0;
00038 __IO uint8_t _RTR = 0;
00039 __IO uint8_t _DLC = 0;
00040 __IO uint8_t _Data[8] = {0};
00041 __IO uint8_t _FMI = 0;
00042 /* Private function prototypes -----------------------------------------------*/
00043 static ITStatus CheckITStatus(uint8_t CAN_Reg, uint8_t It_Bit);
00044
00045 /* Private functions ---------------------------------------------------------*/
00046 /**
00047   * @addtogroup CAN_Public_Functions
00048   * @{
00049   */
00050
00051 /**
00052   * @brief  Deinitializes the CAN peripheral registers to their default reset values.
00053   * @param  None
00054   * @retval None
00055   */
00056 void CAN_DeInit(void)
00057 {
00058     /* Request initialisation */
00059     CAN->MCR = CAN_MCR_INRQ;
00060     CAN->PSR = CAN_Page_Config;
00061     CAN_OperatingModeRequest(CAN_OperatingMode_Initialization);
00062     CAN->Page.Config.ESR = CAN_ESR_RESET_VALUE;
00063     CAN->Page.Config.EIER = CAN_EIER_RESET_VALUE;
00064     CAN->Page.Config.BTR1 = CAN_BTR1_RESET_VALUE;
00065     CAN->Page.Config.BTR2 = CAN_BTR2_RESET_VALUE;
00066     CAN->Page.Config.FMR1 = CAN_FMR1_RESET_VALUE;
00067     CAN->Page.Config.FMR2 = CAN_FMR2_RESET_VALUE;
00068     CAN->Page.Config.FCR1 = CAN_FCR_RESET_VALUE;
00069     CAN->Page.Config.FCR2 = CAN_FCR_RESET_VALUE;
00070     CAN->Page.Config.FCR3 = CAN_FCR_RESET_VALUE;
00071     CAN_OperatingModeRequest(CAN_OperatingMode_Normal);
00072     CAN->PSR = CAN_Page_RxFifo;
00073     CAN->Page.RxFIFO.MDLCR = CAN_MDLC_RESET_VALUE;
00074     CAN->PSR = CAN_Page_TxMailBox0;
00075     CAN->Page.TxMailbox.MDLCR = CAN_MDLC_RESET_VALUE;
00076     CAN->PSR = CAN_Page_TxMailBox1;
00077     CAN->Page.TxMailbox.MDLCR = CAN_MDLC_RESET_VALUE;
00078     CAN->PSR = CAN_Page_TxMailBox2;
00079     CAN->Page.TxMailbox.MDLCR = CAN_MDLC_RESET_VALUE;
00080
00081     CAN->MCR = CAN_MCR_RESET_VALUE;
00082     CAN->MSR = (uint8_t)(~CAN_MSR_RESET_VALUE);/* rc_w1 */
00083     CAN->TSR = (uint8_t)(~CAN_TSR_RESET_VALUE);/* rc_w1 */
00084     CAN->RFR = (uint8_t)(~CAN_RFR_RESET_VALUE);/* rc_w1 */
00085     CAN->IER = CAN_IER_RESET_VALUE;
00086     CAN->DGR = CAN_DGR_RESET_VALUE;
00087     CAN->PSR = CAN_PSR_RESET_VALUE;
00088 }
00089
00090 /**
00091   * @brief  Initializes the CAN peripheral according to the specified parameters.
00092   * @param   CAN_MasterCtrl : Master control option, can be one or a combination of @ref CAN_MasterCtrl_TypeDef.
00093   * @param   CAN_Mode : CAN mode , can be one of @ref CAN_Mode_TypeDef.
00094   * @param   CAN_SynJumpWidth : CAN Synchronisation Jump Width , can be one of @ref CAN_SynJumpWidth_TypeDef.
00095   * @param   CAN_BitSeg1 : CAN bit segment 1 , can be one of @ref CAN_BitSeg1_TypeDef.
00096   * @param   CAN_BitSeg2 : CAN bit segment 2 , can be one of @ref CAN_BitSeg2_TypeDef.
00097   * @param   CAN_Prescaler : CAN Baud Rate Prescaler , can be a value from 0x01 to 0xFF.
00098   * @retval Indicates if initialization is succeed. it can be one of @ref CAN_InitStatus_TypeDef enumeration.
00099   */
00100 CAN_InitStatus_TypeDef CAN_Init(CAN_MasterCtrl_TypeDef CAN_MasterCtrl,
00101                                 CAN_Mode_TypeDef CAN_Mode,
00102                                 CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth,
00103                                 CAN_BitSeg1_TypeDef CAN_BitSeg1,
00104                                 CAN_BitSeg2_TypeDef CAN_BitSeg2,
00105                                 uint8_t CAN_Prescaler)
00106 {
00107     CAN_InitStatus_TypeDef InitStatus =  CAN_InitStatus_Failed;
00108     uint16_t timeout = CAN_ACKNOWLEDGE_TIMEOUT;
00109     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00110
00111
00112     /* Check the parameters */
00113     assert_param(IS_CAN_MASTERCTRL_OK(CAN_MasterCtrl));
00114     assert_param(IS_CAN_MODE_OK(CAN_Mode));
00115     assert_param(IS_CAN_SYNJUMPWIDTH_OK(CAN_SynJumpWidth));
00116     assert_param(IS_CAN_BITSEG1_OK(CAN_BitSeg1));
00117     assert_param(IS_CAN_BITSEG2_OK(CAN_BitSeg2));
00118     assert_param(IS_CAN_PRESCALER_OK(CAN_Prescaler));
00119
00120     /* Request initialisation */
00121     CAN->MCR = CAN_MCR_INRQ;
00122     /* Wait the acknowledge */
00123     while (((uint8_t)(CAN->MSR & CAN_MSR_INAK) != 0x01) && ((uint16_t)timeout != 0))
00124     {
00125         timeout--;
00126     }
00127
00128     /* Check acknowledged */
00129     if ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
00130     {
00131
00132         InitStatus =  CAN_InitStatus_Failed;
00133
00134     }
00135     else
00136     {
00137         /* Set the time triggered communication mode  &  Set the automatic bus-off management  &   Set the automatic wake-up mode
00138         &     Set the no automatic retransmission & Set the receive FIFO locked mode & Set the transmit FIFO priority */
00139         CAN->MCR |= (uint8_t)CAN_MasterCtrl;
00140
00141         /* Set the bit timing register */
00142         CAN->DGR |= (uint8_t)CAN_Mode ;
00143         CAN->PSR = CAN_Page_Config;
00144         CAN->Page.Config.BTR1 = (uint8_t)((uint8_t)(CAN_Prescaler - (uint8_t)1) | CAN_SynJumpWidth);
00145         CAN->Page.Config.BTR2 = (uint8_t)(CAN_BitSeg1 | (uint8_t)CAN_BitSeg2);
00146
00147         /* Request leave initialisation */
00148         CAN->MCR &= (uint8_t)(~CAN_MCR_INRQ);
00149         /* Wait the acknowledge */
00150         timeout = 0xFFFF;
00151         while ((((uint8_t)(CAN->MSR & CAN_MSR_INAK) == 0x01))&&(timeout != 0))
00152         {
00153             timeout--;
00154         }
00155         /* Check acknowledged */
00156         if ((CAN->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
00157         {
00158             InitStatus = CAN_InitStatus_Failed;
00159         }
00160         else
00161         {
00162             InitStatus = CAN_InitStatus_Success;
00163         }
00164     }
00165     /*Restore Last Page*/
00166     CAN_SelectPage(can_page);
00167
00168     /* Return the status of initialization */
00169     return (CAN_InitStatus_TypeDef)InitStatus;
00170 }
00171
00172 /**
00173   * @brief  Initializes the CAN peripheral Filter according to the specified parameters.
00174   * @param   CAN_FilterNumber : CAN Filter number , can be one of @ref CAN_FilterNumber_TypeDef
00175   * @param   CAN_FilterActivation : CAN Filter Activation state , can be one of @ref FunctionalState
00176   * @param   CAN_FilterMode : CAN Filter Mode , can be one of @ref CAN_FilterMode_TypeDef
00177   * @param   CAN_FilterScale : CAN Filter Scale , can be one of @ref CAN_FilterScale_TypeDef
00178   * @param   CAN_FilterID1 : CAN Filter ID 1 , can be a value from 0x00 to 0xFF
00179   * @param   CAN_FilterID2 : CAN Filter ID 2 , can be a value from 0x00 to 0xFF
00180   * @param   CAN_FilterID3 : CAN Filter ID 3 , can be a value from 0x00 to 0xFF
00181   * @param   CAN_FilterID4 : CAN Filter ID 4 , can be a value from 0x00 to 0xFF
00182   * @param   CAN_FilterIDMask1 : CAN Filter ID 1/ Mask 1  , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
00183   * @param   CAN_FilterIDMask2 : CAN Filter ID 2/ Mask 2 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
00184   * @param   CAN_FilterIDMask3 : CAN Filter ID 3/ Mask 3 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
00185   * @param   CAN_FilterIDMask4 : CAN Filter ID 4/ Mask 4 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter
00186   * @retval None
00187   */
00188 void CAN_FilterInit(CAN_FilterNumber_TypeDef CAN_FilterNumber,
00189                     FunctionalState CAN_FilterActivation,
00190                     CAN_FilterMode_TypeDef CAN_FilterMode,
00191                     CAN_FilterScale_TypeDef CAN_FilterScale,
00192                     uint8_t CAN_FilterID1,
00193                     uint8_t CAN_FilterID2,
00194                     uint8_t CAN_FilterID3,
00195                     uint8_t CAN_FilterID4,
00196                     uint8_t CAN_FilterIDMask1,
00197                     uint8_t CAN_FilterIDMask2,
00198                     uint8_t CAN_FilterIDMask3,
00199                     uint8_t CAN_FilterIDMask4)
00200 {
00201     uint8_t fact = 0;
00202     uint8_t fsc  = 0;
00203     uint8_t fmhl = 0;
00204
00205     CAN_Page_TypeDef can_page_filter = CAN_Page_Filter01;
00206     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00207
00208     /* Check the parameters */
00209     assert_param(IS_CAN_FILTER_NUMBER_OK(CAN_FilterNumber));
00210     assert_param(IS_FUNCTIONALSTATE_OK(CAN_FilterActivation));
00211     assert_param(IS_CAN_FILTER_MODE_OK(CAN_FilterMode));
00212     assert_param(IS_CAN_FILTER_SCALE_OK(CAN_FilterScale));
00213
00214
00215     if (CAN_FilterNumber == CAN_FilterNumber_0)
00216     {
00217         fact = 0x01;
00218         fsc  = 0x00;
00219         fmhl = 0x03;
00220
00221         can_page_filter = CAN_Page_Filter01;
00222     }
00223     else if (CAN_FilterNumber == CAN_FilterNumber_1)
00224     {
00225         fact = 0x10;
00226         fsc  = 0x04;
00227         fmhl = 0x0C;
00228
00229         can_page_filter = CAN_Page_Filter01;
00230     }
00231     else if (CAN_FilterNumber == CAN_FilterNumber_2)
00232     {
00233         fact = 0x01;
00234         fsc  = 0x00;
00235         fmhl = 0x30;
00236
00237         can_page_filter = CAN_Page_Filter23;
00238     }
00239     else if (CAN_FilterNumber == CAN_FilterNumber_3)
00240     {
00241         fact = 0x10;
00242         fsc  = 0x04;
00243         fmhl = 0xC0;
00244
00245         can_page_filter = CAN_Page_Filter23;
00246     }
00247     else if (CAN_FilterNumber == CAN_FilterNumber_4)
00248     {
00249         fact = 0x01;
00250         fsc  = 0x00;
00251         fmhl = 0x03;
00252
00253         can_page_filter = CAN_Page_Filter45;
00254     }
00255     else /*if (CAN_FilterNumber == CAN_FilterNumber_5)*/
00256     {
00257         fact = 0x10;
00258         fsc  = 0x04;
00259         fmhl = 0x0C;
00260
00261         can_page_filter = CAN_Page_Filter45;
00262     }
00263
00264
00265     CAN_OperatingModeRequest(CAN_OperatingMode_Initialization);
00266
00267     CAN->PSR = CAN_Page_Config;
00268     /*---------------------------------------------------------*/
00269     /*Configuration of Filter Scale                            */
00270     /*---------------------------------------------------------*/
00271
00272     if (can_page_filter == CAN_Page_Filter01) /* FCR1 */
00273     {
00274         /* Filter Deactivation  & Reset the Filter Scale */
00275         CAN->Page.Config.FCR1 &= (uint8_t)(~(uint8_t)(fact | (uint8_t)((uint8_t)(CAN_FCR1_FSC00|CAN_FCR1_FSC01) << fsc )));
00276         /* Set the new Filter Scale */
00277         CAN->Page.Config.FCR1 |= (uint8_t)(CAN_FilterScale << fsc);
00278     }
00279     else if (can_page_filter == CAN_Page_Filter23) /* FCR2*/
00280     {
00281         /* Filter Deactivation  & Reset the Filter Scale */
00282         CAN->Page.Config.FCR2 &= (uint8_t)~(uint8_t)( fact | (uint8_t)((uint8_t)(CAN_FCR1_FSC00|CAN_FCR1_FSC01) << fsc ));
00283
00284         /* Set the new Filter Scale */
00285         CAN->Page.Config.FCR2 |= (uint8_t)(CAN_FilterScale << fsc);
00286
00287     }
00288     else /*if(can_page_filter == CAN_Page_Filter45)*/ /* FCR3*/
00289     {
00290         /* Filter Deactivation  & Reset the Filter Scale */
00291         CAN->Page.Config.FCR3 &= (uint8_t)~(uint8_t)( fact | (uint8_t)((uint8_t)(CAN_FCR1_FSC00|CAN_FCR1_FSC01) << fsc ));
00292
00293         /* Set the new Filter Scale */
00294         CAN->Page.Config.FCR3 |= (uint8_t)(CAN_FilterScale << fsc);
00295     }
00296
00297     /*---------------------------------------------------------*/
00298     /*Configuration of Filter Mode                             */
00299     /*---------------------------------------------------------*/
00300     if (can_page_filter != CAN_Page_Filter45) /* FMR1*/
00301     {
00302         /* Filter Mode */
00303         if (CAN_FilterMode == CAN_FilterMode_IdMask)
00304         {
00305             /*Id/Mask mode for the filter*/
00306             CAN->Page.Config.FMR1 &= (uint8_t)~(fmhl);
00307         }
00308         else if ( CAN_FilterMode == CAN_FilterMode_IdList)
00309         {
00310             /*Identifier list mode for the filter*/
00311             CAN->Page.Config.FMR1 |= (uint8_t)(fmhl);
00312         }
00313         else if ( CAN_FilterMode == CAN_FilterMode_IdList_IdMask)
00314         {
00315             /*Identifier list mode is first  for the filter*/
00316             CAN->Page.Config.FMR1 |= (uint8_t)(fmhl & CAN_IDLIST_IDMASK_MASK);
00317         }
00318         else /* ( CAN_FilterMode == CAN_FilterMode_IdMask_IdList)*/
00319         {
00320             /*Id Mask mode is first  for the filter*/
00321             CAN->Page.Config.FMR1 |= (uint8_t)(fmhl & CAN_IDMASK_IDLIST_MASK);
00322         }
00323
00324
00325     }
00326     else /* FMR2 */
00327     {
00328
00329         /* Filter Mode */
00330         if (CAN_FilterMode == CAN_FilterMode_IdMask)
00331         {
00332             /*Id/Mask mode for the filter*/
00333             CAN->Page.Config.FMR2 &= (uint8_t)~(fmhl);
00334         }
00335         else if ( CAN_FilterMode == CAN_FilterMode_IdList)
00336         {
00337             /*Identifier list mode for the filter*/
00338             CAN->Page.Config.FMR2 |= (uint8_t)(fmhl);
00339         }
00340         else if ( CAN_FilterMode == CAN_FilterMode_IdList_IdMask)
00341         {
00342             /*Identifier list mode is first  for the filter*/
00343             CAN->Page.Config.FMR2 |= (uint8_t)(fmhl & CAN_IDLIST_IDMASK_MASK);
00344         }
00345         else /* ( CAN_FilterMode == CAN_FilterMode_IdMask_IdList)*/
00346         {
00347             /*Id Mask mode is first  for the filter*/
00348             CAN->Page.Config.FMR2 |= (uint8_t)(fmhl & CAN_IDMASK_IDLIST_MASK);
00349         }
00350     }
00351     /*---------------------------------------------------------*/
00352     /*Configuration of Filter IDs                              */
00353     /*---------------------------------------------------------*/
00354     CAN->PSR = (uint8_t)can_page_filter;
00355     if (fsc != 0)
00356     {
00357         /* Filter Scale */
00358         if (CAN_FilterScale == CAN_FilterScale_8Bit)
00359         {
00360             CAN->Page.Filter.FR09 = CAN_FilterID1;
00361             CAN->Page.Filter.FR10 = CAN_FilterIDMask1;
00362             CAN->Page.Filter.FR11 = CAN_FilterID2;
00363             CAN->Page.Filter.FR12 = CAN_FilterIDMask2;
00364             CAN->Page.Filter.FR13 = CAN_FilterID3;
00365             CAN->Page.Filter.FR14 = CAN_FilterIDMask3;
00366             CAN->Page.Filter.FR15 = CAN_FilterID4;
00367             CAN->Page.Filter.FR16 = CAN_FilterIDMask4;
00368         }
00369         else if (CAN_FilterScale == CAN_FilterScale_16_8Bit)
00370         {
00371             CAN->Page.Filter.FR09 = CAN_FilterID1;
00372             CAN->Page.Filter.FR10 = CAN_FilterID2;
00373             CAN->Page.Filter.FR11 = CAN_FilterIDMask1;
00374             CAN->Page.Filter.FR12 = CAN_FilterIDMask2;
00375             CAN->Page.Filter.FR13 = CAN_FilterID3;
00376             CAN->Page.Filter.FR14 = CAN_FilterIDMask3;
00377             CAN->Page.Filter.FR15 = CAN_FilterID4;
00378             CAN->Page.Filter.FR16 = CAN_FilterIDMask4;
00379         }
00380         else if (CAN_FilterScale == CAN_FilterScale_16Bit)
00381         {
00382             CAN->Page.Filter.FR09 = CAN_FilterID1;
00383             CAN->Page.Filter.FR10 = CAN_FilterID2;
00384             CAN->Page.Filter.FR11 = CAN_FilterIDMask1;
00385             CAN->Page.Filter.FR12 = CAN_FilterIDMask2;
00386             CAN->Page.Filter.FR13 = CAN_FilterID3;
00387             CAN->Page.Filter.FR14 = CAN_FilterID4;
00388             CAN->Page.Filter.FR15 = CAN_FilterIDMask3;
00389             CAN->Page.Filter.FR16 = CAN_FilterIDMask4;
00390         }
00391         else if (CAN_FilterScale == CAN_FilterScale_32Bit)
00392         {
00393             CAN->Page.Filter.FR09 = CAN_FilterID1;
00394             CAN->Page.Filter.FR10 = CAN_FilterID2;
00395             CAN->Page.Filter.FR11 = CAN_FilterID3;
00396             CAN->Page.Filter.FR12 = CAN_FilterID4;
00397             CAN->Page.Filter.FR13 = CAN_FilterIDMask1;
00398             CAN->Page.Filter.FR14 = CAN_FilterIDMask2;
00399             CAN->Page.Filter.FR15 = CAN_FilterIDMask3;
00400             CAN->Page.Filter.FR16 = CAN_FilterIDMask4;
00401         }
00402     }
00403     else
00404     {
00405         /* Filter Scale */
00406         if (CAN_FilterScale == CAN_FilterScale_8Bit)
00407         {
00408             CAN->Page.Filter.FR01 = CAN_FilterID1;
00409             CAN->Page.Filter.FR02 = CAN_FilterIDMask1;
00410             CAN->Page.Filter.FR03 = CAN_FilterID2;
00411             CAN->Page.Filter.FR04 = CAN_FilterIDMask2;
00412             CAN->Page.Filter.FR05 = CAN_FilterID3;
00413             CAN->Page.Filter.FR06 = CAN_FilterIDMask3;
00414             CAN->Page.Filter.FR07 = CAN_FilterID4;
00415             CAN->Page.Filter.FR08 = CAN_FilterIDMask4;
00416         }
00417         else if (CAN_FilterScale == CAN_FilterScale_16_8Bit)
00418         {
00419             CAN->Page.Filter.FR01 = CAN_FilterID1;
00420             CAN->Page.Filter.FR02 = CAN_FilterID2;
00421             CAN->Page.Filter.FR03 = CAN_FilterIDMask1;
00422             CAN->Page.Filter.FR04 = CAN_FilterIDMask2;
00423             CAN->Page.Filter.FR05 = CAN_FilterID3;
00424             CAN->Page.Filter.FR06 = CAN_FilterIDMask3;
00425             CAN->Page.Filter.FR07 = CAN_FilterID4;
00426             CAN->Page.Filter.FR08 = CAN_FilterIDMask4;
00427         }
00428         else if (CAN_FilterScale == CAN_FilterScale_16Bit)
00429         {
00430             CAN->Page.Filter.FR01 = CAN_FilterID1;
00431             CAN->Page.Filter.FR02 = CAN_FilterID2;
00432             CAN->Page.Filter.FR03 = CAN_FilterIDMask1;
00433             CAN->Page.Filter.FR04 = CAN_FilterIDMask2;
00434             CAN->Page.Filter.FR05 = CAN_FilterID3;
00435             CAN->Page.Filter.FR06 = CAN_FilterID4;
00436             CAN->Page.Filter.FR07 = CAN_FilterIDMask3;
00437             CAN->Page.Filter.FR08 = CAN_FilterIDMask4;
00438         }
00439         else if (CAN_FilterScale == CAN_FilterScale_32Bit)
00440         {
00441             CAN->Page.Filter.FR01 = CAN_FilterID1;
00442             CAN->Page.Filter.FR02 = CAN_FilterID2;
00443             CAN->Page.Filter.FR03 = CAN_FilterID3;
00444             CAN->Page.Filter.FR04 = CAN_FilterID4;
00445             CAN->Page.Filter.FR05 = CAN_FilterIDMask1;
00446             CAN->Page.Filter.FR06 = CAN_FilterIDMask2;
00447             CAN->Page.Filter.FR07 = CAN_FilterIDMask3;
00448             CAN->Page.Filter.FR08 = CAN_FilterIDMask4;
00449         }
00450     }
00451
00452
00453     /*---------------------------------------------------------*/
00454     /*Configuration of Filter Activation                       */
00455     /*---------------------------------------------------------*/
00456     /* Filter activation */
00457     CAN->PSR = CAN_Page_Config;
00458     if (CAN_FilterActivation != DISABLE)
00459     {
00460         if ((CAN_FilterNumber & 0x06) == 0x00) /* FCR1*/
00461         {   CAN->Page.Config.FCR1 |= (uint8_t)fact;
00462         }
00463         else if ((CAN_FilterNumber & 0x06) == 0x02) /*FCR2*/
00464         { CAN->Page.Config.FCR2 |= (uint8_t)fact;
00465         }
00466         else /*if((CAN_FilterNumber & 0x06) == 0x04)*/ /*FCR3*/
00467         { CAN->Page.Config.FCR3 |= (uint8_t)fact;
00468         }
00469     }
00470     CAN_OperatingModeRequest(CAN_OperatingMode_Normal);
00471     /*Restore Last Page*/
00472     CAN_SelectPage(can_page);
00473 }
00474
00475 /**
00476   * @brief   Enables or disables the specified CAN interrupts.
00477   * @param    CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
00478   * @param   NewState : CAN_IT new state , can be one of @ref FunctionalState
00479   * @retval None
00480   */
00481 void CAN_ITConfig(CAN_IT_TypeDef CAN_IT, FunctionalState NewState)
00482 {
00483     uint8_t tmperrorinterrupt = 0;
00484     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00485
00486
00487     /* Check the parameters */
00488     assert_param(IS_CAN_IT_CONFIG_OK(CAN_IT));
00489     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00490
00491     tmperrorinterrupt = (uint8_t)(((uint16_t)CAN_IT) >>7);
00492     tmperrorinterrupt = (uint8_t)((uint8_t)((uint16_t)tmperrorinterrupt & 0xF0) |
00493                                   (uint8_t)((uint8_t)((uint16_t)tmperrorinterrupt & 0x0F) >>1));
00494
00495     CAN->PSR = CAN_Page_Config;
00496     if (NewState != DISABLE)
00497     {
00498         /* Enable the selected CAN interrupt */
00499         CAN->IER |= (uint8_t)(CAN_IT);
00500         CAN->Page.Config.EIER |= (uint8_t)(tmperrorinterrupt);
00501     }
00502     else
00503     {
00504         /* Disable the selected CAN interrupt */
00505         CAN->IER &= (uint8_t)~(uint8_t)((uint16_t)CAN_IT);
00506         CAN->Page.Config.EIER &= (uint8_t)~(tmperrorinterrupt);
00507     }
00508     /*Restore Last Page*/
00509     CAN_SelectPage(can_page);
00510 }
00511
00512 /**
00513   * @brief   Enables or Disables the ST7 CAN Compatibility.
00514   * if the ST7 compatibility is Enabled, CAN provides only 2 mailboxes.
00515   * if the ST7 compatibility is Disabled, CAN provides 3 mailboxes.
00516   * @param   CAN_ST7Compatibility : CAN ST7 Compatibility , this parameter can be one of @ref CAN_ST7Compatibility_TypeDef enumeration.
00517   * @retval None
00518   */
00519 void CAN_ST7CompatibilityCmd(CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)
00520 {
00521     /* Check the parameters */
00522     assert_param(IS_CAN_ST7_COMPATIBILITY_OK(CAN_ST7Compatibility));
00523     /*Reset the old configuration of TXM2E */
00524     CAN->DGR &= (uint8_t)(~CAN_DGR_TXM2E);
00525
00526     /*Set the old configuration of TXM2E */
00527     CAN->DGR |= (uint8_t)CAN_ST7Compatibility;
00528 }
00529
00530 /**
00531   * @brief  Enables or disables the CAN Time TriggerOperation communication mode.
00532   * @param   NewState : Mode new state , can be one of @ref FunctionalState
00533   * @retval None
00534   */
00535 void CAN_TTComModeCmd(FunctionalState NewState)
00536 {
00537     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00538     /* Check the parameters */
00539     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00540     if (NewState != DISABLE)
00541     {
00542         /*Enable the TTCM mode */
00543         CAN->MCR |= CAN_MCR_TTCM;
00544         /*Set TGT bits setting in Tx and FIFO pages*/
00545         CAN->PSR = CAN_Page_TxMailBox0;
00546         CAN->Page.TxMailbox.MDLCR |= CAN_MDLCR_TGT;
00547         CAN->PSR = CAN_Page_TxMailBox1;
00548         CAN->Page.TxMailbox.MDLCR |= CAN_MDLCR_TGT;
00549         CAN->PSR = CAN_Page_TxMailBox2;
00550         CAN->Page.TxMailbox.MDLCR |= CAN_MDLCR_TGT;
00551         CAN->PSR = CAN_Page_RxFifo;
00552         CAN->Page.RxFIFO.MDLCR |= CAN_MDLCR_TGT;
00553     }
00554     else
00555     {
00556         /*Disable the TTCM mode */
00557         CAN->MCR &= ((uint8_t)~CAN_MCR_TTCM);
00558         /*Reset TGT bits setting in Tx and FIFO pages*/
00559         CAN->PSR = CAN_Page_TxMailBox0;
00560         CAN->Page.TxMailbox.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);
00561         CAN->PSR = CAN_Page_TxMailBox1;
00562         CAN->Page.TxMailbox.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);
00563         CAN->PSR = CAN_Page_TxMailBox2;
00564         CAN->Page.TxMailbox.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);
00565         CAN->PSR = CAN_Page_RxFifo;
00566         CAN->Page.RxFIFO.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);
00567     }
00568     /*Restore Last Page*/
00569     CAN_SelectPage(can_page);
00570 }
00571
00572 /**
00573   * @brief  Initiates the transmission of a message.
00574   * @param   CAN_Id the ID number of the message, its size depends on @ref CAN_IDE value.
00575   * @param[in] CAN_IDE the ID type of the message, this parameter can be one of the @ref CAN_Id_TypeDef enumeration.
00576   * @param[in] CAN_RTR the message type, this parameter can be one of the @ref CAN_RTR_TypeDef enumeration.
00577   * @param[in] CAN_DLC the number of data in the message type, this parameter can be a value between 0 to 7.
00578   * @param[in] CAN_Data pointer to a the @ref uint8_t table which contains data to sent.
00579   * @retval Transmit Status, this returned value can be one of the @ref CAN_TxStatus_TypeDef enumeration.
00580   */
00581 CAN_TxStatus_TypeDef CAN_Transmit(uint32_t CAN_Id,
00582                                   CAN_Id_TypeDef CAN_IDE,
00583                                   CAN_RTR_TypeDef CAN_RTR,
00584                                   uint8_t CAN_DLC,
00585                                   uint8_t *CAN_Data)
00586 {
00587     CAN_TxStatus_TypeDef CAN_TxStatus = CAN_TxStatus_NoMailBox;
00588     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00589     /* Check the parameters */
00590     assert_param(IS_CAN_IDTYPE_OK(CAN_IDE));
00591     if (CAN_IDE != CAN_Id_Standard)
00592     {
00593         assert_param(IS_CAN_EXTID_OK(CAN_Id));
00594     }
00595     else
00596     {
00597         assert_param(IS_CAN_STDID_OK(CAN_Id));
00598     }
00599     assert_param(IS_CAN_RTR_OK(CAN_RTR));
00600     assert_param(IS_CAN_DLC_OK(CAN_DLC));
00601     /* Select one empty transmit mailbox */
00602     if ((CAN->TPR & CAN_TPR_TME0) == CAN_TPR_TME0)
00603     {
00604         CAN_TxStatus = CAN_TxStatus_MailBox0Ok;
00605     }
00606     else if ((CAN->TPR & CAN_TPR_TME1) == CAN_TPR_TME1)
00607     {
00608         CAN_TxStatus = CAN_TxStatus_MailBox1Ok;
00609     }
00610     else if ((CAN->TPR & CAN_TPR_TME2) == CAN_TPR_TME2)
00611     {
00612         CAN_TxStatus = CAN_TxStatus_MailBox2Ok;
00613     }
00614     else
00615     {
00616         CAN_TxStatus = CAN_TxStatus_NoMailBox;
00617     }
00618     if (CAN_TxStatus != CAN_TxStatus_NoMailBox)
00619     {
00620         CAN->PSR = (uint8_t)CAN_TxStatus;
00621         /* Set up the Id */
00622         if (CAN_IDE != CAN_Id_Standard)
00623         {
00624             CAN_Id &= (uint32_t)CAN_EXTID_SIZE;
00625             CAN->Page.TxMailbox.MIDR4 = (uint8_t)(CAN_Id);
00626             CAN_Id = CAN_Id>>8;
00627             CAN->Page.TxMailbox.MIDR3 = (uint8_t)(CAN_Id);
00628             CAN_Id = CAN_Id>>8;
00629             CAN->Page.TxMailbox.MIDR2 = (uint8_t)(CAN_Id);
00630             CAN_Id = CAN_Id>>8;
00631             CAN->Page.TxMailbox.MIDR1 = (uint8_t)(CAN_Id |CAN_IDE | CAN_RTR);
00632         }
00633         else
00634         {
00635             CAN_Id &= (uint16_t)CAN_STDID_SIZE;
00636             CAN->Page.TxMailbox.MIDR1 = (uint8_t)((CAN_Id>>6) | (CAN_RTR)) ;
00637             CAN->Page.TxMailbox.MIDR2 = (uint8_t)(CAN_Id<<2);
00638         }
00639         /* Set up the DLC                 */
00640         /*clear old DLC value*/
00641         CAN->Page.TxMailbox.MDLCR &= (uint8_t)0xF0;
00642         /*set the new value of DLC*/
00643         CAN->Page.TxMailbox.MDLCR |= CAN_DLC;
00644         /* Set up the data field */
00645         CAN->Page.TxMailbox.MDAR1 = CAN_Data[0];
00646         CAN->Page.TxMailbox.MDAR2 = CAN_Data[1];
00647         CAN->Page.TxMailbox.MDAR3 = CAN_Data[2];
00648         CAN->Page.TxMailbox.MDAR4 = CAN_Data[3];
00649         CAN->Page.TxMailbox.MDAR5 = CAN_Data[4];
00650         CAN->Page.TxMailbox.MDAR6 = CAN_Data[5];
00651         CAN->Page.TxMailbox.MDAR7 = CAN_Data[6];
00652         CAN->Page.TxMailbox.MDAR8 = CAN_Data[7];
00653         /* Request transmission */
00654         CAN->Page.TxMailbox.MCSR |= CAN_MCSR_TXRQ;
00655     }
00656     /*Restore Last Page*/
00657     CAN_SelectPage(can_page);
00658     return (CAN_TxStatus_TypeDef)CAN_TxStatus;
00659 }
00660
00661 /**
00662   * @brief  Checks the transmission of a message.
00663   * @param   TransmitMailbox: the number of the mailbox that is used for transmission, can be on of  @ref CAN_TransmitMailBox_TypeDef.
00664   * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.
00665   */
00666 CAN_TxStatus_TypeDef CAN_TransmitStatus(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
00667 {
00668     /* RQCP, TXOK and TME bits */
00669     CAN_TxStatus_TypeDef tstate = CAN_TxStatus_Failed;
00670     uint8_t tmpstate=0;
00671
00672     /* Check the parameters */
00673     assert_param(IS_CAN_TRANSMITMAILBOX_OK(CAN_TransmitMailbox));
00674
00675     switch (CAN_TransmitMailbox)
00676     {
00677     case (CAN_TransmitMailBox_0): tmpstate = (uint8_t)((CAN->TSR & (uint8_t)(CAN_TSR_RQCP0|CAN_TSR_TXOK0)));
00678         tmpstate |= (uint8_t)((CAN->TPR & CAN_TPR_TME0));
00679         break;
00680     case (CAN_TransmitMailBox_1): tmpstate = (uint8_t)((uint8_t)(CAN->TSR & (uint8_t)(CAN_TSR_RQCP1|CAN_TSR_TXOK1))>>1);
00681         tmpstate |= (uint8_t)((uint8_t)(CAN->TPR & CAN_TPR_TME1) >> 1);
00682         break;
00683     case (CAN_TransmitMailBox_2): tmpstate = (uint8_t)((uint8_t)(CAN->TSR & (uint8_t)(CAN_TSR_RQCP2|CAN_TSR_TXOK2))>>2);
00684         tmpstate |= (uint8_t)((uint8_t)(CAN->TPR & CAN_TPR_TME2) >> 2);
00685         break;
00686     default:
00687         tstate = CAN_TxStatus_Failed;
00688         break;
00689     }
00690
00691     switch (tmpstate)
00692     {
00693         /*transmit pending  */
00694     case (0x00): tstate = CAN_TxStatus_Pending;
00695         break;
00696         /* transmit failed  */
00697     case (0x05): tstate = CAN_TxStatus_Failed;
00698         break;
00699         /* transmit succeeded */
00700     case (0x15): tstate = CAN_TxStatus_Ok;
00701         break;
00702         /* transmit mailbox is empty : no activity on this TX mail box */
00703     case (0x04): tstate = CAN_TxStatus_MailBoxEmpty;
00704         break;
00705     default:
00706         tstate = CAN_TxStatus_Failed;
00707         break;
00708     }
00709
00710     return (CAN_TxStatus_TypeDef)tstate;
00711 }
00712
00713 /**
00714   * @brief  Cancels a transmit request.
00715   * @param   TransmitMailbox : the Transmission mailbox, can be one of CAN_TransmitMailBox_TypeDef
00716   * @retval None
00717   */
00718 void CAN_CancelTransmit(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)
00719 {
00720     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00721     /* Check the parameters */
00722     assert_param(IS_CAN_TRANSMITMAILBOX_OK(CAN_TransmitMailbox));
00723     /*switch to the specific page */
00724     CAN->PSR = (uint8_t)CAN_TransmitMailbox;
00725     /* abort transmission */
00726     CAN->Page.TxMailbox.MCSR |= CAN_MCSR_ABRQ;
00727     /*Restore Last Page*/
00728     CAN_SelectPage(can_page);
00729 }
00730
00731 /**
00732   * @brief   Releases the CAN FIFO.
00733   * @param  None
00734   * @retval None
00735   */
00736 void CAN_FIFORelease(void)
00737 {
00738     /* Release FIFO*/
00739     CAN->RFR = CAN_RFR_RFOM; /*rc-w1*/
00740 }
00741
00742 /**
00743   * @brief  Returns the number of pending messages.
00744   * @retval Number of pending messages.
00745   */
00746 CAN_NbrPendingMessage_TypeDef CAN_MessagePending(void)
00747 {
00748     CAN_NbrPendingMessage_TypeDef msgpending = CAN_NbrPendingMessage_0;
00749     msgpending = (CAN_NbrPendingMessage_TypeDef)(CAN->RFR & CAN_RFR_FMP01);
00750     return (CAN_NbrPendingMessage_TypeDef)msgpending;
00751 }
00752
00753 /**
00754   * @brief   Receives a message which contains CAN Id, IDE, RTR
00755   * DLC, datas and FMI number.
00756   * In order to get these data, use CAN_GetReceivedId(), CAN_GetReceivedIDE(), CAN_GetReceivedRTR(),
00757   * CAN_GetReceivedDLC(), CAN_GetReceivedFMI() and CAN_GetReceivedData() functions.
00758   * @param  None
00759   * @retval None
00760   */
00761 void CAN_Receive(void)
00762 {
00763     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00764     uint32_t temp1 = 0, temp2 = 0, temp3 = 0;
00765
00766     /* select Fifo page*/
00767     CAN->PSR = CAN_Page_RxFifo;
00768
00769     /* Get the Id */
00770     _IDE = (uint8_t)(CAN->Page.RxFIFO.MIDR1 & CAN_Id_Extended);
00771     if (_IDE != CAN_Id_Standard)
00772     {
00773       temp1 = ((uint32_t)((uint32_t)CAN->Page.RxFIFO.MIDR3) << 8);
00774       temp2 = ((uint32_t)((uint32_t)CAN->Page.RxFIFO.MIDR2) << 16);
00775       temp3 = ((uint32_t)((uint32_t)CAN->Page.RxFIFO.MIDR1 & 0x1F) << 24);
00776
00777       _Id = (uint32_t)CAN_EXTID_SIZE & ((CAN->Page.RxFIFO.MIDR4) | temp1 | temp2 | temp3 );
00778     }
00779     else
00780     {
00781         temp1 = (uint16_t)((uint16_t)((uint16_t)((uint16_t)CAN->Page.RxFIFO.MIDR1 & 0x1F) << 6));
00782         temp2 = (uint16_t)((uint16_t)((uint16_t)CAN->Page.RxFIFO.MIDR2 >> 2)&0x3F);
00783
00784       _Id = (uint16_t)CAN_STDID_SIZE & (temp1 | temp2 );
00785     }
00786
00787     _RTR = (uint8_t)((uint8_t)0x20 & CAN->Page.RxFIFO.MIDR1);
00788
00789     /* Get the DLC */
00790     _DLC = (uint8_t)(CAN->Page.RxFIFO.MDLCR & (uint8_t)0x0F);
00791
00792     /* Get the FMI */
00793     _FMI = CAN->Page.RxFIFO.MFMI;
00794
00795     /* Get the data field */
00796     _Data[0] = CAN->Page.RxFIFO.MDAR1;
00797     _Data[1] = CAN->Page.RxFIFO.MDAR2;
00798     _Data[2] = CAN->Page.RxFIFO.MDAR3;
00799     _Data[3] = CAN->Page.RxFIFO.MDAR4;
00800     _Data[4] = CAN->Page.RxFIFO.MDAR5;
00801     _Data[5] = CAN->Page.RxFIFO.MDAR6;
00802     _Data[6] = CAN->Page.RxFIFO.MDAR7;
00803     _Data[7] = CAN->Page.RxFIFO.MDAR8;
00804
00805     /* Release the FIFO */
00806     CAN_FIFORelease();
00807     /*Restore Last Page*/
00808     CAN_SelectPage(can_page);
00809 }
00810
00811 /**
00812   * @brief  Gets the  CAN Id of the received message.
00813   * @param  None
00814   * @retval the received CAN message Id.
00815   * @par Required preconditions:
00816   * This function is used to get data loaded by CAN_Receive function.
00817   * Before using this function, CAN_Receive function must be called.
00818   */
00819 uint32_t CAN_GetReceivedId(void)
00820 {
00821     return (_Id);
00822 }
00823
00824 /**
00825   * @brief  Gets the  CAN IDE of the received message.
00826   * @param  None
00827   * @retval the received CAN message IDE.
00828   * @par Required preconditions:
00829   * This function is used to get data loaded by CAN_Receive function.
00830   * Before using this function, CAN_Receive function must be called.
00831   */
00832 CAN_Id_TypeDef CAN_GetReceivedIDE(void)
00833 {
00834     return (CAN_Id_TypeDef)(_IDE);
00835 }
00836
00837 /**
00838   * @brief  Gets the  CAN RTR of the received message.
00839   * @param  None
00840   * @retval the received CAN message RTR.
00841   * @par Required preconditions:
00842   * This function is used to get data loaded by CAN_Receive function.
00843   * Before using this function, CAN_Receive function must be called.
00844   */
00845 CAN_RTR_TypeDef CAN_GetReceivedRTR(void)
00846 {
00847     return (CAN_RTR_TypeDef)(_RTR);
00848 }
00849
00850 /**
00851   * @brief  Gets the  CAN DLC of the received message.
00852   * @param  None
00853   * @retval the received CAN message DLC.
00854   * @par Required preconditions:
00855   * This function is used to get data loaded by CAN_Receive function.
00856   * Before using this function, CAN_Receive function must be called.
00857   */
00858 uint8_t CAN_GetReceivedDLC(void)
00859 {
00860     return (_DLC);
00861 }
00862
00863 /**
00864   * @brief  Gets the  CAN Data of the received message.
00865   * @param   CAN_DataIndexe : number of the received Data, it can
00866   *  be an integer between 0 to 7.
00867   * @retval the received CAN message ith Data.
00868   * @par Required preconditions:
00869   * This function is used to get data loaded by CAN_Receive function.
00870   * Before using this function, CAN_Receive function must be called.
00871   */
00872 uint8_t CAN_GetReceivedData(uint8_t CAN_DataIndex)
00873 {
00874     assert_param(IS_CAN_DLC_OK(CAN_DataIndex));
00875     return (_Data[CAN_DataIndex]);
00876 }
00877
00878 /**
00879   * @brief  Gets the  CAN FMI of the received message.
00880   * @param  None
00881   * @retval the received CAN message FMI.
00882   * @par Required preconditions:
00883   * This function is used to get data loaded by CAN_Receive function.
00884   * Before using this function, CAN_Receive function must be called.
00885   */
00886 uint8_t CAN_GetReceivedFMI(void)
00887 {
00888     return (_FMI);
00889 }
00890
00891 /**
00892   * @brief  Returns the Received time stamp.
00893   * @param  None
00894   * @retval uint16_t the received  time stamp.
00895   */
00896 uint16_t CAN_GetMessageTimeStamp(void)
00897 {
00898     uint16_t timestamp = 0;
00899     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
00900
00901     /*switch to the specific page */
00902     CAN->PSR = CAN_Page_RxFifo;
00903     /* Get the Received Time stamp */
00904     timestamp = CAN->Page.RxFIFO.MTSRL;
00905     timestamp |= (uint16_t)(((uint16_t)CAN->Page.RxFIFO.MTSRH)<<8);
00906
00907     /*Restore Last Page*/
00908     CAN_SelectPage(can_page);
00909
00910     return (uint16_t)(timestamp);
00911 }
00912
00913 /**
00914   * @brief  Enters the Sleep low power mode.
00915   * @param  None
00916   * @retval  CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an other case.
00917   */
00918 CAN_Sleep_TypeDef CAN_Sleep(void)
00919 {
00920
00921     CAN_Sleep_TypeDef sleepstatus = CAN_Sleep_Failed;
00922
00923     /* Request Sleep mode */
00924     CAN->MCR = (uint8_t)((uint8_t)(CAN->MCR & (uint8_t)(~CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
00925
00926     /* Sleep mode status */
00927     if ((CAN->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
00928     {
00929         /* Sleep mode not entered */
00930         sleepstatus =  CAN_Sleep_Ok;
00931     }
00932
00933     /* At this step, sleep mode status */
00934     return (CAN_Sleep_TypeDef) sleepstatus;
00935 }
00936
00937 /**
00938   * @brief  Wakes the CAN up.
00939   * @param  None
00940   * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an other  case.
00941   */
00942 CAN_WakeUp_TypeDef CAN_WakeUp(void)
00943 {
00944     CAN_WakeUp_TypeDef wakeupstatus = CAN_WakeUp_Failed;
00945
00946     /* Wake up request */
00947     CAN->MCR &= (uint8_t)(~CAN_MCR_SLEEP);
00948
00949     /* Sleep mode status */
00950     if ((CAN->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
00951     {
00952         /* Sleep mode exited */
00953         wakeupstatus = CAN_WakeUp_Ok;
00954     }
00955
00956     /* At this step, sleep mode status */
00957     return (CAN_WakeUp_TypeDef)wakeupstatus;
00958 }
00959
00960 /**
00961   * @brief  Select the CAN Operation mode.
00962   * @param  CAN_OperatingMode CAN Operating Mode ,
00963   *         this parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
00964   * @retval the status of the requested mode which can be
00965   *         - CAN_ModeStatus_Failed    CAN failed entring the specific mode
00966   *         - CAN_ModeStatus_Success  CAN Succeed entring the specific mode
00967
00968   */
00969 CAN_ModeStatus_TypeDef CAN_OperatingModeRequest(CAN_OperatingMode_TypeDef CAN_OperatingMode)
00970 {
00971
00972     uint16_t timeout = CAN_ACKNOWLEDGE_TIMEOUT;
00973     uint8_t modestatus = 0;
00974
00975     assert_param(IS_CAN_OPERATINGMODE_OK(CAN_OperatingMode));
00976
00977     if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
00978     {
00979         /* Request initialisation */
00980         CAN->MCR = (uint8_t)((uint8_t)(CAN->MCR & (uint8_t)(~CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
00981
00982         /* Wait the acknowledge */
00983         while (((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
00984         {
00985             timeout--;
00986         }
00987         if ((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
00988         {
00989           modestatus = CAN_ModeStatus_Failed;
00990         }
00991         else
00992         {
00993           modestatus = CAN_ModeStatus_Success;
00994         }
00995
00996     }
00997     else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
00998     {
00999         /* Request leave initialisation and sleep mode  and enter Normal mode */
01000         CAN->MCR &= (uint8_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
01001
01002         /* Wait the acknowledge */
01003         while (((CAN->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
01004         {
01005             timeout--;
01006         }
01007         if ((CAN->MSR & CAN_MODE_MASK) != 0)
01008         {
01009           modestatus = CAN_ModeStatus_Failed;
01010         }
01011         else
01012         {
01013           modestatus = CAN_ModeStatus_Success;
01014         }
01015     }
01016     else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
01017     {
01018         /* Request Sleep mode */
01019         CAN->MCR = (uint8_t)((uint8_t)(CAN->MCR & (uint8_t)(~CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
01020
01021         /* Wait the acknowledge */
01022         while (((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
01023         {
01024             timeout--;
01025         }
01026         if ((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
01027         {
01028            modestatus = CAN_ModeStatus_Failed;
01029         }
01030         else
01031         {
01032            modestatus = CAN_ModeStatus_Success;
01033         }
01034     }
01035     else
01036     {
01037          modestatus = CAN_ModeStatus_Failed;
01038     }
01039   return (CAN_ModeStatus_TypeDef)(modestatus);
01040 }
01041
01042 /**
01043   * @brief  Gets the  Last Error Code.
01044   * @param  None
01045   * @retval Error Code.
01046   */
01047 CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(void)
01048 {
01049     CAN_ErrorCode_TypeDef errcode = CAN_ErrorCode_NoErr;
01050     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
01051
01052     CAN->PSR = CAN_Page_Config;
01053     errcode = (CAN_ErrorCode_TypeDef)((CAN->Page.Config.ESR) & (CAN_ESR_LEC));
01054
01055     /*Restore Last Page*/
01056     CAN_SelectPage(can_page);
01057
01058     return (CAN_ErrorCode_TypeDef)(errcode);
01059 }
01060
01061 /**
01062   * @brief  Clears the CAN's pending flags.
01063   * @param   CAN_FLAG : Flag to be cleared, can be one of the following parameters:
01064   *          CAN_FLAG_RQCP0            Request MailBox0  Flag
01065   *          CAN_FLAG_RQCP1            Request MailBox1  Flag
01066   *          CAN_FLAG_RQCP2            Request MailBox2  Flag
01067   *       CAN_FLAG_FF               FIFO Full  Flag
01068   *       CAN_FLAG_FOV              FIFO Overrun  Flag
01069   *       CAN_FLAG_WKU              wake up   Flag
01070   *          CAN_FLAG_LEC               Last error code Flag
01071   * @retval None
01072   */
01073 void CAN_ClearFlag(CAN_FLAG_TypeDef CAN_Flag)
01074 {
01075     CAN_Page_TypeDef can_page = (CAN_Page_TypeDef)0;
01076     /* Check the parameters */
01077     assert_param(IS_CAN_FLAG_CLEAR_OK(CAN_Flag));
01078     if (((uint16_t)CAN_Flag & 0x0700)!= RESET)
01079     {
01080         if (((uint16_t)CAN_Flag & 0x020B)!= RESET)
01081         {
01082             /*Receive Flags*/
01083             CAN->RFR = (uint8_t)(CAN_Flag);
01084         }
01085         else if (((uint16_t)CAN_Flag & 0x0403)!= RESET)
01086         {
01087             /*Transmit Flags*/
01088             CAN->TSR = (uint8_t)(CAN_Flag);
01089         }
01090         else /*if((CAN_Flag & 0x0108)!=(uint16_t)RESET)*/
01091         {
01092             /*wake up Flags*/
01093             CAN->MSR = (uint8_t)(CAN_Flag);
01094         }
01095     }
01096     else
01097     {
01098         /*Error Flags*/
01099         can_page = CAN_GetSelectedPage();
01100
01101         /* Clear the selected CAN flags */
01102         CAN->PSR = CAN_Page_Config;
01103         CAN->Page.Config.ESR = (uint8_t)RESET;
01104
01105         /*Restore Last Page*/
01106         CAN_SelectPage(can_page);
01107     }
01108 }
01109
01110 /**
01111   * @brief  Checks whether the specified CAN flag is set or not.
01112   * @param   CAN_FLAG: specifies the flag to check, can be one of @ref CAN_FLAG_TypeDef enumeration.
01113   * @retval The new state of CAN_FLAG which can be one of @ref FlagStatus.
01114   */
01115 FlagStatus CAN_GetFlagStatus(CAN_FLAG_TypeDef CAN_Flag)
01116 {
01117     FlagStatus bitstatus = RESET;
01118     CAN_Page_TypeDef can_page = (CAN_Page_TypeDef)0;
01119
01120     /* Check the parameters */
01121     assert_param(IS_CAN_FLAG_STATUS_OK(CAN_Flag));
01122
01123     if (((uint16_t)CAN_Flag & 0x0700)!= RESET)
01124     {
01125         if (((uint16_t)CAN_Flag & 0x020B)!= RESET)
01126         {
01127             /*Receive Flags*/
01128             if ((CAN->RFR & (uint16_t)CAN_Flag )!= RESET)
01129             {
01130                 /* CAN_FLAG is set */
01131                 bitstatus = SET;
01132             }
01133             else
01134             {
01135                 /* CAN_FLAG is reset */
01136                 bitstatus = RESET;
01137             }
01138
01139         }
01140         else if (((uint16_t)CAN_Flag & 0x0403)!= RESET)
01141         {
01142             /*Transmit Flags*/
01143             if ((CAN->TSR & (uint16_t)CAN_Flag )!= RESET)
01144             {
01145                 /* CAN_FLAG is set */
01146                 bitstatus = SET;
01147             }
01148             else
01149             {
01150                 /* CAN_FLAG is reset */
01151                 bitstatus = RESET;
01152             }
01153         }
01154         else /*if((CAN_Flag & 0x0108)!=(uint16_t)RESET)*/
01155         {
01156             /*wake up Flags*/
01157             if ((CAN->MSR & (uint16_t)CAN_Flag )!= RESET)
01158             {
01159                 /* CAN_FLAG is set */
01160                 bitstatus = SET;
01161             }
01162             else
01163             {
01164                 /* CAN_FLAG is reset */
01165                 bitstatus = RESET;
01166             }
01167         }
01168     }
01169     else
01170     {
01171         /*Error Flags*/
01172         can_page = CAN_GetSelectedPage();
01173
01174         CAN->PSR = CAN_Page_Config;
01175         if ((CAN->Page.Config.ESR & (uint16_t)CAN_Flag) != RESET)
01176         {
01177             /* CAN_FLAG is set */
01178             bitstatus = SET;
01179         }
01180         else
01181         {
01182             /* CAN_FLAG is reset */
01183             bitstatus = RESET;
01184         }
01185         /*Restore Last Page*/
01186         CAN_SelectPage(can_page);
01187     }
01188
01189
01190     /* Return the CAN_FLAG status */
01191     return  (FlagStatus)bitstatus;
01192 }
01193
01194 /**
01195   * @brief  Checks whether the specified CAN interrupt has occurred or not.
01196   * @param   CAN_IT: specifies the CAN interrupt source to check, can be one of @ref CAN_IT_TypeDef.
01197   * @retval The new state of CAN_IT, which can be one of @ref ITStatus.
01198   */
01199 ITStatus CAN_GetITStatus(CAN_IT_TypeDef CAN_IT)
01200 {
01201     ITStatus pendingbitstatus = RESET;
01202     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
01203
01204     /* Check the parameters */
01205     assert_param(IS_CAN_IT_STATUS_OK(CAN_IT));
01206
01207
01208     switch (CAN_IT)
01209     {
01210     case CAN_IT_TME:
01211         if ((CAN->IER & CAN_IER_TMEIE) !=RESET)
01212         {
01213             pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP012);
01214         }
01215         else
01216         {
01217             pendingbitstatus = RESET;
01218         }
01219         break;
01220
01221     case CAN_IT_FMP:
01222         if ((CAN->IER & CAN_IER_FMPIE) !=RESET)
01223         {
01224             pendingbitstatus = CheckITStatus(CAN->RFR, CAN_RFR_FMP01);
01225         }
01226         else
01227         {
01228             pendingbitstatus = RESET;
01229         }
01230         break;
01231     case CAN_IT_FF:
01232         if ((CAN->IER & CAN_IER_FFIE) !=RESET)
01233         {
01234             pendingbitstatus = CheckITStatus(CAN->RFR, CAN_RFR_FULL);
01235         }
01236         else
01237         {
01238             pendingbitstatus = RESET;
01239         }
01240         break;
01241     case CAN_IT_FOV:
01242         if ((CAN->IER & CAN_IER_FOVIE) !=RESET)
01243         {
01244             pendingbitstatus = CheckITStatus(CAN->RFR, CAN_RFR_FOVR);
01245         }
01246         else
01247         {
01248             pendingbitstatus = RESET;
01249         }
01250         break;
01251     case CAN_IT_WKU:
01252         if ((CAN->IER & CAN_IER_WKUIE) !=RESET)
01253         {
01254             pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_WKUI);
01255         }
01256         else
01257         {
01258             pendingbitstatus = RESET;
01259         }
01260         break;
01261
01262     case CAN_IT_ERR:
01263         CAN->PSR = CAN_Page_Config;
01264         if ((CAN->Page.Config.EIER & CAN_EIER_ERRIE) !=RESET)
01265         {
01266             pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC);
01267         }
01268         else
01269         {
01270             pendingbitstatus = RESET;
01271         }
01272         break;
01273
01274     case CAN_IT_EWG:
01275         CAN->PSR = CAN_Page_Config;
01276         if ((CAN->Page.Config.EIER & CAN_EIER_EWGIE) !=RESET)
01277         {
01278             pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_EWGF);
01279         }
01280         else
01281         {
01282             pendingbitstatus = RESET;
01283         }
01284         break;
01285
01286     case CAN_IT_EPV:
01287         CAN->PSR = CAN_Page_Config;
01288         if ((CAN->Page.Config.EIER & CAN_EIER_EPVIE) !=RESET)
01289         {
01290             pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_EPVF);
01291         }
01292         else
01293         {
01294             pendingbitstatus = RESET;
01295         }
01296         break;
01297     case CAN_IT_BOF:
01298         CAN->PSR = CAN_Page_Config;
01299         if ((CAN->Page.Config.EIER & CAN_EIER_BOFIE) !=RESET)
01300         {
01301             pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_BOFF);
01302         }
01303         else
01304         {
01305             pendingbitstatus = RESET;
01306         }
01307         break;
01308     case CAN_IT_LEC:
01309         CAN->PSR = CAN_Page_Config;
01310         if ((CAN->Page.Config.EIER & CAN_EIER_LECIE) !=RESET)
01311         {
01312             pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_LEC);
01313         }
01314         else
01315         {
01316             pendingbitstatus = RESET;
01317         }
01318         break;
01319     default :
01320         pendingbitstatus = RESET;
01321         break;
01322     }
01323     /*Restore Last Page*/
01324     CAN_SelectPage(can_page);
01325     /* Return the CAN_IT status */
01326     return  (ITStatus)pendingbitstatus;
01327 }
01328
01329 /**
01330   * @brief   Clears the CAN’s interrupt pending bits.
01331   * @param   CAN_IT: specifies the interrupt pending bit to clear,
01332   *  can be one of the following parameters:
01333   *                            CAN_IT_TME = Transmit mailbox empty interrupt
01334   *                             CAN_IT_FF =FIFO  full    interrupt
01335   *                            CAN_IT_FOV =FIFO  overrun  interrupt
01336   *                             CAN_IT_WKU =Wake-up interrupt
01337   *                             CAN_IT_ERR =General Error interrupt
01338   *                             CAN_IT_EWG =Error warning interrupt
01339   *                             CAN_IT_EPV  =Error passive  interrupt
01340   *                             CAN_IT_BOF = Bus-off   interrupt
01341   *                             CAN_IT_LEC  =Last error code interrupt
01342   * @retval None
01343   */
01344 void CAN_ClearITPendingBit(CAN_IT_TypeDef CAN_IT)
01345 {
01346     CAN_Page_TypeDef can_page = CAN_GetSelectedPage();
01347     /* Check the parameters */
01348     assert_param(IS_CAN_IT_PENDING_BIT_OK(CAN_IT));
01349
01350     switch (CAN_IT)
01351     {
01352     case CAN_IT_TME:
01353         CAN->TSR = CAN_TSR_RQCP012;/* rc_w1*/
01354         break;
01355
01356     case CAN_IT_FF:
01357         CAN->RFR = CAN_RFR_FULL; /* rc_w1*/
01358         break;
01359
01360     case CAN_IT_FOV:
01361         CAN->RFR = CAN_RFR_FOVR; /* rc_w1*/
01362         break;
01363
01364     case CAN_IT_WKU:
01365         CAN->MSR = CAN_MSR_WKUI;  /* rc_w1*/
01366         break;
01367
01368     case CAN_IT_ERR:
01369         CAN->PSR = CAN_Page_Config;
01370         CAN->Page.Config.ESR = (uint8_t)CAN_ESR_RESET_VALUE;
01371         CAN->MSR = CAN_MSR_ERRI;
01372         break;
01373
01374     case CAN_IT_EWG:
01375         CAN->MSR = CAN_MSR_ERRI;
01376         break;
01377
01378     case CAN_IT_EPV:
01379         CAN->MSR = CAN_MSR_ERRI;
01380         break;
01381
01382     case CAN_IT_BOF:
01383         CAN->MSR = CAN_MSR_ERRI;
01384         break;
01385
01386     case CAN_IT_LEC:
01387         CAN->PSR = CAN_Page_Config;
01388         CAN->Page.Config.ESR = (uint8_t)CAN_ESR_RESET_VALUE;
01389         break;
01390
01391
01392
01393     default :
01394         break;
01395     }
01396     /*Restore Last Page*/
01397     CAN_SelectPage(can_page);
01398 }
01399
01400 /**
01401   * @brief  Gets the selected registers page.
01402   * @param  None
01403   * @retval the selected page which can be one of the @ref CAN_Page_TypeDef.
01404   */
01405 CAN_Page_TypeDef CAN_GetSelectedPage(void)
01406 {
01407     return (CAN_Page_TypeDef)(CAN->PSR);
01408 }
01409
01410 /**
01411   * @brief  Sets the registers page to be selected.
01412   * @param   the selected page which can be one of the @ref CAN_Page_TypeDef.
01413   * @retval None
01414   */
01415 void CAN_SelectPage(CAN_Page_TypeDef CAN_Page)
01416 {
01417     CAN->PSR = (uint8_t)CAN_Page;
01418 }
01419
01420 /**
01421   * @brief  Checks whether the CAN interrupt has occurred or not.
01422   * @param   CAN_Reg: specifies the CAN interrupt register to check.
01423   * @param   It_Bit: specifies the interrupt source bit to check.
01424   * @retval The new state of the CAN Interrupt, which can be one of ITStatus.
01425   */
01426 static ITStatus CheckITStatus(uint8_t CAN_Reg, uint8_t It_Bit)
01427 {
01428     ITStatus pendingbitstatus = RESET;
01429     if ((CAN_Reg & It_Bit) != (uint8_t)RESET)
01430     {
01431         /* CAN_IT is set */
01432         pendingbitstatus = SET;
01433     }
01434     else
01435     {
01436         /* CAN_IT is reset */
01437         pendingbitstatus = RESET;
01438     }
01439     return (ITStatus)pendingbitstatus;
01440 }
01441 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_can.h Source File

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stm8s_can.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_can.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the CAN peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_CAN_H
00024 #define __STM8S_CAN_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /* Exported constants --------------------------------------------------------*/
00030 #define CAN_STDID_SIZE ((uint16_t)0x07FF)
00031 #define CAN_EXTID_SIZE ((uint32_t)0x1FFFFFFF)
00032 #define CAN_DLC_MAX ((uint8_t)0x08)
00033
00034
00035 /** @addtogroup CAN_Exported_Types
00036   * @{
00037   */
00038
00039
00040 /**
00041   * @brief  CAN Page Mapping
00042  */
00043 typedef enum
00044 {
00045  CAN_Page_TxMailBox0  = ((uint8_t) 0), /*!< CAN TX mailbox 0 reg page */
00046  CAN_Page_TxMailBox1  = ((uint8_t) 1), /*!< CAN TX mailbox 1 reg page */
00047  CAN_Page_TxMailBox2  = ((uint8_t) 5), /*!< CAN TX mailbox 2 reg page */
00048  CAN_Page_Filter01    = ((uint8_t) 2), /*!< CAN Filters 0 & 1 reg page*/
00049  CAN_Page_Filter23    = ((uint8_t) 3), /*!< CAN Filters 2 & 3 reg page*/
00050  CAN_Page_Filter45    = ((uint8_t) 4), /*!< CAN Filters 4 & 5 reg page*/
00051  CAN_Page_Config      = ((uint8_t) 6), /*!< CAN Configuration control/status reg page*/
00052  CAN_Page_RxFifo      = ((uint8_t) 7) /*!< CAN RX FIFO registers page */
00053 }CAN_Page_TypeDef;
00054
00055
00056
00057 /**
00058   * @brief   CAN sleep constants
00059  */
00060 typedef enum {
00061   CAN_InitStatus_Failed =0,                        /*!< CAN initialization failed */
00062   CAN_InitStatus_Success =! CAN_InitStatus_Failed  /*!< CAN initialization OK*/
00063 } CAN_InitStatus_TypeDef;
00064
00065
00066  /**
00067   * @brief  CAN operating mode */
00068  typedef enum
00069 {
00070   CAN_OperatingMode_Initialization    =((uint8_t)0x00),    /*!< Initialization mode */
00071   CAN_OperatingMode_Normal            =((uint8_t)0x01),    /*!< Normal mode */
00072   CAN_OperatingMode_Sleep             =((uint8_t)0x02)    /*!< sleep mode */
00073 }CAN_OperatingMode_TypeDef;
00074
00075  /**
00076   * @brief  CAN operating mode status */
00077  typedef enum
00078 {
00079   CAN_ModeStatus_Failed    = ((uint8_t)0x00),          /*!< CAN entring the specific mode failed */
00080   CAN_ModeStatus_Success    =! CAN_ModeStatus_Failed   /*!< CAN entring the specific mode Succeed */
00081 }CAN_ModeStatus_TypeDef;
00082
00083  /**
00084   * @brief   CAN Time Triggered Communication mode
00085   */
00086 typedef enum
00087 {
00088  CAN_MasterCtrl_AllDisabled          =((uint8_t)0x00),  /*!<  CAN  ALL Master Control Option are DISABLED */
00089  CAN_MasterCtrl_AllEnabled           =((uint8_t)0xFC),  /*!<  CAN  ALL Master Control Option are DISABLED */
00090  CAN_MasterCtrl_TimeTriggerCOMMode   =((uint8_t)0x80),  /*!<  CAN Time Triggered Communication mode ENABLED */
00091  CAN_MasterCtrl_AutoBusOffManagement =((uint8_t)0x40),  /*!<  CAN Auto Bus Off Management ENABLED */
00092  CAN_MasterCtrl_AutoWakeUpMode       =((uint8_t)0x20),  /*!<  CAN Automatic WakeUp Mode ENABLED , sleep mode is left automatically by hardware  */
00093  CAN_MasterCtrl_NoAutoReTx           =((uint8_t)0x10),  /*!<  CAN Non Automatic Retransmission ENABLED, MSG  will be transmitted only once */
00094  CAN_MasterCtrl_RxFifoLockedMode     =((uint8_t)0x08),  /*!<  CAN Recieve FIFO Locked  against overrun ENABLED */
00095  CAN_MasterCtrl_TxFifoPriority       =((uint8_t)0x04)   /*!<  CAN Transmit FIFO Priority  driven by the request order (not by the identifier of the MSG) */
00096  }CAN_MasterCtrl_TypeDef;
00097
00098 /**
00099   * @brief   CAN  mode options */
00100 typedef enum
00101 {
00102   CAN_Mode_Normal             =((uint8_t)0x00),  /*!< normal mode */
00103   CAN_Mode_LoopBack           =((uint8_t)0x01),  /*!< loopback mode */
00104   CAN_Mode_Silent             =((uint8_t)0x02),  /*!< silent mode */
00105   CAN_Mode_Silent_LoopBack    =((uint8_t)0x03)  /*!< loopback combined with silent mode */
00106 }CAN_Mode_TypeDef;
00107
00108 /**
00109   * @brief  CAN synchronisation jump width (SJW)*/
00110 typedef enum
00111 {
00112   CAN_SynJumpWidth_1TimeQuantum                 =((uint8_t)0x00),  /*!< 1 time quantum */
00113   CAN_SynJumpWidth_2TimeQuantum                 =((uint8_t)0x40),  /*!< 2 time quantum */
00114   CAN_SynJumpWidth_3TimeQuantum                 =((uint8_t)0x80),  /*!< 3 time quantum */
00115   CAN_SynJumpWidth_4TimeQuantum                 =((uint8_t)0xC0)  /*!< 4 time quantum */
00116 }CAN_SynJumpWidth_TypeDef;
00117
00118 /**
00119   * @brief   time quantum in bit segment 1 */
00120 typedef enum
00121 {
00122   CAN_BitSeg1_1TimeQuantum                 =((uint8_t)0x00),  /*!< 1 time quantum */
00123   CAN_BitSeg1_2TimeQuantum                 =((uint8_t)0x01),  /*!< 2 time quantum */
00124   CAN_BitSeg1_3TimeQuantum                 =((uint8_t)0x02),  /*!< 3 time quantum */
00125   CAN_BitSeg1_4TimeQuantum                 =((uint8_t)0x03) , /*!< 4 time quantum */
00126   CAN_BitSeg1_5TimeQuantum                 =((uint8_t)0x04) , /*!< 5 time quantum */
00127   CAN_BitSeg1_6TimeQuantum                 =((uint8_t)0x05) , /*!< 6 time quantum */
00128   CAN_BitSeg1_7TimeQuantum                 =((uint8_t)0x06) , /*!< 7 time quantum */
00129   CAN_BitSeg1_8TimeQuantum                 =((uint8_t)0x07),  /*!< 8 time quantum */
00130   CAN_BitSeg1_9TimeQuantum                 =((uint8_t)0x08),  /*!< 9 time quantum */
00131   CAN_BitSeg1_10TimeQuantum                =((uint8_t)0x09),  /*!< 10 time quantum */
00132   CAN_BitSeg1_11TimeQuantum                =((uint8_t)0x0A),  /*!< 11 time quantum */
00133   CAN_BitSeg1_12TimeQuantum                =((uint8_t)0x0B),  /*!< 12 time quantum */
00134   CAN_BitSeg1_13TimeQuantum                =((uint8_t)0x0C),  /*!< 13 time quantum */
00135   CAN_BitSeg1_14TimeQuantum                =((uint8_t)0x0D),  /*!< 14 time quantum */
00136   CAN_BitSeg1_15TimeQuantum                =((uint8_t)0x0E),  /*!< 15 time quantum */
00137   CAN_BitSeg1_16TimeQuantum                =((uint8_t)0x0F)  /*!< 16 time quantum */
00138 }CAN_BitSeg1_TypeDef;
00139
00140 /**
00141   * @brief   time quantum in bit segment 2 */
00142 typedef enum
00143 {
00144   CAN_BitSeg2_1TimeQuantum                = ((uint8_t)0x00),  /*!< 1 time quantum */
00145   CAN_BitSeg2_2TimeQuantum                = ((uint8_t)0x10),  /*!< 2 time quantum */
00146   CAN_BitSeg2_3TimeQuantum                = ((uint8_t)0x20),  /*!< 3 time quantum */
00147   CAN_BitSeg2_4TimeQuantum                = ((uint8_t)0x30),  /*!< 4 time quantum */
00148   CAN_BitSeg2_5TimeQuantum                = ((uint8_t)0x40),  /*!< 5 time quantum */
00149   CAN_BitSeg2_6TimeQuantum                = ((uint8_t)0x50),  /*!< 6 time quantum */
00150   CAN_BitSeg2_7TimeQuantum                = ((uint8_t)0x60),  /*!< 7 time quantum */
00151   CAN_BitSeg2_8TimeQuantum                = ((uint8_t)0x70)   /*!< 8 time quantum */
00152 }CAN_BitSeg2_TypeDef;
00153
00154
00155 /**
00156   * @brief   CAN filter number */
00157 typedef enum
00158 {
00159   CAN_FilterNumber_0                = ((uint8_t)0x00),  /*!< Filter number 0 */
00160   CAN_FilterNumber_1                = ((uint8_t)0x01),  /*!< Filter number 1 */
00161   CAN_FilterNumber_2                = ((uint8_t)0x02),  /*!< Filter number 2 */
00162   CAN_FilterNumber_3                = ((uint8_t)0x03),  /*!< Filter number 3 */
00163   CAN_FilterNumber_4                = ((uint8_t)0x04),  /*!< Filter number 4 */
00164   CAN_FilterNumber_5                = ((uint8_t)0x05)   /*!< Filter number 5 */
00165 }CAN_FilterNumber_TypeDef;
00166
00167 /**
00168   * @brief   CAN filter mode */
00169 typedef enum
00170 {
00171   CAN_FilterMode_IdMask                  =  ((uint8_t)0x00),    /*!< id/mask mode */
00172   CAN_FilterMode_IdMask_IdList           =  ((uint8_t)0x10),    /*!< Id/Mask mode First and IdList mode second */
00173   CAN_FilterMode_IdList_IdMask           =  ((uint8_t)0x11),    /*!< IdList mode First and IdMask mode second */
00174   CAN_FilterMode_IdList                  =  ((uint8_t)0x01)     /*!< identifier list mode */
00175 }CAN_FilterMode_TypeDef;
00176
00177 /**
00178   * @brief   CAN filter scale */
00179 typedef enum
00180 {
00181   CAN_FilterScale_8Bit       =((uint8_t)0x00), /*!< 8-bit filter scale */
00182   CAN_FilterScale_16_8Bit    =((uint8_t)0x02), /*!< 16/8-bit filter scale */
00183   CAN_FilterScale_16Bit      =((uint8_t)0x04), /*!< 16-bit filter scale */
00184   CAN_FilterScale_32Bit      =((uint8_t)0x06)  /*!< 32-bit filter scale */
00185 }CAN_FilterScale_TypeDef;
00186
00187
00188 /**
00189   * @brief   CAN Tx mailboxes*/
00190 typedef enum
00191 {
00192  CAN_TransmitMailBox_0       = ((uint8_t) 0x00),  /*!< CAN TX mailbox 0 reg page */
00193  CAN_TransmitMailBox_1       = ((uint8_t) 0x01),  /*!< CAN TX mailbox 1 reg page */
00194  CAN_TransmitMailBox_2       = ((uint8_t) 0x05)   /*!< CAN TX mailbox 2 reg page */
00195 }CAN_TransmitMailBox_TypeDef;
00196
00197 /**
00198   * @brief   CAN Pending Messages number*/
00199 typedef enum
00200 {
00201   CAN_NbrPendingMessage_0     =  ((uint8_t)0x00),  /*!< No Msg Pending */
00202   CAN_NbrPendingMessage_1     =  ((uint8_t)0x01),  /*!< 1 Msg Pending */
00203   CAN_NbrPendingMessage_2     =  ((uint8_t)0x02),  /*!< 2 Msg Pending */
00204   CAN_NbrPendingMessage_3     =  ((uint8_t)0x03)  /*!< 3 Msg Pending */
00205 }CAN_NbrPendingMessage_TypeDef;
00206
00207 /**
00208   * @brief   CAN identifier type */
00209 typedef enum
00210 {
00211   CAN_Id_Standard                 =((uint8_t)0x00),  /*!< Standard Id */
00212   CAN_Id_Extended                 =((uint8_t)0x40)  /*!< Extended Id */
00213 }CAN_Id_TypeDef;
00214
00215 /**
00216   * @brief   CAN remote transmission request */
00217 typedef enum
00218 {
00219   CAN_RTR_Data               = ((uint8_t)0x00),  /*!< Data frame */
00220   CAN_RTR_Remote             = ((uint8_t)0x20)  /*!< Remote frame */
00221 }CAN_RTR_TypeDef;
00222
00223 /**
00224   * @brief   CAN transmit Status */
00225 typedef enum
00226 {
00227   CAN_TxStatus_Failed                 =((uint8_t)0xF0), /*!< CAN transmission failed */
00228   CAN_TxStatus_Ok                     =((uint8_t)0xF1), /*!< CAN transmission succeeded */
00229   CAN_TxStatus_Pending                =((uint8_t)0xF2), /*!< CAN transmission pending */
00230   CAN_TxStatus_NoMailBox              =((uint8_t)0xF4), /*!< CAN cell did not provide an empty mailbox */
00231   CAN_TxStatus_MailBoxEmpty           =((uint8_t)0xF5), /*!< CAN Tx mailbox is Empty */
00232   CAN_TxStatus_MailBox0Ok             =((uint8_t)0x00), /*!< CAN transmission succeeded by mail box 1*/
00233   CAN_TxStatus_MailBox1Ok             =((uint8_t)0x01), /*!< CAN transmission succeeded by mail box 2*/
00234   CAN_TxStatus_MailBox2Ok             =((uint8_t)0x05) /*!< CAN transmission succeeded by mail box 3*/
00235 }CAN_TxStatus_TypeDef;
00236
00237 /**
00238   * @brief   CAN sleep Status */
00239 typedef enum
00240 {
00241   CAN_Sleep_Failed             = ((uint8_t)0x00), /*!< CAN did not enter the sleep mode */
00242   CAN_Sleep_Ok                 = ((uint8_t)0x01) /*!< CAN entered the sleep mode */
00243 }CAN_Sleep_TypeDef;
00244 /**
00245   * @brief   CAN wake up status */
00246 typedef enum
00247 {
00248  CAN_WakeUp_Failed          =   ((uint8_t)0x00), /*!< CAN did not leave the sleep mode */
00249  CAN_WakeUp_Ok              =   ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
00250 }CAN_WakeUp_TypeDef;
00251
00252 /**
00253   * @brief   CAN flags */
00254 typedef enum
00255 {
00256   /* if the flag is 0x3XXX, it means that it can be got (CAN_GetFlagStatus) and Cleared (CAN_ClearFlag) */
00257   /* if the flag is 0x1XXX, it means that it can only be got (CAN_GetFlagStatus)  */
00258   /*Transmit Flags*/
00259   CAN_FLAG_RQCP0            =((uint16_t)0x3401), /*!< Request MailBox0  Flag */
00260   CAN_FLAG_RQCP1            =((uint16_t)0x3402), /*!< Request MailBox1  Flag */
00261   CAN_FLAG_RQCP2            =((uint16_t)0x3404), /*!< Request MailBox2  Flag */
00262   /*Receive Flags*/
00263   CAN_FLAG_FMP              =((uint16_t)0x1203), /*!< FIFO Message Pending Flag */
00264   CAN_FLAG_FF               =((uint16_t)0x3208), /*!< FIFO Full  Flag */
00265   CAN_FLAG_FOV              =((uint16_t)0x3210), /*!< FIFO Overrun  Flag */
00266   /*Wake up Flag*/
00267   CAN_FLAG_WKU              =((uint16_t)0x3108), /*!< wake up   Flag */
00268   /*Error Flags*/
00269   CAN_FLAG_EWG              =((uint16_t)0x1001), /*!< Error Warning Flag */
00270   CAN_FLAG_EPV              =((uint16_t)0x1002), /*!< Error Passive Flag */
00271   CAN_FLAG_BOF              =((uint16_t)0x1004), /*!< Bus-Off Flag */
00272   CAN_FLAG_LEC              =((uint16_t)0x3070) /*!< Last error code Flag */
00273 }CAN_FLAG_TypeDef;
00274
00275 /**
00276   * @brief   CAN interrupts */
00277 typedef enum
00278 {
00279   /*Transmit Interruption*/
00280   CAN_IT_TME                  =((uint16_t)0x0001), /*!< Transmit mailbox empty interrupt */
00281   /*Receive Interruptions*/
00282   CAN_IT_FMP                  =((uint16_t)0x0002), /*!< FIFO  message pending interrupt   */
00283   CAN_IT_FF                   =((uint16_t)0x0004), /*!< FIFO  full    interrupt                    */
00284   CAN_IT_FOV                  =((uint16_t)0x0008), /*!< FIFO  overrun  interrupt               */
00285   /*Wake Up Interruption*/
00286   CAN_IT_WKU                  =((uint16_t)0x0080), /*!< Wake-up interrupt                         */
00287   /*Error Interruptions*/
00288   CAN_IT_ERR                  =((uint16_t)0x4000), /*!< Genaral Error interrupt                 */
00289   CAN_IT_EWG                  =((uint16_t)0x0100), /*!< Error warning interrupt                */
00290   CAN_IT_EPV                  =((uint16_t)0x0200), /*!< Error passive  interrupt                */
00291   CAN_IT_BOF                  =((uint16_t)0x0400), /*!< Bus-off   interrupt                        */
00292   CAN_IT_LEC                  =((uint16_t)0x0800)  /*!< Last error code interrupt              */
00293 } CAN_IT_TypeDef;
00294
00295 /**
00296   * @brief   CAN ST7 Compatibility*/
00297 typedef enum
00298 {
00299   CAN_ST7Compatibility_Enable     =  ((uint8_t)0x00), /*!< CAN is compatible with ST7 beCAN (only 2 mailboxes are availble)*/
00300   CAN_ST7Compatibility_Disable    =  ((uint8_t)0x10)  /*!< CAN is not compatible with ST7 beCAN ( 3 mailboxes are availble)*/
00301 }CAN_ST7Compatibility_TypeDef;
00302
00303 /**
00304   * @brief   CAN Error Code description */
00305 typedef enum
00306 {
00307   CAN_ErrorCode_NoErr                 = ((uint8_t)0x00),  /*!< No Error  */
00308   CAN_ErrorCode_StuffErr              = ((uint8_t)0x10),  /*!< Stuff Error  */
00309   CAN_ErrorCode_FormErr               = ((uint8_t)0x20),  /*!< Form Error  */
00310   CAN_ErrorCode_ACKErr                = ((uint8_t)0x30),  /*!< Acknowledgment Error  */
00311   CAN_ErrorCode_BitRecessiveErr       = ((uint8_t)0x40),  /*!< Bit Recessive Error  */
00312   CAN_ErrorCode_BitDominantErr        = ((uint8_t)0x50),  /*!< Bit Dominant Error  */
00313   CAN_ErrorCode_CRCErr                = ((uint8_t)0x60),  /*!< CRC Error  */
00314   CAN_ErrorCode_SoftwareSetErr        = ((uint8_t)0x70)  /*!< Software Set Error  */
00315 }CAN_ErrorCode_TypeDef;
00316 /**
00317   * @}
00318   */
00319 /* Private macros ------------------------------------------------------------*/
00320 /** @addtogroup CAN_Private_Macros
00321   * @{
00322   */
00323 /**
00324   * @brief  Macro used by the assert function in order to check the CAN ST7 Compatibility parameters.
00325   */
00326 #define IS_CAN_ST7_COMPATIBILITY_OK(STATE) (((STATE) == CAN_ST7Compatibility_Enable) || ((STATE) == CAN_ST7Compatibility_Disable))
00327 /**
00328   * @brief  Macro used by the assert function in order to check  CAN operating mode.
00329   */
00330 #define IS_CAN_OPERATINGMODE_OK(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
00331                                     ((MODE) == CAN_OperatingMode_Normal)|| \
00332                         ((MODE) == CAN_OperatingMode_Sleep))
00333 /**
00334   * @brief  Macro used by the assert function in order to check CAN Time Triggered Communication mode.
00335   */
00336 #define IS_CAN_MASTERCTRL_OK(MODE) (((MODE) == CAN_MasterCtrl_AllDisabled) || \
00337                                     (((MODE) <= CAN_MasterCtrl_AllEnabled) && ((MODE) >= CAN_MasterCtrl_TxFifoPriority)))
00338 /**
00339   * @brief  Macro used by the assert function in order to check   CAN  mode options .
00340   */
00341 #define IS_CAN_MODE_OK(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
00342                            ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))
00343 /**
00344   * @brief  Macro used by the assert function in order to check the CAN synchronisation jump width (SJW).
00345   */
00346 #define IS_CAN_SYNJUMPWIDTH_OK(SJW) (((SJW) == CAN_SynJumpWidth_1TimeQuantum) || ((SJW) == CAN_SynJumpWidth_2TimeQuantum)|| \
00347                          ((SJW) == CAN_SynJumpWidth_3TimeQuantum) || ((SJW) == CAN_SynJumpWidth_4TimeQuantum))
00348 /**
00349   * @brief  Macro used by the assert function in order to check time quantum in bit segment 1 .
00350   */
00351 #define IS_CAN_BITSEG1_OK(BS1) ((BS1) <= CAN_BitSeg1_16TimeQuantum)
00352 /**
00353   * @brief  Macro used by the assert function in order to check time quantum in bit segment 2.
00354   */
00355 #define IS_CAN_BITSEG2_OK(BS2) ((((BS2) >= CAN_BitSeg2_2TimeQuantum) && ((BS2) <= CAN_BitSeg2_8TimeQuantum))|| ((BS2) == CAN_BitSeg2_1TimeQuantum))
00356 /**
00357   * @brief  Macro used by the assert function in order to check CAN clock prescaler.
00358   */
00359 #define IS_CAN_PRESCALER_OK(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 64))
00360 /**
00361   * @brief  Macro used by the assert function in order to check CAN filter number.
00362   */
00363 #define IS_CAN_FILTER_NUMBER_OK(NUMBER) (((NUMBER) == CAN_FilterNumber_0) || \
00364                                        ((NUMBER) == CAN_FilterNumber_1) || \
00365                                        ((NUMBER) == CAN_FilterNumber_2) || \
00366                                        ((NUMBER) == CAN_FilterNumber_3) || \
00367                                        ((NUMBER) == CAN_FilterNumber_4) || \
00368                                        ((NUMBER) == CAN_FilterNumber_5))
00369 /**
00370   * @brief  Macro used by the assert function in order to check  CAN filter mode.
00371   */
00372 #define IS_CAN_FILTER_MODE_OK(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
00373                                      ((MODE) == CAN_FilterMode_IdMask_IdList) || \
00374                                      ((MODE) == CAN_FilterMode_IdList_IdMask) || \
00375                                   ((MODE) == CAN_FilterMode_IdList))
00376 /**
00377   * @brief  Macro used by the assert function in order to check CAN filter scale.
00378   */
00379 #define IS_CAN_FILTER_SCALE_OK(SCALE) (((SCALE) == CAN_FilterScale_8Bit)|| \
00380                                     ((SCALE) == CAN_FilterScale_16_8Bit) ||\
00381                                     ((SCALE) == CAN_FilterScale_16Bit  )||\
00382                                     ((SCALE) == CAN_FilterScale_32Bit))
00383 /**
00384   * @brief  Macro used by the assert function in order to check CAN Tx mailboxes.
00385   */
00386 #define IS_CAN_TRANSMITMAILBOX_OK(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TransmitMailBox_0) || \
00387                                                  ((TRANSMITMAILBOX) == CAN_TransmitMailBox_1) || \
00388                                                  ((TRANSMITMAILBOX) == CAN_TransmitMailBox_2))
00389 /**
00390   * @brief  Macro used by the assert function in order to check the Standard ID to be sent.
00391   */
00392 #define IS_CAN_STDID_OK(STDID)   ((STDID) <= ((uint16_t)CAN_STDID_SIZE))
00393 /**
00394   * @brief  Macro used by the assert function in order to check the Extended ID to be sent.
00395   */
00396 #define IS_CAN_EXTID_OK(EXTID)   ((EXTID) <= ((uint32_t)CAN_EXTID_SIZE))
00397 /**
00398   * @brief  Macro used by the assert function in order to check the DLC to be sent.
00399   */
00400 #define IS_CAN_DLC_OK(DLC)       ((DLC) <= CAN_DLC_MAX)
00401 /**
00402   * @brief  Macro used by the assert function in order to check the type of the ID to be sent.
00403   */
00404 #define IS_CAN_IDTYPE_OK(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended))
00405 /**
00406   * @brief  Macro used by the assert function in order to check CAN  transmission  Frame Type.
00407   */
00408 #define IS_CAN_RTR_OK(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
00409
00410 /**
00411   * @brief  Macro used by the assert function in order to check  CAN flags which can be got by @ref CAN_GetFlagStatus
00412   */
00413 #define IS_CAN_FLAG_STATUS_OK(FLAG) (((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_RQCP1) ||\
00414                                   ((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_FMP) ||\
00415                                   ((FLAG) == CAN_FLAG_FF) || ((FLAG) == CAN_FLAG_FOV) ||\
00416                                   ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_EWG) ||\
00417                                   ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_BOF) ||\
00418                                   ((FLAG) == CAN_FLAG_LEC))
00419 /**
00420   * @brief  Macro used by the assert function in order to check  CAN flags which can be cleared by @ref CAN_ClearFlag
00421   */
00422 #define IS_CAN_FLAG_CLEAR_OK(FLAG) (((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_RQCP1) ||\
00423                                     ((FLAG) == CAN_FLAG_RQCP2) ||  ((FLAG) == CAN_FLAG_FF)   ||\
00424                                     ((FLAG) == CAN_FLAG_FOV)  ||  ((FLAG) == CAN_FLAG_WKU) ||\
00425                                     ((FLAG) == CAN_FLAG_LEC))
00426 /**
00427   * @brief  Macro used by the assert function in order to check the  CAN Configuration interrupts.
00428   */
00429 #define CAN_IT_CONFIG_MASK  ~(uint16_t)(CAN_IT_TME|CAN_IT_FMP|CAN_IT_FF|CAN_IT_FOV|CAN_IT_WKU|CAN_IT_EWG|CAN_IT_EPV|CAN_IT_BOF|CAN_IT_LEC|CAN_IT_ERR)
00430 #define IS_CAN_IT_CONFIG_OK(IT) (((IT) != 0x0000) && ((uint16_t)((uint16_t)(IT) & (uint16_t)CAN_IT_CONFIG_MASK) == 0x0000))
00431 /**
00432   * @brief  Macro used by the assert function in order to check the  CAN status interrupts.
00433   */
00434 #define IS_CAN_IT_STATUS_OK(IT) (((IT) == CAN_IT_TME)   || ((IT) == CAN_IT_FMP) ||\
00435                              ((IT) == CAN_IT_FF)    || ((IT) == CAN_IT_FOV) || \
00436                              ((IT) == CAN_IT_WKU)   || ((IT) == CAN_IT_ERR)  || \
00437                              ((IT) == CAN_IT_EWG)   || ((IT) == CAN_IT_EPV)  || \
00438                              ((IT) == CAN_IT_BOF)   || ((IT) == CAN_IT_LEC)  )
00439 /**
00440   * @brief  Macro used by the assert function in order to check the  CAN Pending bit interrupts.
00441   */
00442 #define IS_CAN_IT_PENDING_BIT_OK(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF)  ||\
00443                                       ((IT) == CAN_IT_FOV)  || ((IT) == CAN_IT_WKU) ||\
00444                                       ((IT) == CAN_IT_ERR)  || ((IT) == CAN_IT_EWG) ||\
00445                                       ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)||\
00446                                       ((IT) == CAN_IT_LEC))
00447 /**
00448   * @brief  Macro used by the assert function in order to check the Last Error Code.
00449   */
00450 #define IS_CAN_LAST_ERROR_CODE_OK(CODE)  (((CODE) & 0x8F) == 0x00)
00451 /**
00452   * @}
00453   */
00454
00455 /* Exported function protypes ----------------------------------------------- */
00456 /** @addtogroup CAN_Exported_Functions
00457   * @{
00458   */
00459 void CAN_DeInit(void);
00460 CAN_InitStatus_TypeDef CAN_Init(CAN_MasterCtrl_TypeDef CAN_MasterCtrl,
00461                                 CAN_Mode_TypeDef CAN_Mode,
00462                                 CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth,
00463                                 CAN_BitSeg1_TypeDef CAN_BitSeg1,
00464                                 CAN_BitSeg2_TypeDef CAN_BitSeg2,
00465                                 uint8_t CAN_Prescaler);
00466
00467 void CAN_FilterInit(CAN_FilterNumber_TypeDef CAN_FilterNumber,
00468                     FunctionalState CAN_FilterActivation,
00469                     CAN_FilterMode_TypeDef CAN_FilterMode,
00470                     CAN_FilterScale_TypeDef CAN_FilterScale,
00471                     uint8_t CAN_FilterID1,
00472                     uint8_t CAN_FilterID2,
00473                     uint8_t CAN_FilterID3,
00474                      uint8_t CAN_FilterID4,
00475                     uint8_t CAN_FilterIDMask1,
00476                      uint8_t CAN_FilterIDMask2,
00477                     uint8_t CAN_FilterIDMask3,
00478                     uint8_t CAN_FilterIDMask4);
00479 void CAN_ITConfig(CAN_IT_TypeDef CAN_IT, FunctionalState NewState);
00480 void CAN_ST7CompatibilityCmd(CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility);
00481 CAN_TxStatus_TypeDef CAN_Transmit( uint32_t CAN_Id,
00482                                    CAN_Id_TypeDef CAN_IDE,
00483                                    CAN_RTR_TypeDef CAN_RTR,
00484                                    uint8_t CAN_DLC,
00485                                    uint8_t *CAN_Data);
00486 void CAN_TTComModeCmd(FunctionalState NewState);
00487 CAN_TxStatus_TypeDef CAN_TransmitStatus(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox);
00488 void CAN_CancelTransmit(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox);
00489 void CAN_FIFORelease(void);
00490 CAN_NbrPendingMessage_TypeDef CAN_MessagePending(void);
00491 void CAN_Receive(void);
00492 uint32_t CAN_GetReceivedId(void);
00493 CAN_Id_TypeDef CAN_GetReceivedIDE(void);
00494 CAN_RTR_TypeDef CAN_GetReceivedRTR(void);
00495 uint8_t CAN_GetReceivedDLC(void);
00496 uint8_t CAN_GetReceivedData(uint8_t CAN_DataIndex);
00497 uint8_t CAN_GetReceivedFMI(void);
00498 uint16_t CAN_GetMessageTimeStamp(void);
00499 CAN_Sleep_TypeDef CAN_Sleep(void);
00500 CAN_WakeUp_TypeDef CAN_WakeUp(void);
00501 CAN_ModeStatus_TypeDef CAN_OperatingModeRequest(CAN_OperatingMode_TypeDef CAN_OperatingMode);
00502 CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(void);
00503 CAN_Page_TypeDef CAN_GetSelectedPage(void);
00504 void CAN_SelectPage(CAN_Page_TypeDef CAN_Page);
00505 FlagStatus CAN_GetFlagStatus(CAN_FLAG_TypeDef CAN_Flag);
00506 void CAN_ClearFlag(CAN_FLAG_TypeDef CAN_Flag);
00507 ITStatus CAN_GetITStatus(CAN_IT_TypeDef CAN_IT);
00508 void CAN_ClearITPendingBit(CAN_IT_TypeDef CAN_IT);
00509 /**
00510   * @}
00511   */
00512 #endif /* __STM8S_CAN_H */
00513
00514 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_clk.c Source File

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stm8s_clk.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_clk.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the CLK peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023
00024 #include "stm8s_clk.h"
00025
00026 /** @addtogroup STM8S_StdPeriph_Driver
00027   * @{
00028   */
00029 /* Private typedef -----------------------------------------------------------*/
00030 /* Private define ------------------------------------------------------------*/
00031 /* Private macro -------------------------------------------------------------*/
00032 /* Private variables ---------------------------------------------------------*/
00033 /* Private function prototypes -----------------------------------------------*/
00034
00035 /* Private Constants ---------------------------------------------------------*/
00036
00037 /**
00038   * @addtogroup CLK_Private_Constants
00039   * @{
00040   */
00041
00042 CONST uint8_t HSIDivFactor[4] = {1, 2, 4, 8}; /*!< Holds the different HSI Divider factors */
00043 CONST uint8_t CLKPrescTable[8] = {1, 2, 4, 8, 10, 16, 20, 40}; /*!< Holds the different CLK prescaler values */
00044
00045 /**
00046   * @}
00047   */
00048
00049 /* Public functions ----------------------------------------------------------*/
00050 /**
00051   * @addtogroup CLK_Public_Functions
00052   * @{
00053   */
00054
00055 /**
00056   * @brief  Deinitializes the CLK peripheral registers to their default reset
00057   * values.
00058   * @param  None
00059   * @retval None
00060   * @par Warning:
00061   * Resetting the CCOR register: \n
00062   * When the CCOEN bit is set, the reset of the CCOR register require
00063   * two consecutive write instructions in order to reset first the CCOEN bit
00064   * and the second one is to reset the CCOSEL bits.
00065   */
00066 void CLK_DeInit(void)
00067 {
00068
00069     CLK->ICKR = CLK_ICKR_RESET_VALUE;
00070     CLK->ECKR = CLK_ECKR_RESET_VALUE;
00071     CLK->SWR  = CLK_SWR_RESET_VALUE;
00072     CLK->SWCR = CLK_SWCR_RESET_VALUE;
00073     CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
00074     CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
00075     CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
00076     CLK->CSSR = CLK_CSSR_RESET_VALUE;
00077     CLK->CCOR = CLK_CCOR_RESET_VALUE;
00078     while ((CLK->CCOR & CLK_CCOR_CCOEN)!= 0)
00079     {}
00080     CLK->CCOR = CLK_CCOR_RESET_VALUE;
00081     CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
00082     CLK->SWIMCCR = CLK_SWIMCCR_RESET_VALUE;
00083
00084 }
00085
00086 /**
00087   * @brief   Configures the High Speed Internal oscillator (HSI).
00088   * @par Full description:
00089   * If CLK_FastHaltWakeup is enabled, HSI oscillator is automatically
00090   * switched-on (HSIEN=1) and selected as next clock master
00091   * (CKM=SWI=HSI) when resuming from HALT/ActiveHalt modes.\n
00092   * @param   NewState this parameter is the Wake-up Mode state.
00093   * @retval None
00094   */
00095 void CLK_FastHaltWakeUpCmd(FunctionalState NewState)
00096 {
00097
00098     /* check the parameters */
00099     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00100
00101     if (NewState != DISABLE)
00102     {
00103         /* Set FHWU bit (HSI oscillator is automatically switched-on) */
00104         CLK->ICKR |= CLK_ICKR_FHWU;
00105     }
00106     else  /* FastHaltWakeup = DISABLE */
00107     {
00108         /* Reset FHWU bit */
00109         CLK->ICKR &= (uint8_t)(~CLK_ICKR_FHWU);
00110     }
00111
00112 }
00113
00114 /**
00115   * @brief  Enable or Disable the External High Speed oscillator (HSE).
00116   * @param   NewState new state of HSEEN, value accepted ENABLE, DISABLE.
00117   * @retval None
00118   */
00119 void CLK_HSECmd(FunctionalState NewState)
00120 {
00121
00122     /* Check the parameters */
00123     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00124
00125     if (NewState != DISABLE)
00126     {
00127         /* Set HSEEN bit */
00128         CLK->ECKR |= CLK_ECKR_HSEEN;
00129     }
00130     else
00131     {
00132         /* Reset HSEEN bit */
00133         CLK->ECKR &= (uint8_t)(~CLK_ECKR_HSEEN);
00134     }
00135
00136 }
00137
00138 /**
00139   * @brief  Enables or disables the Internal High Speed oscillator (HSI).
00140   * @param   NewState new state of HSIEN, value accepted ENABLE, DISABLE.
00141   * @retval None
00142   */
00143 void CLK_HSICmd(FunctionalState NewState)
00144 {
00145
00146     /* Check the parameters */
00147     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00148
00149     if (NewState != DISABLE)
00150     {
00151         /* Set HSIEN bit */
00152         CLK->ICKR |= CLK_ICKR_HSIEN;
00153     }
00154     else
00155     {
00156         /* Reset HSIEN bit */
00157         CLK->ICKR &= (uint8_t)(~CLK_ICKR_HSIEN);
00158     }
00159
00160 }
00161
00162 /**
00163   * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
00164   * @param    NewState new state of LSIEN, value accepted ENABLE, DISABLE.
00165   * @retval None
00166   */
00167 void CLK_LSICmd(FunctionalState NewState)
00168 {
00169
00170     /* Check the parameters */
00171     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00172
00173     if (NewState != DISABLE)
00174     {
00175         /* Set LSIEN bit */
00176         CLK->ICKR |= CLK_ICKR_LSIEN;
00177     }
00178     else
00179     {
00180         /* Reset LSIEN bit */
00181         CLK->ICKR &= (uint8_t)(~CLK_ICKR_LSIEN);
00182     }
00183
00184 }
00185
00186 /**
00187   * @brief  Enables or disablle the Configurable Clock Output (CCO).
00188   * @param   NewState : New state of CCEN bit (CCO register).
00189   * This parameter can be any of the @ref FunctionalState enumeration.
00190   * @retval None
00191   */
00192 void CLK_CCOCmd(FunctionalState NewState)
00193 {
00194
00195     /* Check the parameters */
00196     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00197
00198     if (NewState != DISABLE)
00199     {
00200         /* Set CCOEN bit */
00201         CLK->CCOR |= CLK_CCOR_CCOEN;
00202     }
00203     else
00204     {
00205         /* Reset CCOEN bit */
00206         CLK->CCOR &= (uint8_t)(~CLK_CCOR_CCOEN);
00207     }
00208
00209 }
00210
00211 /**
00212   * @brief  Starts or Stops manually the clock switch execution.
00213   * @par Full description:
00214   * NewState parameter set the SWEN.
00215   * @param   NewState new state of SWEN, value accepted ENABLE, DISABLE.
00216   * @retval None
00217   */
00218 void CLK_ClockSwitchCmd(FunctionalState NewState)
00219 {
00220
00221     /* Check the parameters */
00222     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00223
00224     if (NewState != DISABLE )
00225     {
00226         /* Enable the Clock Switch */
00227         CLK->SWCR |= CLK_SWCR_SWEN;
00228     }
00229     else
00230     {
00231         /* Disable the Clock Switch */
00232         CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN);
00233     }
00234
00235 }
00236
00237 /**
00238   * @brief  Configures the slow active halt wake up
00239   * @param   NewState: specifies the Slow Active Halt wake up state.
00240   * can be set of the following values:
00241   * - DISABLE: Slow Active Halt mode disabled;
00242   * - ENABLE:  Slow Active Halt mode enabled.
00243   * @retval None
00244   */
00245 void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState)
00246 {
00247
00248     /* check the parameters */
00249     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00250
00251     if (NewState != DISABLE)
00252     {
00253         /* Set S_ACTHALT bit */
00254         CLK->ICKR |= CLK_ICKR_SWUAH;
00255     }
00256     else
00257     {
00258         /* Reset S_ACTHALT bit */
00259         CLK->ICKR &= (uint8_t)(~CLK_ICKR_SWUAH);
00260     }
00261
00262 }
00263
00264 /**
00265   * @brief   Enables or disables the specified peripheral CLK.
00266   * @param   CLK_Peripheral : This parameter specifies the peripheral clock to gate.
00267   * This parameter can be any of the  @ref CLK_Peripheral_TypeDef enumeration.
00268   * @param   NewState : New state of specified peripheral clock.
00269   * This parameter can be any of the @ref FunctionalState enumeration.
00270   * @retval None
00271   */
00272 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
00273 {
00274
00275     /* Check the parameters */
00276     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00277     assert_param(IS_CLK_PERIPHERAL_OK(CLK_Peripheral));
00278
00279     if (((uint8_t)CLK_Peripheral & (uint8_t)0x10) == 0x00)
00280     {
00281         if (NewState != DISABLE)
00282         {
00283             /* Enable the peripheral Clock */
00284             CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
00285         }
00286         else
00287         {
00288             /* Disable the peripheral Clock */
00289             CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
00290         }
00291     }
00292     else
00293     {
00294         if (NewState != DISABLE)
00295         {
00296             /* Enable the peripheral Clock */
00297             CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
00298         }
00299         else
00300         {
00301             /* Disable the peripheral Clock */
00302             CLK->PCKENR2 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
00303         }
00304     }
00305
00306 }
00307
00308 /**
00309   * @brief  configures the Switch from one clock to another
00310   * @param   CLK_SwitchMode select the clock switch mode.
00311   * It can be set of the values of @ref CLK_SwitchMode_TypeDef
00312   * @param   CLK_NewClock choice of the future clock.
00313   * It can be set of the values of @ref CLK_Source_TypeDef
00314   * @param   NewState Enable or Disable the Clock Switch interrupt.
00315   * @param   CLK_CurrentClockState current clock to switch OFF or to keep ON.
00316   * It can be set of the values of @ref CLK_CurrentClockState_TypeDef
00317   * @retval ErrorStatus this shows the clock switch status (ERROR/SUCCESS).
00318   */
00319 ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
00320 {
00321
00322     CLK_Source_TypeDef clock_master;
00323     uint16_t DownCounter = CLK_TIMEOUT;
00324     ErrorStatus Swif = ERROR;
00325
00326     /* Check the parameters */
00327     assert_param(IS_CLK_SOURCE_OK(CLK_NewClock));
00328     assert_param(IS_CLK_SWITCHMODE_OK(CLK_SwitchMode));
00329     assert_param(IS_FUNCTIONALSTATE_OK(ITState));
00330     assert_param(IS_CLK_CURRENTCLOCKSTATE_OK(CLK_CurrentClockState));
00331
00332     /* Current clock master saving */
00333     clock_master = (CLK_Source_TypeDef)CLK->CMSR;
00334
00335     /* Automatic switch mode management */
00336     if (CLK_SwitchMode == CLK_SWITCHMODE_AUTO)
00337     {
00338
00339         /* Enables Clock switch */
00340         CLK->SWCR |= CLK_SWCR_SWEN;
00341
00342         /* Enables or Disables Switch interrupt */
00343         if (ITState != DISABLE)
00344         {
00345             CLK->SWCR |= CLK_SWCR_SWIEN;
00346         }
00347         else
00348         {
00349             CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);
00350         }
00351
00352         /* Selection of the target clock source */
00353         CLK->SWR = (uint8_t)CLK_NewClock;
00354
00355         while ((((CLK->SWCR & CLK_SWCR_SWBSY) != 0 )&& (DownCounter != 0)))
00356         {
00357             DownCounter--;
00358         }
00359
00360         if (DownCounter != 0)
00361         {
00362             Swif = SUCCESS;
00363         }
00364         else
00365         {
00366             Swif = ERROR;
00367         }
00368
00369     }
00370     else /* CLK_SwitchMode == CLK_SWITCHMODE_MANUAL */
00371     {
00372
00373         /* Enables or Disables Switch interrupt  if required  */
00374         if (ITState != DISABLE)
00375         {
00376             CLK->SWCR |= CLK_SWCR_SWIEN;
00377         }
00378         else
00379         {
00380             CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);
00381         }
00382
00383         /* Selection of the target clock source */
00384         CLK->SWR = (uint8_t)CLK_NewClock;
00385
00386         /* In manual mode, there is no risk to be stuck in a loop, value returned
00387           is then always SUCCESS */
00388         Swif = SUCCESS;
00389
00390     }
00391
00392     /* Switch OFF current clock if required */
00393     if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSI))
00394     {
00395         CLK->ICKR &= (uint8_t)(~CLK_ICKR_HSIEN);
00396     }
00397     else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_LSI))
00398     {
00399         CLK->ICKR &= (uint8_t)(~CLK_ICKR_LSIEN);
00400     }
00401     else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSE))
00402     {
00403         CLK->ECKR &= (uint8_t)(~CLK_ECKR_HSEEN);
00404     }
00405
00406     return(Swif);
00407
00408 }
00409
00410 /**
00411   * @brief  Configures the HSI clock dividers.
00412   * @param   HSIPrescaler : Specifies the HSI clock divider to apply.
00413   * This parameter can be any of the @ref CLK_Prescaler_TypeDef enumeration.
00414   * @retval None
00415   */
00416 void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler)
00417 {
00418
00419     /* check the parameters */
00420     assert_param(IS_CLK_HSIPRESCALER_OK(HSIPrescaler));
00421
00422     /* Clear High speed internal clock prescaler */
00423     CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_HSIDIV);
00424
00425     /* Set High speed internal clock prescaler */
00426     CLK->CKDIVR |= (uint8_t)HSIPrescaler;
00427
00428 }
00429
00430 /**
00431   * @brief  Output the selected clock on a dedicated I/O pin.
00432   * @param   CLK_CCO : Specifies the clock source.
00433   * This parameter can be any of the  @ref CLK_Output_TypeDef enumeration.
00434   * @retval None
00435   * @par Required preconditions:
00436   * The dedicated I/O pin must be set at 1 in the corresponding Px_CR1 register \n
00437   * to be set as input with pull-up or push-pull output.
00438   */
00439 void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO)
00440 {
00441
00442     /* check the parameters */
00443     assert_param(IS_CLK_OUTPUT_OK(CLK_CCO));
00444
00445     /* Clears of the CCO type bits part */
00446     CLK->CCOR &= (uint8_t)(~CLK_CCOR_CCOSEL);
00447
00448     /* Selects the source provided on cco_ck output */
00449     CLK->CCOR |= (uint8_t)CLK_CCO;
00450
00451     /* Enable the clock output */
00452     CLK->CCOR |= CLK_CCOR_CCOEN;
00453
00454 }
00455
00456 /**
00457   * @brief   Enables or disables the specified CLK interrupts.
00458   * @param   CLK_IT This parameter specifies the interrupt sources.
00459   * It can be one of the values of @ref CLK_IT_TypeDef.
00460   * @param   NewState New state of the Interrupt.
00461   * Value accepted ENABLE, DISABLE.
00462   * @retval None
00463   */
00464 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
00465 {
00466
00467     /* check the parameters */
00468     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00469     assert_param(IS_CLK_IT_OK(CLK_IT));
00470
00471     if (NewState != DISABLE)
00472     {
00473         switch (CLK_IT)
00474         {
00475         case CLK_IT_SWIF: /* Enable the clock switch interrupt */
00476             CLK->SWCR |= CLK_SWCR_SWIEN;
00477             break;
00478         case CLK_IT_CSSD: /* Enable the clock security system detection interrupt */
00479             CLK->CSSR |= CLK_CSSR_CSSDIE;
00480             break;
00481         default:
00482             break;
00483         }
00484     }
00485     else  /*(NewState == DISABLE)*/
00486     {
00487         switch (CLK_IT)
00488         {
00489         case CLK_IT_SWIF: /* Disable the clock switch interrupt */
00490             CLK->SWCR  &= (uint8_t)(~CLK_SWCR_SWIEN);
00491             break;
00492         case CLK_IT_CSSD: /* Disable the clock security system detection interrupt */
00493             CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDIE);
00494             break;
00495         default:
00496             break;
00497         }
00498     }
00499
00500 }
00501
00502 /**
00503   * @brief  Configures the HSI and CPU clock dividers.
00504   * @param   ClockPrescaler Specifies the HSI or CPU clock divider to apply.
00505   * @retval None
00506   */
00507 void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef CLK_Prescaler)
00508 {
00509
00510     /* check the parameters */
00511     assert_param(IS_CLK_PRESCALER_OK(CLK_Prescaler));
00512
00513     if (((uint8_t)CLK_Prescaler & (uint8_t)0x80) == 0x00) /* Bit7 = 0 means HSI divider */
00514     {
00515         CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_HSIDIV);
00516         CLK->CKDIVR |= (uint8_t)((uint8_t)CLK_Prescaler & (uint8_t)CLK_CKDIVR_HSIDIV);
00517     }
00518     else /* Bit7 = 1 means CPU divider */
00519     {
00520         CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_CPUDIV);
00521         CLK->CKDIVR |= (uint8_t)((uint8_t)CLK_Prescaler & (uint8_t)CLK_CKDIVR_CPUDIV);
00522     }
00523
00524 }
00525 /**
00526   * @brief  Configures the SWIM clock frequency on the fly.
00527   * @param   CLK_SWIMDivider Specifies the SWIM clock divider to apply.
00528   * can be one of the value of @ref CLK_SWIMDivider_TypeDef
00529   * @retval None
00530   */
00531 void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
00532 {
00533
00534     /* check the parameters */
00535     assert_param(IS_CLK_SWIMDIVIDER_OK(CLK_SWIMDivider));
00536
00537     if (CLK_SWIMDivider != CLK_SWIMDIVIDER_2)
00538     {
00539         /* SWIM clock is not divided by 2 */
00540         CLK->SWIMCCR |= CLK_SWIMCCR_SWIMDIV;
00541     }
00542     else /* CLK_SWIMDivider == CLK_SWIMDIVIDER_2 */
00543     {
00544         /* SWIM clock is divided by 2 */
00545         CLK->SWIMCCR &= (uint8_t)(~CLK_SWIMCCR_SWIMDIV);
00546     }
00547
00548 }
00549
00550 /**
00551   * @brief  Enables the Clock Security System.
00552   * @par Full description:
00553   * once CSS is enabled it cannot be disabled until the next reset.
00554   * @param  None
00555   * @retval None
00556   */
00557 void CLK_ClockSecuritySystemEnable(void)
00558 {
00559     /* Set CSSEN bit */
00560     CLK->CSSR |= CLK_CSSR_CSSEN;
00561 }
00562
00563 /**
00564   * @brief  Returns the clock source used as system clock.
00565   * @param  None
00566   * @retval  Clock source used.
00567   * can be one of the values of @ref CLK_Source_TypeDef
00568   */
00569 CLK_Source_TypeDef CLK_GetSYSCLKSource(void)
00570 {
00571     return((CLK_Source_TypeDef)CLK->CMSR);
00572 }
00573
00574 /**
00575   * @brief  This function returns the frequencies of different on chip clocks.
00576   * @param  None
00577   * @retval the master clock frequency
00578   */
00579 uint32_t CLK_GetClockFreq(void)
00580 {
00581
00582     uint32_t clockfrequency = 0;
00583     CLK_Source_TypeDef clocksource = CLK_SOURCE_HSI;
00584     uint8_t tmp = 0, presc = 0;
00585
00586     /* Get CLK source. */
00587     clocksource = (CLK_Source_TypeDef)CLK->CMSR;
00588
00589     if (clocksource == CLK_SOURCE_HSI)
00590     {
00591         tmp = (uint8_t)(CLK->CKDIVR & CLK_CKDIVR_HSIDIV);
00592         tmp = (uint8_t)(tmp >> 3);
00593         presc = HSIDivFactor[tmp];
00594         clockfrequency = HSI_VALUE / presc;
00595     }
00596     else if ( clocksource == CLK_SOURCE_LSI)
00597     {
00598         clockfrequency = LSI_VALUE;
00599     }
00600     else
00601     {
00602         clockfrequency = HSE_VALUE;
00603     }
00604
00605     return((uint32_t)clockfrequency);
00606
00607 }
00608
00609 /**
00610   * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
00611   * @par Full description:
00612   * @param   CLK_HSICalibrationValue calibration trimming value.
00613   * can be one of the values of @ref CLK_HSITrimValue_TypeDef
00614   * @retval None
00615   */
00616 void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
00617 {
00618
00619     /* check the parameters */
00620     assert_param(IS_CLK_HSITRIMVALUE_OK(CLK_HSICalibrationValue));
00621
00622     /* Store the new value */
00623     CLK->HSITRIMR = (uint8_t)( (uint8_t)(CLK->HSITRIMR & (uint8_t)(~CLK_HSITRIMR_HSITRIM))|((uint8_t)CLK_HSICalibrationValue));
00624
00625 }
00626
00627 /**
00628   * @brief  Reset the SWBSY flag (SWICR Reister)
00629   * @par Full description:
00630   * This function reset SWBSY flag in order to reset clock switch operations (target
00631   * oscillator is broken, stabilization is longing too much, etc.).  If at the same time \n
00632   * software attempts to set SWEN and clear SWBSY, SWBSY action takes precedence.
00633   * @param  None
00634   * @retval None
00635   */
00636 void CLK_SYSCLKEmergencyClear(void)
00637 {
00638     CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWBSY);
00639 }
00640
00641 /**
00642   * @brief  Checks whether the specified CLK flag is set or not.
00643   * @par Full description:
00644   * @param   CLK_FLAG Flag to check.
00645   * can be one of the values of @ref CLK_Flag_TypeDef
00646   * @retval FlagStatus, status of the checked flag
00647   */
00648 FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG)
00649 {
00650
00651     uint16_t statusreg = 0;
00652     uint8_t tmpreg = 0;
00653     FlagStatus bitstatus = RESET;
00654
00655     /* check the parameters */
00656     assert_param(IS_CLK_FLAG_OK(CLK_FLAG));
00657
00658     /* Get the CLK register index */
00659     statusreg = (uint16_t)((uint16_t)CLK_FLAG & (uint16_t)0xFF00);
00660
00661
00662     if (statusreg == 0x0100) /* The flag to check is in ICKRregister */
00663     {
00664         tmpreg = CLK->ICKR;
00665     }
00666     else if (statusreg == 0x0200) /* The flag to check is in ECKRregister */
00667     {
00668         tmpreg = CLK->ECKR;
00669     }
00670     else if (statusreg == 0x0300) /* The flag to check is in SWIC register */
00671     {
00672         tmpreg = CLK->SWCR;
00673     }
00674     else if (statusreg == 0x0400) /* The flag to check is in CSS register */
00675     {
00676         tmpreg = CLK->CSSR;
00677     }
00678     else /* The flag to check is in CCO register */
00679     {
00680         tmpreg = CLK->CCOR;
00681     }
00682
00683     if ((tmpreg & (uint8_t)CLK_FLAG) != (uint8_t)RESET)
00684     {
00685         bitstatus = SET;
00686     }
00687     else
00688     {
00689         bitstatus = RESET;
00690     }
00691
00692     /* Return the flag status */
00693     return((FlagStatus)bitstatus);
00694
00695 }
00696
00697 /**
00698   * @brief  Checks whether the specified CLK interrupt has is enabled or not.
00699   * @param   CLK_IT specifies the CLK interrupt.
00700   * can be one of the values of @ref CLK_IT_TypeDef
00701   * @retval ITStatus, new state of CLK_IT (SET or RESET).
00702   */
00703 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
00704 {
00705
00706     ITStatus bitstatus = RESET;
00707
00708     /* check the parameters */
00709     assert_param(IS_CLK_IT_OK(CLK_IT));
00710
00711     if (CLK_IT == CLK_IT_SWIF)
00712     {
00713         /* Check the status of the clock switch interrupt */
00714         if ((CLK->SWCR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
00715         {
00716             bitstatus = SET;
00717         }
00718         else
00719         {
00720             bitstatus = RESET;
00721         }
00722     }
00723     else /* CLK_IT == CLK_IT_CSSDIE */
00724     {
00725         /* Check the status of the security system detection interrupt */
00726         if ((CLK->CSSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
00727         {
00728             bitstatus = SET;
00729         }
00730         else
00731         {
00732             bitstatus = RESET;
00733         }
00734     }
00735
00736     /* Return the CLK_IT status */
00737     return bitstatus;
00738
00739 }
00740
00741 /**
00742   * @brief  Clears the CLK’s interrupt pending bits.
00743   * @param   CLK_IT specifies the interrupt pending bits.
00744   * can be one of the values of @ref CLK_IT_TypeDef
00745   * @retval None
00746   */
00747 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
00748 {
00749
00750     /* check the parameters */
00751     assert_param(IS_CLK_IT_OK(CLK_IT));
00752
00753     if (CLK_IT == (uint8_t)CLK_IT_CSSD)
00754     {
00755         /* Clear the status of the security system detection interrupt */
00756         CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSD);
00757     }
00758     else /* CLK_PendingBit == (uint8_t)CLK_IT_SWIF */
00759     {
00760         /* Clear the status of the clock switch interrupt */
00761         CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIF);
00762     }
00763
00764 }
00765 /**
00766   * @}
00767   */
00768
00769 /**
00770   * @}
00771   */
00772
00773 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_clk.h Source File

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stm8s_clk.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_clk.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the CLK peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM8S_CLK_H
00025 #define __STM8S_CLK_H
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 /* Contains the description of all STM8 hardware registers */
00029 #include "stm8s.h"
00030
00031 /* Exported types ------------------------------------------------------------*/
00032 /** @addtogroup CLK_Exported_Types
00033   * @{
00034   */
00035
00036 /**
00037    * @brief  Switch Mode Auto, Manual.
00038    */
00039 typedef enum {
00040   CLK_SWITCHMODE_MANUAL = (uint8_t)0x00, /*!< Enable the manual clock switching mode */
00041   CLK_SWITCHMODE_AUTO   = (uint8_t)0x01  /*!< Enable the automatic clock switching mode */
00042 } CLK_SwitchMode_TypeDef;
00043
00044 /**
00045    * @brief  Current Clock State.
00046    */
00047 typedef enum {
00048   CLK_CURRENTCLOCKSTATE_DISABLE = (uint8_t)0x00, /*!< Current clock disable */
00049   CLK_CURRENTCLOCKSTATE_ENABLE  = (uint8_t)0x01  /*!< Current clock enable */
00050 } CLK_CurrentClockState_TypeDef;
00051
00052 /**
00053    * @brief   Clock security system configuration.
00054    */
00055 typedef enum {
00056   CLK_CSSCONFIG_ENABLEWITHIT = (uint8_t)0x05, /*!< Enable CSS with detection interrupt */
00057   CLK_CSSCONFIG_ENABLE    = (uint8_t)0x01, /*!< Enable CSS without detection interrupt */
00058   CLK_CSSCONFIG_DISABLE      = (uint8_t)0x00  /*!< Leave CSS desactivated (to be used in CLK_Init() function) */
00059 } CLK_CSSConfig_TypeDef;
00060
00061 /**
00062    * @brief   CLK Clock Source.
00063    */
00064 typedef enum {
00065   CLK_SOURCE_HSI    = (uint8_t)0xE1, /*!< Clock Source HSI. */
00066   CLK_SOURCE_LSI    = (uint8_t)0xD2, /*!< Clock Source LSI. */
00067   CLK_SOURCE_HSE    = (uint8_t)0xB4 /*!< Clock Source HSE. */
00068 } CLK_Source_TypeDef;
00069
00070 /**
00071    * @brief   CLK HSI Calibration Value.
00072    */
00073 typedef enum {
00074   CLK_HSITRIMVALUE_0   = (uint8_t)0x00, /*!< HSI Calibtation Value 0 */
00075   CLK_HSITRIMVALUE_1   = (uint8_t)0x01, /*!< HSI Calibtation Value 1 */
00076   CLK_HSITRIMVALUE_2   = (uint8_t)0x02, /*!< HSI Calibtation Value 2 */
00077   CLK_HSITRIMVALUE_3   = (uint8_t)0x03, /*!< HSI Calibtation Value 3 */
00078   CLK_HSITRIMVALUE_4   = (uint8_t)0x04, /*!< HSI Calibtation Value 4 */
00079   CLK_HSITRIMVALUE_5   = (uint8_t)0x05, /*!< HSI Calibtation Value 5 */
00080   CLK_HSITRIMVALUE_6   = (uint8_t)0x06, /*!< HSI Calibtation Value 6 */
00081   CLK_HSITRIMVALUE_7   = (uint8_t)0x07  /*!< HSI Calibtation Value 7 */
00082 } CLK_HSITrimValue_TypeDef;
00083
00084 /**
00085    * @brief    CLK  Clock Output
00086    */
00087 typedef enum {
00088   CLK_OUTPUT_HSI      = (uint8_t)0x00, /*!< Clock Output HSI */
00089   CLK_OUTPUT_LSI      = (uint8_t)0x02, /*!< Clock Output LSI */
00090   CLK_OUTPUT_HSE      = (uint8_t)0x04, /*!< Clock Output HSE */
00091   CLK_OUTPUT_CPU      = (uint8_t)0x08, /*!< Clock Output CPU */
00092   CLK_OUTPUT_CPUDIV2  = (uint8_t)0x0A, /*!< Clock Output CPU/2 */
00093   CLK_OUTPUT_CPUDIV4  = (uint8_t)0x0C, /*!< Clock Output CPU/4 */
00094   CLK_OUTPUT_CPUDIV8  = (uint8_t)0x0E, /*!< Clock Output CPU/8 */
00095   CLK_OUTPUT_CPUDIV16 = (uint8_t)0x10, /*!< Clock Output CPU/16 */
00096   CLK_OUTPUT_CPUDIV32 = (uint8_t)0x12, /*!< Clock Output CPU/32 */
00097   CLK_OUTPUT_CPUDIV64 = (uint8_t)0x14, /*!< Clock Output CPU/64 */
00098   CLK_OUTPUT_HSIRC    = (uint8_t)0x16, /*!< Clock Output HSI RC */
00099   CLK_OUTPUT_MASTER   = (uint8_t)0x18, /*!< Clock Output Master */
00100   CLK_OUTPUT_OTHERS   = (uint8_t)0x1A  /*!< Clock Output OTHER */
00101 } CLK_Output_TypeDef;
00102
00103 /**
00104    * @brief    CLK Enable peripheral
00105    */
00106 /* Elements values convention: 0xXY
00107     X = choice between the peripheral registers
00108         X = 0 : PCKENR1
00109         X = 1 : PCKENR2
00110     Y = Peripheral position in the register
00111 */
00112 typedef enum {
00113   CLK_PERIPHERAL_I2C     = (uint8_t)0x00, /*!< Peripheral Clock Enable 1, I2C */
00114   CLK_PERIPHERAL_SPI     = (uint8_t)0x01, /*!< Peripheral Clock Enable 1, SPI */
00115 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || defined(STM8AF62Ax)
00116   CLK_PERIPHERAL_UART1   = (uint8_t)0x02, /*!< Peripheral Clock Enable 1, UART1 */
00117 #else
00118   CLK_PERIPHERAL_UART1   = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, UART1 */
00119 #endif
00120   CLK_PERIPHERAL_UART2   = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, UART2 */
00121   CLK_PERIPHERAL_UART3   = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, UART3 */
00122   CLK_PERIPHERAL_TIMER6  = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, Timer6 */
00123   CLK_PERIPHERAL_TIMER4  = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, Timer4 */
00124   CLK_PERIPHERAL_TIMER5  = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, Timer5 */
00125   CLK_PERIPHERAL_TIMER2  = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, Timer2 */
00126   CLK_PERIPHERAL_TIMER3  = (uint8_t)0x06, /*!< Peripheral Clock Enable 1, Timer3 */
00127   CLK_PERIPHERAL_TIMER1  = (uint8_t)0x07, /*!< Peripheral Clock Enable 1, Timer1 */
00128   CLK_PERIPHERAL_AWU     = (uint8_t)0x12, /*!< Peripheral Clock Enable 2, AWU */
00129   CLK_PERIPHERAL_ADC     = (uint8_t)0x13, /*!< Peripheral Clock Enable 2, ADC */
00130   CLK_PERIPHERAL_CAN     = (uint8_t)0x17 /*!< Peripheral Clock Enable 2, CAN */
00131 } CLK_Peripheral_TypeDef;
00132
00133 /**
00134    * @brief   CLK Flags.
00135    */
00136 /* Elements values convention: 0xXZZ
00137     X = choice between the flags registers
00138         X = 1 : ICKR
00139         X = 2 : ECKR
00140         X = 3 : SWCR
00141     X = 4 : CSSR
00142  X = 5 : CCOR
00143    ZZ = flag mask in the register (same as map file)
00144 */
00145 typedef enum {
00146   CLK_FLAG_LSIRDY  = (uint16_t)0x0110, /*!< Low speed internal oscillator ready Flag */
00147   CLK_FLAG_HSIRDY  = (uint16_t)0x0102, /*!< High speed internal oscillator ready Flag */
00148   CLK_FLAG_HSERDY  = (uint16_t)0x0202, /*!< High speed external oscillator ready Flag */
00149   CLK_FLAG_SWIF    = (uint16_t)0x0308, /*!< Clock switch interrupt Flag */
00150   CLK_FLAG_SWBSY   = (uint16_t)0x0301, /*!< Switch busy Flag */
00151   CLK_FLAG_CSSD    = (uint16_t)0x0408, /*!< Clock security system detection Flag */
00152   CLK_FLAG_AUX     = (uint16_t)0x0402, /*!< Auxiliary oscillator connected to master clock */
00153   CLK_FLAG_CCOBSY  = (uint16_t)0x0504, /*!< Configurable clock output busy */
00154   CLK_FLAG_CCORDY  = (uint16_t)0x0502 /*!< Configurable clock output ready */
00155
00156 }CLK_Flag_TypeDef;
00157
00158 /**
00159    * @brief  CLK interrupt configuration and Flags cleared by software.
00160    */
00161 typedef enum {
00162   CLK_IT_CSSD   = (uint8_t)0x0C, /*!< Clock security system detection Flag */
00163   CLK_IT_SWIF   = (uint8_t)0x1C /*!< Clock switch interrupt Flag */
00164 }CLK_IT_TypeDef;
00165
00166 /**
00167    * @brief   CLK Clock Divisor.
00168    */
00169 /* Warning:
00170    0xxxxxx = HSI divider
00171    1xxxxxx = CPU divider
00172    Other bits correspond to the divider's bits mapping
00173 */
00174 typedef enum {
00175   CLK_PRESCALER_HSIDIV1   = (uint8_t)0x00, /*!< High speed internal clock prescaler: 1 */
00176   CLK_PRESCALER_HSIDIV2   = (uint8_t)0x08, /*!< High speed internal clock prescaler: 2 */
00177   CLK_PRESCALER_HSIDIV4   = (uint8_t)0x10, /*!< High speed internal clock prescaler: 4 */
00178   CLK_PRESCALER_HSIDIV8   = (uint8_t)0x18, /*!< High speed internal clock prescaler: 8 */
00179   CLK_PRESCALER_CPUDIV1   = (uint8_t)0x80, /*!< CPU clock division factors 1 */
00180   CLK_PRESCALER_CPUDIV2   = (uint8_t)0x81, /*!< CPU clock division factors 2 */
00181   CLK_PRESCALER_CPUDIV4   = (uint8_t)0x82, /*!< CPU clock division factors 4 */
00182   CLK_PRESCALER_CPUDIV8   = (uint8_t)0x83, /*!< CPU clock division factors 8 */
00183   CLK_PRESCALER_CPUDIV16  = (uint8_t)0x84, /*!< CPU clock division factors 16 */
00184   CLK_PRESCALER_CPUDIV32  = (uint8_t)0x85, /*!< CPU clock division factors 32 */
00185   CLK_PRESCALER_CPUDIV64  = (uint8_t)0x86, /*!< CPU clock division factors 64 */
00186   CLK_PRESCALER_CPUDIV128 = (uint8_t)0x87  /*!< CPU clock division factors 128 */
00187 } CLK_Prescaler_TypeDef;
00188
00189 /**
00190    * @brief   SWIM Clock divider.
00191    */
00192 typedef enum {
00193   CLK_SWIMDIVIDER_2 = (uint8_t)0x00, /*!< SWIM clock is divided by 2 */
00194   CLK_SWIMDIVIDER_OTHER = (uint8_t)0x01 /*!< SWIM clock is not divided by 2 */
00195 }CLK_SWIMDivider_TypeDef;
00196
00197 /**
00198   * @}
00199   */
00200
00201 /* Exported constants --------------------------------------------------------*/
00202
00203 /** @addtogroup CLK_Exported_Constants
00204   * @{
00205   */
00206 #define CLK_TIMEOUT ((uint16_t)0x491)    /*!< Timeout for the clock switch operation. */
00207 /**
00208   * @}
00209   */
00210
00211 /* Private macros ------------------------------------------------------------*/
00212 /** @addtogroup CLK_Private_Macros
00213   * @{
00214   */
00215
00216 /**
00217   * @brief  Macros used by the assert function in order to check the different functions parameters.
00218   */
00219
00220 /**
00221   * @brief  Macros used by the assert function in order to check the clock switching modes.
00222   */
00223 #define IS_CLK_SWITCHMODE_OK(MODE) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO))
00224
00225 /**
00226   * @brief  Macros used by the assert function in order to check the current clock state.
00227   */
00228 #define IS_CLK_CURRENTCLOCKSTATE_OK(STATE) (((STATE) == CLK_CURRENTCLOCKSTATE_DISABLE) ||\
00229                                             ((STATE) == CLK_CURRENTCLOCKSTATE_ENABLE))
00230
00231 /**
00232   * @brief  Macros used by the assert function in order to check the CSS configuration.
00233   */
00234 #define IS_CLK_CSSCONFIG_OK(CSSVALUE) (((CSSVALUE) == CLK_CSSCONFIG_ENABLEWITHIT) ||\
00235                                        ((CSSVALUE) == CLK_CSSCONFIG_ENABLE) ||\
00236                                        ((CSSVALUE) == CLK_CSSCONFIG_DISABLE))
00237
00238 /**
00239   * @brief  Macros used by the assert function in order to check the different clock sources.
00240   */
00241 #define IS_CLK_SOURCE_OK(SOURCE) (((SOURCE) == CLK_SOURCE_HSI) ||\
00242                                   ((SOURCE) == CLK_SOURCE_LSI) ||\
00243                                   ((SOURCE) == CLK_SOURCE_HSE))
00244
00245 /**
00246   * @brief  Macros used by the assert function in order to check the different HSI trimming values.
00247   */
00248 #define IS_CLK_HSITRIMVALUE_OK(TRIMVALUE) (((TRIMVALUE) == CLK_HSITRIMVALUE_0) ||\
00249     ((TRIMVALUE) == CLK_HSITRIMVALUE_1) ||\
00250     ((TRIMVALUE) == CLK_HSITRIMVALUE_2) ||\
00251     ((TRIMVALUE) == CLK_HSITRIMVALUE_3) ||\
00252     ((TRIMVALUE) == CLK_HSITRIMVALUE_4) ||\
00253     ((TRIMVALUE) == CLK_HSITRIMVALUE_5) ||\
00254     ((TRIMVALUE) == CLK_HSITRIMVALUE_6) ||\
00255     ((TRIMVALUE) == CLK_HSITRIMVALUE_7))
00256
00257 /**
00258   * @brief  Macros used by the assert function in order to check the different clocks to output.
00259   */
00260 #define IS_CLK_OUTPUT_OK(OUTPUT) (((OUTPUT) == CLK_OUTPUT_HSI) ||\
00261                                   ((OUTPUT) == CLK_OUTPUT_HSE) ||\
00262                                   ((OUTPUT) == CLK_OUTPUT_LSI) ||\
00263                                   ((OUTPUT) == CLK_OUTPUT_CPU) ||\
00264                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV2) ||\
00265                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV4) ||\
00266                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV8) ||\
00267                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV16) ||\
00268                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV32) ||\
00269                                   ((OUTPUT) == CLK_OUTPUT_CPUDIV64) ||\
00270                                   ((OUTPUT) == CLK_OUTPUT_HSIRC) ||\
00271                                   ((OUTPUT) == CLK_OUTPUT_MASTER) ||\
00272                                   ((OUTPUT) == CLK_OUTPUT_OTHERS))
00273
00274 /**
00275   * @brief  Macros used by the assert function in order to check the different peripheral's clock.
00276   */
00277 #define IS_CLK_PERIPHERAL_OK(PERIPHERAL) (((PERIPHERAL) == CLK_PERIPHERAL_I2C) ||\
00278     ((PERIPHERAL) == CLK_PERIPHERAL_SPI) ||\
00279     ((PERIPHERAL) == CLK_PERIPHERAL_UART3) ||\
00280     ((PERIPHERAL) == CLK_PERIPHERAL_UART2) ||\
00281     ((PERIPHERAL) == CLK_PERIPHERAL_UART1) ||\
00282     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER4) ||\
00283     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER2) ||\
00284     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER5) ||\
00285     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER6) ||\
00286     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER3) ||\
00287     ((PERIPHERAL) == CLK_PERIPHERAL_TIMER1) ||\
00288     ((PERIPHERAL) == CLK_PERIPHERAL_CAN) ||\
00289     ((PERIPHERAL) == CLK_PERIPHERAL_ADC) ||\
00290     ((PERIPHERAL) == CLK_PERIPHERAL_AWU))
00291
00292 /**
00293   * @brief  Macros used by the assert function in order to check the different clock flags.
00294   */
00295 #define IS_CLK_FLAG_OK(FLAG) (((FLAG) == CLK_FLAG_LSIRDY) ||\
00296                               ((FLAG) == CLK_FLAG_HSIRDY) ||\
00297                               ((FLAG) == CLK_FLAG_HSERDY) ||\
00298                               ((FLAG) == CLK_FLAG_SWIF) ||\
00299                               ((FLAG) == CLK_FLAG_SWBSY) ||\
00300                               ((FLAG) == CLK_FLAG_CSSD) ||\
00301                               ((FLAG) == CLK_FLAG_AUX) ||\
00302                               ((FLAG) == CLK_FLAG_CCOBSY) ||\
00303                               ((FLAG) == CLK_FLAG_CCORDY))
00304
00305 /**
00306   * @brief  Macros used by the assert function in order to check the different clock IT pending bits.
00307   */
00308 #define IS_CLK_IT_OK(IT) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF))
00309
00310 /**
00311   * @brief  Macros used by the assert function in order to check the different HSI prescaler values.
00312   */
00313 #define IS_CLK_HSIPRESCALER_OK(PRESCALER) (((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\
00314     ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\
00315     ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\
00316     ((PRESCALER) == CLK_PRESCALER_HSIDIV8))
00317
00318 /**
00319   * @brief  Macros used by the assert function in order to check the different clock  prescaler values.
00320   */
00321 #define IS_CLK_PRESCALER_OK(PRESCALER) (((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\
00322                                         ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\
00323                                         ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\
00324                                         ((PRESCALER) == CLK_PRESCALER_HSIDIV8) ||\
00325                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV1) ||\
00326                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV2) ||\
00327                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV4) ||\
00328                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV8) ||\
00329                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV16) ||\
00330                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV32) ||\
00331                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV64) ||\
00332                                         ((PRESCALER) == CLK_PRESCALER_CPUDIV128))
00333
00334 /**
00335   * @brief  Macros used by the assert function in order to check the different SWIM dividers values.
00336   */
00337 #define IS_CLK_SWIMDIVIDER_OK(SWIMDIVIDER) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER))
00338
00339 /**
00340   * @}
00341   */
00342
00343 /** @addtogroup CLK_Exported_functions
00344   * @{
00345   */
00346 void CLK_DeInit(void);
00347 void CLK_HSECmd(FunctionalState NewState);
00348 void CLK_HSICmd(FunctionalState NewState);
00349 void CLK_LSICmd(FunctionalState NewState);
00350 void CLK_CCOCmd(FunctionalState NewState);
00351 void CLK_ClockSwitchCmd(FunctionalState NewState);
00352 void CLK_FastHaltWakeUpCmd(FunctionalState NewState);
00353 void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState);
00354 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState);
00355 ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState);
00356 void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler);
00357 void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO);
00358 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState);
00359 void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef CLK_Prescaler);
00360 void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider);
00361 void CLK_ClockSecuritySystemEnable(void);
00362 void CLK_SYSCLKEmergencyClear(void);
00363 void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue);
00364 uint32_t CLK_GetClockFreq(void);
00365 CLK_Source_TypeDef CLK_GetSYSCLKSource(void);
00366 FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG);
00367 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT);
00368 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT);
00369
00370 /**
00371   * @}
00372   */
00373 #endif /* __STM8S_CLK_H */
00374
00375 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_exti.c Source File

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  • STM8S_StdPeriph_Driver
  • src

stm8s_exti.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_exti.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the EXTI peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_exti.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034
00035 /* Public functions ----------------------------------------------------------*/
00036
00037 /**
00038   * @addtogroup EXTI_Public_Functions
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  Deinitializes the external interrupt control registers to their default reset value.
00044   * @param  None
00045   * @retval None
00046   */
00047 void EXTI_DeInit(void)
00048 {
00049     EXTI->CR1 = EXTI_CR1_RESET_VALUE;
00050     EXTI->CR2 = EXTI_CR2_RESET_VALUE;
00051 }
00052
00053 /**
00054   * @brief  Set the external interrupt sensitivity of the selected port.
00055   * @warning
00056   * - The modification of external interrupt sensitivity is only possible when the interrupts are disabled.
00057   * - The normal behavior is to disable the interrupts before calling this function, and re-enable them after.
00058   * @param   Port The port number to access.
00059   * @param   SensitivityValue The external interrupt sensitivity value to set.
00060   * @retval None
00061   * @par Required preconditions:
00062   * Global interrupts must be disabled before calling this function.
00063   */
00064 void EXTI_SetExtIntSensitivity(EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)
00065 {
00066
00067     /* Check function parameters */
00068     assert_param(IS_EXTI_PORT_OK(Port));
00069     assert_param(IS_EXTI_SENSITIVITY_OK(SensitivityValue));
00070
00071     /* Set external interrupt sensitivity */
00072     switch (Port)
00073     {
00074     case EXTI_PORT_GPIOA:
00075         EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PAIS);
00076         EXTI->CR1 |= (uint8_t)(SensitivityValue);
00077         break;
00078     case EXTI_PORT_GPIOB:
00079         EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PBIS);
00080         EXTI->CR1 |= (uint8_t)((uint8_t)(SensitivityValue) << 2);
00081         break;
00082     case EXTI_PORT_GPIOC:
00083         EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PCIS);
00084         EXTI->CR1 |= (uint8_t)((uint8_t)(SensitivityValue) << 4);
00085         break;
00086     case EXTI_PORT_GPIOD:
00087         EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PDIS);
00088         EXTI->CR1 |= (uint8_t)((uint8_t)(SensitivityValue) << 6);
00089         break;
00090     case EXTI_PORT_GPIOE:
00091         EXTI->CR2 &= (uint8_t)(~EXTI_CR2_PEIS);
00092         EXTI->CR2 |= (uint8_t)(SensitivityValue);
00093         break;
00094     default:
00095         break;
00096     }
00097 }
00098
00099 /**
00100   * @brief  Set the TLI interrupt sensitivity.
00101   * @param   SensitivityValue The TLI interrupt sensitivity value.
00102   * @retval None
00103   * @par Required preconditions:
00104   * Global interrupts must be disabled before calling this function.
00105   */
00106 void EXTI_SetTLISensitivity(EXTI_TLISensitivity_TypeDef SensitivityValue)
00107 {
00108     /* Check function parameters */
00109     assert_param(IS_EXTI_TLISENSITIVITY_OK(SensitivityValue));
00110
00111     /* Set TLI interrupt sensitivity */
00112     EXTI->CR2 &= (uint8_t)(~EXTI_CR2_TLIS);
00113     EXTI->CR2 |= (uint8_t)(SensitivityValue);
00114 }
00115
00116 /**
00117   * @brief  Get the external interrupt sensitivity of the selected port.
00118   * @param   Port The port number to access.
00119   * @retval EXTI_Sensitivity_TypeDef The external interrupt sensitivity of the selected port.
00120   */
00121 EXTI_Sensitivity_TypeDef EXTI_GetExtIntSensitivity(EXTI_Port_TypeDef Port)
00122 {
00123     uint8_t value = 0;
00124
00125     /* Check function parameters */
00126     assert_param(IS_EXTI_PORT_OK(Port));
00127
00128     switch (Port)
00129     {
00130     case EXTI_PORT_GPIOA:
00131         value = (uint8_t)(EXTI->CR1 & EXTI_CR1_PAIS);
00132         break;
00133     case EXTI_PORT_GPIOB:
00134         value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_PBIS) >> 2);
00135         break;
00136     case EXTI_PORT_GPIOC:
00137         value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_PCIS) >> 4);
00138         break;
00139     case EXTI_PORT_GPIOD:
00140         value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_PDIS) >> 6);
00141         break;
00142     case EXTI_PORT_GPIOE:
00143         value = (uint8_t)(EXTI->CR2 & EXTI_CR2_PEIS);
00144         break;
00145     default:
00146         break;
00147     }
00148
00149     return((EXTI_Sensitivity_TypeDef)value);
00150 }
00151
00152 /**
00153   * @brief  Get the TLI interrupt sensitivity.
00154   * @param  None
00155   * @retval EXTI_TLISensitivity_TypeDef The TLI interrupt sensitivity read.
00156   */
00157 EXTI_TLISensitivity_TypeDef EXTI_GetTLISensitivity(void)
00158 {
00159
00160     uint8_t value = 0;
00161
00162     /* Get TLI interrupt sensitivity */
00163     value = (uint8_t)(EXTI->CR2 & EXTI_CR2_TLIS);
00164
00165     return((EXTI_TLISensitivity_TypeDef)value);
00166 }
00167
00168 /**
00169   * @}
00170   */
00171
00172 /**
00173   * @}
00174   */
00175
00176 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_exti.h Source File

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  • STM8S_StdPeriph_Driver
  • inc

stm8s_exti.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_exti.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the EXTI peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_EXTI_H__
00024 #define __STM8S_EXTI_H__
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030
00031 /** @addtogroup EXTI_Exported_Types
00032   * @{
00033   */
00034
00035 /**
00036   * @brief  EXTI Sensitivity values for PORTA to PORTE
00037   */
00038 typedef enum {
00039   EXTI_SENSITIVITY_FALL_LOW  = (uint8_t)0x00, /*!< Interrupt on Falling edge and Low level */
00040   EXTI_SENSITIVITY_RISE_ONLY = (uint8_t)0x01, /*!< Interrupt on Rising edge only */
00041   EXTI_SENSITIVITY_FALL_ONLY = (uint8_t)0x02, /*!< Interrupt on Falling edge only */
00042   EXTI_SENSITIVITY_RISE_FALL = (uint8_t)0x03  /*!< Interrupt on Rising and Falling edges */
00043 } EXTI_Sensitivity_TypeDef;
00044
00045 /**
00046   * @brief  EXTI Sensitivity values for TLI
00047   */
00048 typedef enum {
00049   EXTI_TLISENSITIVITY_FALL_ONLY = (uint8_t)0x00, /*!< Top Level Interrupt on Falling edge only */
00050   EXTI_TLISENSITIVITY_RISE_ONLY = (uint8_t)0x04  /*!< Top Level Interrupt on Rising edge only */
00051 } EXTI_TLISensitivity_TypeDef;
00052
00053 /**
00054   * @brief  EXTI PortNum possible values
00055   */
00056 typedef enum {
00057   EXTI_PORT_GPIOA = (uint8_t)0x00, /*!< GPIO Port A */
00058   EXTI_PORT_GPIOB = (uint8_t)0x01, /*!< GPIO Port B */
00059   EXTI_PORT_GPIOC = (uint8_t)0x02, /*!< GPIO Port C */
00060   EXTI_PORT_GPIOD = (uint8_t)0x03, /*!< GPIO Port D */
00061   EXTI_PORT_GPIOE = (uint8_t)0x04  /*!< GPIO Port E */
00062 } EXTI_Port_TypeDef;
00063
00064 /**
00065   * @}
00066   */
00067
00068 /* Private macros ------------------------------------------------------------*/
00069
00070 /** @addtogroup EXTI_Private_Macros
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  Macro used by the assert function in order to check the different sensitivity values for PORTA to PORTE.
00076   */
00077 #define IS_EXTI_SENSITIVITY_OK(SensitivityValue) \
00078   (((SensitivityValue) == EXTI_SENSITIVITY_FALL_LOW) || \
00079    ((SensitivityValue) == EXTI_SENSITIVITY_RISE_ONLY) || \
00080    ((SensitivityValue) == EXTI_SENSITIVITY_FALL_ONLY) || \
00081    ((SensitivityValue) == EXTI_SENSITIVITY_RISE_FALL))
00082
00083 /**
00084   * @brief  Macro used by the assert function in order to check the different sensitivity values for TLI.
00085   */
00086 #define IS_EXTI_TLISENSITIVITY_OK(SensitivityValue) \
00087   (((SensitivityValue) == EXTI_TLISENSITIVITY_FALL_ONLY) || \
00088    ((SensitivityValue) == EXTI_TLISENSITIVITY_RISE_ONLY))
00089
00090 /**
00091   * @brief  Macro used by the assert function in order to check the different Port values
00092   */
00093 #define IS_EXTI_PORT_OK(PORT) \
00094   (((PORT) == EXTI_PORT_GPIOA) ||\
00095    ((PORT) == EXTI_PORT_GPIOB) ||\
00096    ((PORT) == EXTI_PORT_GPIOC) ||\
00097    ((PORT) == EXTI_PORT_GPIOD) ||\
00098    ((PORT) == EXTI_PORT_GPIOE))
00099
00100 /**
00101   * @brief  Macro used by the assert function in order to check the different values of the EXTI PinMask
00102   */
00103 #define IS_EXTI_PINMASK_OK(PinMask) ((((PinMask) & (uint8_t)0x00) == (uint8_t)0x00) && ((PinMask) != (uint8_t)0x00))
00104
00105 /**
00106   * @}
00107   */
00108
00109 /* Exported functions ------------------------------------------------------- */
00110
00111 /** @addtogroup EXTI_Exported_Functions
00112   * @{
00113   */
00114
00115 void EXTI_DeInit(void);
00116 void EXTI_SetExtIntSensitivity(EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue);
00117 void EXTI_SetTLISensitivity(EXTI_TLISensitivity_TypeDef SensitivityValue);
00118 EXTI_Sensitivity_TypeDef EXTI_GetExtIntSensitivity(EXTI_Port_TypeDef Port);
00119 EXTI_TLISensitivity_TypeDef EXTI_GetTLISensitivity(void);
00120
00121 /**
00122   * @}
00123   */
00124
00125 #endif /* __STM8S_EXTI_H__ */
00126
00127 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_flash.c Source File

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  • STM8S_StdPeriph_Driver
  • src

stm8s_flash.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_flash.c
00004   * @author  MCD Application Team
00005         * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the FLASH peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_flash.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /**
00029 @code
00030  This driver provides functions to configure and program the Flash memory of all
00031  STM8S devices.
00032
00033  It includes as well functions that can be either executed from RAM or not, and
00034  other functions that must be executed from RAM otherwise useless.
00035
00036  The table below lists the functions that can be executed from RAM.
00037
00038  +--------------------------------------------------------------------------------|
00039  |   Functions prototypes      |    RAM execution            |     Comments       |
00040  ---------------------------------------------------------------------------------|
00041  |                             | Mandatory in case of block  | Can be executed    |
00042  | FLASH_WaitForLastOperation  | Operation:                  | from Flash in case |
00043  |                             | - Block programming         | of byte and word   |
00044  |                             | - Block erase               | Operations         |
00045  |--------------------------------------------------------------------------------|
00046  | FLASH_ProgramBlock          |       Exclusively           | useless from Flash |
00047  |--------------------------------------------------------------------------------|
00048  | FLASH_EraseBlock            |       Exclusively           | useless from Flash |
00049  |--------------------------------------------------------------------------------|
00050
00051  To be able to execute functions from RAM several steps have to be followed.
00052  These steps may differ from one toolchain to another.
00053  A detailed description is available below within this driver.
00054  You can also refer to the FLASH examples provided within the
00055  STM8S_StdPeriph_Lib package.
00056
00057 @endcode
00058 */
00059
00060
00061 /* Private typedef -----------------------------------------------------------*/
00062 /* Private define ------------------------------------------------------------*/
00063 #define FLASH_CLEAR_BYTE ((uint8_t)0x00)
00064 #define FLASH_SET_BYTE  ((uint8_t)0xFF)
00065 #define OPERATION_TIMEOUT  ((uint32_t)0xFFFFF)
00066 /* Private macro -------------------------------------------------------------*/
00067 /* Private variables ---------------------------------------------------------*/
00068 /* Private function prototypes -----------------------------------------------*/
00069 /* Private Constants ---------------------------------------------------------*/
00070
00071 /** @addtogroup FLASH_Public_functions
00072   * @{
00073   */
00074
00075 /**
00076   * @brief   Unlocks the program or data EEPROM memory
00077   * @param  FLASH_MemType : Memory type to unlock
00078   *         This parameter can be a value of @ref FLASH_MemType_TypeDef
00079   * @retval None
00080   */
00081 void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType)
00082 {
00083     /* Check parameter */
00084     assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));
00085
00086     /* Unlock program memory */
00087     if (FLASH_MemType == FLASH_MEMTYPE_PROG)
00088     {
00089         FLASH->PUKR = FLASH_RASS_KEY1;
00090         FLASH->PUKR = FLASH_RASS_KEY2;
00091     }
00092     /* Unlock data memory */
00093     else
00094     {
00095         FLASH->DUKR = FLASH_RASS_KEY2; /* Warning: keys are reversed on data memory !!! */
00096         FLASH->DUKR = FLASH_RASS_KEY1;
00097     }
00098 }
00099
00100 /**
00101   * @brief   Locks the program or data EEPROM memory
00102   * @param  FLASH_MemType : Memory type
00103   *         This parameter can be a value of @ref FLASH_MemType_TypeDef
00104   * @retval None
00105   */
00106 void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType)
00107 {
00108     /* Check parameter */
00109     assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));
00110
00111   /* Lock memory */
00112   FLASH->IAPSR &= (uint8_t)FLASH_MemType;
00113 }
00114
00115 /**
00116   * @brief   Deinitializes the FLASH registers to their default reset values.
00117   * @param  None
00118   * @retval None
00119   */
00120 void FLASH_DeInit(void)
00121 {
00122     FLASH->CR1 = FLASH_CR1_RESET_VALUE;
00123     FLASH->CR2 = FLASH_CR2_RESET_VALUE;
00124     FLASH->NCR2 = FLASH_NCR2_RESET_VALUE;
00125     FLASH->IAPSR &= (uint8_t)(~FLASH_IAPSR_DUL);
00126     FLASH->IAPSR &= (uint8_t)(~FLASH_IAPSR_PUL);
00127     (void) FLASH->IAPSR; /* Reading of this register causes the clearing of status flags */
00128 }
00129
00130 /**
00131   * @brief   Enables or Disables the Flash interrupt mode
00132   * @param  NewState : The new state of the flash interrupt mode
00133   *         This parameter can be a value of @ref FunctionalState enumeration.
00134   * @retval None
00135   */
00136 void FLASH_ITConfig(FunctionalState NewState)
00137 {
00138       /* Check parameter */
00139   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00140
00141     if (NewState != DISABLE)
00142     {
00143         FLASH->CR1 |= FLASH_CR1_IE; /* Enables the interrupt sources */
00144     }
00145     else
00146     {
00147         FLASH->CR1 &= (uint8_t)(~FLASH_CR1_IE); /* Disables the interrupt sources */
00148     }
00149 }
00150
00151 /**
00152   * @brief   Erases one byte in the program or data EEPROM memory
00153   * @note   PointerAttr define is declared in the stm8s.h file to select if
00154   *         the pointer will be declared as near (2 bytes) or far (3 bytes).
00155   * @param  Address : Address of the byte to erase
00156   * @retval None
00157   */
00158 void FLASH_EraseByte(uint32_t Address)
00159 {
00160     /* Check parameter */
00161     assert_param(IS_FLASH_ADDRESS_OK(Address));
00162
00163     /* Erase byte */
00164    *(PointerAttr uint8_t*) (uint16_t)Address = FLASH_CLEAR_BYTE;
00165
00166 }
00167
00168 /**
00169   * @brief   Programs one byte in program or data EEPROM memory
00170   * @note   PointerAttr define is declared in the stm8s.h file to select if
00171   *         the pointer will be declared as near (2 bytes) or far (3 bytes).
00172   * @param  Address : Address where the byte will be programmed
00173   * @param  Data : Value to be programmed
00174   * @retval None
00175   */
00176 void FLASH_ProgramByte(uint32_t Address, uint8_t Data)
00177 {
00178     /* Check parameters */
00179     assert_param(IS_FLASH_ADDRESS_OK(Address));
00180     *(PointerAttr uint8_t*) (uint16_t)Address = Data;
00181 }
00182
00183 /**
00184   * @brief   Reads any byte from flash memory
00185   * @note   PointerAttr define is declared in the stm8s.h file to select if
00186   *         the pointer will be declared as near (2 bytes) or far (3 bytes).
00187   * @param  Address : Address to read
00188   * @retval Value of the byte
00189   */
00190 uint8_t FLASH_ReadByte(uint32_t Address)
00191 {
00192     /* Check parameter */
00193     assert_param(IS_FLASH_ADDRESS_OK(Address));
00194
00195     /* Read byte */
00196     return(*(PointerAttr uint8_t *) (uint16_t)Address);
00197
00198 }
00199 /**
00200   * @brief   Programs one word (4 bytes) in program or data EEPROM memory
00201   * @note   PointerAttr define is declared in the stm8s.h file to select if
00202   *         the pointer will be declared as near (2 bytes) or far (3 bytes).
00203   * @param  Address : The address where the data will be programmed
00204   * @param  Data : Value to be programmed
00205   * @retval None
00206   */
00207 void FLASH_ProgramWord(uint32_t Address, uint32_t Data)
00208 {
00209     /* Check parameters */
00210     assert_param(IS_FLASH_ADDRESS_OK(Address));
00211
00212     /* Enable Word Write Once */
00213     FLASH->CR2 |= FLASH_CR2_WPRG;
00214     FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NWPRG);
00215
00216     /* Write one byte - from lowest address*/
00217     *((PointerAttr uint8_t*)(uint16_t)Address)       = *((uint8_t*)(&Data));
00218     /* Write one byte*/
00219     *(((PointerAttr uint8_t*)(uint16_t)Address) + 1) = *((uint8_t*)(&Data)+1);
00220     /* Write one byte*/
00221     *(((PointerAttr uint8_t*)(uint16_t)Address) + 2) = *((uint8_t*)(&Data)+2);
00222     /* Write one byte - from higher address*/
00223     *(((PointerAttr uint8_t*)(uint16_t)Address) + 3) = *((uint8_t*)(&Data)+3);
00224 }
00225
00226 /**
00227   * @brief   Programs option byte
00228   * @param  Address : option byte address to program
00229   * @param  Data : Value to write
00230   * @retval None
00231   */
00232 void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data)
00233 {
00234     /* Check parameter */
00235     assert_param(IS_OPTION_BYTE_ADDRESS_OK(Address));
00236
00237     /* Enable write access to option bytes */
00238     FLASH->CR2 |= FLASH_CR2_OPT;
00239     FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NOPT);
00240
00241     /* check if the option byte to program is ROP*/
00242     if (Address == 0x4800)
00243     {
00244        /* Program option byte*/
00245        *((NEAR uint8_t*)Address) = Data;
00246     }
00247     else
00248     {
00249        /* Program option byte and his complement */
00250        *((NEAR uint8_t*)Address) = Data;
00251        *((NEAR uint8_t*)((uint16_t)(Address + 1))) = (uint8_t)(~Data);
00252     }
00253     FLASH_WaitForLastOperation(FLASH_MEMTYPE_PROG);
00254
00255     /* Disable write access to option bytes */
00256     FLASH->CR2 &= (uint8_t)(~FLASH_CR2_OPT);
00257     FLASH->NCR2 |= FLASH_NCR2_NOPT;
00258 }
00259
00260 /**
00261   * @brief   Erases option byte
00262   * @param  Address : Option byte address to erase
00263   * @retval None
00264   */
00265 void FLASH_EraseOptionByte(uint16_t Address)
00266 {
00267     /* Check parameter */
00268     assert_param(IS_OPTION_BYTE_ADDRESS_OK(Address));
00269
00270     /* Enable write access to option bytes */
00271     FLASH->CR2 |= FLASH_CR2_OPT;
00272     FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NOPT);
00273
00274      /* check if the option byte to erase is ROP */
00275      if (Address == 0x4800)
00276     {
00277        /* Erase option byte */
00278        *((NEAR uint8_t*)Address) = FLASH_CLEAR_BYTE;
00279     }
00280     else
00281     {
00282        /* Erase option byte and his complement */
00283        *((NEAR uint8_t*)Address) = FLASH_CLEAR_BYTE;
00284        *((NEAR uint8_t*)((uint16_t)(Address + (uint16_t)1 ))) = FLASH_SET_BYTE;
00285     }
00286     FLASH_WaitForLastOperation(FLASH_MEMTYPE_PROG);
00287
00288     /* Disable write access to option bytes */
00289     FLASH->CR2 &= (uint8_t)(~FLASH_CR2_OPT);
00290     FLASH->NCR2 |= FLASH_NCR2_NOPT;
00291 }
00292 /**
00293   * @brief   Reads one option byte
00294   * @param  Address  option byte address to read.
00295   * @retval Option byte read value + its complement
00296   */
00297 uint16_t FLASH_ReadOptionByte(uint16_t Address)
00298 {
00299     uint8_t value_optbyte, value_optbyte_complement = 0;
00300     uint16_t res_value = 0;
00301
00302     /* Check parameter */
00303     assert_param(IS_OPTION_BYTE_ADDRESS_OK(Address));
00304
00305
00306     value_optbyte = *((NEAR uint8_t*)Address); /* Read option byte */
00307     value_optbyte_complement = *(((NEAR uint8_t*)Address) + 1); /* Read option byte complement */
00308
00309     /* Read-out protection option byte */
00310     if (Address == 0x4800)
00311     {
00312         res_value =      value_optbyte;
00313     }
00314     else
00315     {
00316         if (value_optbyte == (uint8_t)(~value_optbyte_complement))
00317         {
00318             res_value = (uint16_t)((uint16_t)value_optbyte << 8);
00319             res_value = res_value | (uint16_t)value_optbyte_complement;
00320         }
00321         else
00322         {
00323             res_value = FLASH_OPTIONBYTE_ERROR;
00324         }
00325     }
00326     return(res_value);
00327 }
00328
00329 /**
00330   * @brief   Select the Flash behaviour in low power mode
00331   * @param  FLASH_LPMode Low power mode selection
00332   *         This parameter can be any of the @ref FLASH_LPMode_TypeDef values.
00333   * @retval None
00334   */
00335 void FLASH_SetLowPowerMode(FLASH_LPMode_TypeDef FLASH_LPMode)
00336 {
00337     /* Check parameter */
00338     assert_param(IS_FLASH_LOW_POWER_MODE_OK(FLASH_LPMode));
00339
00340     /* Clears the two bits */
00341     FLASH->CR1 &= (uint8_t)(~(FLASH_CR1_HALT | FLASH_CR1_AHALT));
00342
00343     /* Sets the new mode */
00344     FLASH->CR1 |= (uint8_t)FLASH_LPMode;
00345 }
00346
00347 /**
00348   * @brief   Sets the fixed programming time
00349   * @param  FLASH_ProgTime Indicates the programming time to be fixed
00350   *         This parameter can be any of the @ref FLASH_ProgramTime_TypeDef values.
00351   * @retval None
00352   */
00353 void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime)
00354 {
00355     /* Check parameter */
00356     assert_param(IS_FLASH_PROGRAM_TIME_OK(FLASH_ProgTime));
00357
00358     FLASH->CR1 &= (uint8_t)(~FLASH_CR1_FIX);
00359     FLASH->CR1 |= (uint8_t)FLASH_ProgTime;
00360 }
00361
00362 /**
00363   * @brief  Returns the Flash behaviour type in low power mode
00364   * @param  None
00365   * @retval FLASH_LPMode_TypeDef Flash behaviour type in low power mode
00366   */
00367 FLASH_LPMode_TypeDef FLASH_GetLowPowerMode(void)
00368 {
00369     return((FLASH_LPMode_TypeDef)(FLASH->CR1 & (uint8_t)(FLASH_CR1_HALT | FLASH_CR1_AHALT)));
00370 }
00371
00372 /**
00373   * @brief  Returns the fixed programming time
00374   * @param  None
00375   * @retval FLASH_ProgramTime_TypeDef Fixed programming time value
00376   */
00377 FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void)
00378 {
00379     return((FLASH_ProgramTime_TypeDef)(FLASH->CR1 & FLASH_CR1_FIX));
00380 }
00381
00382 /**
00383   * @brief  Returns the Boot memory size in bytes
00384   * @param  None
00385   * @retval Boot memory size in bytes
00386   */
00387 uint32_t FLASH_GetBootSize(void)
00388 {
00389     uint32_t temp = 0;
00390
00391     /* Calculates the number of bytes */
00392     temp = (uint32_t)((uint32_t)FLASH->FPR * (uint32_t)512);
00393
00394     /* Correction because size of 127.5 kb doesn't exist */
00395     if (FLASH->FPR == 0xFF)
00396     {
00397         temp += 512;
00398     }
00399
00400     /* Return value */
00401     return(temp);
00402 }
00403
00404 /**
00405   * @brief  Checks whether the specified SPI flag is set or not.
00406   * @param  FLASH_FLAG : Specifies the flag to check.
00407   *         This parameter can be any of the @ref FLASH_Flag_TypeDef enumeration.
00408   * @retval FlagStatus : Indicates the state of FLASH_FLAG.
00409   *         This parameter can be any of the @ref FlagStatus enumeration.
00410   * @note   This function can clear the EOP, WR_PG_DIS flags in the IAPSR register.
00411   */
00412 FlagStatus FLASH_GetFlagStatus(FLASH_Flag_TypeDef FLASH_FLAG)
00413 {
00414     FlagStatus status = RESET;
00415     /* Check parameters */
00416     assert_param(IS_FLASH_FLAGS_OK(FLASH_FLAG));
00417
00418     /* Check the status of the specified FLASH flag */
00419     if ((FLASH->IAPSR & (uint8_t)FLASH_FLAG) != (uint8_t)RESET)
00420     {
00421         status = SET; /* FLASH_FLAG is set */
00422     }
00423     else
00424     {
00425         status = RESET; /* FLASH_FLAG is reset*/
00426     }
00427
00428     /* Return the FLASH_FLAG status */
00429     return status;
00430 }
00431
00432 /**
00433 @code
00434  All the functions defined below must be executed from RAM exclusively, except
00435  for the FLASH_WaitForLastOperation function which can be executed from Flash.
00436
00437  Steps of the execution from RAM differs from one toolchain to another:
00438  - For Cosmic Compiler:
00439     1- Define a segment FLASH_CODE by the mean of " #pragma section (FLASH_CODE)".
00440     This segment is defined in the stm8s_flash.c file.
00441   2- Uncomment the "#define RAM_EXECUTION  (1)" line in the stm8s.h file,
00442     or define it in Cosmic compiler preprocessor to enable the FLASH_CODE segment
00443    definition.
00444   3- In STVD Select Project\Settings\Linker\Category "input" and in the RAM section
00445     add the FLASH_CODE segment with "-ic" options.
00446   4- In main.c file call the _fctcpy() function with first segment character as
00447     parameter "_fctcpy('F');" to load the declared moveable code segment
00448     (FLASH_CODE) in RAM before execution.
00449   5- By default the _fctcpy function is packaged in the Cosmic machine library,
00450     so the function prototype "int _fctcopy(char name);" must be added in main.c
00451     file.
00452
00453   - For Raisonance Compiler
00454    1- Use the inram keyword in the function declaration to specify that it can be
00455     executed from RAM.
00456     This is done within the stm8s_flash.c file, and it's conditioned by
00457     RAM_EXECUTION definition.
00458    2- Uncomment the "#define RAM_EXECUTION  (1)" line in the stm8s.h file, or
00459    define it in Raisonance compiler preprocessor to enable the access for the
00460    inram functions.
00461    3- An inram function code is copied from Flash to RAM by the C startup code.
00462    In some applications, the RAM area where the code was initially stored may be
00463    erased or corrupted, so it may be desirable to perform the copy again.
00464    Depending on the application memory model, the memcpy() or fmemcpy() functions
00465    should be used to perform the copy.
00466       • In case your project uses the SMALL memory model (code smaller than 64K),
00467        memcpy()function is recommended to perform the copy
00468       • In case your project uses the LARGE memory model, functions can be
00469       everywhenre in the 24-bits address space (not limited to the first 64KB of
00470       code), In this case, the use of memcpy() function will not be appropriate,
00471       you need to use the specific fmemcpy() function (which copies objects with
00472       24-bit addresses).
00473       - The linker automatically defines 2 symbols for each inram function:
00474            • __address__functionname is a symbol that holds the Flash address
00475            where the given function code is stored.
00476            • __size__functionname is a symbol that holds the function size in bytes.
00477      And we already have the function address (which is itself a pointer)
00478   4- In main.c file these two steps should be performed for each inram function:
00479      • Import the "__address__functionname" and "__size__functionname" symbols
00480        as global variables:
00481          extern int __address__functionname; // Symbol holding the flash address
00482          extern int __size__functionname;    // Symbol holding the function size
00483      • In case of SMALL memory model use, Call the memcpy() function to copy the
00484       inram function to the RAM destination address:
00485                 memcpy(functionname, // RAM destination address
00486                       (void*)&__address__functionname, // Flash source address
00487                       (int)&__size__functionname); // Code size of the function
00488      • In case of LARGE memory model use, call the fmemcpy() function to copy
00489      the inram function to the RAM destination address:
00490                  memcpy(functionname, // RAM destination address
00491                       (void @far*)&__address__functionname, // Flash source address
00492                       (int)&__size__functionname); // Code size of the function
00493
00494  - For IAR Compiler:
00495     1- Use the __ramfunc keyword in the function declaration to specify that it
00496     can be executed from RAM..
00497     This is done within the stm8s_flash.c file, and it's conditioned by
00498     RAM_EXECUTION definition.
00499     2- Uncomment the "#define RAM_EXECUTION  (1)" line in the stm8s.h file, or
00500    define it in IAR compiler preprocessor to enable the access for the
00501    __ramfunc functions.
00502
00503  The FLASH examples given within the STM8S_StdPeriph_Lib package, details all
00504  the steps described above.
00505
00506 @endcode
00507 */
00508
00509 /**
00510   * @brief
00511   *******************************************************************************
00512   *                         Execution from RAM enable
00513   *******************************************************************************
00514   *
00515   * To enable execution from RAM you can either uncomment the following define
00516   * in the stm8s.h file or define it in your toolchain compiler preprocessor
00517   * - #define RAM_EXECUTION  (1)
00518   */
00519
00520 #if defined (_COSMIC_) && defined (RAM_EXECUTION)
00521  #pragma section (FLASH_CODE)
00522 #endif  /* _COSMIC_ && RAM_EXECUTION */
00523 /**
00524   * @brief  Wait for a Flash operation to complete.
00525   * @note   The call and execution of this function must be done from RAM in case
00526   *         of Block operation, otherwise it can be executed from Flash
00527   * @param  FLASH_MemType : Memory type
00528   *         This parameter can be a value of @ref FLASH_MemType_TypeDef
00529   * @retval FLASH status
00530   */
00531 IN_RAM(FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType))
00532 {
00533     uint8_t flagstatus = 0x00;
00534     uint32_t timeout = OPERATION_TIMEOUT;
00535
00536     /* Wait until operation completion or write protection page occurred */
00537 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
00538     defined(STM8S005) || defined(STM8AF52Ax) || defined(STM8AF62Ax) || defined(STM8AF626x)
00539     if (FLASH_MemType == FLASH_MEMTYPE_PROG)
00540     {
00541         while ((flagstatus == 0x00) && (timeout != 0x00))
00542         {
00543             flagstatus = (uint8_t)(FLASH->IAPSR & (uint8_t)(FLASH_IAPSR_EOP |
00544                                               FLASH_IAPSR_WR_PG_DIS));
00545             timeout--;
00546         }
00547     }
00548     else
00549     {
00550         while ((flagstatus == 0x00) && (timeout != 0x00))
00551         {
00552             flagstatus = (uint8_t)(FLASH->IAPSR & (uint8_t)(FLASH_IAPSR_HVOFF |
00553                                               FLASH_IAPSR_WR_PG_DIS));
00554             timeout--;
00555         }
00556     }
00557 #else /*STM8S103, STM8S903*/
00558     while ((flagstatus == 0x00) && (timeout != 0x00))
00559     {
00560         flagstatus = (uint8_t)(FLASH->IAPSR & (FLASH_IAPSR_EOP | FLASH_IAPSR_WR_PG_DIS));
00561         timeout--;
00562     }
00563
00564 #endif /* STM8S208, STM8S207, STM8S105, STM8AF52Ax, STM8AF62Ax, STM8AF262x */
00565
00566     if (timeout == 0x00 )
00567     {
00568         flagstatus = FLASH_STATUS_TIMEOUT;
00569     }
00570
00571     return((FLASH_Status_TypeDef)flagstatus);
00572 }
00573
00574 /**
00575   * @brief  Erases a block in the program or data memory.
00576   * @note   This function should be called and executed from RAM.
00577   * @param  FLASH_MemType :  The type of memory to erase
00578   * @param  BlockNum : Indicates the block number to erase
00579   * @retval None.
00580   */
00581 IN_RAM(void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType))
00582 {
00583   uint32_t startaddress = 0;
00584
00585 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
00586     defined (STM8S903) || defined (STM8AF626x)
00587   uint32_t PointerAttr  *pwFlash;
00588 #elif defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF62Ax) || defined (STM8AF52Ax)
00589   uint8_t PointerAttr  *pwFlash;
00590 #endif
00591
00592   /* Check parameters */
00593   assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));
00594   if (FLASH_MemType == FLASH_MEMTYPE_PROG)
00595   {
00596       assert_param(IS_FLASH_PROG_BLOCK_NUMBER_OK(BlockNum));
00597       startaddress = FLASH_PROG_START_PHYSICAL_ADDRESS;
00598   }
00599   else
00600   {
00601       assert_param(IS_FLASH_DATA_BLOCK_NUMBER_OK(BlockNum));
00602       startaddress = FLASH_DATA_START_PHYSICAL_ADDRESS;
00603   }
00604
00605     /* Point to the first block address */
00606 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF62Ax) || defined (STM8AF52Ax)
00607     pwFlash = (PointerAttr uint8_t *)(uint32_t)(startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE));
00608 #elif defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
00609       defined (STM8S903) || defined (STM8AF626x)
00610     pwFlash = (PointerAttr uint32_t *)(uint16_t)(startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE));
00611 #endif  /* STM8S208, STM8S207 */
00612
00613     /* Enable erase block mode */
00614     FLASH->CR2 |= FLASH_CR2_ERASE;
00615     FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NERASE);
00616
00617 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) ||  \
00618     defined (STM8S903) || defined (STM8AF626x)
00619     *pwFlash = (uint32_t)0;
00620 #elif defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF62Ax) || \
00621       defined (STM8AF52Ax)
00622   *pwFlash = (uint8_t)0;
00623   *(pwFlash + 1) = (uint8_t)0;
00624   *(pwFlash + 2) = (uint8_t)0;
00625   *(pwFlash + 3) = (uint8_t)0;
00626 #endif
00627 }
00628
00629 /**
00630   * @brief  Programs a memory block
00631   * @note   This function should be called and executed from RAM.
00632   * @param  FLASH_MemType : The type of memory to program
00633   * @param  BlockNum : The block number
00634   * @param  FLASH_ProgMode : The programming mode.
00635   * @param  Buffer : Pointer to buffer containing source data.
00636   * @retval None.
00637   */
00638 IN_RAM(void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType,
00639                         FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer))
00640 {
00641     uint16_t Count = 0;
00642     uint32_t startaddress = 0;
00643
00644     /* Check parameters */
00645     assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));
00646     assert_param(IS_FLASH_PROGRAM_MODE_OK(FLASH_ProgMode));
00647     if (FLASH_MemType == FLASH_MEMTYPE_PROG)
00648     {
00649         assert_param(IS_FLASH_PROG_BLOCK_NUMBER_OK(BlockNum));
00650         startaddress = FLASH_PROG_START_PHYSICAL_ADDRESS;
00651     }
00652     else
00653     {
00654         assert_param(IS_FLASH_DATA_BLOCK_NUMBER_OK(BlockNum));
00655         startaddress = FLASH_DATA_START_PHYSICAL_ADDRESS;
00656     }
00657
00658     /* Point to the first block address */
00659     startaddress = startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE);
00660
00661     /* Selection of Standard or Fast programming mode */
00662     if (FLASH_ProgMode == FLASH_PROGRAMMODE_STANDARD)
00663     {
00664         /* Standard programming mode */ /*No need in standard mode */
00665         FLASH->CR2 |= FLASH_CR2_PRG;
00666         FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NPRG);
00667     }
00668     else
00669     {
00670         /* Fast programming mode */
00671         FLASH->CR2 |= FLASH_CR2_FPRG;
00672         FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NFPRG);
00673     }
00674
00675     /* Copy data bytes from RAM to FLASH memory */
00676     for (Count = 0; Count < FLASH_BLOCK_SIZE; Count++)
00677     {
00678 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
00679     defined(STM8S005) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8AF626x)
00680   *((PointerAttr uint8_t*) (uint16_t)startaddress + Count) = ((uint8_t)(Buffer[Count]));
00681 #elif defined(STM8S103) || defined(STM8S003) ||  defined (STM8S903)
00682   *((PointerAttr uint8_t*) (uint16_t)startaddress + Count) = ((uint8_t)(Buffer[Count]));
00683 #endif
00684     }
00685 }
00686
00687 #if defined (_COSMIC_) && defined (RAM_EXECUTION)
00688  /* End of FLASH_CODE section */
00689  #pragma section ()
00690 #endif /* _COSMIC_ && RAM_EXECUTION */
00691
00692
00693 /**
00694   * @}
00695   */
00696
00697 /**
00698   * @}
00699   */
00700
00701 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_flash.h Source File

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  • STM8S_StdPeriph_Driver
  • inc

stm8s_flash.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_flash.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the FLASH peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_FLASH_H
00024 #define __STM8S_FLASH_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /* Exported constants --------------------------------------------------------*/
00030
00031 /** @addtogroup FLASH_Exported_Constants
00032   * @{
00033   */
00034
00035 #define FLASH_PROG_START_PHYSICAL_ADDRESS ((uint32_t)0x008000) /*!< Program memory: start address */
00036
00037 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
00038  #define FLASH_PROG_END_PHYSICAL_ADDRESS   ((uint32_t)0x027FFF) /*!< Program memory: end address */
00039  #define FLASH_PROG_BLOCKS_NUMBER          ((uint16_t)1024)     /*!< Program memory: total number of blocks */
00040  #define FLASH_DATA_START_PHYSICAL_ADDRESS ((uint32_t)0x004000) /*!< Data EEPROM memory: start address */
00041  #define FLASH_DATA_END_PHYSICAL_ADDRESS   ((uint32_t)0x0047FF) /*!< Data EEPROM memory: end address */
00042  #define FLASH_DATA_BLOCKS_NUMBER          ((uint16_t)16)       /*!< Data EEPROM memory: total number of blocks */
00043  #define FLASH_BLOCK_SIZE                  ((uint8_t)128)       /*!< Number of bytes in a block (common for Program and Data memories) */
00044 #endif /* STM8S208, STM8S207, STM8S007, STM8AF52Ax, STM8AF62Ax */
00045
00046 #if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
00047  #define FLASH_PROG_END_PHYSICAL_ADDRESS   ((uint32_t)0xFFFF)   /*!< Program memory: end address */
00048  #define FLASH_PROG_BLOCKS_NUMBER          ((uint16_t)256)      /*!< Program memory: total number of blocks */
00049  #define FLASH_DATA_START_PHYSICAL_ADDRESS ((uint32_t)0x004000) /*!< Data EEPROM memory: start address */
00050  #define FLASH_DATA_END_PHYSICAL_ADDRESS   ((uint32_t)0x0043FF) /*!< Data EEPROM memory: end address */
00051  #define FLASH_DATA_BLOCKS_NUMBER          ((uint16_t)8)        /*!< Data EEPROM memory: total number of blocks */
00052  #define FLASH_BLOCK_SIZE                  ((uint8_t)128)       /*!< Number of bytes in a block (common for Program and Data memories) */
00053 #endif /* STM8S105 or STM8AF626x */
00054
00055 #if defined(STM8S103) || defined(STM8S003) ||  defined(STM8S903)
00056  #define FLASH_PROG_END_PHYSICAL_ADDRESS   ((uint32_t)0x9FFF)   /*!< Program memory: end address */
00057  #define FLASH_PROG_BLOCKS_NUMBER          ((uint16_t)128)      /*!< Program memory: total number of blocks */
00058  #define FLASH_DATA_START_PHYSICAL_ADDRESS ((uint32_t)0x004000) /*!< Data EEPROM memory: start address */
00059  #define FLASH_DATA_END_PHYSICAL_ADDRESS   ((uint32_t)0x00427F) /*!< Data EEPROM memory: end address */
00060  #define FLASH_DATA_BLOCKS_NUMBER          ((uint16_t)10)       /*!< Data EEPROM memory: total number of blocks */
00061  #define FLASH_BLOCK_SIZE                  ((uint8_t)64)        /*!< Number of bytes in a block (common for Program and Data memories) */
00062 #endif /* STM8S103, STM8S903 */
00063
00064 #define FLASH_RASS_KEY1 ((uint8_t)0x56) /*!< First RASS key */
00065 #define FLASH_RASS_KEY2 ((uint8_t)0xAE) /*!< Second RASS key */
00066
00067 #define OPTION_BYTE_START_PHYSICAL_ADDRESS  ((uint16_t)0x4800)
00068 #define OPTION_BYTE_END_PHYSICAL_ADDRESS    ((uint16_t)0x487F)
00069 #define FLASH_OPTIONBYTE_ERROR              ((uint16_t)0x5555) /*!< Error code option byte
00070                                                                    (if value read is not equal to complement value read) */
00071 /**
00072   * @}
00073   */
00074
00075 /* Exported types ------------------------------------------------------------*/
00076
00077 /** @addtogroup FLASH_Exported_Types
00078   * @{
00079   */
00080
00081 /**
00082   * @brief  FLASH Memory types
00083   */
00084 typedef enum {
00085     FLASH_MEMTYPE_PROG      = (uint8_t)0xFD, /*!< Program memory */
00086     FLASH_MEMTYPE_DATA      = (uint8_t)0xF7  /*!< Data EEPROM memory */
00087 } FLASH_MemType_TypeDef;
00088
00089 /**
00090   * @brief  FLASH programming modes
00091   */
00092 typedef enum {
00093     FLASH_PROGRAMMODE_STANDARD = (uint8_t)0x00, /*!< Standard programming mode */
00094     FLASH_PROGRAMMODE_FAST     = (uint8_t)0x10  /*!< Fast programming mode */
00095 } FLASH_ProgramMode_TypeDef;
00096
00097 /**
00098   * @brief  FLASH fixed programming time
00099   */
00100 typedef enum {
00101     FLASH_PROGRAMTIME_STANDARD = (uint8_t)0x00, /*!< Standard programming time fixed at 1/2 tprog */
00102     FLASH_PROGRAMTIME_TPROG    = (uint8_t)0x01  /*!< Programming time fixed at tprog */
00103 } FLASH_ProgramTime_TypeDef;
00104
00105 /**
00106   * @brief  FLASH Low Power mode select
00107   */
00108 typedef enum {
00109     FLASH_LPMODE_POWERDOWN         = (uint8_t)0x04, /*!< HALT: Power-Down / ACTIVE-HALT: Power-Down */
00110     FLASH_LPMODE_STANDBY           = (uint8_t)0x08, /*!< HALT: Standby    / ACTIVE-HALT: Standby */
00111     FLASH_LPMODE_POWERDOWN_STANDBY = (uint8_t)0x00, /*!< HALT: Power-Down / ACTIVE-HALT: Standby */
00112     FLASH_LPMODE_STANDBY_POWERDOWN = (uint8_t)0x0C  /*!< HALT: Standby    / ACTIVE-HALT: Power-Down */
00113 }
00114 FLASH_LPMode_TypeDef;
00115
00116 /**
00117   * @brief  FLASH status of the last operation
00118   */
00119 typedef enum {
00120 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
00121     defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined(STM8AF626x)
00122                 FLASH_STATUS_END_HIGH_VOLTAGE           = (uint8_t)0x40, /*!< End of high voltage */
00123 #endif /* STM8S208, STM8S207, STM8S105, STM8AF62Ax, STM8AF52Ax, STM8AF626x */
00124                 FLASH_STATUS_SUCCESSFUL_OPERATION       = (uint8_t)0x04, /*!< End of operation flag */
00125                 FLASH_STATUS_TIMEOUT = (uint8_t)0x02, /*!< Time out error */
00126     FLASH_STATUS_WRITE_PROTECTION_ERROR     = (uint8_t)0x01 /*!< Write attempted to protected page */
00127 } FLASH_Status_TypeDef;
00128
00129 /**
00130   * @brief  FLASH flags definition
00131  * - Warning : FLAG value = mapping position register
00132   */
00133 typedef enum {
00134 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
00135     defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined(STM8AF626x)
00136     FLASH_FLAG_HVOFF     = (uint8_t)0x40,     /*!< End of high voltage flag */
00137 #endif /* STM8S208, STM8S207, STM8S105, STM8AF62Ax, STM8AF52Ax, STM8AF626x */
00138     FLASH_FLAG_DUL       = (uint8_t)0x08,     /*!< Data EEPROM unlocked flag */
00139     FLASH_FLAG_EOP       = (uint8_t)0x04,     /*!< End of programming (write or erase operation) flag */
00140     FLASH_FLAG_PUL       = (uint8_t)0x02,     /*!< Flash Program memory unlocked flag */
00141     FLASH_FLAG_WR_PG_DIS = (uint8_t)0x01      /*!< Write attempted to protected page flag */
00142 } FLASH_Flag_TypeDef;
00143
00144 /**
00145   * @}
00146   */
00147
00148 /* Private macros ------------------------------------------------------------*/
00149
00150 /**
00151   * @brief  Macros used by the assert function in order to check the different functions parameters.
00152   * @addtogroup FLASH_Private_Macros
00153   * @{
00154   */
00155
00156 /**
00157   * @brief  Macro used by the assert function in order to check the different sensitivity values for the flash program Address
00158   */
00159
00160 #define IS_FLASH_PROG_ADDRESS_OK(ADDRESS) (((ADDRESS) >= FLASH_PROG_START_PHYSICAL_ADDRESS) && \
00161     ((ADDRESS) <= FLASH_PROG_END_PHYSICAL_ADDRESS))
00162
00163 /**
00164   * @brief  Macro used by the assert function in order to check the different sensitivity values for the data eeprom Address
00165   */
00166
00167 #define IS_FLASH_DATA_ADDRESS_OK(ADDRESS) (((ADDRESS) >= FLASH_DATA_START_PHYSICAL_ADDRESS) && \
00168     ((ADDRESS) <= FLASH_DATA_END_PHYSICAL_ADDRESS))
00169
00170 /**
00171   * @brief  Macro used by the assert function in order to check the different sensitivity values for the data eeprom and flash program Address
00172   */
00173 #define IS_FLASH_ADDRESS_OK(ADDRESS)((((ADDRESS) >= FLASH_PROG_START_PHYSICAL_ADDRESS) && ((ADDRESS) <= FLASH_PROG_END_PHYSICAL_ADDRESS)) || \
00174                                      (((ADDRESS) >= FLASH_DATA_START_PHYSICAL_ADDRESS) && ((ADDRESS) <= FLASH_DATA_END_PHYSICAL_ADDRESS)))
00175
00176 /**
00177   * @brief  Macro used by the assert function in order to check the different sensitivity values for the flash program Block number
00178   */
00179 #define IS_FLASH_PROG_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_PROG_BLOCKS_NUMBER)
00180
00181 /**
00182   * @brief  Macro used by the assert function in order to check the different sensitivity values for the data eeprom Block number
00183   */
00184 #define IS_FLASH_DATA_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_DATA_BLOCKS_NUMBER)
00185
00186 /**
00187   * @brief  Macro used by the assert function in order to check the different sensitivity values for the flash memory type
00188   */
00189
00190 #define IS_MEMORY_TYPE_OK(MEMTYPE) (((MEMTYPE) == FLASH_MEMTYPE_PROG) || \
00191                                     ((MEMTYPE) == FLASH_MEMTYPE_DATA))
00192
00193 /**
00194   * @brief  Macro used by the assert function in order to check the different sensitivity values for the flash program mode
00195   */
00196
00197 #define IS_FLASH_PROGRAM_MODE_OK(MODE) (((MODE) == FLASH_PROGRAMMODE_STANDARD) || \
00198                                         ((MODE) == FLASH_PROGRAMMODE_FAST))
00199
00200 /**
00201   * @brief  Macro used by the assert function in order to check the program time mode
00202   */
00203
00204 #define IS_FLASH_PROGRAM_TIME_OK(TIME) (((TIME) == FLASH_PROGRAMTIME_STANDARD) || \
00205                                         ((TIME) == FLASH_PROGRAMTIME_TPROG))
00206
00207 /**
00208   * @brief  Macro used by the assert function in order to check the different
00209   *         sensitivity values for the low power mode
00210   */
00211
00212 #define IS_FLASH_LOW_POWER_MODE_OK(LPMODE) (((LPMODE) == FLASH_LPMODE_POWERDOWN) || \
00213     ((LPMODE) == FLASH_LPMODE_STANDBY) || \
00214     ((LPMODE) == FLASH_LPMODE_POWERDOWN_STANDBY) || \
00215     ((LPMODE) == FLASH_LPMODE_STANDBY_POWERDOWN))
00216
00217 /**
00218   * @brief  Macro used by the assert function in order to check the different
00219   *         sensitivity values for the option bytes Address
00220   */
00221 #define IS_OPTION_BYTE_ADDRESS_OK(ADDRESS) (((ADDRESS) >= OPTION_BYTE_START_PHYSICAL_ADDRESS) && \
00222     ((ADDRESS) <= OPTION_BYTE_END_PHYSICAL_ADDRESS))
00223
00224
00225 /**
00226   * @brief  Macro used by the assert function in order to check the different flags values
00227   */
00228 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
00229     defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined(STM8AF626x)
00230  #define IS_FLASH_FLAGS_OK(FLAG) (((FLAG) == FLASH_FLAG_HVOFF) || \
00231                                  ((FLAG) == FLASH_FLAG_DUL) || \
00232                                  ((FLAG) == FLASH_FLAG_EOP) || \
00233                                  ((FLAG) == FLASH_FLAG_PUL) || \
00234                                  ((FLAG) == FLASH_FLAG_WR_PG_DIS))
00235 #else /* STM8S103, STM8S903 */
00236  #define IS_FLASH_FLAGS_OK(FLAG) (((FLAG) == FLASH_FLAG_DUL) || \
00237                                  ((FLAG) == FLASH_FLAG_EOP) || \
00238                                  ((FLAG) == FLASH_FLAG_PUL) || \
00239                                  ((FLAG) == FLASH_FLAG_WR_PG_DIS))
00240 #endif /* STM8S208, STM8S207, STM8S105, STM8AF62Ax, STM8AF52Ax, STM8AF626x */
00241 /**
00242   * @}
00243   */
00244
00245 /* Exported functions ------------------------------------------------------- */
00246
00247 /** @addtogroup FLASH_Exported_Functions
00248   * @{
00249   */
00250 void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType);
00251 void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType);
00252 void FLASH_DeInit(void);
00253 void FLASH_ITConfig(FunctionalState NewState);
00254 void FLASH_EraseByte(uint32_t Address);
00255 void FLASH_ProgramByte(uint32_t Address, uint8_t Data);
00256 uint8_t FLASH_ReadByte(uint32_t Address);
00257 void FLASH_ProgramWord(uint32_t Address, uint32_t Data);
00258 uint16_t FLASH_ReadOptionByte(uint16_t Address);
00259 void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data);
00260 void FLASH_EraseOptionByte(uint16_t Address);
00261 void FLASH_SetLowPowerMode(FLASH_LPMode_TypeDef FLASH_LPMode);
00262 void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime);
00263 FLASH_LPMode_TypeDef FLASH_GetLowPowerMode(void);
00264 FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void);
00265 uint32_t FLASH_GetBootSize(void);
00266 FlagStatus FLASH_GetFlagStatus(FLASH_Flag_TypeDef FLASH_FLAG);
00267
00268 /**
00269 @code
00270  All the functions declared below must be executed from RAM exclusively, except
00271  for the FLASH_WaitForLastOperation function which can be executed from Flash.
00272
00273  Steps of the execution from RAM differs from one toolchain to another.
00274  for more details refer to stm8s_flash.c file.
00275
00276  To enable execution from RAM you can either uncomment the following define
00277  in the stm8s.h file or define it in your toolchain compiler preprocessor
00278  - #define RAM_EXECUTION  (1)
00279
00280 @endcode
00281 */
00282 IN_RAM(void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType));
00283 IN_RAM(void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType,
00284                         FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer));
00285 IN_RAM(FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType));
00286
00287 /**
00288   * @}
00289   */
00290
00291 #endif /*__STM8S_FLASH_H */
00292
00293 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_gpio.c Source File

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  • STM8S_StdPeriph_Driver
  • src

stm8s_gpio.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_gpio.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the GPIO peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_gpio.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034
00035 /* Public functions ----------------------------------------------------------*/
00036
00037 /**
00038   * @addtogroup GPIO_Public_Functions
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
00044   * @param  GPIOx: Select the GPIO peripheral number (x = A to I).
00045   * @retval None
00046   */
00047 void GPIO_DeInit(GPIO_TypeDef* GPIOx)
00048 {
00049     GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */
00050     GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */
00051     GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */
00052     GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */
00053 }
00054
00055 /**
00056   * @brief  Initializes the GPIOx according to the specified parameters.
00057   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00058   * @param  GPIO_Pin : This parameter contains the pin number, it can be any value
00059   *         of the @ref GPIO_Pin_TypeDef enumeration.
00060   * @param  GPIO_Mode : This parameter can be a value of the
00061   *         @Ref GPIO_Mode_TypeDef enumeration.
00062   * @retval None
00063   */
00064
00065 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
00066 {
00067     /*----------------------*/
00068     /* Check the parameters */
00069     /*----------------------*/
00070
00071     assert_param(IS_GPIO_MODE_OK(GPIO_Mode));
00072     assert_param(IS_GPIO_PIN_OK(GPIO_Pin));
00073
00074   /* Reset corresponding bit to GPIO_Pin in CR2 register */
00075   GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
00076
00077     /*-----------------------------*/
00078     /* Input/Output mode selection */
00079     /*-----------------------------*/
00080
00081     if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x80) != (uint8_t)0x00) /* Output mode */
00082     {
00083         if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x10) != (uint8_t)0x00) /* High level */
00084         {
00085             GPIOx->ODR |= (uint8_t)GPIO_Pin;
00086         }
00087         else /* Low level */
00088         {
00089             GPIOx->ODR &= (uint8_t)(~(GPIO_Pin));
00090         }
00091         /* Set Output mode */
00092         GPIOx->DDR |= (uint8_t)GPIO_Pin;
00093     }
00094     else /* Input mode */
00095     {
00096         /* Set Input mode */
00097         GPIOx->DDR &= (uint8_t)(~(GPIO_Pin));
00098     }
00099
00100     /*------------------------------------------------------------------------*/
00101     /* Pull-Up/Float (Input) or Push-Pull/Open-Drain (Output) modes selection */
00102     /*------------------------------------------------------------------------*/
00103
00104     if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x40) != (uint8_t)0x00) /* Pull-Up or Push-Pull */
00105     {
00106         GPIOx->CR1 |= (uint8_t)GPIO_Pin;
00107     }
00108     else /* Float or Open-Drain */
00109     {
00110         GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
00111     }
00112
00113     /*-----------------------------------------------------*/
00114     /* Interrupt (Input) or Slope (Output) modes selection */
00115     /*-----------------------------------------------------*/
00116
00117     if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x20) != (uint8_t)0x00) /* Interrupt or Slow slope */
00118     {
00119         GPIOx->CR2 |= (uint8_t)GPIO_Pin;
00120     }
00121     else /* No external interrupt or No slope control */
00122     {
00123         GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
00124     }
00125 }
00126
00127 /**
00128   * @brief  Writes data to the specified GPIO data port.
00129   * @note   The port must be configured in output mode.
00130   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00131   * @param  GPIO_PortVal : Specifies the value to be written to the port output
00132   *         data register.
00133   * @retval None
00134   */
00135 void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t PortVal)
00136 {
00137     GPIOx->ODR = PortVal;
00138 }
00139
00140 /**
00141   * @brief  Writes high level to the specified GPIO pins.
00142   * @note   The port must be configured in output mode.
00143   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00144   * @param  PortPins : Specifies the pins to be turned high to the port output.
00145   *         data register.
00146   * @retval None
00147   */
00148 void GPIO_WriteHigh(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)
00149 {
00150     GPIOx->ODR |= (uint8_t)PortPins;
00151 }
00152
00153 /**
00154   * @brief  Writes low level to the specified GPIO pins.
00155   * @note   The port must be configured in output mode.
00156   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00157   * @param  PortPins : Specifies the pins to be turned low to the port output.
00158   *         data register.
00159   * @retval None
00160   */
00161 void GPIO_WriteLow(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)
00162 {
00163     GPIOx->ODR &= (uint8_t)(~PortPins);
00164 }
00165
00166 /**
00167   * @brief  Writes reverse level to the specified GPIO pins.
00168   * @note   The port must be configured in output mode.
00169   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00170   * @param  PortPins : Specifies the pins to be reversed to the port output.
00171   *         data register.
00172   * @retval None
00173   */
00174 void GPIO_WriteReverse(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)
00175 {
00176     GPIOx->ODR ^= (uint8_t)PortPins;
00177 }
00178
00179 /**
00180   * @brief  Reads the specified GPIO output data port.
00181   * @note   The port must be configured in input mode.
00182   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00183   * @retval GPIO output data port value.
00184   */
00185 uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
00186 {
00187     return ((uint8_t)GPIOx->ODR);
00188 }
00189
00190 /**
00191   * @brief  Reads the specified GPIO input data port.
00192   * @note   The port must be configured in input mode.
00193   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00194   * @retval GPIO input data port value.
00195   */
00196 uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
00197 {
00198     return ((uint8_t)GPIOx->IDR);
00199 }
00200
00201 /**
00202   * @brief  Reads the specified GPIO input data pin.
00203   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00204   * @param  GPIO_Pin : Specifies the pin number.
00205   * @retval BitStatus : GPIO input pin status.
00206   */
00207 BitStatus GPIO_ReadInputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
00208 {
00209     return ((BitStatus)(GPIOx->IDR & (uint8_t)GPIO_Pin));
00210 }
00211
00212 /**
00213   * @brief  Configures the external pull-up on GPIOx pins.
00214   * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
00215   * @param  GPIO_Pin : Specifies the pin number
00216   * @param  NewState : The new state of the pull up pin.
00217   * @retval None
00218   */
00219 void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
00220 {
00221     /* Check the parameters */
00222     assert_param(IS_GPIO_PIN_OK(GPIO_Pin));
00223     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00224
00225     if (NewState != DISABLE) /* External Pull-Up Set*/
00226     {
00227         GPIOx->CR1 |= (uint8_t)GPIO_Pin;
00228     } else /* External Pull-Up Reset*/
00229     {
00230         GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
00231     }
00232 }
00233
00234 /**
00235   * @}
00236   */
00237
00238 /**
00239   * @}
00240   */
00241
00242 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_gpio.h Source File

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  • STM8S_StdPeriph_Driver
  • inc

stm8s_gpio.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_gpio.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the GPIO peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_GPIO_H
00024 #define __STM8S_GPIO_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /* Exported variables ------------------------------------------------------- */
00030 /* Exported types ------------------------------------------------------------*/
00031
00032 /** @addtogroup GPIO_Exported_Types
00033   * @{
00034   */
00035
00036 /**
00037   * @brief  GPIO modes
00038   *
00039   * Bits definitions:
00040   * - Bit 7: 0 = INPUT mode
00041   *          1 = OUTPUT mode
00042   *          1 = PULL-UP (input) or PUSH-PULL (output)
00043   * - Bit 5: 0 = No external interrupt (input) or No slope control (output)
00044   *          1 = External interrupt (input) or Slow control enabled (output)
00045   * - Bit 4: 0 = Low level (output)
00046   *          1 = High level (output push-pull) or HI-Z (output open-drain)
00047   */
00048 typedef enum
00049 {
00050   GPIO_MODE_IN_FL_NO_IT      = (uint8_t)0x00,  /*!< Input floating, no external interrupt */
00051   GPIO_MODE_IN_PU_NO_IT      = (uint8_t)0x40,  /*!< Input pull-up, no external interrupt */
00052   GPIO_MODE_IN_FL_IT         = (uint8_t)0x20,  /*!< Input floating, external interrupt */
00053   GPIO_MODE_IN_PU_IT         = (uint8_t)0x60,  /*!< Input pull-up, external interrupt */
00054   GPIO_MODE_OUT_OD_LOW_FAST  = (uint8_t)0xA0,  /*!< Output open-drain, low level, 10MHz */
00055   GPIO_MODE_OUT_PP_LOW_FAST  = (uint8_t)0xE0,  /*!< Output push-pull, low level, 10MHz */
00056   GPIO_MODE_OUT_OD_LOW_SLOW  = (uint8_t)0x80,  /*!< Output open-drain, low level, 2MHz */
00057   GPIO_MODE_OUT_PP_LOW_SLOW  = (uint8_t)0xC0,  /*!< Output push-pull, low level, 2MHz */
00058   GPIO_MODE_OUT_OD_HIZ_FAST  = (uint8_t)0xB0,  /*!< Output open-drain, high-impedance level,10MHz */
00059   GPIO_MODE_OUT_PP_HIGH_FAST = (uint8_t)0xF0,  /*!< Output push-pull, high level, 10MHz */
00060   GPIO_MODE_OUT_OD_HIZ_SLOW  = (uint8_t)0x90,  /*!< Output open-drain, high-impedance level, 2MHz */
00061   GPIO_MODE_OUT_PP_HIGH_SLOW = (uint8_t)0xD0   /*!< Output push-pull, high level, 2MHz */
00062 }GPIO_Mode_TypeDef;
00063
00064 /**
00065   * @brief  Definition of the GPIO pins. Used by the @ref GPIO_Init function in
00066   * order to select the pins to be initialized.
00067   */
00068
00069 typedef enum
00070 {
00071   GPIO_PIN_0    = ((uint8_t)0x01),  /*!< Pin 0 selected */
00072   GPIO_PIN_1    = ((uint8_t)0x02),  /*!< Pin 1 selected */
00073   GPIO_PIN_2    = ((uint8_t)0x04),  /*!< Pin 2 selected */
00074   GPIO_PIN_3    = ((uint8_t)0x08),   /*!< Pin 3 selected */
00075   GPIO_PIN_4    = ((uint8_t)0x10),  /*!< Pin 4 selected */
00076   GPIO_PIN_5    = ((uint8_t)0x20),  /*!< Pin 5 selected */
00077   GPIO_PIN_6    = ((uint8_t)0x40),  /*!< Pin 6 selected */
00078   GPIO_PIN_7    = ((uint8_t)0x80),  /*!< Pin 7 selected */
00079   GPIO_PIN_LNIB = ((uint8_t)0x0F),  /*!< Low nibble pins selected */
00080   GPIO_PIN_HNIB = ((uint8_t)0xF0),  /*!< High nibble pins selected */
00081   GPIO_PIN_ALL  = ((uint8_t)0xFF)   /*!< All pins selected */
00082 }GPIO_Pin_TypeDef;
00083
00084 /**
00085   * @}
00086   */
00087
00088 /* Exported constants --------------------------------------------------------*/
00089 /* Exported macros -----------------------------------------------------------*/
00090 /* Private macros ------------------------------------------------------------*/
00091
00092 /** @addtogroup GPIO_Private_Macros
00093   * @{
00094   */
00095
00096 /**
00097   * @brief  Macro used by the assert function to check the different functions parameters.
00098   */
00099
00100 /**
00101   * @brief  Macro used by the assert function in order to check the different
00102   * values of GPIOMode_TypeDef.
00103   */
00104 #define IS_GPIO_MODE_OK(MODE) \
00105   (((MODE) == GPIO_MODE_IN_FL_NO_IT)    || \
00106    ((MODE) == GPIO_MODE_IN_PU_NO_IT)    || \
00107    ((MODE) == GPIO_MODE_IN_FL_IT)       || \
00108    ((MODE) == GPIO_MODE_IN_PU_IT)       || \
00109    ((MODE) == GPIO_MODE_OUT_OD_LOW_FAST)  || \
00110    ((MODE) == GPIO_MODE_OUT_PP_LOW_FAST)  || \
00111    ((MODE) == GPIO_MODE_OUT_OD_LOW_SLOW)  || \
00112    ((MODE) == GPIO_MODE_OUT_PP_LOW_SLOW)  || \
00113    ((MODE) == GPIO_MODE_OUT_OD_HIZ_FAST)  || \
00114    ((MODE) == GPIO_MODE_OUT_PP_HIGH_FAST)  || \
00115    ((MODE) == GPIO_MODE_OUT_OD_HIZ_SLOW)  || \
00116    ((MODE) == GPIO_MODE_OUT_PP_HIGH_SLOW))
00117
00118 /**
00119   * @brief  Macro used by the assert function in order to check the different
00120   * values of GPIO_Pins.
00121   */
00122 #define IS_GPIO_PIN_OK(PIN)  ((PIN) != (uint8_t)0x00)
00123
00124 /**
00125   * @}
00126   */
00127
00128 /* Exported functions ------------------------------------------------------- */
00129 /** @addtogroup GPIO_Exported_Functions
00130   * @{
00131   */
00132
00133 void GPIO_DeInit(GPIO_TypeDef* GPIOx);
00134 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode);
00135 void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t PortVal);
00136 void GPIO_WriteHigh(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins);
00137 void GPIO_WriteLow(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins);
00138 void GPIO_WriteReverse(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins);
00139 uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
00140 uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
00141 BitStatus GPIO_ReadInputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
00142 void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState);
00143 /**
00144   * @}
00145   */
00146
00147 #endif /* __STM8L_GPIO_H */
00148
00149 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_i2c.c Source File

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  • Globals
  • STM8S_StdPeriph_Driver
  • src

stm8s_i2c.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_i2c.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the I2C peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_i2c.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029
00030 /** @defgroup I2C_Private_Defines
00031   * @{
00032   */
00033 /* I2C register mask */
00034 #define REGISTER_Mask               ((uint16_t)0x3000)
00035 #define REGISTER_SR1_Index          ((uint16_t)0x0100)
00036 #define REGISTER_SR2_Index          ((uint16_t)0x0200)
00037 /* I2C Interrupt Enable mask */
00038 #define ITEN_Mask                   ((uint16_t)0x0700)
00039 /* I2C FLAG mask */
00040 #define FLAG_Mask                   ((uint16_t)0x00FF)
00041 /**
00042   * @}
00043   */
00044
00045 /* Private macro -------------------------------------------------------------*/
00046 /* Private variables ---------------------------------------------------------*/
00047 /* Private function prototypes -----------------------------------------------*/
00048 /* Private functions ---------------------------------------------------------*/
00049
00050
00051 /**
00052   * @addtogroup I2C_Public_Functions
00053   * @{
00054   */
00055
00056 /**
00057   * @brief  Deinitializes the I2C peripheral registers to their default reset values.
00058   * @param  None
00059   * @retval None
00060   */
00061 void I2C_DeInit(void)
00062 {
00063   I2C->CR1 = I2C_CR1_RESET_VALUE;
00064   I2C->CR2 = I2C_CR2_RESET_VALUE;
00065   I2C->FREQR = I2C_FREQR_RESET_VALUE;
00066   I2C->OARL = I2C_OARL_RESET_VALUE;
00067   I2C->OARH = I2C_OARH_RESET_VALUE;
00068   I2C->ITR = I2C_ITR_RESET_VALUE;
00069   I2C->CCRL = I2C_CCRL_RESET_VALUE;
00070   I2C->CCRH = I2C_CCRH_RESET_VALUE;
00071   I2C->TRISER = I2C_TRISER_RESET_VALUE;
00072 }
00073
00074 /**
00075   * @brief  Initializes the I2C according to the specified parameters in standard
00076   *         or fast mode.
00077   * @param  OutputClockFrequencyHz : Specifies the output clock frequency in Hz.
00078   * @param  OwnAddress : Specifies the own address.
00079   * @param  I2C_DutyCycle : Specifies the duty cycle to apply in fast mode.
00080   *         This parameter can be any of the  @ref I2C_DutyCycle_TypeDef enumeration.
00081   * @note   This parameter don't have impact when the OutputClockFrequency lower
00082   *         than 100KHz.
00083   * @param  Ack : Specifies the acknowledge mode to apply.
00084   *         This parameter can be any of the  @ref I2C_Ack_TypeDef enumeration.
00085   * @param  AddMode : Specifies the acknowledge address to apply.
00086   *         This parameter can be any of the  @ref I2C_AddMode_TypeDef enumeration.
00087   * @param  InputClockFrequencyMHz : Specifies the input clock frequency in MHz.
00088   * @retval None
00089   */
00090 void I2C_Init(uint32_t OutputClockFrequencyHz, uint16_t OwnAddress,
00091               I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack,
00092               I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz )
00093 {
00094   uint16_t result = 0x0004;
00095   uint16_t tmpval = 0;
00096   uint8_t tmpccrh = 0;
00097
00098   /* Check the parameters */
00099   assert_param(IS_I2C_ACK_OK(Ack));
00100   assert_param(IS_I2C_ADDMODE_OK(AddMode));
00101   assert_param(IS_I2C_OWN_ADDRESS_OK(OwnAddress));
00102   assert_param(IS_I2C_DUTYCYCLE_OK(I2C_DutyCycle));
00103   assert_param(IS_I2C_INPUT_CLOCK_FREQ_OK(InputClockFrequencyMHz));
00104   assert_param(IS_I2C_OUTPUT_CLOCK_FREQ_OK(OutputClockFrequencyHz));
00105
00106
00107   /*------------------------- I2C FREQ Configuration ------------------------*/
00108   /* Clear frequency bits */
00109   I2C->FREQR &= (uint8_t)(~I2C_FREQR_FREQ);
00110   /* Write new value */
00111   I2C->FREQR |= InputClockFrequencyMHz;
00112
00113   /*--------------------------- I2C CCR Configuration ------------------------*/
00114   /* Disable I2C to configure TRISER */
00115   I2C->CR1 &= (uint8_t)(~I2C_CR1_PE);
00116
00117   /* Clear CCRH & CCRL */
00118   I2C->CCRH &= (uint8_t)(~(I2C_CCRH_FS | I2C_CCRH_DUTY | I2C_CCRH_CCR));
00119   I2C->CCRL &= (uint8_t)(~I2C_CCRL_CCR);
00120
00121   /* Detect Fast or Standard mode depending on the Output clock frequency selected */
00122   if (OutputClockFrequencyHz > I2C_MAX_STANDARD_FREQ) /* FAST MODE */
00123   {
00124     /* Set F/S bit for fast mode */
00125     tmpccrh = I2C_CCRH_FS;
00126
00127     if (I2C_DutyCycle == I2C_DUTYCYCLE_2)
00128     {
00129       /* Fast mode speed calculate: Tlow/Thigh = 2 */
00130       result = (uint16_t) ((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz * 3));
00131     }
00132     else /* I2C_DUTYCYCLE_16_9 */
00133     {
00134       /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
00135       result = (uint16_t) ((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz * 25));
00136       /* Set DUTY bit */
00137       tmpccrh |= I2C_CCRH_DUTY;
00138     }
00139
00140     /* Verify and correct CCR value if below minimum value */
00141     if (result < (uint16_t)0x01)
00142     {
00143       /* Set the minimum allowed value */
00144       result = (uint16_t)0x0001;
00145     }
00146
00147     /* Set Maximum Rise Time: 300ns max in Fast Mode
00148     = [300ns/(1/InputClockFrequencyMHz.10e6)]+1
00149     = [(InputClockFrequencyMHz * 3)/10]+1 */
00150     tmpval = ((InputClockFrequencyMHz * 3) / 10) + 1;
00151     I2C->TRISER = (uint8_t)tmpval;
00152
00153   }
00154   else /* STANDARD MODE */
00155   {
00156
00157     /* Calculate standard mode speed */
00158     result = (uint16_t)((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz << (uint8_t)1));
00159
00160     /* Verify and correct CCR value if below minimum value */
00161     if (result < (uint16_t)0x0004)
00162     {
00163       /* Set the minimum allowed value */
00164       result = (uint16_t)0x0004;
00165     }
00166
00167     /* Set Maximum Rise Time: 1000ns max in Standard Mode
00168     = [1000ns/(1/InputClockFrequencyMHz.10e6)]+1
00169     = InputClockFrequencyMHz+1 */
00170     I2C->TRISER = (uint8_t)(InputClockFrequencyMHz + (uint8_t)1);
00171
00172   }
00173
00174   /* Write CCR with new calculated value */
00175   I2C->CCRL = (uint8_t)result;
00176   I2C->CCRH = (uint8_t)((uint8_t)((uint8_t)(result >> 8) & I2C_CCRH_CCR) | tmpccrh);
00177
00178   /* Enable I2C */
00179   I2C->CR1 |= I2C_CR1_PE;
00180
00181   /* Configure I2C acknowledgement */
00182   I2C_AcknowledgeConfig(Ack);
00183
00184   /*--------------------------- I2C OAR Configuration ------------------------*/
00185   I2C->OARL = (uint8_t)(OwnAddress);
00186   I2C->OARH = (uint8_t)((uint8_t)(AddMode | I2C_OARH_ADDCONF) |
00187                    (uint8_t)((OwnAddress & (uint16_t)0x0300) >> (uint8_t)7));
00188 }
00189
00190 /**
00191   * @brief  Enables or disables the I2C peripheral.
00192   * @param  NewState : Indicate the new I2C peripheral state.
00193   *         This parameter can be any of the @ref FunctionalState enumeration.
00194   * @retval None
00195   */
00196 void I2C_Cmd(FunctionalState NewState)
00197 {
00198
00199   /* Check function parameters */
00200   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00201
00202   if (NewState != DISABLE)
00203   {
00204     /* Enable I2C peripheral */
00205     I2C->CR1 |= I2C_CR1_PE;
00206   }
00207   else /* NewState == DISABLE */
00208   {
00209     /* Disable I2C peripheral */
00210     I2C->CR1 &= (uint8_t)(~I2C_CR1_PE);
00211   }
00212 }
00213
00214 /**
00215   * @brief  Enables or disables the I2C General Call feature.
00216   * @param  NewState : State of the General Call feature.
00217   *         This parameter can be any of the @ref FunctionalState enumeration.
00218   * @retval None
00219   */
00220 void I2C_GeneralCallCmd(FunctionalState NewState)
00221 {
00222
00223   /* Check function parameters */
00224   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00225
00226   if (NewState != DISABLE)
00227   {
00228     /* Enable General Call */
00229     I2C->CR1 |= I2C_CR1_ENGC;
00230   }
00231   else /* NewState == DISABLE */
00232   {
00233     /* Disable General Call */
00234     I2C->CR1 &= (uint8_t)(~I2C_CR1_ENGC);
00235   }
00236 }
00237
00238 /**
00239   * @brief  Generates I2C communication START condition.
00240   * @note   CCR must be programmed, i.e. I2C_Init function must have been called
00241   *         with a valid I2C_ClockSpeed
00242   * @param  NewState : Enable or disable the start condition.
00243   *         This parameter can be any of the @ref FunctionalState enumeration.
00244   * @retval None
00245   */
00246 void I2C_GenerateSTART(FunctionalState NewState)
00247 {
00248
00249   /* Check function parameters */
00250   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00251
00252   if (NewState != DISABLE)
00253   {
00254     /* Generate a START condition */
00255     I2C->CR2 |= I2C_CR2_START;
00256   }
00257   else /* NewState == DISABLE */
00258   {
00259     /* Disable the START condition generation */
00260     I2C->CR2 &= (uint8_t)(~I2C_CR2_START);
00261   }
00262 }
00263
00264 /**
00265   * @brief  Generates I2C communication STOP condition.
00266   * @param   NewState : Enable or disable the stop condition.
00267   *          This parameter can be any of the @ref FunctionalState enumeration.
00268   * @retval None
00269   */
00270 void I2C_GenerateSTOP(FunctionalState NewState)
00271 {
00272
00273   /* Check function parameters */
00274   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00275
00276   if (NewState != DISABLE)
00277   {
00278     /* Generate a STOP condition */
00279     I2C->CR2 |= I2C_CR2_STOP;
00280   }
00281   else /* NewState == DISABLE */
00282   {
00283     /* Disable the STOP condition generation */
00284     I2C->CR2 &= (uint8_t)(~I2C_CR2_STOP);
00285   }
00286 }
00287
00288 /**
00289   * @brief  Enables or disables I2C software reset.
00290   * @param  NewState : Specifies the new state of the I2C software reset.
00291   *         This parameter can be any of the @ref FunctionalState enumeration.
00292   * @retval None
00293   */
00294 void I2C_SoftwareResetCmd(FunctionalState NewState)
00295 {
00296   /* Check function parameters */
00297   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00298
00299   if (NewState != DISABLE)
00300   {
00301     /* Peripheral under reset */
00302     I2C->CR2 |= I2C_CR2_SWRST;
00303   }
00304   else /* NewState == DISABLE */
00305   {
00306     /* Peripheral not under reset */
00307     I2C->CR2 &= (uint8_t)(~I2C_CR2_SWRST);
00308   }
00309 }
00310
00311 /**
00312   * @brief  Enables or disables the I2C clock stretching.
00313   * @param  NewState : Specifies the new state of the I2C Clock stretching.
00314   *         This parameter can be any of the @ref FunctionalState enumeration.
00315   * @retval None
00316   */
00317
00318 void I2C_StretchClockCmd(FunctionalState NewState)
00319 {
00320   /* Check function parameters */
00321   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00322
00323   if (NewState != DISABLE)
00324   {
00325     /* Clock Stretching Enable */
00326     I2C->CR1 &= (uint8_t)(~I2C_CR1_NOSTRETCH);
00327
00328   }
00329   else /* NewState == DISABLE */
00330   {
00331     /* Clock Stretching Disable (Slave mode) */
00332     I2C->CR1 |= I2C_CR1_NOSTRETCH;
00333   }
00334 }
00335
00336 /**
00337   * @brief  Enable or Disable the I2C acknowledge and position acknowledge feature.
00338   * @note   This function must be called before data reception start
00339   * @param  Ack : Specifies the acknowledge mode to apply.
00340   *         This parameter can be any of the  @ref I2C_Ack_TypeDef enumeration.
00341   * @retval None
00342   */
00343 void I2C_AcknowledgeConfig(I2C_Ack_TypeDef Ack)
00344 {
00345
00346   /* Check function parameters */
00347   assert_param(IS_I2C_ACK_OK(Ack));
00348
00349   if (Ack == I2C_ACK_NONE)
00350   {
00351     /* Disable the acknowledgement */
00352     I2C->CR2 &= (uint8_t)(~I2C_CR2_ACK);
00353   }
00354   else
00355   {
00356     /* Enable the acknowledgement */
00357     I2C->CR2 |= I2C_CR2_ACK;
00358
00359     if (Ack == I2C_ACK_CURR)
00360     {
00361       /* Configure (N)ACK on current byte */
00362       I2C->CR2 &= (uint8_t)(~I2C_CR2_POS);
00363     }
00364     else
00365     {
00366       /* Configure (N)ACK on next byte */
00367       I2C->CR2 |= I2C_CR2_POS;
00368     }
00369   }
00370 }
00371
00372 /**
00373   * @brief  Enables or disables the specified I2C interrupt.
00374   * @param  ITName : Name of the interrupt to enable or disable.
00375   *         This parameter can be any of the  @ref I2C_IT_TypeDef enumeration.
00376   * @param  NewState : State of the interrupt to apply.
00377   *         This parameter can be any of the @ref FunctionalState enumeration.
00378   * @retval None
00379   */
00380 void I2C_ITConfig(I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
00381 {
00382
00383   /* Check functions parameters */
00384   assert_param(IS_I2C_INTERRUPT_OK(I2C_IT));
00385   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00386
00387   if (NewState != DISABLE)
00388   {
00389     /* Enable the selected I2C interrupts */
00390     I2C->ITR |= (uint8_t)I2C_IT;
00391   }
00392   else /* NewState == DISABLE */
00393   {
00394     /* Disable the selected I2C interrupts */
00395     I2C->ITR &= (uint8_t)(~(uint8_t)I2C_IT);
00396   }
00397 }
00398
00399 /**
00400   * @brief  Selects the specified I2C fast mode duty cycle.
00401   * @param  I2C_DutyCycle : Specifies the duty cycle to apply.
00402   *         This parameter can be any of the @ref I2C_DutyCycle_TypeDef enumeration.
00403   * @retval None
00404   */
00405 void I2C_FastModeDutyCycleConfig(I2C_DutyCycle_TypeDef I2C_DutyCycle)
00406 {
00407
00408   /* Check function parameters */
00409   assert_param(IS_I2C_DUTYCYCLE_OK(I2C_DutyCycle));
00410
00411   if (I2C_DutyCycle == I2C_DUTYCYCLE_16_9)
00412   {
00413     /* I2C fast mode Tlow/Thigh = 16/9 */
00414     I2C->CCRH |= I2C_CCRH_DUTY;
00415   }
00416   else /* I2C_DUTYCYCLE_2 */
00417   {
00418     /* I2C fast mode Tlow/Thigh = 2 */
00419     I2C->CCRH &= (uint8_t)(~I2C_CCRH_DUTY);
00420   }
00421 }
00422
00423 /**
00424   * @brief  Returns the most recent received data.
00425   * @param  None
00426   * @retval uint8_t : The value of the received byte data.
00427   */
00428 uint8_t I2C_ReceiveData(void)
00429 {
00430   /* Return the data present in the DR register */
00431   return ((uint8_t)I2C->DR);
00432 }
00433
00434 /**
00435   * @brief  Transmits the 7-bit address (to select the) slave device.
00436   * @param   Address : Specifies the slave address which will be transmitted.
00437   * @param   Direction : Specifies whether the I2C device will be a Transmitter or a Receiver.
00438   * This parameter can be any of the @ref I2C_Direction_TypeDef enumeration.
00439   * @retval None
00440   */
00441 void I2C_Send7bitAddress(uint8_t Address, I2C_Direction_TypeDef Direction)
00442 {
00443   /* Check function parameters */
00444   assert_param(IS_I2C_ADDRESS_OK(Address));
00445   assert_param(IS_I2C_DIRECTION_OK(Direction));
00446
00447   /* Clear bit0 (direction) just in case */
00448   Address &= (uint8_t)0xFE;
00449
00450   /* Send the Address + Direction */
00451   I2C->DR = (uint8_t)(Address | (uint8_t)Direction);
00452 }
00453
00454 /**
00455   * @brief  Send a byte by writing in the DR register.
00456   * @param   Data : Byte to be sent.
00457   * @retval None
00458   */
00459 void I2C_SendData(uint8_t Data)
00460 {
00461   /* Write in the DR register the data to be sent */
00462   I2C->DR = Data;
00463 }
00464
00465 /**
00466  * @brief
00467  ****************************************************************************************
00468  *
00469  *                         I2C State Monitoring Functions
00470  *
00471  ****************************************************************************************
00472  * This I2C driver provides three different ways for I2C state monitoring
00473  *  depending on the application requirements and constraints:
00474  *
00475  *
00476  * 1) Basic state monitoring:
00477  *    Using I2C_CheckEvent() function:
00478  *    It compares the status registers (SR1, SR2 and SR3) content to a given event
00479  *    (can be the combination of one or more flags).
00480  *    It returns SUCCESS if the current status includes the given flags
00481  *    and returns ERROR if one or more flags are missing in the current status.
00482  *    - When to use:
00483  *      - This function is suitable for most applications as well as for startup
00484  *      activity since the events are fully described in the product reference manual
00485  *      (RM0016).
00486  *      - It is also suitable for users who need to define their own events.
00487  *    - Limitations:
00488  *      - If an error occurs (ie. error flags are set besides to the monitored flags),
00489  *        the I2C_CheckEvent() function may return SUCCESS despite the communication
00490  *        hold or corrupted real state.
00491  *        In this case, it is advised to use error interrupts to monitor the error
00492  *        events and handle them in the interrupt IRQ handler.
00493  *
00494  *        @note
00495  *        For error management, it is advised to use the following functions:
00496  *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
00497  *          - I2C_IRQHandler() which is called when the I2C interurpts occur.
00498  *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
00499  *           I2C_IRQHandler() function in order to determine which error occured.
00500  *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
00501  *            and/or I2C_GenerateStop() in order to clear the error flag and
00502  *            source and return to correct communication status.
00503  *
00504  *
00505  *  2) Advanced state monitoring:
00506  *     Using the function I2C_GetLastEvent() which returns the image of both SR1
00507  *     & SR3 status registers in a single word (uint16_t) (Status Register 3 value
00508  *     is shifted left by 8 bits and concatenated to Status Register 1).
00509  *     - When to use:
00510  *       - This function is suitable for the same applications above but it allows to
00511  *         overcome the limitations of I2C_GetFlagStatus() function (see below).
00512  *         The returned value could be compared to events already defined in the
00513  *         library (stm8s_i2c.h) or to custom values defined by user.
00514  *       - This function is suitable when multiple flags are monitored at the same time.
00515  *       - At the opposite of I2C_CheckEvent() function, this function allows user to
00516  *         choose when an event is accepted (when all events flags are set and no
00517  *         other flags are set or just when the needed flags are set like
00518  *         I2C_CheckEvent() function).
00519  *     - Limitations:
00520  *       - User may need to define his own events.
00521  *       - Same remark concerning the error management is applicable for this
00522  *         function if user decides to check only regular communication flags (and
00523  *         ignores error flags).
00524  *
00525  *
00526  *  3) Flag-based state monitoring:
00527  *     Using the function I2C_GetFlagStatus() which simply returns the status of
00528  *     one single flag (ie. I2C_FLAG_RXNE ...).
00529  *     - When to use:
00530  *        - This function could be used for specific applications or in debug phase.
00531  *        - It is suitable when only one flag checking is needed (most I2C events
00532  *          are monitored through multiple flags).
00533  *     - Limitations:
00534  *        - When calling this function, the Status register is accessed. Some flags are
00535  *          cleared when the status register is accessed. So checking the status
00536  *          of one Flag, may clear other ones.
00537  *        - Function may need to be called twice or more in order to monitor one
00538  *          single event.
00539  *
00540  *  For detailed description of Events, please refer to section I2C_Events in
00541  *  stm8s_i2c.h file.
00542  *
00543  */
00544 /**
00545  *
00546  *  1) Basic state monitoring
00547  *******************************************************************************
00548  */
00549
00550 /**
00551   * @brief  Checks whether the last I2C Event is equal to the one passed
00552   *   as parameter.
00553   * @param  I2C_EVENT: specifies the event to be checked.
00554   *   This parameter can be one of the following values:
00555   *     @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED           : EV1
00556   *     @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED              : EV1
00557   *     @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED            : EV1
00558   *     @arg I2C_EVENT_SLAVE_BYTE_RECEIVED                         : EV2
00559   *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)    : EV2
00560   *     @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED                      : EV3
00561   *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
00562   *     @arg I2C_EVENT_SLAVE_ACK_FAILURE                           : EV3_2
00563   *     @arg I2C_EVENT_SLAVE_STOP_DETECTED                         : EV4
00564   *     @arg I2C_EVENT_MASTER_MODE_SELECT                          : EV5
00565   *     @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED            : EV6
00566   *     @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED               : EV6
00567   *     @arg I2C_EVENT_MASTER_BYTE_RECEIVED                        : EV7
00568   *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING                    : EV8
00569   *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED                     : EV8_2
00570   *     @arg I2C_EVENT_MASTER_MODE_ADDRESS10                       : EV9
00571   *
00572   * @note: For detailed description of Events, please refer to section
00573   *    I2C_Events in stm8s_i2c.h file.
00574   *
00575   * @retval An ErrorStatus enumeration value:
00576   * - SUCCESS: Last event is equal to the I2C_EVENT
00577   * - ERROR: Last event is different from the I2C_EVENT
00578   */
00579 ErrorStatus I2C_CheckEvent(I2C_Event_TypeDef I2C_Event)
00580 {
00581   __IO uint16_t lastevent = 0x00;
00582   uint8_t flag1 = 0x00 ;
00583   uint8_t flag2 = 0x00;
00584   ErrorStatus status = ERROR;
00585
00586   /* Check the parameters */
00587   assert_param(IS_I2C_EVENT_OK(I2C_Event));
00588
00589   if (I2C_Event == I2C_EVENT_SLAVE_ACK_FAILURE)
00590   {
00591     lastevent = I2C->SR2 & I2C_SR2_AF;
00592   }
00593   else
00594   {
00595     flag1 = I2C->SR1;
00596     flag2 = I2C->SR3;
00597     lastevent = ((uint16_t)((uint16_t)flag2 << (uint16_t)8) | (uint16_t)flag1);
00598   }
00599   /* Check whether the last event is equal to I2C_EVENT */
00600   if (((uint16_t)lastevent & (uint16_t)I2C_Event) == (uint16_t)I2C_Event)
00601   {
00602     /* SUCCESS: last event is equal to I2C_EVENT */
00603     status = SUCCESS;
00604   }
00605   else
00606   {
00607     /* ERROR: last event is different from I2C_EVENT */
00608     status = ERROR;
00609   }
00610
00611   /* Return status */
00612   return status;
00613 }
00614
00615 /**
00616  *
00617  *  2) Advanced state monitoring
00618  *******************************************************************************
00619  */
00620 /**
00621   * @brief  Returns the last I2C Event.
00622   *
00623   * @note: For detailed description of Events, please refer to section
00624   *    I2C_Events in stm8s_i2c.h file.
00625   *
00626   * @retval The last event
00627   *   This parameter can be any of the  @ref I2C_Event_TypeDef enumeration.
00628   */
00629 I2C_Event_TypeDef I2C_GetLastEvent(void)
00630 {
00631   __IO uint16_t lastevent = 0;
00632   uint16_t flag1 = 0;
00633   uint16_t flag2 = 0;
00634
00635   if ((I2C->SR2 & I2C_SR2_AF) != 0x00)
00636   {
00637     lastevent = I2C_EVENT_SLAVE_ACK_FAILURE;
00638   }
00639   else
00640   {
00641     /* Read the I2C status register */
00642     flag1 = I2C->SR1;
00643     flag2 = I2C->SR3;
00644
00645     /* Get the last event value from I2C status register */
00646     lastevent = ((uint16_t)((uint16_t)flag2 << 8) | (uint16_t)flag1);
00647   }
00648   /* Return status */
00649   return (I2C_Event_TypeDef)lastevent;
00650 }
00651
00652 /**
00653  *
00654  *  3) Flag-based state monitoring
00655  *******************************************************************************
00656  */
00657 /**
00658   * @brief  Checks whether the specified I2C flag is set or not.
00659   * @param  I2C_FLAG: specifies the flag to check.
00660   *   This parameter can be one of the following values:
00661   *     @arg I2C_FLAG_GENERALCALL: General call header flag (Slave mode)
00662   *     @arg I2C_FLAG_TRANSMITTERRECEIVER: Transmitter/Receiver flag
00663   *     @arg I2C_FLAG_BUSBUSY: Bus busy flag
00664   *     @arg I2C_FLAG_MASTERSLAVE: Master/Slave flag
00665   *     @arg I2C_FLAG_WAKEUPFROMHALT: Wake up from HALT flag
00666   *     @arg I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
00667   *     @arg I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
00668   *     @arg I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
00669   *     @arg I2C_FLAG_BUSERROR: Bus error flag
00670   *     @arg I2C_FLAG_TXEMPTY: Data register empty flag (Transmitter)
00671   *     @arg I2C_FLAG_RXNOTEMPTY: Data register not empty (Receiver) flag
00672   *     @arg I2C_FLAG_STOPDETECTION: Stop detection flag (Slave mode)
00673   *     @arg I2C_FLAG_HEADERSENT: 10-bit header sent flag (Master mode)
00674   *     @arg I2C_FLAG_TRANSFERFINISHED: Byte transfer finished flag
00675   *     @arg I2C_FLAG_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL”
00676   *   Address matched flag (Slave mode)”ENDAD”
00677   *     @arg I2C_FLAG_STARTDETECTION: Start bit flag (Master mode)
00678   * @retval The new state of I2C_FLAG (SET or RESET).
00679   */
00680 FlagStatus I2C_GetFlagStatus(I2C_Flag_TypeDef I2C_Flag)
00681 {
00682   uint8_t tempreg = 0;
00683   uint8_t regindex = 0;
00684   FlagStatus bitstatus = RESET;
00685
00686   /* Check the parameters */
00687   assert_param(IS_I2C_FLAG_OK(I2C_Flag));
00688
00689   /* Read flag register index */
00690   regindex = (uint8_t)((uint16_t)I2C_Flag >> 8);
00691   /* Check SRx index */
00692   switch (regindex)
00693   {
00694       /* Returns whether the status register to check is SR1 */
00695     case 0x01:
00696       tempreg = (uint8_t)I2C->SR1;
00697       break;
00698
00699       /* Returns whether the status register to check is SR2 */
00700     case 0x02:
00701       tempreg = (uint8_t)I2C->SR2;
00702       break;
00703
00704       /* Returns whether the status register to check is SR3 */
00705     case 0x03:
00706       tempreg = (uint8_t)I2C->SR3;
00707       break;
00708
00709     default:
00710       break;
00711   }
00712
00713   /* Check the status of the specified I2C flag */
00714   if ((tempreg & (uint8_t)I2C_Flag ) != 0)
00715   {
00716     /* Flag is set */
00717     bitstatus = SET;
00718   }
00719   else
00720   {
00721     /* Flag is reset */
00722     bitstatus = RESET;
00723   }
00724   /* Return the flag status */
00725   return bitstatus;
00726 }
00727
00728 /**
00729   * @brief  Clear flags
00730   * @param  I2C_Flag : Specifies the flag to clear
00731   *   This parameter can be any combination of the following values:
00732   *                       - I2C_FLAG_WAKEUPFROMHALT: Wakeup from Halt
00733   *                       - I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
00734   *                       - I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag
00735   *                       - I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
00736   *                       - I2C_FLAG_BUSERROR: Bus error flag.
00737   * @note Notes:
00738   *                       - STOPF (STOP detection) is cleared by software
00739   *                         sequence: a read operation to I2C_SR1 register
00740   *                         (I2C_GetFlagStatus()) followed by a write operation
00741   *                         to I2C_CR2 register.
00742   *                       - ADD10 (10-bit header sent) is cleared by software
00743   *                         sequence: a read operation to I2C_SR1
00744   *                         (I2C_GetFlagStatus()) followed by writing the
00745   *                         second byte of the address in DR register.
00746   *                       - BTF (Byte Transfer Finished) is cleared by software
00747   *                         sequence: a read operation to I2C_SR1 register
00748   *                         (I2C_GetFlagStatus()) followed by a read/write to
00749   *                         I2C_DR register (I2C_SendData()).
00750   *                       - ADDR (Address sent) is cleared by software sequence:
00751   *                         a read operation to I2C_SR1 register
00752   *                         (I2C_GetFlagStatus()) followed by a read operation to
00753   *                         I2C_SR3 register ((void)(I2C->SR3)).
00754   *                       - SB (Start Bit) is cleared software sequence: a read
00755   *                         operation to I2C_SR1 register (I2C_GetFlagStatus())
00756   *                         followed by a write operation to I2C_DR register
00757   *                         (I2C_SendData()).
00758   * @retval None
00759   */
00760 void I2C_ClearFlag(I2C_Flag_TypeDef I2C_FLAG)
00761 {
00762   uint16_t flagpos = 0;
00763   /* Check the parameters */
00764   assert_param(IS_I2C_CLEAR_FLAG_OK(I2C_FLAG));
00765
00766   /* Get the I2C flag position */
00767   flagpos = (uint16_t)I2C_FLAG & FLAG_Mask;
00768   /* Clear the selected I2C flag */
00769   I2C->SR2 = (uint8_t)((uint16_t)(~flagpos));
00770 }
00771
00772 /**
00773   * @brief  Checks whether the specified I2C interrupt has occurred or not.
00774   * @param  I2C_ITPendingBit: specifies the interrupt source to check.
00775   *            This parameter can be one of the following values:
00776   *               - I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
00777   *               - I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)
00778   *               - I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure flag
00779   *               - I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost flag (Master mode)
00780   *               - I2C_ITPENDINGBIT_BUSERROR: Bus error flag
00781   *               - I2C_ITPENDINGBIT_TXEMPTY: Data register empty flag (Transmitter)
00782   *               - I2C_ITPENDINGBIT_RXNOTEMPTY: Data register not empty (Receiver) flag
00783   *               - I2C_ITPENDINGBIT_STOPDETECTION: Stop detection flag (Slave mode)
00784   *               - I2C_ITPENDINGBIT_HEADERSENT: 10-bit header sent flag (Master mode)
00785   *               - I2C_ITPENDINGBIT_TRANSFERFINISHED: Byte transfer finished flag
00786   *               - I2C_ITPENDINGBIT_ADDRESSSENTMATCHED: Address sent flag (Master mode) “ADSL”
00787   *                              Address matched flag (Slave mode)“ENDAD”
00788   *               - I2C_ITPENDINGBIT_STARTDETECTION: Start bit flag (Master mode)
00789   * @retval The new state of I2C_ITPendingBit
00790   *   This parameter can be any of the @ref ITStatus enumeration.
00791   */
00792 ITStatus I2C_GetITStatus(I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
00793 {
00794   ITStatus bitstatus = RESET;
00795   __IO uint8_t enablestatus = 0;
00796   uint16_t tempregister = 0;
00797
00798     /* Check the parameters */
00799     assert_param(IS_I2C_ITPENDINGBIT_OK(I2C_ITPendingBit));
00800
00801   tempregister = (uint8_t)( ((uint16_t)((uint16_t)I2C_ITPendingBit & ITEN_Mask)) >> 8);
00802
00803   /* Check if the interrupt source is enabled or not */
00804   enablestatus = (uint8_t)(I2C->ITR & ( uint8_t)tempregister);
00805
00806   if ((uint16_t)((uint16_t)I2C_ITPendingBit & REGISTER_Mask) == REGISTER_SR1_Index)
00807   {
00808     /* Check the status of the specified I2C flag */
00809     if (((I2C->SR1 & (uint8_t)I2C_ITPendingBit) != RESET) && enablestatus)
00810     {
00811       /* I2C_IT is set */
00812       bitstatus = SET;
00813     }
00814     else
00815     {
00816       /* I2C_IT is reset */
00817       bitstatus = RESET;
00818     }
00819   }
00820   else
00821   {
00822     /* Check the status of the specified I2C flag */
00823     if (((I2C->SR2 & (uint8_t)I2C_ITPendingBit) != RESET) && enablestatus)
00824     {
00825       /* I2C_IT is set */
00826       bitstatus = SET;
00827     }
00828     else
00829     {
00830       /* I2C_IT is reset */
00831       bitstatus = RESET;
00832     }
00833   }
00834   /* Return the I2C_IT status */
00835   return  bitstatus;
00836
00837 }
00838
00839 /**
00840   * @brief  Clear IT pending bit
00841   * @param  I2C_IT: specifies the interrupt pending bit to clear.
00842   *            This parameter can be any combination of the following values:
00843   *                 - I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt
00844   *                 - I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun interrupt (Slave mode)
00845   *                 - I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure interrupt
00846   *                 - I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost interrupt (Master mode)
00847   *                 - I2C_ITPENDINGBIT_BUSERROR: Bus error interrupt
00848   *
00849   *             Notes:
00850   *                  - STOPF (STOP detection) is cleared by software
00851   *                    sequence: a read operation to I2C_SR1 register
00852   *                    (I2C_GetITStatus()) followed by a write operation to
00853   *                    I2C_CR2 register (I2C_AcknowledgeConfig() to configure
00854   *                    the I2C peripheral Acknowledge).
00855   *                  - ADD10 (10-bit header sent) is cleared by software
00856   *                    sequence: a read operation to I2C_SR1
00857   *                    (I2C_GetITStatus()) followed by writing the second
00858   *                    byte of the address in I2C_DR register.
00859   *                  - BTF (Byte Transfer Finished) is cleared by software
00860   *                    sequence: a read operation to I2C_SR1 register
00861   *                    (I2C_GetITStatus()) followed by a read/write to
00862   *                    I2C_DR register (I2C_SendData()).
00863   *                  - ADDR (Address sent) is cleared by software sequence:
00864   *                    a read operation to I2C_SR1 register (I2C_GetITStatus())
00865   *                    followed by a read operation to I2C_SR3 register
00866   *                    ((void)(I2C->SR3)).
00867   *                  - SB (Start Bit) is cleared by software sequence: a
00868   *                    read operation to I2C_SR1 register (I2C_GetITStatus())
00869   *                    followed by a write operation to I2C_DR register
00870   *                    (I2C_SendData()).
00871   * @retval None
00872   */
00873 void I2C_ClearITPendingBit(I2C_ITPendingBit_TypeDef I2C_ITPendingBit)
00874 {
00875   uint16_t flagpos = 0;
00876
00877   /* Check the parameters */
00878   assert_param(IS_I2C_CLEAR_ITPENDINGBIT_OK(I2C_ITPendingBit));
00879
00880   /* Get the I2C flag position */
00881   flagpos = (uint16_t)I2C_ITPendingBit & FLAG_Mask;
00882
00883   /* Clear the selected I2C flag */
00884   I2C->SR2 = (uint8_t)((uint16_t)~flagpos);
00885 }
00886
00887 /**
00888   * @}
00889   */
00890
00891 /**
00892   * @}
00893   */
00894 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_i2c.h Source File

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stm8s_i2c.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_i2c.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief  This file contains all functions prototype and macros for the I2C peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_I2C_H
00024 #define __STM8S_I2C_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030
00031 /** @addtogroup I2C_Exported_Types
00032   * @{
00033   */
00034
00035 /**
00036   * @brief  I2C duty cycle (fast mode only)
00037   */
00038 typedef enum
00039 {
00040   I2C_DUTYCYCLE_2    = (uint8_t)0x00,  /*!< Fast mode Tlow/THigh = 2 */
00041   I2C_DUTYCYCLE_16_9 = (uint8_t)0x40   /*!< Fast mode Tlow/Thigh = 16/9 */
00042 } I2C_DutyCycle_TypeDef;
00043
00044 /**
00045   * @brief  I2C Acknowledgement configuration
00046   */
00047 typedef enum
00048 {
00049   I2C_ACK_NONE = (uint8_t)0x00,  /*!< No acknowledge */
00050   I2C_ACK_CURR = (uint8_t)0x01,  /*!< Acknowledge on the current byte */
00051   I2C_ACK_NEXT = (uint8_t)0x02   /*!< Acknowledge on the next byte */
00052 } I2C_Ack_TypeDef;
00053
00054 /**
00055   * @brief  I2C Addressing Mode (slave mode only)
00056   */
00057 typedef enum
00058 {
00059   I2C_ADDMODE_7BIT  = (uint8_t)0x00,  /*!< 7-bit slave address (10-bit address not acknowledged) */
00060   I2C_ADDMODE_10BIT = (uint8_t)0x80   /*!< 10-bit slave address (7-bit address not acknowledged) */
00061 } I2C_AddMode_TypeDef;
00062
00063 /**
00064   * @brief  I2C Interrupt sources
00065   * Warning: the values correspond to the bit position in the ITR register
00066   */
00067 typedef enum
00068 {
00069     I2C_IT_ERR     = (uint8_t)0x01,     /*!< Error Interruption */
00070     I2C_IT_EVT     = (uint8_t)0x02,     /*!< Event Interruption */
00071     I2C_IT_BUF     = (uint8_t)0x04      /*!< Buffer Interruption */
00072 } I2C_IT_TypeDef;
00073
00074 /**
00075   * @brief  I2C transfer direction
00076   * Warning: the values correspond to the ADD0 bit position in the OARL register
00077   */
00078 typedef enum
00079 {
00080   I2C_DIRECTION_TX = (uint8_t)0x00,  /*!< Transmission direction */
00081   I2C_DIRECTION_RX = (uint8_t)0x01   /*!< Reception direction */
00082 } I2C_Direction_TypeDef;
00083
00084 /**
00085   * @brief  I2C Flags
00086   * @brief Elements values convention: 0xXXYY
00087   *  X = SRx registers index
00088   *      X = 1 : SR1
00089   *      X = 2 : SR2
00090   *      X = 3 : SR3
00091   *  Y = Flag mask in the register
00092   */
00093
00094 typedef enum
00095 {
00096   /* SR1 register flags */
00097   I2C_FLAG_TXEMPTY             = (uint16_t)0x0180,  /*!< Transmit Data Register Empty flag */
00098   I2C_FLAG_RXNOTEMPTY          = (uint16_t)0x0140,  /*!< Read Data Register Not Empty flag */
00099   I2C_FLAG_STOPDETECTION       = (uint16_t)0x0110,  /*!< Stop detected flag */
00100   I2C_FLAG_HEADERSENT          = (uint16_t)0x0108,  /*!< 10-bit Header sent flag */
00101   I2C_FLAG_TRANSFERFINISHED    = (uint16_t)0x0104,  /*!< Data Byte Transfer Finished flag */
00102   I2C_FLAG_ADDRESSSENTMATCHED  = (uint16_t)0x0102,  /*!< Address Sent/Matched (master/slave) flag */
00103   I2C_FLAG_STARTDETECTION      = (uint16_t)0x0101,  /*!< Start bit sent flag */
00104
00105   /* SR2 register flags */
00106   I2C_FLAG_WAKEUPFROMHALT      = (uint16_t)0x0220,  /*!< Wake Up From Halt Flag */
00107   I2C_FLAG_OVERRUNUNDERRUN     = (uint16_t)0x0208,  /*!< Overrun/Underrun flag */
00108   I2C_FLAG_ACKNOWLEDGEFAILURE  = (uint16_t)0x0204,  /*!< Acknowledge Failure Flag */
00109   I2C_FLAG_ARBITRATIONLOSS     = (uint16_t)0x0202,  /*!< Arbitration Loss Flag */
00110   I2C_FLAG_BUSERROR            = (uint16_t)0x0201,  /*!< Misplaced Start or Stop condition */
00111
00112   /* SR3 register flags */
00113   I2C_FLAG_GENERALCALL         = (uint16_t)0x0310,  /*!< General Call header received Flag */
00114   I2C_FLAG_TRANSMITTERRECEIVER = (uint16_t)0x0304,  /*!< Transmitter Receiver Flag */
00115   I2C_FLAG_BUSBUSY             = (uint16_t)0x0302,  /*!< Bus Busy Flag */
00116   I2C_FLAG_MASTERSLAVE         = (uint16_t)0x0301   /*!< Master Slave Flag */
00117 } I2C_Flag_TypeDef;
00118
00119 /**
00120   * @brief I2C Pending bits
00121   * Elements values convention: 0xXYZZ
00122   *  X = SRx registers index
00123   *      X = 1 : SR1
00124   *      X = 2 : SR2
00125   *  Y = Position of the corresponding Interrupt
00126   *  ZZ = flag mask in the dedicated register(X register)
00127   */
00128
00129 typedef enum
00130 {
00131     /* SR1 register flags */
00132     I2C_ITPENDINGBIT_TXEMPTY             = (uint16_t)0x1680,    /*!< Transmit Data Register Empty  */
00133     I2C_ITPENDINGBIT_RXNOTEMPTY          = (uint16_t)0x1640,    /*!< Read Data Register Not Empty  */
00134     I2C_ITPENDINGBIT_STOPDETECTION       = (uint16_t)0x1210,    /*!< Stop detected  */
00135     I2C_ITPENDINGBIT_HEADERSENT          = (uint16_t)0x1208,    /*!< 10-bit Header sent */
00136     I2C_ITPENDINGBIT_TRANSFERFINISHED    = (uint16_t)0x1204,    /*!< Data Byte Transfer Finished  */
00137     I2C_ITPENDINGBIT_ADDRESSSENTMATCHED  = (uint16_t)0x1202,    /*!< Address Sent/Matched (master/slave)  */
00138     I2C_ITPENDINGBIT_STARTDETECTION      = (uint16_t)0x1201,    /*!< Start bit sent  */
00139
00140     /* SR2 register flags */
00141     I2C_ITPENDINGBIT_WAKEUPFROMHALT      = (uint16_t)0x2220,    /*!< Wake Up From Halt  */
00142     I2C_ITPENDINGBIT_OVERRUNUNDERRUN     = (uint16_t)0x2108,    /*!< Overrun/Underrun  */
00143     I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE  = (uint16_t)0x2104,    /*!< Acknowledge Failure  */
00144     I2C_ITPENDINGBIT_ARBITRATIONLOSS     = (uint16_t)0x2102,    /*!< Arbitration Loss  */
00145     I2C_ITPENDINGBIT_BUSERROR            = (uint16_t)0x2101     /*!< Misplaced Start or Stop condition */
00146 } I2C_ITPendingBit_TypeDef;
00147
00148 /**
00149   * @brief I2C possible events
00150   * Values convention: 0xXXYY
00151   * XX = Event SR3 corresponding value
00152   * YY = Event SR1 corresponding value
00153   * @note if Event = EV3_2 the rule above does not apply
00154   * YY = Event SR2 corresponding value
00155   */
00156
00157 typedef enum
00158 {
00159   /*========================================
00160
00161                        I2C Master Events (Events grouped in order of communication)
00162                                                           ==========================================*/
00163   /**
00164     * @brief  Communication start
00165     *
00166     * After sending the START condition (I2C_GenerateSTART() function) the master
00167     * has to wait for this event. It means that the Start condition has been correctly
00168     * released on the I2C bus (the bus is free, no other devices is communicating).
00169     *
00170     */
00171   /* --EV5 */
00172   I2C_EVENT_MASTER_MODE_SELECT               = (uint16_t)0x0301,  /*!< BUSY, MSL and SB flag */
00173
00174   /**
00175     * @brief  Address Acknowledge
00176     *
00177     * After checking on EV5 (start condition correctly released on the bus), the
00178     * master sends the address of the slave(s) with which it will communicate
00179     * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
00180     * Master transmitter or Receiver).
00181     * Then the master has to wait that a slave acknowledges his address.
00182     * If an acknowledge is sent on the bus, one of the following events will
00183     * be set:
00184     *
00185     *  1) In case of Master Receiver (7-bit addressing):
00186     *  the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.
00187     *
00188     *  2) In case of Master Transmitter (7-bit addressing):
00189     *  the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set
00190     *
00191     *  3) In case of 10-Bit addressing mode, the master (just after generating the START
00192     *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
00193     *  function).
00194     *  Then master should wait on EV9. It means that the 10-bit addressing
00195     *  header has been correctly sent on the bus.
00196     *  Then master should send the second part of the 10-bit address (LSB) using
00197     *  the function I2C_Send7bitAddress(). Then master should wait for event EV6.
00198     *
00199     */
00200   /* --EV6 */
00201   I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782,  /*!< BUSY, MSL, ADDR, TXE and TRA flags */
00202   I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED    = (uint16_t)0x0302,  /*!< BUSY, MSL and ADDR flags */
00203   /* --EV9 */
00204   I2C_EVENT_MASTER_MODE_ADDRESS10            = (uint16_t)0x0308,  /*!< BUSY, MSL and ADD10 flags */
00205
00206   /**
00207     * @brief Communication events
00208     *
00209     * If a communication is established (START condition generated and slave address
00210     * acknowledged) then the master has to check on one of the following events for
00211     * communication procedures:
00212     *
00213     * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
00214     *    the data received from the slave (I2C_ReceiveData() function).
00215     *
00216     * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
00217     *    function) then to wait on event EV8 or EV8_2.
00218     *    These two events are similar:
00219     *     - EV8 means that the data has been written in the data register and is
00220     *       being shifted out.
00221     *     - EV8_2 means that the data has been physically shifted out and output
00222     *       on the bus.
00223     *     In most cases, using EV8 is sufficient for the application.
00224     *     Using EV8_2 leads to a slower communication but ensures more reliable test.
00225     *     EV8_2 is also more suitable than EV8 for testing on the last data transmission
00226     *     (before Stop condition generation).
00227     *
00228     *  @note In case the user software does not guarantee that this event EV7 is
00229     *  managed before the current byte end of transfer, then user may check on EV7
00230     *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
00231     *  In this case the communication may be slower.
00232     *
00233     */
00234   /* Master RECEIVER mode -----------------------------*/
00235   /* --EV7 */
00236   I2C_EVENT_MASTER_BYTE_RECEIVED             = (uint16_t)0x0340,  /*!< BUSY, MSL and RXNE flags */
00237
00238   /* Master TRANSMITTER mode --------------------------*/
00239   /* --EV8 */
00240   I2C_EVENT_MASTER_BYTE_TRANSMITTING         = (uint16_t)0x0780,  /*!< TRA, BUSY, MSL, TXE flags */
00241   /* --EV8_2 */
00242
00243   I2C_EVENT_MASTER_BYTE_TRANSMITTED          = (uint16_t)0x0784,  /*!< EV8_2: TRA, BUSY, MSL, TXE and BTF flags */
00244
00245
00246   /*========================================
00247
00248                        I2C Slave Events (Events grouped in order of communication)
00249                                                           ==========================================*/
00250
00251   /**
00252     * @brief  Communication start events
00253     *
00254     * Wait on one of these events at the start of the communication. It means that
00255     * the I2C peripheral detected a Start condition on the bus (generated by master
00256     * device) followed by the peripheral address.
00257     * The peripheral generates an ACK condition on the bus (if the acknowledge
00258     * feature is enabled through function I2C_AcknowledgeConfig()) and the events
00259     * listed above are set :
00260     *
00261     * 1) In normal case (only one address managed by the slave), when the address
00262     *   sent by the master matches the own address of the peripheral (configured by
00263     *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
00264     *   (where XXX could be TRANSMITTER or RECEIVER).
00265     *
00266     * 2) In case the address sent by the master is General Call (address 0x00) and
00267     *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
00268     *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
00269     *
00270     */
00271
00272   /* --EV1  (all the events below are variants of EV1) */
00273   /* 1) Case of One Single Address managed by the slave */
00274   I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED    = (uint16_t)0x0202,  /*!< BUSY and ADDR flags */
00275   I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682,  /*!< TRA, BUSY, TXE and ADDR flags */
00276
00277   /* 2) Case of General Call enabled for the slave */
00278   I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED  = (uint16_t)0x1200,  /*!< EV2: GENCALL and BUSY flags */
00279
00280   /**
00281     * @brief  Communication events
00282     *
00283     * Wait on one of these events when EV1 has already been checked :
00284     *
00285     * - Slave RECEIVER mode:
00286     *     - EV2: When the application is expecting a data byte to be received.
00287     *     - EV4: When the application is expecting the end of the communication:
00288     *       master sends a stop condition and data transmission is stopped.
00289     *
00290     * - Slave Transmitter mode:
00291     *    - EV3: When a byte has been transmitted by the slave and the application
00292     *      is expecting the end of the byte transmission.
00293     *      The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING
00294     *      are similar. The second one can optionally be used when the user software
00295     *      doesn't guarantee the EV3 is managed before the current byte end of tranfer.
00296     *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission
00297     *      shall end (before sending the STOP condition).
00298     *      In this case slave has to stop sending data bytes and expect a Stop
00299     *      condition on the bus.
00300     *
00301     *  @note In case the  user software does not guarantee that the event EV2 is
00302     *  managed before the current byte end of transfer, then user may check on EV2
00303     *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
00304     *  In this case the communication may be slower.
00305     *
00306     */
00307   /* Slave RECEIVER mode --------------------------*/
00308   /* --EV2 */
00309   I2C_EVENT_SLAVE_BYTE_RECEIVED              = (uint16_t)0x0240,  /*!< BUSY and RXNE flags */
00310   /* --EV4  */
00311   I2C_EVENT_SLAVE_STOP_DETECTED              = (uint16_t)0x0010,  /*!< STOPF flag */
00312
00313   /* Slave TRANSMITTER mode -----------------------*/
00314   /* --EV3 */
00315   I2C_EVENT_SLAVE_BYTE_TRANSMITTED           = (uint16_t)0x0684,  /*!< TRA, BUSY, TXE and BTF flags */
00316   I2C_EVENT_SLAVE_BYTE_TRANSMITTING          = (uint16_t)0x0680,  /*!< TRA, BUSY and TXE flags */
00317   /* --EV3_2 */
00318   I2C_EVENT_SLAVE_ACK_FAILURE                = (uint16_t)0x0004  /*!< AF flag */
00319 } I2C_Event_TypeDef;
00320
00321 /**
00322   * @}
00323   */
00324
00325 /* Exported constants --------------------------------------------------------*/
00326 /** @addtogroup I2C_Exported_Constants
00327   * @{
00328   */
00329 #define I2C_MAX_STANDARD_FREQ ((uint32_t)100000)
00330 #define I2C_MAX_FAST_FREQ     ((uint32_t)400000)
00331 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007)
00332  #define I2C_MAX_INPUT_FREQ     ((uint8_t)24)
00333 #else
00334  #define I2C_MAX_INPUT_FREQ     ((uint8_t)16)
00335 #endif
00336
00337 /**
00338   *@}
00339   */
00340
00341 /* Exported macros -----------------------------------------------------------*/
00342 /* Private macros ------------------------------------------------------------*/
00343
00344 /** @addtogroup I2C_Private_Macros
00345   * @{
00346   */
00347
00348 /**
00349   * @brief  Macro used by the assert function to check the different functions parameters.
00350   */
00351
00352 /**
00353   * @brief   Macro used by the assert function to check the different I2C duty cycles.
00354   */
00355 #define IS_I2C_DUTYCYCLE_OK(DUTY) \
00356   (((DUTY) == I2C_DUTYCYCLE_2) || \
00357    ((DUTY) == I2C_DUTYCYCLE_16_9))
00358
00359 /**
00360   * @brief   Macro used by the assert function to check the different acknowledgement configuration
00361   */
00362 #define IS_I2C_ACK_OK(ACK) \
00363   (((ACK) == I2C_ACK_NONE) || \
00364    ((ACK) == I2C_ACK_CURR) || \
00365    ((ACK) == I2C_ACK_NEXT))
00366
00367 /**
00368   * @brief   Macro used by the assert function to check the different I2C addressing modes.
00369   */
00370 #define IS_I2C_ADDMODE_OK(ADDMODE) \
00371   (((ADDMODE) == I2C_ADDMODE_7BIT) || \
00372    ((ADDMODE) == I2C_ADDMODE_10BIT))
00373
00374 /**
00375   * @brief   Macro used by the assert function to check the different I2C interrupt types.
00376   */
00377 #define IS_I2C_INTERRUPT_OK(IT) \
00378   (((IT) == I2C_IT_ERR)     || \
00379    ((IT) == I2C_IT_EVT)     || \
00380    ((IT) == I2C_IT_BUF)     || \
00381    ((IT) == (I2C_IT_ERR | I2C_IT_EVT)) || \
00382    ((IT) == (I2C_IT_ERR | I2C_IT_BUF)) || \
00383    ((IT) == (I2C_IT_EVT | I2C_IT_BUF)) || \
00384    ((IT) == (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR)))
00385 /**
00386   * @brief   Macro used by the assert function to check the different I2C communcation direction.
00387   */
00388 #define IS_I2C_DIRECTION_OK(DIR) \
00389   (((DIR) == I2C_DIRECTION_TX) || \
00390    ((DIR) == I2C_DIRECTION_RX))
00391
00392 /**
00393   * @brief   Macro used by the assert function to check the different I2C flags.
00394   */
00395 #define IS_I2C_FLAG_OK(FLAG) \
00396   (((FLAG) == I2C_FLAG_TXEMPTY)         || \
00397    ((FLAG) == I2C_FLAG_RXNOTEMPTY)       || \
00398    ((FLAG) == I2C_FLAG_STOPDETECTION)      || \
00399    ((FLAG) == I2C_FLAG_HEADERSENT)       || \
00400    ((FLAG) == I2C_FLAG_TRANSFERFINISHED)   || \
00401    ((FLAG) == I2C_FLAG_ADDRESSSENTMATCHED)  || \
00402    ((FLAG) == I2C_FLAG_STARTDETECTION)    || \
00403    ((FLAG) == I2C_FLAG_WAKEUPFROMHALT)    || \
00404    ((FLAG) == I2C_FLAG_OVERRUNUNDERRUN)    || \
00405    ((FLAG) == I2C_FLAG_ACKNOWLEDGEFAILURE)  || \
00406    ((FLAG) == I2C_FLAG_ARBITRATIONLOSS)    || \
00407    ((FLAG) == I2C_FLAG_BUSERROR)       || \
00408    ((FLAG) == I2C_FLAG_GENERALCALL)      || \
00409    ((FLAG) == I2C_FLAG_TRANSMITTERRECEIVER) || \
00410    ((FLAG) == I2C_FLAG_BUSBUSY) || \
00411    ((FLAG) == I2C_FLAG_MASTERSLAVE))
00412 /**
00413   * @brief   Macro used by the assert function to check the I2C flags to clear.
00414   */
00415
00416 #define IS_I2C_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xFD00) == 0x00) \
00417                                      && ((uint16_t)(FLAG) != 0x00))
00418
00419 /**
00420   * @brief   Macro used by the assert function to check the different I2C possible pending bits.
00421   */
00422 #define IS_I2C_ITPENDINGBIT_OK(ITPENDINGBIT) \
00423    (((ITPENDINGBIT) == I2C_ITPENDINGBIT_TXEMPTY)                                        || \
00424     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_RXNOTEMPTY)                             || \
00425     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STOPDETECTION)                  || \
00426     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_HEADERSENT)                             || \
00427     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_TRANSFERFINISHED)       || \
00428     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ADDRESSSENTMATCHED) || \
00429     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STARTDETECTION)                 || \
00430     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT)                 || \
00431     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN)                || \
00432     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \
00433     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS)                || \
00434     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))
00435
00436 /**
00437   * @brief  Macro used by the assert function to check the different I2C possible
00438   *   pending bits to clear by writing 0.
00439   */
00440 #define IS_I2C_CLEAR_ITPENDINGBIT_OK(ITPENDINGBIT) \
00441    (((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT)     || \
00442     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN)    || \
00443     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \
00444     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS)    || \
00445     ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))
00446
00447 /**
00448   * @brief   Macro used by the assert function to check the different I2C possible events.
00449   */
00450 #define IS_I2C_EVENT_OK(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
00451                              ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
00452                              ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
00453                              ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
00454                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_GENERALCALL)) || \
00455                              ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
00456                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_GENERALCALL)) || \
00457                              ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE) || \
00458                              ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
00459                              ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
00460                              ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
00461                              ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
00462                              ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
00463                              ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
00464                              ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
00465                              ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10))
00466
00467 /**
00468   * @brief   Macro used by the assert function to check the different I2C possible own address.
00469   */
00470 #define IS_I2C_OWN_ADDRESS_OK(ADDRESS) \
00471   ((ADDRESS) <= (uint16_t)0x03FF)
00472
00473 /* The address must be even */
00474 #define IS_I2C_ADDRESS_OK(ADD) \
00475   (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)
00476
00477 /**
00478   * @brief   Macro used by the assert function to check that I2C Input clock frequency must be between 1MHz and 50MHz.
00479   */
00480 #define IS_I2C_INPUT_CLOCK_FREQ_OK(FREQ) \
00481   (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_INPUT_FREQ))
00482
00483
00484 /**
00485   * @brief   Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.
00486   */
00487 #define IS_I2C_OUTPUT_CLOCK_FREQ_OK(FREQ) \
00488   (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))
00489
00490 /**
00491   * @}
00492   */
00493
00494 /* Exported functions ------------------------------------------------------- */
00495 /** @addtogroup I2C_Exported_Functions
00496   * @{
00497   */
00498
00499 void I2C_DeInit(void);
00500 void I2C_Init(uint32_t OutputClockFrequencyHz, uint16_t OwnAddress,
00501               I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack,
00502               I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz );
00503 void I2C_Cmd(FunctionalState NewState);
00504 void I2C_GeneralCallCmd(FunctionalState NewState);
00505 void I2C_GenerateSTART(FunctionalState NewState);
00506 void I2C_GenerateSTOP(FunctionalState NewState);
00507 void I2C_SoftwareResetCmd(FunctionalState NewState);
00508 void I2C_StretchClockCmd(FunctionalState NewState);
00509 void I2C_AcknowledgeConfig(I2C_Ack_TypeDef Ack);
00510 void I2C_FastModeDutyCycleConfig(I2C_DutyCycle_TypeDef I2C_DutyCycle);
00511 void I2C_ITConfig(I2C_IT_TypeDef I2C_IT, FunctionalState NewState);
00512 uint8_t I2C_ReceiveData(void);
00513 void I2C_Send7bitAddress(uint8_t Address, I2C_Direction_TypeDef Direction);
00514 void I2C_SendData(uint8_t Data);
00515 /**
00516  * @brief
00517  ****************************************************************************************
00518  *
00519  *                         I2C State Monitoring Functions
00520  *
00521  ****************************************************************************************
00522  * This I2C driver provides three different ways for I2C state monitoring
00523  *  depending on the application requirements and constraints:
00524  *
00525  *
00526  * 1) Basic state monitoring:
00527  *    Using I2C_CheckEvent() function:
00528  *    It compares the status registers (SR1, SR2 and SR3) content to a given event
00529  *    (can be the combination of one or more flags).
00530  *    It returns SUCCESS if the current status includes the given flags
00531  *    and returns ERROR if one or more flags are missing in the current status.
00532  *    - When to use:
00533  *      - This function is suitable for most applications as well as for startup
00534  *      activity since the events are fully described in the product reference manual
00535  *      (RM0016).
00536  *      - It is also suitable for users who need to define their own events.
00537  *    - Limitations:
00538  *      - If an error occurs (ie. error flags are set besides to the monitored flags),
00539  *        the I2C_CheckEvent() function may return SUCCESS despite the communication
00540  *        hold or corrupted real state.
00541  *        In this case, it is advised to use error interrupts to monitor the error
00542  *        events and handle them in the interrupt IRQ handler.
00543  *
00544  *        @note
00545  *        For error management, it is advised to use the following functions:
00546  *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
00547  *          - I2C_IRQHandler() which is called when the I2C interurpts occur.
00548  *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
00549  *           I2Cx_IRQHandler() function in order to determine which error occured.
00550  *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
00551  *            and/or I2C_GenerateStop() in order to clear the error flag and
00552  *            source and return to correct communication status.
00553  *
00554  *
00555  *  2) Advanced state monitoring:
00556  *     Using the function I2C_GetLastEvent() which returns the image of both SR1
00557  *     & SR3 status registers in a single word (uint16_t) (Status Register 3 value
00558  *     is shifted left by 8 bits and concatenated to Status Register 1).
00559  *     - When to use:
00560  *       - This function is suitable for the same applications above but it allows to
00561  *         overcome the limitations of I2C_GetFlagStatus() function (see below).
00562  *         The returned value could be compared to events already defined in the
00563  *         library (stm8s_i2c.h) or to custom values defined by user.
00564  *       - This function is suitable when multiple flags are monitored at the same time.
00565  *       - At the opposite of I2C_CheckEvent() function, this function allows user to
00566  *         choose when an event is accepted (when all events flags are set and no
00567  *         other flags are set or just when the needed flags are set like
00568  *         I2C_CheckEvent() function).
00569  *     - Limitations:
00570  *       - User may need to define his own events.
00571  *       - Same remark concerning the error management is applicable for this
00572  *         function if user decides to check only regular communication flags (and
00573  *         ignores error flags).
00574  *
00575  *
00576  *  3) Flag-based state monitoring:
00577  *     Using the function I2C_GetFlagStatus() which simply returns the status of
00578  *     one single flag (ie. I2C_FLAG_RXNE ...).
00579  *     - When to use:
00580  *        - This function could be used for specific applications or in debug phase.
00581  *        - It is suitable when only one flag checking is needed (most I2C events
00582  *          are monitored through multiple flags).
00583  *     - Limitations:
00584  *        - When calling this function, the Status register is accessed. Some flags are
00585  *          cleared when the status register is accessed. So checking the status
00586  *          of one Flag, may clear other ones.
00587  *        - Function may need to be called twice or more in order to monitor one
00588  *          single event.
00589  *
00590  */
00591
00592 /**
00593  *
00594  *  1) Basic state monitoring
00595  *******************************************************************************
00596  */
00597 ErrorStatus I2C_CheckEvent(I2C_Event_TypeDef I2C_Event);
00598 /**
00599  *
00600  *  2) Advanced state monitoring
00601  *******************************************************************************
00602  */
00603 I2C_Event_TypeDef I2C_GetLastEvent(void);
00604 /**
00605  *
00606  *  3) Flag-based state monitoring
00607  *******************************************************************************
00608  */
00609 FlagStatus I2C_GetFlagStatus(I2C_Flag_TypeDef I2C_Flag);
00610 /**
00611  *
00612  *******************************************************************************
00613  */
00614 void I2C_ClearFlag(I2C_Flag_TypeDef I2C_FLAG);
00615 ITStatus I2C_GetITStatus(I2C_ITPendingBit_TypeDef I2C_ITPendingBit);
00616 void I2C_ClearITPendingBit(I2C_ITPendingBit_TypeDef I2C_ITPendingBit);
00617
00618
00619 /**
00620   * @}
00621   */
00622
00623 #endif /* __STM8S_I2C_H */
00624
00625 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_itc.c Source File

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stm8s_itc.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_itc.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the ITC peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_itc.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034
00035 /** @addtogroup ITC_Private_Functions
00036   * @{
00037   */
00038
00039 /**
00040   * @brief  Utility function used to read CC register.
00041   * @param  None
00042   * @retval CPU CC register value
00043   */
00044 uint8_t ITC_GetCPUCC(void)
00045 {
00046 #ifdef _COSMIC_
00047   _asm("push cc");
00048   _asm("pop a");
00049   return; /* Ignore compiler warning, the returned value is in A register */
00050 #elif defined _RAISONANCE_ /* _RAISONANCE_ */
00051   return _getCC_();
00052 #else /* _IAR_ */
00053   asm("push cc");
00054   asm("pop a"); /* Ignore compiler warning, the returned value is in A register */
00055 #endif /* _COSMIC_*/
00056 }
00057
00058
00059 /**
00060   * @}
00061   */
00062
00063 /* Public functions ----------------------------------------------------------*/
00064
00065 /** @addtogroup ITC_Public_Functions
00066   * @{
00067   */
00068
00069 /**
00070   * @brief  Deinitializes the ITC registers to their default reset value.
00071   * @param  None
00072   * @retval None
00073   */
00074 void ITC_DeInit(void)
00075 {
00076     ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
00077     ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
00078     ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
00079     ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
00080     ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
00081     ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
00082     ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
00083     ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
00084 }
00085
00086 /**
00087   * @brief  Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
00088   * @param  None
00089   * @retval The interrupt software priority bits value.
00090   */
00091 uint8_t ITC_GetSoftIntStatus(void)
00092 {
00093     return (uint8_t)(ITC_GetCPUCC() & CPU_CC_I1I0);
00094 }
00095
00096 /**
00097   * @brief  Gets the software priority of the specified interrupt source.
00098   * @param  IrqNum : Specifies the peripheral interrupt source.
00099   * @retval ITC_PriorityLevel_TypeDef : Specifies the software priority of the interrupt source.
00100   */
00101 ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum)
00102 {
00103
00104     uint8_t Value = 0;
00105     uint8_t Mask = 0;
00106
00107     /* Check function parameters */
00108     assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum));
00109
00110     /* Define the mask corresponding to the bits position in the SPR register */
00111     Mask = (uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U));
00112
00113     switch (IrqNum)
00114     {
00115     case ITC_IRQ_TLI: /* TLI software priority can be read but has no meaning */
00116     case ITC_IRQ_AWU:
00117     case ITC_IRQ_CLK:
00118     case ITC_IRQ_PORTA:
00119         Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */
00120         break;
00121     case ITC_IRQ_PORTB:
00122     case ITC_IRQ_PORTC:
00123     case ITC_IRQ_PORTD:
00124     case ITC_IRQ_PORTE:
00125         Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */
00126         break;
00127 #if defined(STM8S208) || defined(STM8AF52Ax)
00128     case ITC_IRQ_CAN_RX:
00129     case ITC_IRQ_CAN_TX:
00130 #endif /*STM8S208 or STM8AF52Ax */
00131
00132 #ifdef STM8S903
00133     case ITC_IRQ_PORTF:
00134 #endif /*STM8S903*/
00135
00136     case ITC_IRQ_SPI:
00137     case ITC_IRQ_TIM1_OVF:
00138         Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */
00139         break;
00140     case ITC_IRQ_TIM1_CAPCOM:
00141 #ifdef STM8S903
00142     case ITC_IRQ_TIM5_OVFTRI:
00143     case ITC_IRQ_TIM5_CAPCOM:
00144 #else
00145     case ITC_IRQ_TIM2_OVF:
00146     case ITC_IRQ_TIM2_CAPCOM:
00147 #endif /*STM8S903*/
00148
00149     case ITC_IRQ_TIM3_OVF:
00150         Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */
00151         break;
00152     case ITC_IRQ_TIM3_CAPCOM:
00153     case ITC_IRQ_UART1_TX:
00154     case ITC_IRQ_UART1_RX:
00155     case ITC_IRQ_I2C:
00156         Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */
00157         break;
00158 #if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
00159     case ITC_IRQ_UART2_TX:
00160     case ITC_IRQ_UART2_RX:
00161 #endif /*STM8S105 or STM8AF626x*/
00162
00163 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \
00164     defined(STM8AF62Ax)
00165     case ITC_IRQ_UART3_TX:
00166     case ITC_IRQ_UART3_RX:
00167     case ITC_IRQ_ADC2:
00168 #endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */
00169
00170 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
00171     defined(STM8S903) || defined(STM8AF626x)
00172     case ITC_IRQ_ADC1:
00173 #endif /*STM8S105, STM8S103 or STM8S905 or STM8AF626x */
00174
00175 #ifdef STM8S903
00176     case ITC_IRQ_TIM6_OVFTRI:
00177 #else
00178     case ITC_IRQ_TIM4_OVF:
00179 #endif /*STM8S903*/
00180         Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */
00181         break;
00182     case ITC_IRQ_EEPROM_EEC:
00183         Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */
00184         break;
00185     default:
00186         break;
00187     }
00188
00189     Value >>= (uint8_t)(((uint8_t)IrqNum % 4u) * 2u);
00190
00191     return((ITC_PriorityLevel_TypeDef)Value);
00192
00193 }
00194
00195 /**
00196   * @brief  Sets the software priority of the specified interrupt source.
00197   * @note   - The modification of the software priority is only possible when
00198   *         the interrupts are disabled.
00199   *         - The normal behavior is to disable the interrupt before calling
00200   *         this function, and re-enable it after.
00201   *         - The priority level 0 cannot be set (see product specification
00202   *         for more details).
00203   * @param  IrqNum : Specifies the peripheral interrupt source.
00204   * @param  PriorityValue : Specifies the software priority value to set,
00205   *         can be a value of @ref  ITC_PriorityLevel_TypeDef .
00206   * @retval None
00207 */
00208 void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
00209 {
00210
00211     uint8_t Mask = 0;
00212     uint8_t NewPriority = 0;
00213
00214     /* Check function parameters */
00215     assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum));
00216     assert_param(IS_ITC_PRIORITY_OK(PriorityValue));
00217
00218     /* Check if interrupts are disabled */
00219     assert_param(IS_ITC_INTERRUPTS_DISABLED);
00220
00221     /* Define the mask corresponding to the bits position in the SPR register */
00222     /* The mask is reversed in order to clear the 2 bits after more easily */
00223     Mask = (uint8_t)(~(uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U)));
00224
00225     /* Define the new priority to write */
00226     NewPriority = (uint8_t)((uint8_t)(PriorityValue) << (((uint8_t)IrqNum % 4U) * 2U));
00227
00228     switch (IrqNum)
00229     {
00230
00231     case ITC_IRQ_TLI: /* TLI software priority can be written but has no meaning */
00232     case ITC_IRQ_AWU:
00233     case ITC_IRQ_CLK:
00234     case ITC_IRQ_PORTA:
00235         ITC->ISPR1 &= Mask;
00236         ITC->ISPR1 |= NewPriority;
00237         break;
00238
00239     case ITC_IRQ_PORTB:
00240     case ITC_IRQ_PORTC:
00241     case ITC_IRQ_PORTD:
00242     case ITC_IRQ_PORTE:
00243         ITC->ISPR2 &= Mask;
00244         ITC->ISPR2 |= NewPriority;
00245         break;
00246
00247 #if defined(STM8S208) || defined(STM8AF52Ax)
00248     case ITC_IRQ_CAN_RX:
00249     case ITC_IRQ_CAN_TX:
00250 #endif /*STM8S208 or STM8AF52Ax */
00251
00252 #ifdef STM8S903
00253     case ITC_IRQ_PORTF:
00254 #endif /*STM8S903*/
00255     case ITC_IRQ_SPI:
00256     case ITC_IRQ_TIM1_OVF:
00257         ITC->ISPR3 &= Mask;
00258         ITC->ISPR3 |= NewPriority;
00259         break;
00260
00261     case ITC_IRQ_TIM1_CAPCOM:
00262 #ifdef STM8S903
00263     case ITC_IRQ_TIM5_OVFTRI:
00264     case ITC_IRQ_TIM5_CAPCOM:
00265 #else
00266     case ITC_IRQ_TIM2_OVF:
00267     case ITC_IRQ_TIM2_CAPCOM:
00268 #endif /*STM8S903*/
00269
00270     case ITC_IRQ_TIM3_OVF:
00271         ITC->ISPR4 &= Mask;
00272         ITC->ISPR4 |= NewPriority;
00273         break;
00274
00275     case ITC_IRQ_TIM3_CAPCOM:
00276     case ITC_IRQ_UART1_TX:
00277     case ITC_IRQ_UART1_RX:
00278     case ITC_IRQ_I2C:
00279         ITC->ISPR5 &= Mask;
00280         ITC->ISPR5 |= NewPriority;
00281         break;
00282
00283 #if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
00284     case ITC_IRQ_UART2_TX:
00285     case ITC_IRQ_UART2_RX:
00286 #endif /*STM8S105 or STM8AF626x */
00287
00288 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \
00289     defined(STM8AF62Ax)
00290     case ITC_IRQ_UART3_TX:
00291     case ITC_IRQ_UART3_RX:
00292     case ITC_IRQ_ADC2:
00293 #endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */
00294
00295 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
00296     defined(STM8S903) || defined(STM8AF626x)
00297     case ITC_IRQ_ADC1:
00298 #endif /*STM8S105, STM8S103 or STM8S905 or STM8AF626x */
00299
00300 #ifdef STM8S903
00301     case ITC_IRQ_TIM6_OVFTRI:
00302 #else
00303     case ITC_IRQ_TIM4_OVF:
00304 #endif /*STM8S903*/
00305         ITC->ISPR6 &= Mask;
00306         ITC->ISPR6 |= NewPriority;
00307         break;
00308
00309     case ITC_IRQ_EEPROM_EEC:
00310         ITC->ISPR7 &= Mask;
00311         ITC->ISPR7 |= NewPriority;
00312         break;
00313
00314     default:
00315         break;
00316
00317     }
00318
00319 }
00320
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_itc.h Source File

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  • STM8S_StdPeriph_Driver
  • inc

stm8s_itc.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_itc.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the ITC peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_ITC_H__
00024 #define __STM8S_ITC_H__
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030
00031 /** @addtogroup ITC_Exported_Types
00032   * @{
00033   */
00034
00035 /**
00036   * @brief  ITC Interrupt Lines selection
00037   */
00038 typedef enum {
00039   ITC_IRQ_TLI            = (uint8_t)0,   /*!< Software interrupt */
00040   ITC_IRQ_AWU            = (uint8_t)1,   /*!< Auto wake up from halt interrupt */
00041   ITC_IRQ_CLK            = (uint8_t)2,   /*!< Clock controller interrupt */
00042   ITC_IRQ_PORTA          = (uint8_t)3,   /*!< Port A external interrupts */
00043   ITC_IRQ_PORTB          = (uint8_t)4,   /*!< Port B external interrupts */
00044   ITC_IRQ_PORTC          = (uint8_t)5,   /*!< Port C external interrupts */
00045   ITC_IRQ_PORTD          = (uint8_t)6,   /*!< Port D external interrupts */
00046   ITC_IRQ_PORTE          = (uint8_t)7,   /*!< Port E external interrupts */
00047
00048 #if defined(STM8S208) || defined(STM8AF52Ax)
00049   ITC_IRQ_CAN_RX         = (uint8_t)8,   /*!< beCAN RX interrupt */
00050   ITC_IRQ_CAN_TX         = (uint8_t)9,   /*!< beCAN TX/ER/SC interrupt */
00051 #endif /*STM8S208 or STM8AF52Ax */
00052
00053 #ifdef STM8S903
00054   ITC_IRQ_PORTF          = (uint8_t)8,   /*!< Port F external interrupts */
00055 #endif /*STM8S903*/
00056
00057   ITC_IRQ_SPI            = (uint8_t)10,  /*!< SPI interrupt */
00058   ITC_IRQ_TIM1_OVF       = (uint8_t)11,  /*!< TIM1 update/overflow/underflow/trigger/
00059                                          break interrupt*/
00060   ITC_IRQ_TIM1_CAPCOM    = (uint8_t)12,  /*!< TIM1 capture/compare interrupt */
00061
00062 #ifdef STM8S903
00063   ITC_IRQ_TIM5_OVFTRI    = (uint8_t)13,  /*!< TIM5 update/overflow/underflow/trigger/
00064                                          interrupt */
00065   ITC_IRQ_TIM5_CAPCOM    = (uint8_t)14,  /*!< TIM5 capture/compare interrupt */
00066 #else
00067   ITC_IRQ_TIM2_OVF       = (uint8_t)13,  /*!< TIM2 update /overflow interrupt */
00068   ITC_IRQ_TIM2_CAPCOM    = (uint8_t)14,  /*!< TIM2 capture/compare interrupt */
00069 #endif /*STM8S903*/
00070
00071   ITC_IRQ_TIM3_OVF       = (uint8_t)15,  /*!< TIM3 update /overflow interrupt*/
00072   ITC_IRQ_TIM3_CAPCOM    = (uint8_t)16,  /*!< TIM3 update /overflow interrupt */
00073   ITC_IRQ_UART1_TX       = (uint8_t)17,  /*!< USART1 TX interrupt */
00074   ITC_IRQ_UART1_RX       = (uint8_t)18,  /*!< USART1 RX interrupt */
00075   ITC_IRQ_I2C            = (uint8_t)19,  /*!< I2C interrupt */
00076
00077 #if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
00078   ITC_IRQ_UART2_TX       = (uint8_t)20,  /*!< USART2 TX interrupt */
00079   ITC_IRQ_UART2_RX       = (uint8_t)21,  /*!< USART2 RX interrupt */
00080 #endif /*STM8S105 or STM8AF626x */
00081
00082 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || defined(STM8AF62Ax)
00083   ITC_IRQ_UART3_TX       = (uint8_t)20,  /*!< USART3 TX interrupt */
00084   ITC_IRQ_UART3_RX       = (uint8_t)21,  /*!< USART3 RX interrupt */
00085   ITC_IRQ_ADC2           = (uint8_t)22,  /*!< ADC2 interrupt */
00086 #endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */
00087
00088 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) ||  defined(STM8S903) || defined(STM8AF626x)
00089   ITC_IRQ_ADC1           = (uint8_t)22,  /*!< ADC2 interrupt */
00090 #endif /*STM8S105, STM8S103 or STM8S903 or STM8AF626x */
00091
00092 #ifdef STM8S903
00093   ITC_IRQ_TIM6_OVFTRI    = (uint8_t)23,  /*!< TIM6 update/overflow/underflow/trigger/
00094                                          interrupt */
00095 #else
00096   ITC_IRQ_TIM4_OVF       = (uint8_t)23,  /*!< TIM4 update /overflow interrupt */
00097 #endif /*STM8S903*/
00098
00099   ITC_IRQ_EEPROM_EEC     = (uint8_t)24  /*!< Flash interrupt */
00100 } ITC_Irq_TypeDef;
00101
00102 /**
00103   * @brief  ITC Priority Levels selection
00104   */
00105 typedef enum {
00106   ITC_PRIORITYLEVEL_0 = (uint8_t)0x02, /*!< Software priority level 0 (cannot be written) */
00107   ITC_PRIORITYLEVEL_1 = (uint8_t)0x01, /*!< Software priority level 1 */
00108   ITC_PRIORITYLEVEL_2 = (uint8_t)0x00, /*!< Software priority level 2 */
00109   ITC_PRIORITYLEVEL_3 = (uint8_t)0x03  /*!< Software priority level 3 */
00110 } ITC_PriorityLevel_TypeDef;
00111
00112 /**
00113   * @}
00114   */
00115
00116 /* Exported constants --------------------------------------------------------*/
00117
00118 /** @addtogroup ITC_Exported_Constants
00119   * @{
00120   */
00121
00122 #define CPU_SOFT_INT_DISABLED ((uint8_t)0x28) /*!< Mask for I1 and I0 bits in CPU_CC register */
00123
00124 /**
00125   * @}
00126   */
00127
00128 /* Private macros ------------------------------------------------------------*/
00129
00130 /**
00131   * @brief  Macros used by the assert function in order to check the different functions parameters.
00132   * @addtogroup ITC_Private_Macros
00133   * @{
00134   */
00135
00136 /* Used by assert function */
00137 #define IS_ITC_IRQ_OK(IRQ) ((IRQ) <= (uint8_t)24)
00138
00139 /* Used by assert function */
00140 #define IS_ITC_PRIORITY_OK(PriorityValue) \
00141   (((PriorityValue) == ITC_PRIORITYLEVEL_0) || \
00142    ((PriorityValue) == ITC_PRIORITYLEVEL_1) || \
00143    ((PriorityValue) == ITC_PRIORITYLEVEL_2) || \
00144    ((PriorityValue) == ITC_PRIORITYLEVEL_3))
00145
00146 /* Used by assert function */
00147 #define IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)
00148
00149 /**
00150   * @}
00151   */
00152
00153 /* Exported functions ------------------------------------------------------- */
00154
00155 /** @addtogroup ITC_Exported_Functions
00156   * @{
00157   */
00158
00159 uint8_t ITC_GetCPUCC(void);
00160 void ITC_DeInit(void);
00161 uint8_t ITC_GetSoftIntStatus(void);
00162 void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue);
00163 ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum);
00164
00165 /**
00166   * @}
00167   */
00168
00169 #endif /* __STM8S_ITC_H__ */
00170
00171 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_iwdg.c Source File

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  • src

stm8s_iwdg.c

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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_iwdg.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the IWDG peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_iwdg.h"
00024
00025 /* Private define ------------------------------------------------------------*/
00026 /* Private macro -------------------------------------------------------------*/
00027 /* Private variables ---------------------------------------------------------*/
00028 /* Private function prototypes -----------------------------------------------*/
00029 /* Private functions ---------------------------------------------------------*/
00030 /* Public functions ----------------------------------------------------------*/
00031
00032 /** @addtogroup IWDG_Public_Functions
00033   * @{
00034   */
00035
00036 /**
00037   * @brief  Enables or disables write access to Prescaler and Reload registers.
00038   * @param  IWDG_WriteAccess : New state of write access to Prescaler and Reload
00039   *         registers.  This parameter can be a value of @ref IWDG_WriteAccess_TypeDef.
00040   * @retval None
00041   */
00042 void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
00043 {
00044     /* Check the parameters */
00045     assert_param(IS_IWDG_WRITEACCESS_MODE_OK(IWDG_WriteAccess));
00046
00047     IWDG->KR = (uint8_t)IWDG_WriteAccess; /* Write Access */
00048 }
00049
00050 /**
00051   * @brief  Sets IWDG Prescaler value.
00052   * @note   Write access should be enabled
00053   * @param  IWDG_Prescaler : Specifies the IWDG Prescaler value.
00054   *         This parameter can be a value of @ref IWDG_Prescaler_TypeDef.
00055   * @retval None
00056   */
00057 void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler)
00058 {
00059     /* Check the parameters */
00060     assert_param(IS_IWDG_PRESCALER_OK(IWDG_Prescaler));
00061
00062     IWDG->PR = (uint8_t)IWDG_Prescaler;
00063 }
00064
00065 /**
00066   * @brief  Sets IWDG Reload value.
00067   * @note   Write access should be enabled
00068   * @param  IWDG_Reload : Reload register value.
00069   *         This parameter must be a number between 0 and 0xFF.
00070   * @retval None
00071   */
00072 void IWDG_SetReload(uint8_t IWDG_Reload)
00073 {
00074     IWDG->RLR = IWDG_Reload;
00075 }
00076
00077 /**
00078   * @brief  Reloads IWDG counter
00079   * @note   Write access should be enabled
00080   * @param  None
00081   * @retval None
00082   */
00083 void IWDG_ReloadCounter(void)
00084 {
00085     IWDG->KR = IWDG_KEY_REFRESH;
00086 }
00087
00088 /**
00089   * @brief  Enables IWDG.
00090   * @param  None
00091   * @retval None
00092   */
00093 void IWDG_Enable(void)
00094 {
00095     IWDG->KR = IWDG_KEY_ENABLE;
00096 }
00097
00098 /**
00099   * @}
00100   */
00101
00102 /**
00103   * @}
00104   */
00105
00106 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_iwdg.h Source File

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  • STM8S_StdPeriph_Driver
  • inc

stm8s_iwdg.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_iwdg.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototypes and macros for the IWDG peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_IWDG_H
00024 #define __STM8S_IWDG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup IWDG_Private_Define
00034   * @{
00035   */
00036
00037 /**
00038   * @brief  Define used to prevent watchdog reset
00039   */
00040 #define IWDG_KEY_REFRESH    ((uint8_t)0xAA)  /*!<  This value written in the Key register prevent the watchdog reset */
00041
00042 /**
00043   * @brief  Define used to start the watchdog counter down
00044   */
00045 #define IWDG_KEY_ENABLE     ((uint8_t)0xCC)  /*!<  This value written in the Key register start the watchdog counting down*/
00046
00047 /**
00048  * @}
00049  */
00050
00051 /** @addtogroup IWDG_Private_Macros
00052   * @{
00053   */
00054
00055 /**
00056   * @brief  Macro used by the assert function in order to check the different
00057   * values of the prescaler.
00058   */
00059 #define IS_IWDG_PRESCALER_OK(VALUE) (((VALUE) == IWDG_Prescaler_4   ) || \
00060                                      ((VALUE) == IWDG_Prescaler_8   ) || \
00061                                      ((VALUE) == IWDG_Prescaler_16  ) || \
00062                                      ((VALUE) == IWDG_Prescaler_32  ) || \
00063                                      ((VALUE) == IWDG_Prescaler_64  ) || \
00064                                      ((VALUE) == IWDG_Prescaler_128 ) || \
00065                                      ((VALUE) == IWDG_Prescaler_256))
00066
00067 /**
00068   * @brief  Macro used by the assert function in order to check the different
00069   * values of the counter register.
00070   */
00071 #define IS_IWDG_WRITEACCESS_MODE_OK(MODE) (((MODE) == IWDG_WriteAccess_Enable) || ((MODE) == IWDG_WriteAccess_Disable))
00072
00073 /**
00074   * @}
00075   */
00076
00077 /** @addtogroup IWDG_Exported_Types
00078   * @{
00079   */
00080
00081 /** IWDG write  acces enumeration */
00082 typedef enum
00083 {
00084   IWDG_WriteAccess_Enable  = (uint8_t)0x55, /*!< Code 0x55 in Key register, allow write access to Prescaler and Reload registers */
00085   IWDG_WriteAccess_Disable = (uint8_t)0x00  /*!< Code 0x00 in Key register, not allow write access to Prescaler and Reload registers */
00086 } IWDG_WriteAccess_TypeDef;
00087
00088 /** IWDG prescaler enumaration */
00089 typedef enum
00090 {
00091   IWDG_Prescaler_4   = (uint8_t)0x00, /*!< Used to set prescaler register to 4 */
00092   IWDG_Prescaler_8   = (uint8_t)0x01, /*!< Used to set prescaler register to 8 */
00093   IWDG_Prescaler_16  = (uint8_t)0x02, /*!< Used to set prescaler register to 16 */
00094   IWDG_Prescaler_32  = (uint8_t)0x03, /*!< Used to set prescaler register to 32 */
00095   IWDG_Prescaler_64  = (uint8_t)0x04, /*!< Used to set prescaler register to 64 */
00096   IWDG_Prescaler_128 = (uint8_t)0x05, /*!< Used to set prescaler register to 128 */
00097   IWDG_Prescaler_256 = (uint8_t)0x06  /*!< Used to set prescaler register to 256 */
00098 } IWDG_Prescaler_TypeDef;
00099
00100 /**
00101   * @}
00102   */
00103
00104 /** @addtogroup IWDG_Exported_Functions
00105   * @{
00106   */
00107
00108 void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess);
00109 void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler);
00110 void IWDG_SetReload(uint8_t IWDG_Reload);
00111 void IWDG_ReloadCounter(void);
00112 void IWDG_Enable(void);
00113
00114 /**
00115   * @}
00116   */
00117
00118 #endif /* __STM8S_IWDG_H */
00119
00120 /**
00121   * @}
00122   */
00123
00124 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_rst.c Source File

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  • src

stm8s_rst.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_rst.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the RST peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023
00024 #include "stm8s_rst.h"
00025
00026 /** @addtogroup STM8S_StdPeriph_Driver
00027   * @{
00028   */
00029 /* Private typedef -----------------------------------------------------------*/
00030 /* Private define ------------------------------------------------------------*/
00031 /* Private macro -------------------------------------------------------------*/
00032 /* Private variables ---------------------------------------------------------*/
00033 /* Private function prototypes -----------------------------------------------*/
00034 /* Private Constants ---------------------------------------------------------*/
00035 /* Public functions ----------------------------------------------------------*/
00036 /**
00037   * @addtogroup RST_Public_Functions
00038   * @{
00039   */
00040
00041
00042 /**
00043   * @brief   Checks whether the specified RST flag is set or not.
00044   * @param   RST_Flag : specify the reset flag to check.
00045   *          This parameter can be a value of @ref RST_FLAG_TypeDef.
00046   * @retval  FlagStatus: status of the given RST flag.
00047   */
00048 FlagStatus RST_GetFlagStatus(RST_Flag_TypeDef RST_Flag)
00049 {
00050     /* Check the parameters */
00051     assert_param(IS_RST_FLAG_OK(RST_Flag));
00052
00053     /* Get flag status */
00054
00055     return ((FlagStatus)((uint8_t)RST->SR & (uint8_t)RST_Flag));
00056 }
00057
00058 /**
00059   * @brief  Clears the specified RST flag.
00060   * @param  RST_Flag : specify the reset flag to clear.
00061   *         This parameter can be a value of @ref RST_FLAG_TypeDef.
00062   * @retval None
00063   */
00064 void RST_ClearFlag(RST_Flag_TypeDef RST_Flag)
00065 {
00066     /* Check the parameters */
00067     assert_param(IS_RST_FLAG_OK(RST_Flag));
00068
00069     RST->SR = (uint8_t)RST_Flag;
00070 }
00071
00072 /**
00073   * @}
00074   */
00075
00076 /**
00077   * @}
00078   */
00079
00080 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_rst.h Source File

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  • inc

stm8s_rst.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_rst.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the RST peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021 /* Define to prevent recursive inclusion -------------------------------------*/
00022 #ifndef __STM8S_RST_H
00023 #define __STM8S_RST_H
00024
00025 /* Includes ------------------------------------------------------------------*/
00026 #include "stm8s.h"
00027
00028 /** @addtogroup STM8S_StdPeriph_Driver
00029   * @{
00030   */
00031
00032 /** @addtogroup RST_Exported_Types
00033   * @{
00034   */
00035 typedef enum {
00036   RST_FLAG_EMCF    = (uint8_t)0x10, /*!< EMC reset flag */
00037   RST_FLAG_SWIMF   = (uint8_t)0x08, /*!< SWIM reset flag */
00038   RST_FLAG_ILLOPF  = (uint8_t)0x04, /*!< Illigal opcode reset flag */
00039   RST_FLAG_IWDGF   = (uint8_t)0x02, /*!< Independent watchdog reset flag */
00040   RST_FLAG_WWDGF   = (uint8_t)0x01  /*!< Window watchdog reset flag */
00041 }RST_Flag_TypeDef;
00042
00043 /**
00044   * @}
00045   */
00046
00047 /* Exported constants --------------------------------------------------------*/
00048 /* Exported macros -----------------------------------------------------------*/
00049
00050 /** @addtogroup RST_Private_Macros
00051   * @{
00052   */
00053
00054 /**
00055   * @brief  Macro used by the assert function to check the different functions parameters.
00056   */
00057 /**
00058   * @brief  Macro used by the assert function to check the different RST flags.
00059   */
00060 #define IS_RST_FLAG_OK(FLAG) (((FLAG) == RST_FLAG_EMCF) || \
00061                               ((FLAG) == RST_FLAG_SWIMF)  ||\
00062                               ((FLAG) == RST_FLAG_ILLOPF) ||\
00063                               ((FLAG) == RST_FLAG_IWDGF)  ||\
00064                               ((FLAG) == RST_FLAG_WWDGF))
00065
00066 /**
00067   * @}
00068   */
00069
00070 /** @addtogroup RST_Exported_functions
00071   * @{
00072   */
00073 FlagStatus RST_GetFlagStatus(RST_Flag_TypeDef RST_Flag);
00074 void RST_ClearFlag(RST_Flag_TypeDef RST_Flag);
00075
00076 /**
00077   * @}
00078   */
00079
00080 #endif /* __STM8S_RST_H */
00081
00082 /**
00083   * @}
00084   */
00085 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_spi.c Source File

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  • STM8S_StdPeriph_Driver
  • src

stm8s_spi.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_spi.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the SPI peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_spi.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034
00035 /** @addtogroup SPI_Public_Functions
00036   * @{
00037   */
00038
00039 /**
00040   * @brief  Deinitializes the SPI peripheral registers to their default reset values.
00041   * @param  None
00042   * @retval None
00043   */
00044 void SPI_DeInit(void)
00045 {
00046     SPI->CR1    = SPI_CR1_RESET_VALUE;
00047     SPI->CR2    = SPI_CR2_RESET_VALUE;
00048     SPI->ICR    = SPI_ICR_RESET_VALUE;
00049     SPI->SR     = SPI_SR_RESET_VALUE;
00050     SPI->CRCPR  = SPI_CRCPR_RESET_VALUE;
00051 }
00052
00053 /**
00054   * @brief  Initializes the SPI according to the specified parameters.
00055   * @param  FirstBit : This parameter can be any of the
00056   *         @ref SPI_FirstBit_TypeDef enumeration.
00057   * @param  BaudRatePrescaler : This parameter can be any of the
00058   *         @ref SPI_BaudRatePrescaler_TypeDef enumeration.
00059   * @param  Mode : This parameter can be any of the
00060   *         @ref SPI_Mode_TypeDef enumeration.
00061   * @param  ClockPolarity : This parameter can be any of the
00062   *         @ref SPI_ClockPolarity_TypeDef enumeration.
00063   * @param  ClockPhase : This parameter can be any of the
00064   *         @ref SPI_ClockPhase_TypeDef enumeration.
00065   * @param  Data_Direction : This parameter can be any of the
00066   *         @ref SPI_DataDirection_TypeDef enumeration.
00067   * @param  Slave_Management : This parameter can be any of the
00068   *         @ref SPI_NSS_TypeDef enumeration.
00069   * @param  CRCPolynomial : Configures the CRC polynomial.
00070   * @retval None
00071   */
00072 void SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)
00073 {
00074     /* Check structure elements */
00075     assert_param(IS_SPI_FIRSTBIT_OK(FirstBit));
00076     assert_param(IS_SPI_BAUDRATE_PRESCALER_OK(BaudRatePrescaler));
00077     assert_param(IS_SPI_MODE_OK(Mode));
00078     assert_param(IS_SPI_POLARITY_OK(ClockPolarity));
00079     assert_param(IS_SPI_PHASE_OK(ClockPhase));
00080     assert_param(IS_SPI_DATA_DIRECTION_OK(Data_Direction));
00081     assert_param(IS_SPI_SLAVEMANAGEMENT_OK(Slave_Management));
00082     assert_param(IS_SPI_CRC_POLYNOMIAL_OK(CRCPolynomial));
00083
00084     /* Frame Format, BaudRate, Clock Polarity and Phase configuration */
00085     SPI->CR1 = (uint8_t)((uint8_t)((uint8_t)FirstBit | BaudRatePrescaler) |
00086                     (uint8_t)((uint8_t)ClockPolarity | ClockPhase));
00087
00088     /* Data direction configuration: BDM, BDOE and RXONLY bits */
00089     SPI->CR2 = (uint8_t)((uint8_t)(Data_Direction) | (uint8_t)(Slave_Management));
00090
00091     if (Mode == SPI_MODE_MASTER)
00092     {
00093         SPI->CR2 |= (uint8_t)SPI_CR2_SSI;
00094     }
00095     else
00096     {
00097         SPI->CR2 &= (uint8_t)~(SPI_CR2_SSI);
00098     }
00099
00100     /* Master/Slave mode configuration */
00101     SPI->CR1 |= (uint8_t)(Mode);
00102
00103     /* CRC configuration */
00104     SPI->CRCPR = (uint8_t)CRCPolynomial;
00105 }
00106
00107 /**
00108   * @brief  Enables or disables the SPI peripheral.
00109   * @param  NewState New state of the SPI peripheral.
00110   *         This parameter can be: ENABLE or DISABLE
00111   * @retval None
00112   */
00113 void SPI_Cmd(FunctionalState NewState)
00114 {
00115     /* Check function parameters */
00116     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00117
00118     if (NewState != DISABLE)
00119     {
00120         SPI->CR1 |= SPI_CR1_SPE; /* Enable the SPI peripheral*/
00121     }
00122     else
00123     {
00124         SPI->CR1 &= (uint8_t)(~SPI_CR1_SPE); /* Disable the SPI peripheral*/
00125     }
00126 }
00127
00128 /**
00129   * @brief  Enables or disables the specified interrupts.
00130   * @param  SPI_IT Specifies the SPI interrupts sources to be enabled or disabled.
00131   * @param  NewState: The new state of the specified SPI interrupts.
00132   *         This parameter can be: ENABLE or DISABLE.
00133   * @retval None
00134   */
00135 void SPI_ITConfig(SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
00136 {
00137     uint8_t itpos = 0;
00138     /* Check function parameters */
00139     assert_param(IS_SPI_CONFIG_IT_OK(SPI_IT));
00140     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00141
00142     /* Get the SPI IT index */
00143     itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)SPI_IT & (uint8_t)0x0F));
00144
00145     if (NewState != DISABLE)
00146     {
00147         SPI->ICR |= itpos; /* Enable interrupt*/
00148     }
00149     else
00150     {
00151         SPI->ICR &= (uint8_t)(~itpos); /* Disable interrupt*/
00152     }
00153 }
00154 /**
00155   * @brief  Transmits a Data through the SPI peripheral.
00156   * @param  Data : Byte to be transmitted.
00157   * @retval None
00158   */
00159 void SPI_SendData(uint8_t Data)
00160 {
00161     SPI->DR = Data; /* Write in the DR register the data to be sent*/
00162 }
00163
00164 /**
00165   * @brief  Returns the most recent received data by the SPI peripheral.
00166   * @param  None
00167   * @retval The value of the received data.
00168   */
00169 uint8_t SPI_ReceiveData(void)
00170 {
00171     return ((uint8_t)SPI->DR); /* Return the data in the DR register*/
00172 }
00173
00174 /**
00175   * @brief  Configures internally by software the NSS pin.
00176   * @param  NewState Indicates the new state of the SPI Software slave management.
00177   *         This parameter can be: ENABLE or DISABLE.
00178   * @retval None
00179   */
00180 void SPI_NSSInternalSoftwareCmd(FunctionalState NewState)
00181 {
00182     /* Check function parameters */
00183     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00184
00185     if (NewState != DISABLE)
00186     {
00187         SPI->CR2 |= SPI_CR2_SSI; /* Set NSS pin internally by software*/
00188     }
00189     else
00190     {
00191         SPI->CR2 &= (uint8_t)(~SPI_CR2_SSI); /* Reset NSS pin internally by software*/
00192     }
00193 }
00194
00195 /**
00196   * @brief  Enables the transmit of the CRC value.
00197   * @param  None
00198   * @retval None
00199   */
00200 void SPI_TransmitCRC(void)
00201 {
00202     SPI->CR2 |= SPI_CR2_CRCNEXT; /* Enable the CRC transmission*/
00203 }
00204
00205 /**
00206   * @brief  Enables or disables the CRC value calculation of the transferred bytes.
00207   * @param  NewState Indicates the new state of the SPI CRC value calculation.
00208   *         This parameter can be: ENABLE or DISABLE.
00209   * @retval None
00210   */
00211 void SPI_CalculateCRCCmd(FunctionalState NewState)
00212 {
00213     /* Check function parameters */
00214     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00215
00216     if (NewState != DISABLE)
00217     {
00218         SPI->CR2 |= SPI_CR2_CRCEN; /* Enable the CRC calculation*/
00219     }
00220     else
00221     {
00222         SPI->CR2 &= (uint8_t)(~SPI_CR2_CRCEN); /* Disable the CRC calculation*/
00223     }
00224 }
00225
00226 /**
00227   * @brief  Returns the transmit or the receive CRC register value.
00228   * @param  SPI_CRC Specifies the CRC register to be read.
00229   * @retval The selected CRC register value.
00230   */
00231 uint8_t SPI_GetCRC(SPI_CRC_TypeDef SPI_CRC)
00232 {
00233     uint8_t crcreg = 0;
00234
00235     /* Check function parameters */
00236     assert_param(IS_SPI_CRC_OK(SPI_CRC));
00237
00238     if (SPI_CRC != SPI_CRC_RX)
00239     {
00240         crcreg = SPI->TXCRCR;  /* Get the Tx CRC register*/
00241     }
00242     else
00243     {
00244         crcreg = SPI->RXCRCR; /* Get the Rx CRC register*/
00245     }
00246
00247     /* Return the selected CRC register status*/
00248     return crcreg;
00249 }
00250
00251 /**
00252   * @brief  Reset the Rx CRCR and Tx CRCR registers.
00253   * @param  None
00254   * @retval None
00255   */
00256 void SPI_ResetCRC(void)
00257 {
00258     /* Rx CRCR & Tx CRCR registers are reset when CRCEN (hardware calculation)
00259        bit in SPI_CR2 is written to 1 (enable) */
00260     SPI_CalculateCRCCmd(ENABLE);
00261
00262     /* Previous function disable the SPI */
00263     SPI_Cmd(ENABLE);
00264 }
00265
00266 /**
00267   * @brief  Returns the CRC Polynomial register value.
00268   * @param  None
00269   * @retval The CRC Polynomial register value.
00270   */
00271 uint8_t SPI_GetCRCPolynomial(void)
00272 {
00273     return SPI->CRCPR; /* Return the CRC polynomial register */
00274 }
00275
00276 /**
00277   * @brief  Selects the data transfer direction in bi-directional mode.
00278   * @param  SPI_Direction Specifies the data transfer direction in bi-directional mode.
00279   * @retval None
00280   */
00281 void SPI_BiDirectionalLineConfig(SPI_Direction_TypeDef SPI_Direction)
00282 {
00283     /* Check function parameters */
00284     assert_param(IS_SPI_DIRECTION_OK(SPI_Direction));
00285
00286     if (SPI_Direction != SPI_DIRECTION_RX)
00287     {
00288         SPI->CR2 |= SPI_CR2_BDOE; /* Set the Tx only mode*/
00289     }
00290     else
00291     {
00292         SPI->CR2 &= (uint8_t)(~SPI_CR2_BDOE); /* Set the Rx only mode*/
00293     }
00294 }
00295
00296 /**
00297   * @brief  Checks whether the specified SPI flag is set or not.
00298   * @param  SPI_FLAG : Specifies the flag to check.
00299   *         This parameter can be any of the @ref SPI_FLAG_TypeDef enumeration.
00300   * @retval FlagStatus : Indicates the state of SPI_FLAG.
00301   *         This parameter can be any of the @ref FlagStatus enumeration.
00302   */
00303
00304 FlagStatus SPI_GetFlagStatus(SPI_Flag_TypeDef SPI_FLAG)
00305 {
00306     FlagStatus status = RESET;
00307     /* Check parameters */
00308     assert_param(IS_SPI_FLAGS_OK(SPI_FLAG));
00309
00310     /* Check the status of the specified SPI flag */
00311     if ((SPI->SR & (uint8_t)SPI_FLAG) != (uint8_t)RESET)
00312     {
00313         status = SET; /* SPI_FLAG is set */
00314     }
00315     else
00316     {
00317         status = RESET; /* SPI_FLAG is reset*/
00318     }
00319
00320     /* Return the SPI_FLAG status */
00321     return status;
00322 }
00323
00324 /**
00325   * @brief  Clears the SPI flags.
00326   * @param  SPI_FLAG : Specifies the flag to clear.
00327   *         This parameter can be one of the following values:
00328   *         - SPI_FLAG_CRCERR
00329   *         - SPI_FLAG_WKUP
00330   * @note   - OVR (OverRun Error) interrupt pending bit is cleared by software
00331   *         sequence:
00332   *         a read operation to SPI_DR register (SPI_ReceiveData()) followed by
00333   *         a read operation to SPI_SR register (SPI_GetFlagStatus()).
00334   *         - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
00335   *         a read/write operation to SPI_SR register (SPI_GetFlagStatus()) followed by
00336   *         a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
00337   * @retval None
00338   */
00339 void SPI_ClearFlag(SPI_Flag_TypeDef SPI_FLAG)
00340 {
00341     assert_param(IS_SPI_CLEAR_FLAGS_OK(SPI_FLAG));
00342     /* Clear the flag bit */
00343     SPI->SR = (uint8_t)(~SPI_FLAG);
00344 }
00345
00346 /**
00347   * @brief  Checks whether the specified interrupt has occurred or not.
00348   * @param  SPI_IT: Specifies the SPI interrupt pending bit to check.
00349   *         This parameter can be one of the following values:
00350   *         - SPI_IT_CRCERR
00351   *         - SPI_IT_WKUP
00352   *         - SPI_IT_OVR
00353   *         - SPI_IT_MODF
00354   *         - SPI_IT_RXNE
00355   *         - SPI_IT_TXE
00356   * @retval ITStatus : Indicates the state of the SPI_IT.
00357   *         This parameter can be any of the @ref ITStatus enumeration.
00358   */
00359 ITStatus SPI_GetITStatus(SPI_IT_TypeDef SPI_IT)
00360 {
00361     ITStatus pendingbitstatus = RESET;
00362     uint8_t itpos = 0;
00363     uint8_t itmask1 = 0;
00364     uint8_t itmask2 = 0;
00365     uint8_t enablestatus = 0;
00366     assert_param(IS_SPI_GET_IT_OK(SPI_IT));
00367     /* Get the SPI IT index */
00368     itpos = (uint8_t)((uint8_t)1 << ((uint8_t)SPI_IT & (uint8_t)0x0F));
00369
00370     /* Get the SPI IT mask */
00371     itmask1 = (uint8_t)((uint8_t)SPI_IT >> (uint8_t)4);
00372     /* Set the IT mask */
00373     itmask2 = (uint8_t)((uint8_t)1 << itmask1);
00374     /* Get the SPI_ITPENDINGBIT enable bit status */
00375     enablestatus = (uint8_t)((uint8_t)SPI->SR & itmask2);
00376     /* Check the status of the specified SPI interrupt */
00377     if (((SPI->ICR & itpos) != RESET) && enablestatus)
00378     {
00379         /* SPI_ITPENDINGBIT is set */
00380         pendingbitstatus = SET;
00381     }
00382     else
00383     {
00384         /* SPI_ITPENDINGBIT is reset */
00385         pendingbitstatus = RESET;
00386     }
00387     /* Return the SPI_ITPENDINGBIT status */
00388     return  pendingbitstatus;
00389 }
00390 /**
00391   * @brief  Clears the interrupt pending bits.
00392   * @param  SPI_IT: Specifies the interrupt pending bit to clear.
00393   *         This parameter can be one of the following values:
00394   *         - SPI_IT_CRCERR
00395   *         - SPI_IT_WKUP
00396   * @note   - OVR (OverRun Error) interrupt pending bit is cleared by software sequence:
00397   *         a read operation to SPI_DR register (SPI_ReceiveData()) followed by
00398   *         a read operation to SPI_SR register (SPI_GetITStatus()).
00399   *         - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
00400   *         a read/write operation to SPI_SR register (SPI_GetITStatus()) followed by
00401   *         a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
00402   * @retval None
00403   */
00404 void SPI_ClearITPendingBit(SPI_IT_TypeDef SPI_IT)
00405 {
00406     uint8_t itpos = 0;
00407     assert_param(IS_SPI_CLEAR_IT_OK(SPI_IT));
00408
00409     /* Clear  SPI_IT_CRCERR or SPI_IT_WKUP interrupt pending bits */
00410
00411     /* Get the SPI pending bit index */
00412     itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)(SPI_IT & (uint8_t)0xF0) >> 4));
00413     /* Clear the pending bit */
00414     SPI->SR = (uint8_t)(~itpos);
00415
00416 }
00417 /**
00418   * @}
00419   */
00420
00421 /**
00422   * @}
00423   */
00424
00425 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_spi.h Source File

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  • inc

stm8s_spi.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_spi.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the SPI peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_SPI_H
00024 #define __STM8S_SPI_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup SPI_Exported_Types
00034   * @{
00035   */
00036
00037 /**
00038   * @brief  SPI data direction mode
00039   * Warning: element values correspond to BDM, BDOE, RXONLY bits position
00040   */
00041 typedef enum {
00042   SPI_DATADIRECTION_2LINES_FULLDUPLEX = (uint8_t)0x00, /*!< 2-line uni-directional data mode enable */
00043   SPI_DATADIRECTION_2LINES_RXONLY     = (uint8_t)0x04, /*!< Receiver only in 2 line uni-directional data mode */
00044   SPI_DATADIRECTION_1LINE_RX          = (uint8_t)0x80, /*!< Receiver only in 1 line bi-directional data mode */
00045   SPI_DATADIRECTION_1LINE_TX          = (uint8_t)0xC0  /*!< Transmit only in 1 line bi-directional data mode */
00046 } SPI_DataDirection_TypeDef;
00047
00048 /**
00049   * @brief  SPI Slave Select management
00050   * Warning: element values correspond to LSBFIRST bit position
00051   */
00052 typedef enum
00053 {
00054   SPI_NSS_SOFT  = (uint8_t)0x02, /*!< Software slave management disabled */
00055   SPI_NSS_HARD  = (uint8_t)0x00  /*!< Software slave management enabled */
00056 } SPI_NSS_TypeDef;
00057
00058
00059 /**
00060   * @brief  SPI direction transmit/receive
00061   */
00062
00063 typedef enum {
00064   SPI_DIRECTION_RX = (uint8_t)0x00, /*!< Selects Rx receive direction in bi-directional mode */
00065   SPI_DIRECTION_TX = (uint8_t)0x01  /*!< Selects Tx transmission direction in bi-directional mode */
00066 } SPI_Direction_TypeDef;
00067
00068 /**
00069   * @brief  SPI master/slave mode
00070   * Warning: element values correspond to MSTR bit position
00071   */
00072 typedef enum {
00073   SPI_MODE_MASTER = (uint8_t)0x04, /*!< SPI Master configuration */
00074   SPI_MODE_SLAVE  = (uint8_t)0x00  /*!< SPI Slave configuration */
00075 } SPI_Mode_TypeDef;
00076
00077 /**
00078   * @brief  SPI BaudRate Prescaler
00079   * Warning: element values correspond to BR bits position
00080   */
00081 typedef enum {
00082   SPI_BAUDRATEPRESCALER_2   = (uint8_t)0x00, /*!< SPI frequency = frequency(CPU)/2 */
00083   SPI_BAUDRATEPRESCALER_4   = (uint8_t)0x08, /*!< SPI frequency = frequency(CPU)/4 */
00084   SPI_BAUDRATEPRESCALER_8   = (uint8_t)0x10, /*!< SPI frequency = frequency(CPU)/8 */
00085   SPI_BAUDRATEPRESCALER_16  = (uint8_t)0x18, /*!< SPI frequency = frequency(CPU)/16 */
00086   SPI_BAUDRATEPRESCALER_32  = (uint8_t)0x20, /*!< SPI frequency = frequency(CPU)/32 */
00087   SPI_BAUDRATEPRESCALER_64  = (uint8_t)0x28, /*!< SPI frequency = frequency(CPU)/64 */
00088   SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x30, /*!< SPI frequency = frequency(CPU)/128 */
00089   SPI_BAUDRATEPRESCALER_256 = (uint8_t)0x38  /*!< SPI frequency = frequency(CPU)/256 */
00090 } SPI_BaudRatePrescaler_TypeDef;
00091
00092 /**
00093   * @brief  SPI Clock Polarity
00094   * Warning: element values correspond to CPOL bit position
00095   */
00096 typedef enum {
00097   SPI_CLOCKPOLARITY_LOW  = (uint8_t)0x00, /*!< Clock to 0 when idle */
00098   SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x02  /*!< Clock to 1 when idle */
00099 } SPI_ClockPolarity_TypeDef;
00100
00101 /**
00102   * @brief  SPI Clock Phase
00103   * Warning: element values correspond to CPHA bit position
00104   */
00105 typedef enum {
00106   SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, /*!< The first clock transition is the first data capture edge */
00107   SPI_CLOCKPHASE_2EDGE = (uint8_t)0x01  /*!< The second clock transition is the first data capture edge */
00108 } SPI_ClockPhase_TypeDef;
00109
00110 /**
00111   * @brief  SPI Frame Format: MSB or LSB transmitted first
00112   * Warning: element values correspond to LSBFIRST bit position
00113   */
00114 typedef enum {
00115   SPI_FIRSTBIT_MSB = (uint8_t)0x00, /*!< MSB bit will be transmitted first */
00116   SPI_FIRSTBIT_LSB = (uint8_t)0x80  /*!< LSB bit will be transmitted first */
00117 } SPI_FirstBit_TypeDef;
00118
00119 /**
00120   * @brief  SPI CRC Transmit/Receive
00121   */
00122 typedef enum {
00123   SPI_CRC_RX = (uint8_t)0x00, /*!< Select Tx CRC register */
00124   SPI_CRC_TX = (uint8_t)0x01  /*!< Select Rx CRC register */
00125 } SPI_CRC_TypeDef;
00126
00127 /**
00128   * @brief  SPI flags definition - Warning : FLAG value = mapping position register
00129   */
00130 typedef enum {
00131   SPI_FLAG_BSY    = (uint8_t)0x80, /*!< Busy flag */
00132   SPI_FLAG_OVR    = (uint8_t)0x40, /*!< Overrun flag */
00133   SPI_FLAG_MODF   = (uint8_t)0x20, /*!< Mode fault */
00134   SPI_FLAG_CRCERR = (uint8_t)0x10, /*!< CRC error flag */
00135   SPI_FLAG_WKUP   = (uint8_t)0x08, /*!< Wake-up flag */
00136   SPI_FLAG_TXE    = (uint8_t)0x02, /*!< Transmit buffer empty */
00137   SPI_FLAG_RXNE   = (uint8_t)0x01  /*!< Receive buffer empty */
00138 } SPI_Flag_TypeDef;
00139
00140 /**
00141   * @brief  SPI_IT possible values
00142   * Elements values convention: 0xYX
00143   *   X: Position of the corresponding Interrupt
00144   *   Y: ITPENDINGBIT position
00145   */
00146 typedef enum
00147 {
00148   SPI_IT_WKUP   = (uint8_t)0x34,  /*!< Wake-up interrupt*/
00149   SPI_IT_OVR   = (uint8_t)0x65,  /*!< Overrun interrupt*/
00150   SPI_IT_MODF   = (uint8_t)0x55,  /*!< Mode fault interrupt*/
00151   SPI_IT_CRCERR = (uint8_t)0x45,  /*!< CRC error interrupt*/
00152   SPI_IT_TXE    = (uint8_t)0x17,  /*!< Transmit buffer empty interrupt*/
00153   SPI_IT_RXNE   = (uint8_t)0x06,   /*!< Receive buffer not empty interrupt*/
00154   SPI_IT_ERR    = (uint8_t)0x05   /*!< Error interrupt*/
00155 } SPI_IT_TypeDef;
00156
00157 /**
00158   * @}
00159   */
00160
00161 /* Private define ------------------------------------------------------------*/
00162
00163 /** @addtogroup SPI_Private_Macros
00164   * @brief  Macros used by the assert_param function to check the different functions parameters.
00165   * @{
00166   */
00167
00168 /**
00169   * @brief  Macro used by the assert_param function in order to check the data direction mode values
00170   */
00171 #define IS_SPI_DATA_DIRECTION_OK(MODE) (((MODE) == SPI_DATADIRECTION_2LINES_FULLDUPLEX) || \
00172                                         ((MODE) == SPI_DATADIRECTION_2LINES_RXONLY) || \
00173                                         ((MODE) == SPI_DATADIRECTION_1LINE_RX) || \
00174                                         ((MODE) == SPI_DATADIRECTION_1LINE_TX))
00175
00176 /**
00177   * @brief  Macro used by the assert_param function in order to check the mode
00178   *         half duplex data direction values
00179   */
00180 #define IS_SPI_DIRECTION_OK(DIRECTION) (((DIRECTION) == SPI_DIRECTION_RX) || \
00181                                         ((DIRECTION) == SPI_DIRECTION_TX))
00182
00183 /**
00184   * @brief  Macro used by the assert_param function in order to check the NSS
00185   *         management values
00186   */
00187 #define IS_SPI_SLAVEMANAGEMENT_OK(NSS) (((NSS) == SPI_NSS_SOFT) || \
00188                                         ((NSS) == SPI_NSS_HARD))
00189
00190
00191 /**
00192   * @brief  Macro used by the assert_param function in order to check the different
00193   *         sensitivity values for the CRC polynomial
00194   */
00195 #define IS_SPI_CRC_POLYNOMIAL_OK(POLYNOMIAL) ((POLYNOMIAL) > (uint8_t)0x00)
00196
00197 /**
00198   * @brief  Macro used by the assert_param function in order to check the SPI Mode values
00199   */
00200 #define IS_SPI_MODE_OK(MODE) (((MODE) == SPI_MODE_MASTER) || \
00201                               ((MODE) == SPI_MODE_SLAVE))
00202
00203 /**
00204   * @brief  Macro used by the assert_param function in order to check the baudrate values
00205   */
00206 #define IS_SPI_BAUDRATE_PRESCALER_OK(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
00207     ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
00208     ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
00209     ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
00210     ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
00211     ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
00212     ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
00213     ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
00214
00215 /**
00216   * @brief  Macro used by the assert_param function in order to check the polarity values
00217   */
00218 #define IS_SPI_POLARITY_OK(CLKPOL) (((CLKPOL) == SPI_CLOCKPOLARITY_LOW) || \
00219                                     ((CLKPOL) == SPI_CLOCKPOLARITY_HIGH))
00220
00221 /**
00222   * @brief  Macro used by the assert_param function in order to check the phase values
00223   */
00224 #define IS_SPI_PHASE_OK(CLKPHA) (((CLKPHA) == SPI_CLOCKPHASE_1EDGE) || \
00225                                  ((CLKPHA) == SPI_CLOCKPHASE_2EDGE))
00226
00227 /**
00228   * @brief  Macro used by the assert_param function in order to check the first
00229   *         bit to be transmited values
00230   */
00231 #define IS_SPI_FIRSTBIT_OK(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
00232                                  ((BIT) == SPI_FIRSTBIT_LSB))
00233
00234 /**
00235   * @brief  Macro used by the assert_param function in order to check the CRC
00236   *         Transmit/Receive
00237   */
00238 #define IS_SPI_CRC_OK(CRC) (((CRC) == SPI_CRC_TX) || \
00239                             ((CRC) == SPI_CRC_RX))
00240
00241 /**
00242   * @brief  Macro used by the assert_param function in order to check the
00243   *         different flags values
00244   */
00245 #define IS_SPI_FLAGS_OK(FLAG) (((FLAG) == SPI_FLAG_OVR) || \
00246                                ((FLAG) == SPI_FLAG_MODF) || \
00247                                ((FLAG) == SPI_FLAG_CRCERR) || \
00248                                ((FLAG) == SPI_FLAG_WKUP) || \
00249                                ((FLAG) == SPI_FLAG_TXE) || \
00250                                ((FLAG) == SPI_FLAG_RXNE) || \
00251                                ((FLAG) == SPI_FLAG_BSY))
00252
00253 /**
00254   * @brief  Macro used by the assert_param function in order to check the
00255   *         different sensitivity values for the flag that can be cleared
00256   *         by writing 0
00257   */
00258 #define IS_SPI_CLEAR_FLAGS_OK(FLAG) (((FLAG) == SPI_FLAG_CRCERR) || \
00259                                      ((FLAG) == SPI_FLAG_WKUP))
00260
00261 /**
00262   * @brief  Macro used by the assert_param function in order to check the
00263   *        different sensitivity values for the Interrupts
00264   */
00265 #define IS_SPI_CONFIG_IT_OK(Interrupt) (((Interrupt) == SPI_IT_TXE)  || \
00266                                         ((Interrupt) == SPI_IT_RXNE)  || \
00267                                         ((Interrupt) == SPI_IT_ERR) || \
00268                                         ((Interrupt) == SPI_IT_WKUP))
00269
00270 /**
00271   * @brief  Macro used by the assert_param function in order to check the
00272   *         different sensitivity values for the pending bit
00273   */
00274 #define IS_SPI_GET_IT_OK(ITPendingBit) (((ITPendingBit) == SPI_IT_OVR)  || \
00275                                         ((ITPendingBit) == SPI_IT_MODF) || \
00276                                         ((ITPendingBit) == SPI_IT_CRCERR) || \
00277                                         ((ITPendingBit) == SPI_IT_WKUP) || \
00278                                         ((ITPendingBit) == SPI_IT_TXE)  || \
00279                                         ((ITPendingBit) == SPI_IT_RXNE))
00280
00281 /**
00282   * @brief  Macro used by the assert_param function in order to check the
00283   *         different sensitivity values for the pending bit that can be cleared
00284   *         by writing 0
00285   */
00286 #define IS_SPI_CLEAR_IT_OK(ITPendingBit) (((ITPendingBit) == SPI_IT_CRCERR) || \
00287     ((ITPendingBit) == SPI_IT_WKUP))
00288
00289 /**
00290   * @}
00291   */
00292
00293 /** @addtogroup SPI_Exported_Functions
00294   * @{
00295   */
00296 void SPI_DeInit(void);
00297 void SPI_Init(SPI_FirstBit_TypeDef FirstBit,
00298               SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,
00299               SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity,
00300               SPI_ClockPhase_TypeDef ClockPhase,
00301               SPI_DataDirection_TypeDef Data_Direction,
00302               SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial);
00303 void SPI_Cmd(FunctionalState NewState);
00304 void SPI_ITConfig(SPI_IT_TypeDef SPI_IT, FunctionalState NewState);
00305 void SPI_SendData(uint8_t Data);
00306 uint8_t SPI_ReceiveData(void);
00307 void SPI_NSSInternalSoftwareCmd(FunctionalState NewState);
00308 void SPI_TransmitCRC(void);
00309 void SPI_CalculateCRCCmd(FunctionalState NewState);
00310 uint8_t SPI_GetCRC(SPI_CRC_TypeDef SPI_CRC);
00311 void SPI_ResetCRC(void);
00312 uint8_t SPI_GetCRCPolynomial(void);
00313 void SPI_BiDirectionalLineConfig(SPI_Direction_TypeDef SPI_Direction);
00314 FlagStatus SPI_GetFlagStatus(SPI_Flag_TypeDef SPI_FLAG);
00315 void SPI_ClearFlag(SPI_Flag_TypeDef SPI_FLAG);
00316 ITStatus SPI_GetITStatus(SPI_IT_TypeDef SPI_IT);
00317 void SPI_ClearITPendingBit(SPI_IT_TypeDef SPI_IT);
00318
00319 /**
00320   * @}
00321   */
00322
00323 #endif /* __STM8S_SPI_H */
00324
00325 /**
00326   * @}
00327   */
00328
00329 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim1.c Source File

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stm8s_tim1.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim1.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the TIM1 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_tim1.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 static void TI1_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00034                        uint8_t TIM1_ICFilter);
00035 static void TI2_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00036                        uint8_t TIM1_ICFilter);
00037 static void TI3_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00038                        uint8_t TIM1_ICFilter);
00039 static void TI4_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00040                        uint8_t TIM1_ICFilter);
00041
00042 /**
00043   * @addtogroup TIM1_Public_Functions
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  Deinitializes the TIM1 peripheral registers to their default reset values.
00049   * @param  None
00050   * @retval None
00051   */
00052 void TIM1_DeInit(void)
00053 {
00054     TIM1->CR1  = TIM1_CR1_RESET_VALUE;
00055     TIM1->CR2  = TIM1_CR2_RESET_VALUE;
00056     TIM1->SMCR = TIM1_SMCR_RESET_VALUE;
00057     TIM1->ETR  = TIM1_ETR_RESET_VALUE;
00058     TIM1->IER  = TIM1_IER_RESET_VALUE;
00059     TIM1->SR2  = TIM1_SR2_RESET_VALUE;
00060     /* Disable channels */
00061     TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
00062     TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
00063     /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */
00064     TIM1->CCMR1 = 0x01;
00065     TIM1->CCMR2 = 0x01;
00066     TIM1->CCMR3 = 0x01;
00067     TIM1->CCMR4 = 0x01;
00068     /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
00069     TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
00070     TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
00071     TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE;
00072     TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE;
00073     TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE;
00074     TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE;
00075     TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE;
00076     TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE;
00077     TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE;
00078     TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE;
00079     TIM1->ARRH  = TIM1_ARRH_RESET_VALUE;
00080     TIM1->ARRL  = TIM1_ARRL_RESET_VALUE;
00081     TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE;
00082     TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE;
00083     TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE;
00084     TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE;
00085     TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE;
00086     TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE;
00087     TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE;
00088     TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE;
00089     TIM1->OISR  = TIM1_OISR_RESET_VALUE;
00090     TIM1->EGR   = 0x01; /* TIM1_EGR_UG */
00091     TIM1->DTR   = TIM1_DTR_RESET_VALUE;
00092     TIM1->BKR   = TIM1_BKR_RESET_VALUE;
00093     TIM1->RCR   = TIM1_RCR_RESET_VALUE;
00094     TIM1->SR1   = TIM1_SR1_RESET_VALUE;
00095 }
00096
00097 /**
00098   * @brief  Initializes the TIM1 Time Base Unit according to the specified parameters.
00099   * @param  TIM1_Prescaler specifies the Prescaler value.
00100   * @param  TIM1_CounterMode specifies the counter mode  from @ref TIM1_CounterMode_TypeDef .
00101   * @param  TIM1_Period specifies the Period value.
00102   * @param  TIM1_RepetitionCounter specifies the Repetition counter value
00103   * @retval None
00104   */
00105 void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler,
00106                        TIM1_CounterMode_TypeDef TIM1_CounterMode,
00107                        uint16_t TIM1_Period,
00108                        uint8_t TIM1_RepetitionCounter)
00109 {
00110
00111     /* Check parameters */
00112     assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
00113
00114     /* Set the Autoreload value */
00115     TIM1->ARRH = (uint8_t)(TIM1_Period >> 8);
00116     TIM1->ARRL = (uint8_t)(TIM1_Period);
00117
00118     /* Set the Prescaler value */
00119     TIM1->PSCRH = (uint8_t)(TIM1_Prescaler >> 8);
00120     TIM1->PSCRL = (uint8_t)(TIM1_Prescaler);
00121
00122     /* Select the Counter Mode */
00123     TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)(~(TIM1_CR1_CMS | TIM1_CR1_DIR)))
00124                            | (uint8_t)(TIM1_CounterMode));
00125
00126     /* Set the Repetition Counter value */
00127     TIM1->RCR = TIM1_RepetitionCounter;
00128
00129 }
00130
00131 /**
00132   * @brief  Initializes the TIM1 Channel1 according to the specified parameters.
00133   * @param  TIM1_OCMode specifies the Output Compare mode from
00134   *         @ref TIM1_OCMode_TypeDef.
00135   * @param  TIM1_OutputState specifies the Output State from
00136   *         @ref TIM1_OutputState_TypeDef.
00137   * @param  TIM1_OutputNState specifies the Complementary Output State
00138   *         from @ref TIM1_OutputNState_TypeDef.
00139   * @param  TIM1_Pulse specifies the Pulse width value.
00140   * @param  TIM1_OCPolarity specifies the Output Compare Polarity from
00141   *         @ref TIM1_OCPolarity_TypeDef.
00142   * @param  TIM1_OCNPolarity specifies the Complementary Output Compare Polarity
00143   *         from @ref TIM1_OCNPolarity_TypeDef.
00144   * @param  TIM1_OCIdleState specifies the Output Compare Idle State from
00145   *         @ref TIM1_OCIdleState_TypeDef.
00146   * @param  TIM1_OCNIdleState specifies the Complementary Output Compare Idle
00147   *         State from @ref TIM1_OCIdleState_TypeDef.
00148   * @retval None
00149   */
00150 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00151                   TIM1_OutputState_TypeDef TIM1_OutputState,
00152                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00153                   uint16_t TIM1_Pulse,
00154                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00155                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00156                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00157                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
00158 {
00159     /* Check the parameters */
00160     assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00161     assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00162     assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
00163     assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00164     assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
00165     assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00166     assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
00167
00168     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State ,
00169        the Output N State, the Output Polarity & the Output N Polarity*/
00170     TIM1->CCER1 &= (uint8_t)(~( TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE
00171                                | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP));
00172     /* Set the Output State & Set the Output N State & Set the Output Polarity &
00173        Set the Output N Polarity */
00174   TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC1E)
00175                                      | (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC1NE))
00176                            | (uint8_t)( (uint8_t)(TIM1_OCPolarity  & TIM1_CCER1_CC1P)
00177                                         | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC1NP)));
00178
00179     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00180     TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) |
00181                             (uint8_t)TIM1_OCMode);
00182
00183     /* Reset the Output Idle state & the Output N Idle state bits */
00184     TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N));
00185     /* Set the Output Idle state & the Output N Idle state configuration */
00186     TIM1->OISR |= (uint8_t)((uint8_t)( TIM1_OCIdleState & TIM1_OISR_OIS1 ) |
00187                             (uint8_t)( TIM1_OCNIdleState & TIM1_OISR_OIS1N ));
00188
00189     /* Set the Pulse value */
00190     TIM1->CCR1H = (uint8_t)(TIM1_Pulse >> 8);
00191     TIM1->CCR1L = (uint8_t)(TIM1_Pulse);
00192 }
00193
00194 /**
00195   * @brief  Initializes the TIM1 Channel2 according to the specified parameters.
00196   * @param  TIM1_OCMode specifies the Output Compare mode from
00197   *         @ref TIM1_OCMode_TypeDef.
00198   * @param  TIM1_OutputState specifies the Output State from
00199   *         @ref TIM1_OutputState_TypeDef.
00200   * @param  TIM1_OutputNState specifies the Complementary Output State from
00201   *         @ref TIM1_OutputNState_TypeDef.
00202   * @param  TIM1_Pulse specifies the Pulse width value.
00203   * @param  TIM1_OCPolarity specifies the Output Compare Polarity from
00204   *         @ref TIM1_OCPolarity_TypeDef.
00205   * @param  TIM1_OCNPolarity specifies the Complementary Output Compare Polarity
00206   *         from @ref TIM1_OCNPolarity_TypeDef.
00207   * @param  TIM1_OCIdleState specifies the Output Compare Idle State from
00208   *         @ref TIM1_OCIdleState_TypeDef.
00209   * @param  TIM1_OCNIdleState specifies the Complementary Output Compare Idle
00210   *         State from @ref TIM1_OCIdleState_TypeDef.
00211   * @retval None
00212   */
00213 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00214                   TIM1_OutputState_TypeDef TIM1_OutputState,
00215                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00216                   uint16_t TIM1_Pulse,
00217                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00218                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00219                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00220                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
00221 {
00222     /* Check the parameters */
00223     assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00224     assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00225     assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
00226     assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00227     assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
00228     assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00229     assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
00230
00231     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State ,
00232        the Output N State, the Output Polarity & the Output N Polarity*/
00233     TIM1->CCER1 &= (uint8_t)(~( TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE |
00234                                 TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP));
00235
00236     /* Set the Output State & Set the Output N State & Set the Output Polarity &
00237        Set the Output N Polarity */
00238     TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC2E  ) |
00239                              (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC2NE )) |
00240                              (uint8_t)((uint8_t)(TIM1_OCPolarity  & TIM1_CCER1_CC2P  ) |
00241                              (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC2NP )));
00242
00243     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00244     TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) |
00245                              (uint8_t)TIM1_OCMode);
00246
00247     /* Reset the Output Idle state & the Output N Idle state bits */
00248     TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N));
00249     /* Set the Output Idle state & the Output N Idle state configuration */
00250     TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS2 & TIM1_OCIdleState) |
00251                             (uint8_t)(TIM1_OISR_OIS2N & TIM1_OCNIdleState));
00252
00253     /* Set the Pulse value */
00254     TIM1->CCR2H = (uint8_t)(TIM1_Pulse >> 8);
00255     TIM1->CCR2L = (uint8_t)(TIM1_Pulse);
00256
00257 }
00258
00259 /**
00260   * @brief  Initializes the TIM1 Channel3 according to the specified parameters.
00261   * @param  TIM1_OCMode specifies the Output Compare mode  from
00262   *         @ref TIM1_OCMode_TypeDef.
00263   * @param  TIM1_OutputState specifies the Output State
00264   *         from @ref TIM1_OutputState_TypeDef.
00265   * @param  TIM1_OutputNState specifies the Complementary Output State
00266   *         from @ref TIM1_OutputNState_TypeDef.
00267   * @param  TIM1_Pulse specifies the Pulse width value.
00268   * @param  TIM1_OCPolarity specifies the Output Compare Polarity  from
00269   *         @ref TIM1_OCPolarity_TypeDef.
00270   * @param  TIM1_OCNPolarity specifies the Complementary  Output Compare
00271   *         Polarity from @ref TIM1_OCNPolarity_TypeDef.
00272   * @param  TIM1_OCIdleState specifies the Output Compare Idle State
00273   *         from @ref TIM1_OCIdleState_TypeDef.
00274   * @param  TIM1_OCNIdleState specifies the Complementary Output Compare
00275   *         Idle State  from @ref TIM1_OCIdleState_TypeDef.
00276   * @retval None
00277   */
00278 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00279                   TIM1_OutputState_TypeDef TIM1_OutputState,
00280                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00281                   uint16_t TIM1_Pulse,
00282                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00283                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00284                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00285                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
00286 {
00287     /* Check the parameters */
00288     assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00289     assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00290     assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
00291     assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00292     assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
00293     assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00294     assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
00295
00296     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State ,
00297        the Output N State, the Output Polarity & the Output N Polarity*/
00298     TIM1->CCER2 &= (uint8_t)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE |
00299                                 TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));
00300     /* Set the Output State & Set the Output N State & Set the Output Polarity &
00301        Set the Output N Polarity */
00302     TIM1->CCER2 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState  & TIM1_CCER2_CC3E   ) |
00303                              (uint8_t)(TIM1_OutputNState & TIM1_CCER2_CC3NE  )) |
00304                              (uint8_t)((uint8_t)(TIM1_OCPolarity   & TIM1_CCER2_CC3P   ) |
00305                              (uint8_t)(TIM1_OCNPolarity  & TIM1_CCER2_CC3NP  )));
00306
00307     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00308     TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) |
00309                              (uint8_t)TIM1_OCMode);
00310
00311     /* Reset the Output Idle state & the Output N Idle state bits */
00312     TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));
00313     /* Set the Output Idle state & the Output N Idle state configuration */
00314     TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS3 & TIM1_OCIdleState) |
00315                             (uint8_t)(TIM1_OISR_OIS3N & TIM1_OCNIdleState));
00316
00317     /* Set the Pulse value */
00318     TIM1->CCR3H = (uint8_t)(TIM1_Pulse >> 8);
00319     TIM1->CCR3L = (uint8_t)(TIM1_Pulse);
00320
00321 }
00322
00323 /**
00324   * @brief  Initializes the TIM1 Channel4 according to the specified parameters.
00325   * @param  TIM1_OCMode specifies the Output Compare mode  from
00326   *         @ref TIM1_OCMode_TypeDef.
00327   * @param  TIM1_OutputState specifies the Output State
00328   *         from @ref TIM1_OutputState_TypeDef.
00329   * @param  TIM1_Pulse specifies the Pulse width  value.
00330   * @param  TIM1_OCPolarity specifies the Output Compare Polarity
00331   *         from @ref TIM1_OCPolarity_TypeDef.
00332   * @param  TIM1_OCIdleState specifies the Output Compare Idle State
00333   *         from @ref TIM1_OCIdleState_TypeDef.
00334   * @retval None
00335   */
00336 void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00337                   TIM1_OutputState_TypeDef TIM1_OutputState,
00338                   uint16_t TIM1_Pulse,
00339                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00340                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
00341 {
00342     /* Check the parameters */
00343     assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00344     assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00345     assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00346     assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00347
00348     /* Disable the Channel 4: Reset the CCE Bit */
00349     TIM1->CCER2 &= (uint8_t)(~(TIM1_CCER2_CC4E | TIM1_CCER2_CC4P));
00350     /* Set the Output State  &  the Output Polarity */
00351     TIM1->CCER2 |= (uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER2_CC4E ) |
00352                              (uint8_t)(TIM1_OCPolarity  & TIM1_CCER2_CC4P ));
00353
00354     /* Reset the Output Compare Bit  and Set the Output Compare Mode */
00355     TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM)) |
00356                             TIM1_OCMode);
00357
00358     /* Set the Output Idle state */
00359     if (TIM1_OCIdleState != TIM1_OCIDLESTATE_RESET)
00360     {
00361         TIM1->OISR |= (uint8_t)(~TIM1_CCER2_CC4P);
00362     }
00363     else
00364     {
00365         TIM1->OISR &= (uint8_t)(~TIM1_OISR_OIS4);
00366     }
00367
00368     /* Set the Pulse value */
00369     TIM1->CCR4H = (uint8_t)(TIM1_Pulse >> 8);
00370     TIM1->CCR4L = (uint8_t)(TIM1_Pulse);
00371
00372 }
00373
00374 /**
00375   * @brief  Configures the Break feature, dead time, Lock level, the OSSI,
00376   *         and the AOE(automatic output enable).
00377   * @param  TIM1_OSSIState specifies the OSSIS State from @ref TIM1_OSSIState_TypeDef.
00378   * @param  TIM1_LockLevel specifies the lock level from @ref TIM1_LockLevel_TypeDef.
00379   * @param  TIM1_DeadTime specifies the dead time value.
00380   * @param  TIM1_Break specifies the Break state @ref TIM1_BreakState_TypeDef.
00381   * @param  TIM1_BreakPolarity specifies the Break polarity from
00382   *         @ref TIM1_BreakPolarity_TypeDef.
00383   * @param  TIM1_AutomaticOutput specifies the Automatic Output configuration
00384   *         from @ref TIM1_AutomaticOutput_TypeDef.
00385   * @retval None
00386   */
00387 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
00388                      TIM1_LockLevel_TypeDef TIM1_LockLevel,
00389                      uint8_t TIM1_DeadTime,
00390                      TIM1_BreakState_TypeDef TIM1_Break,
00391                      TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
00392                      TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
00393 {
00394     /* Check the parameters */
00395     assert_param(IS_TIM1_OSSI_STATE_OK(TIM1_OSSIState));
00396     assert_param(IS_TIM1_LOCK_LEVEL_OK(TIM1_LockLevel));
00397     assert_param(IS_TIM1_BREAK_STATE_OK(TIM1_Break));
00398     assert_param(IS_TIM1_BREAK_POLARITY_OK(TIM1_BreakPolarity));
00399     assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(TIM1_AutomaticOutput));
00400
00401     TIM1->DTR = (uint8_t)(TIM1_DeadTime);
00402     /* Set the Lock level, the Break enable Bit and the Polarity, the OSSI State,
00403               the dead time value  and the Automatic Output Enable Bit */
00404
00405     TIM1->BKR  =  (uint8_t)((uint8_t)(TIM1_OSSIState | (uint8_t)TIM1_LockLevel)  |
00406                             (uint8_t)((uint8_t)(TIM1_Break | (uint8_t)TIM1_BreakPolarity)  |
00407                             (uint8_t)TIM1_AutomaticOutput));
00408
00409 }
00410
00411 /**
00412   * @brief  Initializes the TIM1 peripheral according to the specified parameters.
00413   * @param  TIM1_Channel specifies the input capture channel from TIM1_Channel_TypeDef.
00414   * @param  TIM1_ICPolarity specifies the Input capture polarity from
00415   *         TIM1_ICPolarity_TypeDef .
00416   * @param  TIM1_ICSelection specifies the Input capture source selection from
00417   *         TIM1_ICSelection_TypeDef.
00418   * @param  TIM1_ICPrescaler specifies the Input capture Prescaler from
00419   *         TIM1_ICPSC_TypeDef.
00420   * @param  TIM1_ICFilter specifies the Input capture filter value.
00421   * @retval None
00422   */
00423 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
00424                  TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00425                  TIM1_ICSelection_TypeDef TIM1_ICSelection,
00426                  TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
00427                  uint8_t TIM1_ICFilter)
00428 {
00429
00430     /* Check the parameters */
00431     assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
00432     assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
00433     assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
00434     assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
00435     assert_param(IS_TIM1_IC_FILTER_OK(TIM1_ICFilter));
00436
00437     if (TIM1_Channel == TIM1_CHANNEL_1)
00438     {
00439         /* TI1 Configuration */
00440         TI1_Config((uint8_t)TIM1_ICPolarity,
00441                    (uint8_t)TIM1_ICSelection,
00442                    (uint8_t)TIM1_ICFilter);
00443         /* Set the Input Capture Prescaler value */
00444         TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
00445     }
00446     else if (TIM1_Channel == TIM1_CHANNEL_2)
00447     {
00448         /* TI2 Configuration */
00449         TI2_Config((uint8_t)TIM1_ICPolarity,
00450                    (uint8_t)TIM1_ICSelection,
00451                    (uint8_t)TIM1_ICFilter);
00452         /* Set the Input Capture Prescaler value */
00453         TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
00454     }
00455     else if (TIM1_Channel == TIM1_CHANNEL_3)
00456     {
00457         /* TI3 Configuration */
00458         TI3_Config((uint8_t)TIM1_ICPolarity,
00459                    (uint8_t)TIM1_ICSelection,
00460                    (uint8_t)TIM1_ICFilter);
00461         /* Set the Input Capture Prescaler value */
00462         TIM1_SetIC3Prescaler(TIM1_ICPrescaler);
00463     }
00464     else
00465     {
00466         /* TI4 Configuration */
00467         TI4_Config((uint8_t)TIM1_ICPolarity,
00468                    (uint8_t)TIM1_ICSelection,
00469                    (uint8_t)TIM1_ICFilter);
00470         /* Set the Input Capture Prescaler value */
00471         TIM1_SetIC4Prescaler(TIM1_ICPrescaler);
00472     }
00473
00474 }
00475
00476 /**
00477   * @brief  Configures the TIM1 peripheral in PWM Input Mode according to the
00478   *         specified parameters.
00479   * @param  TIM1_Channel specifies the input capture channel from
00480   *         @ref TIM1_Channel_TypeDef.
00481   * @param  TIM1_ICPolarity specifies the Input capture polarity from
00482   *         @ref TIM1_ICPolarity_TypeDef .
00483   * @param  TIM1_ICSelection specifies the Input capture source selection  from
00484   *         @ref TIM1_ICSelection_TypeDef.
00485   * @param  TIM1_ICPrescaler specifies the Input capture Prescaler from
00486   *         @ref TIM1_ICPSC_TypeDef.
00487   * @param  TIM1_ICFilter specifies the Input capture filter value.
00488   * @retval None
00489   */
00490 void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel,
00491                      TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00492                      TIM1_ICSelection_TypeDef TIM1_ICSelection,
00493                      TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
00494                      uint8_t TIM1_ICFilter)
00495 {
00496     uint8_t icpolarity = TIM1_ICPOLARITY_RISING;
00497     uint8_t icselection = TIM1_ICSELECTION_DIRECTTI;
00498
00499     /* Check the parameters */
00500     assert_param(IS_TIM1_PWMI_CHANNEL_OK(TIM1_Channel));
00501     assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
00502     assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
00503     assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
00504
00505     /* Select the Opposite Input Polarity */
00506     if (TIM1_ICPolarity != TIM1_ICPOLARITY_FALLING)
00507     {
00508         icpolarity = TIM1_ICPOLARITY_FALLING;
00509     }
00510     else
00511     {
00512         icpolarity = TIM1_ICPOLARITY_RISING;
00513     }
00514
00515     /* Select the Opposite Input */
00516     if (TIM1_ICSelection == TIM1_ICSELECTION_DIRECTTI)
00517     {
00518         icselection = TIM1_ICSELECTION_INDIRECTTI;
00519     }
00520     else
00521     {
00522         icselection = TIM1_ICSELECTION_DIRECTTI;
00523     }
00524
00525     if (TIM1_Channel == TIM1_CHANNEL_1)
00526     {
00527         /* TI1 Configuration */
00528         TI1_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSelection,
00529                    (uint8_t)TIM1_ICFilter);
00530
00531         /* Set the Input Capture Prescaler value */
00532         TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
00533
00534         /* TI2 Configuration */
00535         TI2_Config(icpolarity, icselection, TIM1_ICFilter);
00536
00537         /* Set the Input Capture Prescaler value */
00538         TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
00539     }
00540     else
00541     {
00542         /* TI2 Configuration */
00543         TI2_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSelection,
00544                    (uint8_t)TIM1_ICFilter);
00545
00546         /* Set the Input Capture Prescaler value */
00547         TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
00548
00549         /* TI1 Configuration */
00550         TI1_Config(icpolarity, icselection, TIM1_ICFilter);
00551
00552         /* Set the Input Capture Prescaler value */
00553         TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
00554     }
00555 }
00556
00557 /**
00558   * @brief  Enables or disables the TIM1 peripheral.
00559   * @param  NewState new state of the TIM1 peripheral.
00560         *         This parameter can be ENABLE or DISABLE.
00561   * @retval None
00562   */
00563 void TIM1_Cmd(FunctionalState NewState)
00564 {
00565     /* Check the parameters */
00566     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00567
00568     /* set or Reset the CEN Bit */
00569     if (NewState != DISABLE)
00570     {
00571         TIM1->CR1 |= TIM1_CR1_CEN;
00572     }
00573     else
00574     {
00575         TIM1->CR1 &= (uint8_t)(~TIM1_CR1_CEN);
00576     }
00577 }
00578
00579 /**
00580   * @brief  Enables or disables the TIM1 peripheral Main Outputs.
00581   * @param  NewState new state of the TIM1 peripheral.
00582         *         This parameter can be ENABLE or DISABLE.
00583   * @retval None
00584   */
00585 void TIM1_CtrlPWMOutputs(FunctionalState NewState)
00586 {
00587     /* Check the parameters */
00588     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00589
00590     /* Set or Reset the MOE Bit */
00591
00592     if (NewState != DISABLE)
00593     {
00594         TIM1->BKR |= TIM1_BKR_MOE;
00595     }
00596     else
00597     {
00598         TIM1->BKR &= (uint8_t)(~TIM1_BKR_MOE);
00599     }
00600 }
00601
00602 /**
00603   * @brief  Enables or disables the specified TIM1 interrupts.
00604   * @param  NewState new state of the TIM1 peripheral.
00605   *         This parameter can be: ENABLE or DISABLE.
00606   * @param  TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled.
00607   *         This parameter can be any combination of the following values:
00608   *           - TIM1_IT_UPDATE: TIM1 update Interrupt source
00609   *           - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
00610   *           - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
00611   *           - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
00612   *           - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
00613   *           - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt source
00614   *           - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
00615   *           - TIM1_IT_BREAK: TIM1 Break Interrupt source
00616   * @param  NewState new state of the TIM1 peripheral.
00617   * @retval None
00618   */
00619 void TIM1_ITConfig(TIM1_IT_TypeDef  TIM1_IT, FunctionalState NewState)
00620 {
00621     /* Check the parameters */
00622     assert_param(IS_TIM1_IT_OK(TIM1_IT));
00623     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00624
00625     if (NewState != DISABLE)
00626     {
00627         /* Enable the Interrupt sources */
00628         TIM1->IER |= (uint8_t)TIM1_IT;
00629     }
00630     else
00631     {
00632         /* Disable the Interrupt sources */
00633         TIM1->IER &= (uint8_t)(~(uint8_t)TIM1_IT);
00634     }
00635 }
00636
00637 /**
00638   * @brief  Configures the TIM1 internal Clock.
00639   * @param  None
00640   * @retval None
00641   */
00642 void TIM1_InternalClockConfig(void)
00643 {
00644     /* Disable slave mode to clock the prescaler directly with the internal clock */
00645     TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_SMS);
00646 }
00647
00648 /**
00649   * @brief  Configures the TIM1 External clock Mode1.
00650   * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
00651   *         This parameter can be one of the following values:
00652   *                       - TIM1_EXTTRGPSC_OFF
00653   *                       - TIM1_EXTTRGPSC_DIV2
00654   *                       - TIM1_EXTTRGPSC_DIV4
00655   *                       - TIM1_EXTTRGPSC_DIV8.
00656   * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
00657   *         This parameter can be one of the following values:
00658   *                       - TIM1_EXTTRGPOLARITY_INVERTED
00659   *                       - TIM1_EXTTRGPOLARITY_NONINVERTED
00660   * @param  ExtTRGFilter specifies the External Trigger Filter.
00661   *         This parameter must be a value between 0x00 and 0x0F
00662   * @retval None
00663   */
00664 void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00665                               TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00666                               uint8_t ExtTRGFilter)
00667 {
00668     /* Check the parameters */
00669     assert_param(IS_TIM1_EXT_PRESCALER_OK(TIM1_ExtTRGPrescaler));
00670     assert_param(IS_TIM1_EXT_POLARITY_OK(TIM1_ExtTRGPolarity));
00671
00672     /* Configure the ETR Clock source */
00673     TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
00674
00675     /* Select the External clock mode1 & Select the Trigger selection : ETRF */
00676     TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~(uint8_t)(TIM1_SMCR_SMS | TIM1_SMCR_TS )))
00677                            | (uint8_t)((uint8_t)TIM1_SLAVEMODE_EXTERNAL1 | TIM1_TS_ETRF ));
00678 }
00679
00680 /**
00681   * @brief  Configures the TIM1 External clock Mode2.
00682   * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
00683   *         This parameter can be one of the following values:
00684   *                       - TIM1_EXTTRGPSC_OFF
00685   *                       - TIM1_EXTTRGPSC_DIV2
00686   *                       - TIM1_EXTTRGPSC_DIV4
00687   *                       - TIM1_EXTTRGPSC_DIV8.
00688   * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
00689   *         This parameter can be one of the following values:
00690   *                       - TIM1_EXTTRGPOLARITY_INVERTED
00691   *                       - TIM1_EXTTRGPOLARITY_NONINVERTED
00692   * @param  ExtTRGFilter specifies the External Trigger Filter.
00693   *         This parameter must be a value between 0x00 and 0x0F
00694   * @retval None
00695   */
00696 void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00697                               TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00698                               uint8_t ExtTRGFilter)
00699 {
00700     /* Check the parameters */
00701     assert_param(IS_TIM1_EXT_PRESCALER_OK(TIM1_ExtTRGPrescaler));
00702     assert_param(IS_TIM1_EXT_POLARITY_OK(TIM1_ExtTRGPolarity));
00703
00704     /* Configure the ETR Clock source */
00705     TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
00706
00707     /* Enable the External clock mode2 */
00708     TIM1->ETR |= TIM1_ETR_ECE;
00709 }
00710
00711 /**
00712   * @brief  Configures the TIM1 External Trigger.
00713   * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
00714   *         This parameter can be one of the following values:
00715   *                       - TIM1_EXTTRGPSC_OFF
00716   *                       - TIM1_EXTTRGPSC_DIV2
00717   *                       - TIM1_EXTTRGPSC_DIV4
00718   *                       - TIM1_EXTTRGPSC_DIV8.
00719   * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
00720   *         This parameter can be one of the following values:
00721   *                       - TIM1_EXTTRGPOLARITY_INVERTED
00722   *                       - TIM1_EXTTRGPOLARITY_NONINVERTED
00723   * @param  ExtTRGFilter specifies the External Trigger Filter.
00724   *         This parameter must be a value between 0x00 and 0x0F
00725   * @retval None
00726   */
00727 void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00728                     TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00729                     uint8_t ExtTRGFilter)
00730 {
00731     /* Check the parameters */
00732     assert_param(IS_TIM1_EXT_TRG_FILTER_OK(ExtTRGFilter));
00733     /* Set the Prescaler, the Filter value and the Polarity */
00734     TIM1->ETR |= (uint8_t)((uint8_t)(TIM1_ExtTRGPrescaler | (uint8_t)TIM1_ExtTRGPolarity )|
00735                       (uint8_t)ExtTRGFilter );
00736 }
00737
00738 /**
00739   * @brief  Configures the TIM1 Trigger as External Clock.
00740   * @param  TIM1_TIxExternalCLKSource specifies Trigger source.
00741   *         This parameter can be one of the following values:
00742   *                     - TIM1_TIXEXTERNALCLK1SOURCE_TI1: TI1 Edge Detector
00743   *                     - TIM1_TIXEXTERNALCLK1SOURCE_TI2: Filtered TIM1 Input 1
00744   *                     - TIM1_TIXEXTERNALCLK1SOURCE_TI1ED: Filtered TIM1 Input 2
00745   * @param  TIM1_ICPolarity specifies the TIx Polarity.
00746   *         This parameter can be:
00747   *                     - TIM1_ICPOLARITY_RISING
00748   *                     - TIM1_ICPOLARITY_FALLING
00749   * @param  ICFilter specifies the filter value.
00750   *         This parameter must be a value between 0x00 and 0x0F
00751   * @retval None
00752   */
00753 void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource,
00754                                  TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00755                                  uint8_t ICFilter)
00756 {
00757     /* Check the parameters */
00758     assert_param(IS_TIM1_TIXCLK_SOURCE_OK(TIM1_TIxExternalCLKSource));
00759     assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
00760     assert_param(IS_TIM1_IC_FILTER_OK(ICFilter));
00761
00762     /* Configure the TIM1 Input Clock Source */
00763     if (TIM1_TIxExternalCLKSource == TIM1_TIXEXTERNALCLK1SOURCE_TI2)
00764     {
00765         TI2_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSELECTION_DIRECTTI, (uint8_t)ICFilter);
00766     }
00767     else
00768     {
00769         TI1_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSELECTION_DIRECTTI, (uint8_t)ICFilter);
00770     }
00771
00772     /* Select the Trigger source */
00773     TIM1_SelectInputTrigger((TIM1_TS_TypeDef)TIM1_TIxExternalCLKSource);
00774
00775     /* Select the External clock mode1 */
00776     TIM1->SMCR |= (uint8_t)(TIM1_SLAVEMODE_EXTERNAL1);
00777 }
00778
00779 /**
00780   * @brief  Selects the TIM1 Input Trigger source.
00781   * @param   TIM1_InputTriggerSource specifies Input Trigger source.
00782   * This parameter can be one of the following values:
00783   *                       - TIM1_TS_TI1F_ED: TI1 Edge Detector
00784   *                       - TIM1_TS_TI1FP1: Filtered Timer Input 1
00785   *                       - TIM1_TS_TI2FP2: Filtered Timer Input 2
00786   *                       - TIM1_TS_ETRF: External Trigger input
00787   * @retval None
00788   */
00789 void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource)
00790 {
00791     /* Check the parameters */
00792     assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource));
00793
00794     /* Select the Tgigger Source */
00795     TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_TS)) | (uint8_t)TIM1_InputTriggerSource);
00796 }
00797
00798
00799 /**
00800   * @brief  Enables or Disables the TIM1 Update event.
00801   * @param   NewState new state of the TIM1 peripheral Preload register. This parameter can
00802   * be ENABLE or DISABLE.
00803   * @retval None
00804   */
00805
00806 void TIM1_UpdateDisableConfig(FunctionalState NewState)
00807 {
00808     /* Check the parameters */
00809     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00810
00811     /* Set or Reset the UDIS Bit */
00812     if (NewState != DISABLE)
00813     {
00814         TIM1->CR1 |= TIM1_CR1_UDIS;
00815     }
00816     else
00817     {
00818         TIM1->CR1 &= (uint8_t)(~TIM1_CR1_UDIS);
00819     }
00820 }
00821
00822 /**
00823   * @brief  Selects the TIM1 Update Request Interrupt source.
00824   * @param   TIM1_UpdateSource specifies the Update source.
00825   * This parameter can be one of the following values
00826   *                       - TIM1_UPDATESOURCE_REGULAR
00827   *                       - TIM1_UPDATESOURCE_GLOBAL
00828   * @retval None
00829   */
00830 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
00831 {
00832     /* Check the parameters */
00833     assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource));
00834
00835     /* Set or Reset the URS Bit */
00836     if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL)
00837     {
00838         TIM1->CR1 |= TIM1_CR1_URS;
00839     }
00840     else
00841     {
00842         TIM1->CR1 &= (uint8_t)(~TIM1_CR1_URS);
00843     }
00844 }
00845
00846
00847 /**
00848   * @brief  Enables or Disables the TIM1’s Hall sensor interface.
00849   * @param   NewState new state of the TIM1 Hall sensor interface.This parameter can
00850   * be ENABLE or DISABLE.
00851   * @retval None
00852   */
00853 void TIM1_SelectHallSensor(FunctionalState NewState)
00854 {
00855     /* Check the parameters */
00856     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00857
00858     /* Set or Reset the TI1S Bit */
00859     if (NewState != DISABLE)
00860     {
00861         TIM1->CR2 |= TIM1_CR2_TI1S;
00862     }
00863     else
00864     {
00865         TIM1->CR2 &= (uint8_t)(~TIM1_CR2_TI1S);
00866     }
00867 }
00868
00869
00870 /**
00871   * @brief  Selects the TIM1’s One Pulse Mode.
00872   * @param   TIM1_OPMode specifies the OPM Mode to be used.
00873   * This parameter can be one of the following values
00874   *                    - TIM1_OPMODE_SINGLE
00875   *                    - TIM1_OPMODE_REPETITIVE
00876   * @retval None
00877   */
00878 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)
00879 {
00880     /* Check the parameters */
00881     assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode));
00882
00883     /* Set or Reset the OPM Bit */
00884     if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE)
00885     {
00886         TIM1->CR1 |= TIM1_CR1_OPM;
00887     }
00888     else
00889     {
00890         TIM1->CR1 &= (uint8_t)(~TIM1_CR1_OPM);
00891     }
00892
00893 }
00894
00895
00896 /**
00897   * @brief  Selects the TIM1 Trigger Output Mode.
00898   * @param   TIM1_TRGOSource specifies the Trigger Output source.
00899   * This parameter can be one of the following values
00900   *                       - TIM1_TRGOSOURCE_RESET
00901   *                       - TIM1_TRGOSOURCE_ENABLE
00902   *                       - TIM1_TRGOSOURCE_UPDATE
00903   *                       - TIM1_TRGOSource_OC1
00904   *                       - TIM1_TRGOSOURCE_OC1REF
00905   *                       - TIM1_TRGOSOURCE_OC2REF
00906   *                       - TIM1_TRGOSOURCE_OC3REF
00907   * @retval None
00908   */
00909 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
00910 {
00911     /* Check the parameters */
00912     assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource));
00913
00914     /* Reset the MMS Bits & Select the TRGO source */
00915     TIM1->CR2 = (uint8_t)((uint8_t)(TIM1->CR2 & (uint8_t)(~TIM1_CR2_MMS)) |
00916                           (uint8_t) TIM1_TRGOSource);
00917 }
00918
00919 /**
00920   * @brief  Selects the TIM1 Slave Mode.
00921   * @param   TIM1_SlaveMode specifies the TIM1 Slave Mode.
00922   * This parameter can be one of the following values
00923   *                       - TIM1_SLAVEMODE_RESET
00924   *                       - TIM1_SLAVEMODE_GATED
00925   *                       - TIM1_SLAVEMODE_TRIGGER
00926   *                       - TIM1_SLAVEMODE_EXTERNAL1
00927   * @retval None
00928   */
00929 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
00930 {
00931
00932     /* Check the parameters */
00933     assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode));
00934
00935     /* Reset the SMS Bits */ /* Select the Slave Mode */
00936     TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_SMS)) |
00937                            (uint8_t)TIM1_SlaveMode);
00938
00939 }
00940
00941 /**
00942   * @brief  Sets or Resets the TIM1 Master/Slave Mode.
00943   * @param   NewState new state of the synchronization between TIM1 and its slaves
00944   *  (through TRGO). This parameter can be ENABLE or DISABLE.
00945   * @retval None
00946   */
00947 void TIM1_SelectMasterSlaveMode(FunctionalState NewState)
00948 {
00949     /* Check the parameters */
00950     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00951
00952     /* Set or Reset the MSM Bit */
00953     if (NewState != DISABLE)
00954     {
00955         TIM1->SMCR |= TIM1_SMCR_MSM;
00956     }
00957     else
00958     {
00959         TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_MSM);
00960     }
00961 }
00962
00963 /**
00964   * @brief  Configures the TIM1 Encoder Interface.
00965   * @param   TIM1_EncoderMode specifies the TIM1 Encoder Mode.
00966   * This parameter can be one of the following values
00967   * - TIM1_ENCODERMODE_TI1: Counter counts on TI1FP1 edge
00968         * depending on TI2FP2 level.
00969   * - TIM1_ENCODERMODE_TI2: Counter counts on TI2FP2 edge
00970   *     depending on TI1FP1 level.
00971   * - TIM1_ENCODERMODE_TI12: Counter counts on both TI1FP1 and
00972   * TI2FP2 edges depending on the level of the other input.
00973   * @param   TIM1_IC1Polarity specifies the IC1 Polarity.
00974   * This parameter can be one of the following values
00975   *                       - TIM1_ICPOLARITY_FALLING
00976   *                       - TIM1_ICPOLARITY_RISING
00977   * @param   TIM1_IC2Polarity specifies the IC2 Polarity.
00978   * This parameter can be one of the following values
00979   *                       - TIM1_ICPOLARITY_FALLING
00980   *                       - TIM1_ICPOLARITY_RISING
00981   * @retval None
00982   */
00983 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
00984                                  TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
00985                                  TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
00986 {
00987
00988
00989     /* Check the parameters */
00990     assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode));
00991     assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity));
00992     assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity));
00993
00994     /* Set the TI1 and the TI2 Polarities */
00995     if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING)
00996     {
00997         TIM1->CCER1 |= TIM1_CCER1_CC1P;
00998     }
00999     else
01000     {
01001         TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
01002     }
01003
01004     if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING)
01005     {
01006         TIM1->CCER1 |= TIM1_CCER1_CC2P;
01007     }
01008     else
01009     {
01010         TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
01011     }
01012     /* Set the encoder Mode */
01013     TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(TIM1_SMCR_MSM | TIM1_SMCR_TS))
01014                            | (uint8_t) TIM1_EncoderMode);
01015
01016     /* Select the Capture Compare 1 and the Capture Compare 2 as input */
01017     TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_CCxS))
01018                             | (uint8_t) CCMR_TIxDirect_Set);
01019     TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_CCxS))
01020                             | (uint8_t) CCMR_TIxDirect_Set);
01021
01022 }
01023
01024 /**
01025   * @brief  Configures the TIM1 Prescaler.
01026   * @param   Prescaler specifies the Prescaler Register value
01027   * This parameter must be a value between 0x0000 and 0xFFFF
01028   * @param   TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode.
01029   * This parameter can be one of the following values
01030   * - TIM1_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
01031   * - TIM1_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
01032   * @retval None
01033   */
01034
01035 void TIM1_PrescalerConfig(uint16_t Prescaler,
01036                           TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
01037 {
01038     /* Check the parameters */
01039     assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode));
01040
01041     /* Set the Prescaler value */
01042     TIM1->PSCRH = (uint8_t)(Prescaler >> 8);
01043     TIM1->PSCRL = (uint8_t)(Prescaler);
01044
01045     /* Set or reset the UG Bit */
01046     TIM1->EGR = (uint8_t)TIM1_PSCReloadMode;
01047
01048 }
01049
01050 /**
01051   * @brief  Specifies the TIM1 Counter Mode to be used.
01052   * @param   TIM1_CounterMode specifies the Counter Mode to be used
01053   * This parameter can be one of the following values:
01054   * - TIM1_COUNTERMODE_UP: TIM1 Up Counting Mode
01055   * - TIM1_COUNTERMODE_DOWN: TIM1 Down Counting Mode
01056   * - TIM1_COUNTERMODE_CENTERALIGNED1: TIM1 Center Aligned Mode1
01057   * - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
01058   * - TIM1_COUNTERMODE_CENTERALIGNED3: TIM1 Center Aligned Mode3
01059   * @retval None
01060   */
01061 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)
01062 {
01063     /* Check the parameters */
01064     assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
01065
01066
01067     /* Reset the CMS and DIR Bits & Set the Counter Mode */
01068     TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)((uint8_t)(~TIM1_CR1_CMS) & (uint8_t)(~TIM1_CR1_DIR)))
01069                           | (uint8_t)TIM1_CounterMode);
01070 }
01071
01072
01073 /**
01074   * @brief  Forces the TIM1 Channel1 output waveform to active or inactive level.
01075   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01076   * This parameter can be one of the following values:
01077   * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC1REF
01078   * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
01079   * @retval None
01080   */
01081 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01082 {
01083     /* Check the parameters */
01084     assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01085
01086     /* Reset the OCM Bits & Configure the Forced output Mode */
01087     TIM1->CCMR1 =  (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM))|
01088                              (uint8_t)TIM1_ForcedAction);
01089 }
01090
01091
01092 /**
01093   * @brief  Forces the TIM1 Channel2 output waveform to active or inactive level.
01094   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01095   * This parameter can be one of the following values:
01096   * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC2REF
01097   * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
01098   * @retval None
01099   */
01100 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01101 {
01102     /* Check the parameters */
01103     assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01104
01105     /* Reset the OCM Bits & Configure the Forced output Mode */
01106     TIM1->CCMR2  =  (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM))
01107                               | (uint8_t)TIM1_ForcedAction);
01108 }
01109
01110
01111 /**
01112   * @brief  Forces the TIM1 Channel3 output waveform to active or inactive level.
01113   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01114   * This parameter can be one of the following values:
01115   *                       - TIM1_FORCEDACTION_ACTIVE: Force active level on OC3REF
01116   *                       - TIM1_FORCEDACTION_INACTIVE: Force inactive level on
01117   *                         OC3REF.
01118   * @retval None
01119   */
01120 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01121 {
01122     /* Check the parameters */
01123     assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01124
01125     /* Reset the OCM Bits */ /* Configure The Forced output Mode */
01126     TIM1->CCMR3  =  (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM))
01127                               | (uint8_t)TIM1_ForcedAction);
01128 }
01129
01130
01131 /**
01132   * @brief  Forces the TIM1 Channel4 output waveform to active or inactive level.
01133   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01134   * This parameter can be one of the following values:
01135   *                       - TIM1_FORCEDACTION_ACTIVE: Force active level on OC4REF
01136   *                       - TIM1_FORCEDACTION_INACTIVE: Force inactive level on
01137   *                         OC4REF.
01138   * @retval None
01139   */
01140 void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01141 {
01142     /* Check the parameters */
01143     assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01144
01145     /* Reset the OCM Bits & Configure the Forced output Mode */
01146     TIM1->CCMR4  =  (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM))
01147                               | (uint8_t)TIM1_ForcedAction);
01148 }
01149
01150
01151 /**
01152   * @brief  Enables or disables TIM1 peripheral Preload register on ARR.
01153   * @param   NewState new state of the TIM1 peripheral Preload register.
01154   * This parameter can be ENABLE or DISABLE.
01155   * @retval None
01156   */
01157 void TIM1_ARRPreloadConfig(FunctionalState NewState)
01158 {
01159     /* Check the parameters */
01160     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01161
01162     /* Set or Reset the ARPE Bit */
01163     if (NewState != DISABLE)
01164     {
01165         TIM1->CR1 |= TIM1_CR1_ARPE;
01166     }
01167     else
01168     {
01169         TIM1->CR1 &= (uint8_t)(~TIM1_CR1_ARPE);
01170     }
01171 }
01172
01173
01174 /**
01175   * @brief  Selects the TIM1 peripheral Commutation event.
01176   * @param   NewState new state of the Commutation event.
01177   * This parameter can be ENABLE or DISABLE.
01178   * @retval None
01179   */
01180 void TIM1_SelectCOM(FunctionalState NewState)
01181 {
01182     /* Check the parameters */
01183     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01184
01185     /* Set or Reset the COMS Bit */
01186     if (NewState != DISABLE)
01187     {
01188         TIM1->CR2 |= TIM1_CR2_COMS;
01189     }
01190     else
01191     {
01192         TIM1->CR2 &= (uint8_t)(~TIM1_CR2_COMS);
01193     }
01194 }
01195
01196 /**
01197   * @brief  Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
01198   * @param   NewState new state of the Capture Compare Preload Control bit.
01199   * This parameter can be ENABLE or DISABLE.
01200   * @retval None
01201   */
01202 void TIM1_CCPreloadControl(FunctionalState NewState)
01203 {
01204     /* Check the parameters */
01205     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01206
01207     /* Set or Reset the CCPC Bit */
01208     if (NewState != DISABLE)
01209     {
01210         TIM1->CR2 |= TIM1_CR2_CCPC;
01211     }
01212     else
01213     {
01214         TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCPC);
01215     }
01216 }
01217
01218
01219 /**
01220   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR1.
01221   * @param   NewState new state of the Capture Compare Preload register.
01222   * This parameter can be ENABLE or DISABLE.
01223   * @retval None
01224   */
01225 void TIM1_OC1PreloadConfig(FunctionalState NewState)
01226 {
01227     /* Check the parameters */
01228     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01229
01230     /* Set or Reset the OC1PE Bit */
01231     if (NewState != DISABLE)
01232     {
01233         TIM1->CCMR1 |= TIM1_CCMR_OCxPE;
01234     }
01235     else
01236     {
01237         TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01238     }
01239 }
01240
01241
01242 /**
01243   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR2.
01244   * @param   NewState new state of the Capture Compare Preload register.
01245   * This parameter can be ENABLE or DISABLE.
01246   * @retval None
01247   */
01248 void TIM1_OC2PreloadConfig(FunctionalState NewState)
01249 {
01250     /* Check the parameters */
01251     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01252
01253     /* Set or Reset the OC2PE Bit */
01254     if (NewState != DISABLE)
01255     {
01256         TIM1->CCMR2 |= TIM1_CCMR_OCxPE;
01257     }
01258     else
01259     {
01260         TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01261     }
01262 }
01263
01264
01265 /**
01266   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR3.
01267   * @param   NewState new state of the Capture Compare Preload register.
01268   * This parameter can be ENABLE or DISABLE.
01269   * @retval None
01270   */
01271 void TIM1_OC3PreloadConfig(FunctionalState NewState)
01272 {
01273     /* Check the parameters */
01274     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01275
01276     /* Set or Reset the OC3PE Bit */
01277     if (NewState != DISABLE)
01278     {
01279         TIM1->CCMR3 |= TIM1_CCMR_OCxPE;
01280     }
01281     else
01282     {
01283         TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01284     }
01285 }
01286
01287
01288 /**
01289   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR4.
01290   * @param   NewState new state of the Capture Compare Preload register.
01291   * This parameter can be ENABLE or DISABLE.
01292   * @retval None
01293   */
01294
01295 void TIM1_OC4PreloadConfig(FunctionalState NewState)
01296 {
01297     /* Check the parameters */
01298     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01299
01300     /* Set or Reset the OC4PE Bit */
01301     if (NewState != DISABLE)
01302     {
01303         TIM1->CCMR4 |= TIM1_CCMR_OCxPE;
01304     }
01305     else
01306     {
01307         TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01308     }
01309 }
01310
01311 /**
01312   * @brief  Configures the TIM1 Capture Compare 1 Fast feature.
01313   * @param   NewState new state of the Output Compare Fast Enable bit.
01314   * This parameter can be ENABLE or DISABLE.
01315   * @retval None
01316   */
01317 void TIM1_OC1FastConfig(FunctionalState NewState)
01318 {
01319     /* Check the parameters */
01320     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01321
01322     /* Set or Reset the OC1FE Bit */
01323     if (NewState != DISABLE)
01324     {
01325         TIM1->CCMR1 |= TIM1_CCMR_OCxFE;
01326     }
01327     else
01328     {
01329         TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01330     }
01331 }
01332
01333
01334 /**
01335   * @brief  Configures the TIM1 Capture Compare 2 Fast feature.
01336   * @param   NewState new state of the Output Compare Fast Enable bit.
01337   * This parameter can be ENABLE or DISABLE.
01338   * @retval None
01339   */
01340
01341 void TIM1_OC2FastConfig(FunctionalState NewState)
01342 {
01343     /* Check the parameters */
01344     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01345
01346     /* Set or Reset the OC2FE Bit */
01347     if (NewState != DISABLE)
01348     {
01349         TIM1->CCMR2 |= TIM1_CCMR_OCxFE;
01350     }
01351     else
01352     {
01353         TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01354     }
01355 }
01356
01357
01358 /**
01359   * @brief  Configures the TIM1 Capture Compare 3 Fast feature.
01360   * @param   NewState new state of the Output Compare Fast Enable bit.
01361   * This parameter can be ENABLE or DISABLE.
01362   * @retval None
01363   */
01364 void TIM1_OC3FastConfig(FunctionalState NewState)
01365 {
01366     /* Check the parameters */
01367     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01368
01369     /* Set or Reset the OC3FE Bit */
01370     if (NewState != DISABLE)
01371     {
01372         TIM1->CCMR3 |= TIM1_CCMR_OCxFE;
01373     }
01374     else
01375     {
01376         TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01377     }
01378 }
01379
01380
01381 /**
01382   * @brief  Configures the TIM1 Capture Compare 4 Fast feature.
01383   * @param   NewState new state of the Output Compare Fast Enable bit.
01384   * This parameter can be ENABLE or DISABLE.
01385   * @retval None
01386   */
01387 void TIM1_OC4FastConfig(FunctionalState NewState)
01388 {
01389     /* Check the parameters */
01390     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01391
01392     /* Set or Reset the OC4FE Bit */
01393     if (NewState != DISABLE)
01394     {
01395         TIM1->CCMR4 |= TIM1_CCMR_OCxFE;
01396     }
01397     else
01398     {
01399         TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01400     }
01401 }
01402
01403
01404 /**
01405   * @brief  Configures the TIM1 event to be generated by software.
01406   * @param   TIM1_EventSource specifies the event source.
01407   * This parameter can be one of the following values:
01408   *                       - TIM1_EVENTSOURCE_UPDATE: TIM1 update Event source
01409   *                       - TIM1_EVENTSOURCE_CC1: TIM1 Capture Compare 1 Event source
01410   *                       - TIM1_EVENTSOURCE_CC2: TIM1 Capture Compare 2 Event source
01411   *                       - TIM1_EVENTSOURCE_CC3: TIM1 Capture Compare 3 Event source
01412   *                       - TIM1_EVENTSOURCE_CC4: TIM1 Capture Compare 4 Event source
01413   *                       - TIM1_EVENTSOURCE_COM: TIM1 COM Event source
01414   *                       - TIM1_EVENTSOURCE_TRIGGER: TIM1 Trigger Event source
01415   *                       - TIM1_EventSourceBreak: TIM1 Break Event source
01416   * @retval None
01417   */
01418 void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource)
01419 {
01420     /* Check the parameters */
01421     assert_param(IS_TIM1_EVENT_SOURCE_OK(TIM1_EventSource));
01422
01423     /* Set the event sources */
01424     TIM1->EGR = (uint8_t)TIM1_EventSource;
01425 }
01426
01427
01428 /**
01429   * @brief  Configures the TIM1 Channel 1 polarity.
01430   * @param   TIM1_OCPolarity specifies the OC1 Polarity.
01431   * This parameter can be one of the following values:
01432   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01433   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01434   * @retval None
01435   */
01436 void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01437 {
01438     /* Check the parameters */
01439     assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01440
01441     /* Set or Reset the CC1P Bit */
01442     if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01443     {
01444         TIM1->CCER1 |= TIM1_CCER1_CC1P;
01445     }
01446     else
01447     {
01448         TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
01449     }
01450 }
01451
01452
01453 /**
01454   * @brief  Configures the TIM1 Channel 1N polarity.
01455   * @param   TIM1_OCNPolarity specifies the OC1N Polarity.
01456   * This parameter can be one of the following values:
01457   *                       - TIM1_OCNPOLARITY_LOW: Output Compare active low
01458   *                       - TIM1_OCNPOLARITY_HIGH: Output Compare active high
01459   * @retval None
01460   */
01461 void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
01462 {
01463     /* Check the parameters */
01464     assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
01465
01466     /* Set or Reset the CC3P Bit */
01467     if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)
01468     {
01469         TIM1->CCER1 |= TIM1_CCER1_CC1NP;
01470     }
01471     else
01472     {
01473         TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NP);
01474     }
01475 }
01476
01477
01478 /**
01479   * @brief  Configures the TIM1 Channel 2 polarity.
01480   * @param   TIM1_OCPolarity specifies the OC2 Polarity.
01481   * This parameter can be one of the following values:
01482   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01483   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01484   * @retval None
01485   */
01486 void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01487 {
01488     /* Check the parameters */
01489     assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01490
01491     /* Set or Reset the CC2P Bit */
01492     if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01493     {
01494         TIM1->CCER1 |= TIM1_CCER1_CC2P;
01495     }
01496     else
01497     {
01498         TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
01499     }
01500 }
01501
01502 /**
01503   * @brief  Configures the TIM1 Channel 2N polarity.
01504   * @param   TIM1_OCNPolarity specifies the OC2N Polarity.
01505   * This parameter can be one of the following values:
01506   *                       - TIM1_OCNPOLARITY_LOW: Output Compare active low
01507   *                       - TIM1_OCNPOLARITY_HIGH: Output Compare active high
01508   * @retval None
01509   */
01510 void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
01511 {
01512     /* Check the parameters */
01513     assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
01514
01515     /* Set or Reset the CC3P Bit */
01516     if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)
01517     {
01518         TIM1->CCER1 |= TIM1_CCER1_CC2NP;
01519     }
01520     else
01521     {
01522         TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NP);
01523     }
01524 }
01525
01526
01527 /**
01528   * @brief  Configures the TIM1 Channel 3 polarity.
01529   * @param   TIM1_OCPolarity specifies the OC3 Polarity.
01530   * This parameter can be one of the following values:
01531   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01532   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01533   * @retval None
01534   */
01535 void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01536 {
01537     /* Check the parameters */
01538     assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01539
01540     /* Set or Reset the CC3P Bit */
01541     if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01542     {
01543         TIM1->CCER2 |= TIM1_CCER2_CC3P;
01544     }
01545     else
01546     {
01547         TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P);
01548     }
01549 }
01550
01551
01552 /**
01553   * @brief  Configures the TIM1 Channel 3N polarity.
01554   * @param   TIM1_OCNPolarity specifies the OC3N Polarity.
01555   * This parameter can be one of the following values:
01556   *                       - TIM1_OCNPOLARITY_LOW: Output Compare active low
01557   *                       - TIM1_OCNPOLARITY_HIGH: Output Compare active high
01558   * @retval None
01559   */
01560 void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
01561 {
01562     /* Check the parameters */
01563     assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
01564
01565     /* Set or Reset the CC3P Bit */
01566     if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)
01567     {
01568         TIM1->CCER2 |= TIM1_CCER2_CC3NP;
01569     }
01570     else
01571     {
01572         TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NP);
01573     }
01574 }
01575
01576 /**
01577   * @brief  Configures the TIM1 Channel 4 polarity.
01578   * @param   TIM1_OCPolarity specifies the OC4 Polarity.
01579   * This parameter can be one of the following values:
01580   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01581   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01582   * @retval None
01583   */
01584 void TIM1_OC4PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01585 {
01586     /* Check the parameters */
01587     assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01588
01589     /* Set or Reset the CC4P Bit */
01590     if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01591     {
01592         TIM1->CCER2 |= TIM1_CCER2_CC4P;
01593     }
01594     else
01595     {
01596         TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4P);
01597     }
01598 }
01599
01600
01601 /**
01602   * @brief  Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
01603   * @param   TIM1_Channel specifies the TIM1 Channel.
01604   * This parameter can be one of the following values:
01605   *                       - TIM1_CHANNEL_1: TIM1 Channel1
01606   *                       - TIM1_CHANNEL_2: TIM1 Channel2
01607   *                       - TIM1_CHANNEL_3: TIM1 Channel3
01608   *                       - TIM1_CHANNEL_4: TIM1 Channel4
01609   * @param   NewState specifies the TIM1 Channel CCxE bit new state.
01610   * This parameter can be: ENABLE or DISABLE.
01611   * @retval None
01612   */
01613 void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
01614 {
01615     /* Check the parameters */
01616     assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
01617     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01618
01619     if (TIM1_Channel == TIM1_CHANNEL_1)
01620     {
01621         /* Set or Reset the CC1E Bit */
01622         if (NewState != DISABLE)
01623         {
01624             TIM1->CCER1 |= TIM1_CCER1_CC1E;
01625         }
01626         else
01627         {
01628             TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
01629         }
01630
01631     }
01632     else if (TIM1_Channel == TIM1_CHANNEL_2)
01633     {
01634         /* Set or Reset the CC2E Bit */
01635         if (NewState != DISABLE)
01636         {
01637             TIM1->CCER1 |= TIM1_CCER1_CC2E;
01638         }
01639         else
01640         {
01641             TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);
01642         }
01643     }
01644     else if (TIM1_Channel == TIM1_CHANNEL_3)
01645     {
01646         /* Set or Reset the CC3E Bit */
01647         if (NewState != DISABLE)
01648         {
01649             TIM1->CCER2 |= TIM1_CCER2_CC3E;
01650         }
01651         else
01652         {
01653             TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);
01654         }
01655     }
01656     else
01657     {
01658         /* Set or Reset the CC4E Bit */
01659         if (NewState != DISABLE)
01660         {
01661             TIM1->CCER2 |= TIM1_CCER2_CC4E;
01662         }
01663         else
01664         {
01665             TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);
01666         }
01667     }
01668 }
01669
01670 /**
01671   * @brief  Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
01672   * @param   TIM1_Channel specifies the TIM1 Channel.
01673   * This parameter can be one of the following values:
01674   *                       - TIM1_CHANNEL_1: TIM1 Channel1
01675   *                       - TIM1_CHANNEL_2: TIM1 Channel2
01676   *                       - TIM1_CHANNEL_3: TIM1 Channel3
01677   * @param   NewState specifies the TIM1 Channel CCxNE bit new state.
01678   * This parameter can be: ENABLE or DISABLE.
01679   * @retval None
01680   */
01681 void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
01682 {
01683     /* Check the parameters */
01684     assert_param(IS_TIM1_COMPLEMENTARY_CHANNEL_OK(TIM1_Channel));
01685     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01686
01687     if (TIM1_Channel == TIM1_CHANNEL_1)
01688     {
01689         /* Set or Reset the CC1NE Bit */
01690         if (NewState != DISABLE)
01691         {
01692             TIM1->CCER1 |= TIM1_CCER1_CC1NE;
01693         }
01694         else
01695         {
01696             TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NE);
01697         }
01698     }
01699     else if (TIM1_Channel == TIM1_CHANNEL_2)
01700     {
01701         /* Set or Reset the CC2NE Bit */
01702         if (NewState != DISABLE)
01703         {
01704             TIM1->CCER1 |= TIM1_CCER1_CC2NE;
01705         }
01706         else
01707         {
01708             TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NE);
01709         }
01710     }
01711     else
01712     {
01713         /* Set or Reset the CC3NE Bit */
01714         if (NewState != DISABLE)
01715         {
01716             TIM1->CCER2 |= TIM1_CCER2_CC3NE;
01717         }
01718         else
01719         {
01720             TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NE);
01721         }
01722     }
01723 }
01724
01725
01726 /**
01727   * @brief  Selects the TIM1 Output Compare Mode. This function disables the
01728   * selected channel before changing the Output Compare Mode. User has to
01729   * enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions.
01730   * @param   TIM1_Channel specifies the TIM1 Channel.
01731   * This parameter can be one of the following values:
01732   *                       - TIM1_CHANNEL_1: TIM1 Channel1
01733   *                       - TIM1_CHANNEL_2: TIM1 Channel2
01734   *                       - TIM1_CHANNEL_3: TIM1 Channel3
01735   *                       - TIM1_CHANNEL_4: TIM1 Channel4
01736   * @param   TIM1_OCMode specifies the TIM1 Output Compare Mode.
01737   * This paramter can be one of the following values:
01738   *                       - TIM1_OCMODE_TIMING
01739   *                       - TIM1_OCMODE_ACTIVE
01740   *                       - TIM1_OCMODE_TOGGLE
01741   *                       - TIM1_OCMODE_PWM1
01742   *                       - TIM1_OCMODE_PWM2
01743   *                       - TIM1_FORCEDACTION_ACTIVE
01744   *                       - TIM1_FORCEDACTION_INACTIVE
01745   * @retval None
01746   */
01747 void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
01748 {
01749     /* Check the parameters */
01750     assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
01751     assert_param(IS_TIM1_OCM_OK(TIM1_OCMode));
01752
01753     if (TIM1_Channel == TIM1_CHANNEL_1)
01754     {
01755         /* Disable the Channel 1: Reset the CCE Bit */
01756         TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
01757
01758         /* Reset the Output Compare Bits & Set the Output Compare Mode */
01759         TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM))
01760                                 | (uint8_t)TIM1_OCMode);
01761     }
01762     else if (TIM1_Channel == TIM1_CHANNEL_2)
01763     {
01764         /* Disable the Channel 2: Reset the CCE Bit */
01765         TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);
01766
01767         /* Reset the Output Compare Bits & Set the Output Compare Mode */
01768         TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM))
01769                                 | (uint8_t)TIM1_OCMode);
01770     }
01771     else if (TIM1_Channel == TIM1_CHANNEL_3)
01772     {
01773         /* Disable the Channel 3: Reset the CCE Bit */
01774         TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);
01775
01776         /* Reset the Output Compare Bits & Set the Output Compare Mode */
01777         TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM))
01778                                 | (uint8_t)TIM1_OCMode);
01779     }
01780     else
01781     {
01782         /* Disable the Channel 4: Reset the CCE Bit */
01783         TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);
01784
01785         /* Reset the Output Compare Bits & Set the Output Compare Mode */
01786         TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM))
01787                                 | (uint8_t)TIM1_OCMode);
01788     }
01789 }
01790
01791
01792 /**
01793   * @brief  Sets the TIM1 Counter Register value.
01794   * @param   Counter specifies the Counter register new value.
01795   * This parameter is between 0x0000 and 0xFFFF.
01796   * @retval None
01797   */
01798 void TIM1_SetCounter(uint16_t Counter)
01799 {
01800     /* Set the Counter Register value */
01801     TIM1->CNTRH = (uint8_t)(Counter >> 8);
01802     TIM1->CNTRL = (uint8_t)(Counter);
01803
01804 }
01805
01806
01807 /**
01808   * @brief  Sets the TIM1 Autoreload Register value.
01809   * @param   Autoreload specifies the Autoreload register new value.
01810   * This parameter is between 0x0000 and 0xFFFF.
01811   * @retval None
01812   */
01813 void TIM1_SetAutoreload(uint16_t Autoreload)
01814 {
01815
01816     /* Set the Autoreload Register value */
01817     TIM1->ARRH = (uint8_t)(Autoreload >> 8);
01818     TIM1->ARRL = (uint8_t)(Autoreload);
01819
01820 }
01821
01822
01823 /**
01824   * @brief  Sets the TIM1 Capture Compare1 Register value.
01825   * @param   Compare1 specifies the Capture Compare1 register new value.
01826   * This parameter is between 0x0000 and 0xFFFF.
01827   * @retval None
01828   */
01829 void TIM1_SetCompare1(uint16_t Compare1)
01830 {
01831     /* Set the Capture Compare1 Register value */
01832     TIM1->CCR1H = (uint8_t)(Compare1 >> 8);
01833     TIM1->CCR1L = (uint8_t)(Compare1);
01834
01835 }
01836
01837
01838 /**
01839   * @brief  Sets the TIM1 Capture Compare2 Register value.
01840   * @param   Compare2 specifies the Capture Compare2 register new value.
01841   * This parameter is between 0x0000 and 0xFFFF.
01842   * @retval None
01843   */
01844 void TIM1_SetCompare2(uint16_t Compare2)
01845 {
01846     /* Set the Capture Compare2 Register value */
01847     TIM1->CCR2H = (uint8_t)(Compare2 >> 8);
01848     TIM1->CCR2L = (uint8_t)(Compare2);
01849
01850 }
01851
01852
01853 /**
01854   * @brief  Sets the TIM1 Capture Compare3 Register value.
01855   * @param   Compare3 specifies the Capture Compare3 register new value.
01856   * This parameter is between 0x0000 and 0xFFFF.
01857   * @retval None
01858   */
01859 void TIM1_SetCompare3(uint16_t Compare3)
01860 {
01861     /* Set the Capture Compare3 Register value */
01862     TIM1->CCR3H = (uint8_t)(Compare3 >> 8);
01863     TIM1->CCR3L = (uint8_t)(Compare3);
01864
01865 }
01866
01867
01868 /**
01869   * @brief  Sets the TIM1 Capture Compare4 Register value.
01870   * @param   Compare4 specifies the Capture Compare4 register new value.
01871   * This parameter is between 0x0000 and 0xFFFF.
01872   * @retval None
01873   */
01874 void TIM1_SetCompare4(uint16_t Compare4)
01875 {
01876     /* Set the Capture Compare4 Register value */
01877     TIM1->CCR4H = (uint8_t)(Compare4 >> 8);
01878     TIM1->CCR4L = (uint8_t)(Compare4);
01879 }
01880
01881
01882 /**
01883   * @brief  Sets the TIM1 Input Capture 1 prescaler.
01884   * @param   TIM1_IC1Prescaler specifies the Input Capture prescaler new value
01885   * This parameter can be one of the following values:
01886   *                       - TIM1_ICPSC_DIV1: no prescaler
01887   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01888   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01889   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01890   * @retval None
01891   */
01892 void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
01893 {
01894     /* Check the parameters */
01895     assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC1Prescaler));
01896
01897     /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
01898     TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_ICxPSC))
01899                             | (uint8_t)TIM1_IC1Prescaler);
01900
01901 }
01902
01903 /**
01904   * @brief  Sets the TIM1 Input Capture 2 prescaler.
01905   * @param   TIM1_IC2Prescaler specifies the Input Capture prescaler new value
01906   * This parameter can be one of the following values:
01907   *                       - TIM1_ICPSC_DIV1: no prescaler
01908   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01909   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01910   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01911   * @retval None
01912   */
01913 void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
01914 {
01915
01916     /* Check the parameters */
01917     assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC2Prescaler));
01918
01919     /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
01920     TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_ICxPSC))
01921                             | (uint8_t)TIM1_IC2Prescaler);
01922 }
01923
01924
01925 /**
01926   * @brief  Sets the TIM1 Input Capture 3 prescaler.
01927   * @param   TIM1_IC3Prescaler specifies the Input Capture prescaler new value
01928   * This parameter can be one of the following values:
01929   *                       - TIM1_ICPSC_DIV1: no prescaler
01930   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01931   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01932   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01933   * @retval None
01934   */
01935 void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
01936 {
01937
01938     /* Check the parameters */
01939     assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC3Prescaler));
01940
01941     /* Reset the IC1PSC Bits & Set the IC1PSC value */
01942     TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_ICxPSC)) |
01943                             (uint8_t)TIM1_IC3Prescaler);
01944 }
01945
01946 /**
01947   * @brief  Sets the TIM1 Input Capture 4 prescaler.
01948   * @param  TIM1_IC4Prescaler specifies the Input Capture prescaler new value
01949   *         This parameter can be one of the following values:
01950   *                       - TIM1_ICPSC_DIV1: no prescaler
01951   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01952   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01953   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01954   * @retval None
01955   */
01956 void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
01957 {
01958
01959     /* Check the parameters */
01960     assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC4Prescaler));
01961
01962     /* Reset the IC1PSC Bits &  Set the IC1PSC value */
01963     TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_ICxPSC)) |
01964                             (uint8_t)TIM1_IC4Prescaler);
01965 }
01966
01967 /**
01968   * @brief  Gets the TIM1 Input Capture 1 value.
01969   * @param  None
01970   * @retval Capture Compare 1 Register value.
01971   */
01972 uint16_t TIM1_GetCapture1(void)
01973 {
01974     /* Get the Capture 1 Register value */
01975
01976     uint16_t tmpccr1 = 0;
01977     uint8_t tmpccr1l=0, tmpccr1h=0;
01978
01979     tmpccr1h = TIM1->CCR1H;
01980     tmpccr1l = TIM1->CCR1L;
01981
01982     tmpccr1 = (uint16_t)(tmpccr1l);
01983     tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
01984     /* Get the Capture 1 Register value */
01985     return (uint16_t)tmpccr1;
01986 }
01987
01988 /**
01989   * @brief  Gets the TIM1 Input Capture 2 value.
01990   * @param  None
01991   * @retval Capture Compare 2 Register value.
01992   */
01993 uint16_t TIM1_GetCapture2(void)
01994 {
01995     /* Get the Capture 2 Register value */
01996
01997     uint16_t tmpccr2 = 0;
01998     uint8_t tmpccr2l=0, tmpccr2h=0;
01999
02000     tmpccr2h = TIM1->CCR2H;
02001     tmpccr2l = TIM1->CCR2L;
02002
02003     tmpccr2 = (uint16_t)(tmpccr2l);
02004     tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
02005     /* Get the Capture 2 Register value */
02006     return (uint16_t)tmpccr2;
02007 }
02008
02009 /**
02010   * @brief  Gets the TIM1 Input Capture 3 value.
02011   * @param  None
02012   * @retval Capture Compare 3 Register value.
02013   */
02014 uint16_t TIM1_GetCapture3(void)
02015 {
02016     /* Get the Capture 3 Register value */
02017     uint16_t tmpccr3 = 0;
02018     uint8_t tmpccr3l=0, tmpccr3h=0;
02019
02020     tmpccr3h = TIM1->CCR3H;
02021     tmpccr3l = TIM1->CCR3L;
02022
02023     tmpccr3 = (uint16_t)(tmpccr3l);
02024     tmpccr3 |= (uint16_t)((uint16_t)tmpccr3h << 8);
02025     /* Get the Capture 3 Register value */
02026     return (uint16_t)tmpccr3;
02027 }
02028
02029 /**
02030   * @brief  Gets the TIM1 Input Capture 4 value.
02031   * @param  None
02032   * @retval Capture Compare 4 Register value.
02033   */
02034 uint16_t TIM1_GetCapture4(void)
02035 {
02036     /* Get the Capture 4 Register value */
02037     uint16_t tmpccr4 = 0;
02038     uint8_t tmpccr4l=0, tmpccr4h=0;
02039
02040     tmpccr4h = TIM1->CCR4H;
02041     tmpccr4l = TIM1->CCR4L;
02042
02043     tmpccr4 = (uint16_t)(tmpccr4l);
02044     tmpccr4 |= (uint16_t)((uint16_t)tmpccr4h << 8);
02045     /* Get the Capture 4 Register value */
02046     return (uint16_t)tmpccr4;
02047 }
02048
02049 /**
02050   * @brief  Gets the TIM1 Counter value.
02051   * @param  None
02052   * @retval Counter Register value.
02053   */
02054 uint16_t TIM1_GetCounter(void)
02055 {
02056   uint16_t tmpcntr = 0;
02057
02058   tmpcntr = ((uint16_t)TIM1->CNTRH << 8);
02059
02060   /* Get the Counter Register value */
02061     return (uint16_t)(tmpcntr | (uint16_t)(TIM1->CNTRL));
02062 }
02063
02064 /**
02065   * @brief  Gets the TIM1 Prescaler value.
02066   * @param  None
02067   * @retval Prescaler Register value.
02068   */
02069 uint16_t TIM1_GetPrescaler(void)
02070 {
02071    uint16_t temp = 0;
02072
02073    temp = ((uint16_t)TIM1->PSCRH << 8);
02074
02075   /* Get the Prescaler Register value */
02076     return (uint16_t)( temp | (uint16_t)(TIM1->PSCRL));
02077 }
02078
02079 /**
02080   * @brief  Checks whether the specified TIM1 flag is set or not.
02081   * @param  TIM1_FLAG specifies the flag to check.
02082   *         This parameter can be one of the following values:
02083   *                   - TIM1_FLAG_UPDATE: TIM1 update Flag
02084   *                   - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
02085   *                   - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
02086   *                   - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
02087   *                   - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
02088   *                   - TIM1_FLAG_COM: TIM1 Commutation Flag
02089   *                   - TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
02090   *                   - TIM1_FLAG_BREAK: TIM1 Break Flag
02091   *                   - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
02092   *                   - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
02093   *                   - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
02094   *                   - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
02095   * @retval FlagStatus The new state of TIM1_FLAG (SET or RESET).
02096   */
02097 FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG)
02098 {
02099     FlagStatus bitstatus = RESET;
02100     uint8_t tim1_flag_l = 0, tim1_flag_h = 0;
02101
02102     /* Check the parameters */
02103     assert_param(IS_TIM1_GET_FLAG_OK(TIM1_FLAG));
02104
02105     tim1_flag_l = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_FLAG);
02106     tim1_flag_h = (uint8_t)((uint16_t)TIM1_FLAG >> 8);
02107
02108     if ((tim1_flag_l | (uint8_t)(TIM1->SR2 & tim1_flag_h)) != 0)
02109     {
02110         bitstatus = SET;
02111     }
02112     else
02113     {
02114         bitstatus = RESET;
02115     }
02116     return (FlagStatus)(bitstatus);
02117 }
02118
02119 /**
02120   * @brief  Clears the TIM1’s pending flags.
02121   * @param  TIM1_FLAG specifies the flag to clear.
02122   *         This parameter can be one of the following values:
02123   *                       - TIM1_FLAG_UPDATE: TIM1 update Flag
02124   *                       - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
02125   *                       - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
02126   *                       - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
02127   *                       - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
02128   *                       - TIM1_FLAG_COM: TIM1 Commutation Flag
02129   *                       - TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
02130   *                       - TIM1_FLAG_BREAK: TIM1 Break Flag
02131   *                       - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
02132   *                       - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
02133   *                       - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
02134   *                       - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
02135   * @retval None.
02136   */
02137 void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG)
02138 {
02139     /* Check the parameters */
02140     assert_param(IS_TIM1_CLEAR_FLAG_OK(TIM1_FLAG));
02141
02142     /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
02143     TIM1->SR1 = (uint8_t)(~(uint8_t)(TIM1_FLAG));
02144     TIM1->SR2 = (uint8_t)((uint8_t)(~((uint8_t)((uint16_t)TIM1_FLAG >> 8))) &
02145                           (uint8_t)0x1E);
02146 }
02147
02148 /**
02149   * @brief  Checks whether the TIM1 interrupt has occurred or not.
02150   * @param  TIM1_IT specifies the TIM1 interrupt source to check.
02151   *         This parameter can be one of the following values:
02152   *                       - TIM1_IT_UPDATE: TIM1 update Interrupt source
02153   *                       - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
02154   *                       - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
02155   *                       - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
02156   *                       - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
02157   *                       - TIM1_IT_COM: TIM1 Commutation Interrupt source
02158   *                       - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
02159   *                       - TIM1_IT_BREAK: TIM1 Break Interrupt source
02160   * @retval ITStatus The new state of the TIM1_IT(SET or RESET).
02161   */
02162 ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT)
02163 {
02164     ITStatus bitstatus = RESET;
02165     uint8_t TIM1_itStatus = 0, TIM1_itEnable = 0;
02166
02167     /* Check the parameters */
02168     assert_param(IS_TIM1_GET_IT_OK(TIM1_IT));
02169
02170     TIM1_itStatus = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_IT);
02171
02172     TIM1_itEnable = (uint8_t)(TIM1->IER & (uint8_t)TIM1_IT);
02173
02174     if ((TIM1_itStatus != (uint8_t)RESET ) && (TIM1_itEnable != (uint8_t)RESET ))
02175     {
02176         bitstatus = SET;
02177     }
02178     else
02179     {
02180         bitstatus = RESET;
02181     }
02182     return (ITStatus)(bitstatus);
02183 }
02184
02185 /**
02186   * @brief  Clears the TIM1's interrupt pending bits.
02187   * @param  TIM1_IT specifies the pending bit to clear.
02188   *         This parameter can be one of the following values:
02189   *                       - TIM1_IT_UPDATE: TIM1 update Interrupt source
02190   *                       - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
02191   *                       - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
02192   *                       - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
02193   *                       - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
02194   *                       - TIM1_IT_COM: TIM1 Commutation Interrupt source
02195   *                       - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
02196   *                       - TIM1_IT_BREAK: TIM1 Break Interrupt source
02197   * @retval None.
02198   */
02199 void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT)
02200 {
02201     /* Check the parameters */
02202     assert_param(IS_TIM1_IT_OK(TIM1_IT));
02203
02204     /* Clear the IT pending Bit */
02205     TIM1->SR1 = (uint8_t)(~(uint8_t)TIM1_IT);
02206 }
02207
02208 /**
02209   * @brief  Configure the TI1 as Input.
02210   * @param  TIM1_ICPolarity  The Input Polarity.
02211   *         This parameter can be one of the following values:
02212   *                       - TIM1_ICPOLARITY_FALLING
02213   *                       - TIM1_ICPOLARITY_RISING
02214   * @param  TIM1_ICSelection specifies the input to be used.
02215   *         This parameter can be one of the following values:
02216   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 1 is selected to
02217   *                         be connected to IC1.
02218   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 1 is selected to
02219   *                         be connected to IC2.
02220   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02221   *         This parameter must be a value between 0x00 and 0x0F.
02222   * @retval None
02223   */
02224 static void TI1_Config(uint8_t TIM1_ICPolarity,
02225                        uint8_t TIM1_ICSelection,
02226                        uint8_t TIM1_ICFilter)
02227 {
02228
02229     /* Disable the Channel 1: Reset the CCE Bit */
02230     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
02231
02232     /* Select the Input and set the filter */
02233     TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF ))) |
02234                             (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02235
02236     /* Select the Polarity */
02237     if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02238     {
02239         TIM1->CCER1 |= TIM1_CCER1_CC1P;
02240     }
02241     else
02242     {
02243         TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
02244     }
02245
02246     /* Set the CCE Bit */
02247     TIM1->CCER1 |=  TIM1_CCER1_CC1E;
02248 }
02249
02250 /**
02251   * @brief  Configure the TI2 as Input.
02252   * @param  TIM1_ICPolarity  The Input Polarity.
02253   *         This parameter can be one of the following values:
02254   *                       - TIM1_ICPOLARITY_FALLING
02255   *                       - TIM1_ICPOLARITY_RISING
02256   * @param  TIM1_ICSelection specifies the input to be used.
02257   *         This parameter can be one of the following values:
02258   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 2 is selected to
02259   *                         be connected to IC2.
02260   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 2 is selected to
02261   *                         be connected to IC1.
02262   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02263   *         This parameter must be a value between 0x00 and 0x0F.
02264   * @retval None
02265   */
02266 static void TI2_Config(uint8_t TIM1_ICPolarity,
02267                        uint8_t TIM1_ICSelection,
02268                        uint8_t TIM1_ICFilter)
02269 {
02270     /* Disable the Channel 2: Reset the CCE Bit */
02271     TIM1->CCER1 &=  (uint8_t)(~TIM1_CCER1_CC2E);
02272
02273     /* Select the Input and set the filter */
02274     TIM1->CCMR2  = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF )))
02275                             | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02276     /* Select the Polarity */
02277     if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02278     {
02279         TIM1->CCER1 |= TIM1_CCER1_CC2P;
02280     }
02281     else
02282     {
02283         TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
02284     }
02285     /* Set the CCE Bit */
02286     TIM1->CCER1 |=  TIM1_CCER1_CC2E;
02287 }
02288
02289 /**
02290   * @brief  Configure the TI3 as Input.
02291   * @param  TIM1_ICPolarity  The Input Polarity.
02292   *         This parameter can be one of the following values:
02293   *                       - TIM1_ICPOLARITY_FALLING
02294   *                       - TIM1_ICPOLARITY_RISING
02295   * @param  TIM1_ICSelection specifies the input to be used.
02296   *         This parameter can be one of the following values:
02297   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 3 is selected to
02298   *                         be connected to IC3.
02299   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 3 is selected to
02300   *                         be connected to IC4.
02301   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02302   *         This parameter must be a value between 0x00 and 0x0F.
02303   * @retval None
02304   */
02305 static void TI3_Config(uint8_t TIM1_ICPolarity,
02306                        uint8_t TIM1_ICSelection,
02307                        uint8_t TIM1_ICFilter)
02308 {
02309     /* Disable the Channel 3: Reset the CCE Bit */
02310     TIM1->CCER2 &=  (uint8_t)(~TIM1_CCER2_CC3E);
02311
02312     /* Select the Input and set the filter */
02313     TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF)))
02314                             | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02315
02316     /* Select the Polarity */
02317     if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02318     {
02319         TIM1->CCER2 |= TIM1_CCER2_CC3P;
02320     }
02321     else
02322     {
02323         TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P);
02324     }
02325     /* Set the CCE Bit */
02326     TIM1->CCER2 |=  TIM1_CCER2_CC3E;
02327 }
02328
02329
02330 /**
02331   * @brief  Configure the TI4 as Input.
02332   * @param  TIM1_ICPolarity  The Input Polarity.
02333   *         This parameter can be one of the following values:
02334   *                       - TIM1_ICPOLARITY_FALLING
02335   *                       - TIM1_ICPOLARITY_RISING
02336   * @param  TIM1_ICSelection specifies the input to be used.
02337   *         This parameter can be one of the following values:
02338   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 4 is selected to
02339   *                         be connected to IC4.
02340   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 4 is selected to
02341   *                         be connected to IC3.
02342   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02343   *         This parameter must be a value between 0x00 and 0x0F.
02344   * @retval None
02345   */
02346 static void TI4_Config(uint8_t TIM1_ICPolarity,
02347                        uint8_t TIM1_ICSelection,
02348                        uint8_t TIM1_ICFilter)
02349 {
02350
02351     /* Disable the Channel 4: Reset the CCE Bit */
02352     TIM1->CCER2 &=  (uint8_t)(~TIM1_CCER2_CC4E);
02353
02354     /* Select the Input and set the filter */
02355     TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF )))
02356                             | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02357
02358     /* Select the Polarity */
02359     if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02360     {
02361         TIM1->CCER2 |= TIM1_CCER2_CC4P;
02362     }
02363     else
02364     {
02365         TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4P);
02366     }
02367
02368     /* Set the CCE Bit */
02369     TIM1->CCER2 |=  TIM1_CCER2_CC4E;
02370 }
02371
02372
02373 /**
02374   * @}
02375   */
02376
02377 /**
02378   * @}
02379   */
02380
02381 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim1.h Source File

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stm8s_tim1.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim1.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the TIM1 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_TIM1_H
00024 #define __STM8S_TIM1_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /** @addtogroup TIM1_Exported_Types
00034  * @{
00035  */
00036
00037 /** TIM1 Output Compare and PWM modes */
00038
00039 typedef enum
00040 {
00041   TIM1_OCMODE_TIMING     = ((uint8_t)0x00),
00042   TIM1_OCMODE_ACTIVE     = ((uint8_t)0x10),
00043   TIM1_OCMODE_INACTIVE   = ((uint8_t)0x20),
00044   TIM1_OCMODE_TOGGLE     = ((uint8_t)0x30),
00045   TIM1_OCMODE_PWM1       = ((uint8_t)0x60),
00046   TIM1_OCMODE_PWM2       = ((uint8_t)0x70)
00047 }TIM1_OCMode_TypeDef;
00048
00049 #define IS_TIM1_OC_MODE_OK(MODE) (((MODE) ==  TIM1_OCMODE_TIMING) || \
00050                                   ((MODE) == TIM1_OCMODE_ACTIVE) || \
00051                                   ((MODE) == TIM1_OCMODE_INACTIVE) || \
00052                                   ((MODE) == TIM1_OCMODE_TOGGLE)|| \
00053                                   ((MODE) == TIM1_OCMODE_PWM1) || \
00054                                   ((MODE) == TIM1_OCMODE_PWM2))
00055
00056 #define IS_TIM1_OCM_OK(MODE)(((MODE) ==  TIM1_OCMODE_TIMING) || \
00057                              ((MODE) == TIM1_OCMODE_ACTIVE) || \
00058                              ((MODE) == TIM1_OCMODE_INACTIVE) || \
00059                              ((MODE) == TIM1_OCMODE_TOGGLE)|| \
00060                              ((MODE) == TIM1_OCMODE_PWM1) || \
00061                              ((MODE) == TIM1_OCMODE_PWM2) || \
00062                              ((MODE) == (uint8_t)TIM1_FORCEDACTION_ACTIVE) || \
00063                              ((MODE) == (uint8_t)TIM1_FORCEDACTION_INACTIVE))
00064
00065 /** TIM1 One Pulse Mode */
00066 typedef enum
00067 {
00068   TIM1_OPMODE_SINGLE                 = ((uint8_t)0x01),
00069   TIM1_OPMODE_REPETITIVE             = ((uint8_t)0x00)
00070 }TIM1_OPMode_TypeDef;
00071
00072 #define IS_TIM1_OPM_MODE_OK(MODE) (((MODE) == TIM1_OPMODE_SINGLE) || \
00073                                    ((MODE) == TIM1_OPMODE_REPETITIVE))
00074
00075 /** TIM1 Channel */
00076
00077 typedef enum
00078 {
00079   TIM1_CHANNEL_1                     = ((uint8_t)0x00),
00080   TIM1_CHANNEL_2                     = ((uint8_t)0x01),
00081   TIM1_CHANNEL_3                     = ((uint8_t)0x02),
00082   TIM1_CHANNEL_4                     = ((uint8_t)0x03)
00083 }TIM1_Channel_TypeDef;
00084
00085
00086 #define IS_TIM1_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \
00087                                      ((CHANNEL) == TIM1_CHANNEL_2) || \
00088                                      ((CHANNEL) == TIM1_CHANNEL_3) || \
00089                                      ((CHANNEL) == TIM1_CHANNEL_4))
00090
00091 #define IS_TIM1_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \
00092     ((CHANNEL) == TIM1_CHANNEL_2))
00093
00094 #define IS_TIM1_COMPLEMENTARY_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \
00095     ((CHANNEL) == TIM1_CHANNEL_2) || \
00096     ((CHANNEL) == TIM1_CHANNEL_3))
00097
00098
00099 /** TIM1 Counter Mode */
00100 typedef enum
00101 {
00102   TIM1_COUNTERMODE_UP                = ((uint8_t)0x00),
00103   TIM1_COUNTERMODE_DOWN              = ((uint8_t)0x10),
00104   TIM1_COUNTERMODE_CENTERALIGNED1    = ((uint8_t)0x20),
00105   TIM1_COUNTERMODE_CENTERALIGNED2    = ((uint8_t)0x40),
00106   TIM1_COUNTERMODE_CENTERALIGNED3    = ((uint8_t)0x60)
00107 }TIM1_CounterMode_TypeDef;
00108
00109 #define IS_TIM1_COUNTER_MODE_OK(MODE) (((MODE) == TIM1_COUNTERMODE_UP) || \
00110                                        ((MODE) == TIM1_COUNTERMODE_DOWN) || \
00111                                        ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED1) || \
00112                                        ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED2) || \
00113                                        ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED3))
00114
00115 /** TIM1 Output Compare Polarity */
00116 typedef enum
00117 {
00118   TIM1_OCPOLARITY_HIGH               = ((uint8_t)0x00),
00119   TIM1_OCPOLARITY_LOW                = ((uint8_t)0x22)
00120 }TIM1_OCPolarity_TypeDef;
00121
00122 #define IS_TIM1_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_OCPOLARITY_HIGH) || \
00123     ((POLARITY) == TIM1_OCPOLARITY_LOW))
00124
00125 /** TIM1 Output Compare N Polarity */
00126 typedef enum
00127 {
00128   TIM1_OCNPOLARITY_HIGH              = ((uint8_t)0x00),
00129   TIM1_OCNPOLARITY_LOW               = ((uint8_t)0x88)
00130 }TIM1_OCNPolarity_TypeDef;
00131
00132 #define IS_TIM1_OCN_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_OCNPOLARITY_HIGH) || \
00133     ((POLARITY) == TIM1_OCNPOLARITY_LOW))
00134
00135 /** TIM1 Output Compare states */
00136 typedef enum
00137 {
00138   TIM1_OUTPUTSTATE_DISABLE           = ((uint8_t)0x00),
00139   TIM1_OUTPUTSTATE_ENABLE            = ((uint8_t)0x11)
00140 }TIM1_OutputState_TypeDef;
00141
00142 #define IS_TIM1_OUTPUT_STATE_OK(STATE) (((STATE) == TIM1_OUTPUTSTATE_DISABLE) || \
00143                                         ((STATE) == TIM1_OUTPUTSTATE_ENABLE))
00144
00145 /** TIM1 Output Compare N States */
00146 typedef enum
00147 {
00148   TIM1_OUTPUTNSTATE_DISABLE = ((uint8_t)0x00),
00149   TIM1_OUTPUTNSTATE_ENABLE  = ((uint8_t)0x44)
00150 } TIM1_OutputNState_TypeDef;
00151
00152 #define IS_TIM1_OUTPUTN_STATE_OK(STATE) (((STATE) == TIM1_OUTPUTNSTATE_DISABLE) ||\
00153     ((STATE) == TIM1_OUTPUTNSTATE_ENABLE))
00154
00155 /** TIM1 Break Input enable/disable */
00156 typedef enum
00157 {
00158   TIM1_BREAK_ENABLE                  = ((uint8_t)0x10),
00159   TIM1_BREAK_DISABLE                 = ((uint8_t)0x00)
00160 }TIM1_BreakState_TypeDef;
00161 #define IS_TIM1_BREAK_STATE_OK(STATE) (((STATE) == TIM1_BREAK_ENABLE) || \
00162                                        ((STATE) == TIM1_BREAK_DISABLE))
00163
00164 /** TIM1 Break Polarity */
00165 typedef enum
00166 {
00167   TIM1_BREAKPOLARITY_LOW             = ((uint8_t)0x00),
00168   TIM1_BREAKPOLARITY_HIGH            = ((uint8_t)0x20)
00169 }TIM1_BreakPolarity_TypeDef;
00170 #define IS_TIM1_BREAK_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_BREAKPOLARITY_LOW) || \
00171     ((POLARITY) == TIM1_BREAKPOLARITY_HIGH))
00172
00173 /** TIM1 AOE Bit Set/Reset */
00174 typedef enum
00175 {
00176   TIM1_AUTOMATICOUTPUT_ENABLE        = ((uint8_t)0x40),
00177   TIM1_AUTOMATICOUTPUT_DISABLE       = ((uint8_t)0x00)
00178 }TIM1_AutomaticOutput_TypeDef;
00179
00180 #define IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(STATE) (((STATE) == TIM1_AUTOMATICOUTPUT_ENABLE) || \
00181     ((STATE) == TIM1_AUTOMATICOUTPUT_DISABLE))
00182
00183 /** TIM1 Lock levels */
00184 typedef enum
00185 {
00186   TIM1_LOCKLEVEL_OFF                 = ((uint8_t)0x00),
00187   TIM1_LOCKLEVEL_1                   = ((uint8_t)0x01),
00188   TIM1_LOCKLEVEL_2                   = ((uint8_t)0x02),
00189   TIM1_LOCKLEVEL_3                   = ((uint8_t)0x03)
00190 }TIM1_LockLevel_TypeDef;
00191
00192 #define IS_TIM1_LOCK_LEVEL_OK(LEVEL) (((LEVEL) == TIM1_LOCKLEVEL_OFF) || \
00193                                       ((LEVEL) == TIM1_LOCKLEVEL_1) || \
00194                                       ((LEVEL) == TIM1_LOCKLEVEL_2) || \
00195                                       ((LEVEL) == TIM1_LOCKLEVEL_3))
00196
00197 /** TIM1 OSSI: Off-State Selection for Idle mode states */
00198 typedef enum
00199 {
00200   TIM1_OSSISTATE_ENABLE              = ((uint8_t)0x04),
00201   TIM1_OSSISTATE_DISABLE             = ((uint8_t)0x00)
00202 }TIM1_OSSIState_TypeDef;
00203
00204 #define IS_TIM1_OSSI_STATE_OK(STATE) (((STATE) == TIM1_OSSISTATE_ENABLE) || \
00205                                       ((STATE) == TIM1_OSSISTATE_DISABLE))
00206
00207 /** TIM1 Output Compare Idle State */
00208 typedef enum
00209 {
00210   TIM1_OCIDLESTATE_SET               = ((uint8_t)0x55),
00211   TIM1_OCIDLESTATE_RESET             = ((uint8_t)0x00)
00212 }TIM1_OCIdleState_TypeDef;
00213
00214 #define IS_TIM1_OCIDLE_STATE_OK(STATE) (((STATE) == TIM1_OCIDLESTATE_SET) || \
00215                                         ((STATE) == TIM1_OCIDLESTATE_RESET))
00216
00217 /** TIM1 Output Compare N Idle State */
00218 typedef enum
00219 {
00220   TIM1_OCNIDLESTATE_SET             = ((uint8_t)0x2A),
00221   TIM1_OCNIDLESTATE_RESET           = ((uint8_t)0x00)
00222 }TIM1_OCNIdleState_TypeDef;
00223
00224 #define IS_TIM1_OCNIDLE_STATE_OK(STATE) (((STATE) == TIM1_OCNIDLESTATE_SET) || \
00225     ((STATE) == TIM1_OCNIDLESTATE_RESET))
00226
00227 /** TIM1 Input Capture Polarity */
00228 typedef enum
00229 {
00230   TIM1_ICPOLARITY_RISING            = ((uint8_t)0x00),
00231   TIM1_ICPOLARITY_FALLING           = ((uint8_t)0x01)
00232 }TIM1_ICPolarity_TypeDef;
00233
00234 #define IS_TIM1_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_ICPOLARITY_RISING) || \
00235     ((POLARITY) == TIM1_ICPOLARITY_FALLING))
00236
00237 /** TIM1 Input Capture Selection */
00238 typedef enum
00239 {
00240   TIM1_ICSELECTION_DIRECTTI          = ((uint8_t)0x01),
00241   TIM1_ICSELECTION_INDIRECTTI        = ((uint8_t)0x02),
00242   TIM1_ICSELECTION_TRGI              = ((uint8_t)0x03)
00243 }TIM1_ICSelection_TypeDef;
00244
00245 #define IS_TIM1_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_ICSELECTION_DIRECTTI) || \
00246     ((SELECTION) == TIM1_ICSELECTION_INDIRECTTI) || \
00247     ((SELECTION) == TIM1_ICSELECTION_TRGI))
00248
00249 /** TIM1 Input Capture Prescaler */
00250 typedef enum
00251 {
00252   TIM1_ICPSC_DIV1                    = ((uint8_t)0x00),
00253   TIM1_ICPSC_DIV2                    = ((uint8_t)0x04),
00254   TIM1_ICPSC_DIV4                    = ((uint8_t)0x08),
00255   TIM1_ICPSC_DIV8                    = ((uint8_t)0x0C)
00256 }TIM1_ICPSC_TypeDef;
00257
00258 #define IS_TIM1_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM1_ICPSC_DIV1) || \
00259     ((PRESCALER) == TIM1_ICPSC_DIV2) || \
00260     ((PRESCALER) == TIM1_ICPSC_DIV4) || \
00261     ((PRESCALER) == TIM1_ICPSC_DIV8))
00262
00263 /** TIM1 Input Capture Filer Value */
00264
00265 #define IS_TIM1_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
00266
00267 /** TIM1 External Trigger Filer Value */
00268 #define IS_TIM1_EXT_TRG_FILTER_OK(FILTER) ((FILTER) <= 0x0F)
00269
00270 /** TIM1 interrupt sources */
00271 typedef enum
00272 {
00273   TIM1_IT_UPDATE                     = ((uint8_t)0x01),
00274   TIM1_IT_CC1                        = ((uint8_t)0x02),
00275   TIM1_IT_CC2                        = ((uint8_t)0x04),
00276   TIM1_IT_CC3                        = ((uint8_t)0x08),
00277   TIM1_IT_CC4                        = ((uint8_t)0x10),
00278   TIM1_IT_COM                        = ((uint8_t)0x20),
00279   TIM1_IT_TRIGGER                    = ((uint8_t)0x40),
00280   TIM1_IT_BREAK                      = ((uint8_t)0x80)
00281 }TIM1_IT_TypeDef;
00282
00283 #define IS_TIM1_IT_OK(IT) ((IT) != 0x00)
00284
00285 #define IS_TIM1_GET_IT_OK(IT) (((IT) == TIM1_IT_UPDATE) || \
00286                                ((IT) == TIM1_IT_CC1) || \
00287                                ((IT) == TIM1_IT_CC2) || \
00288                                ((IT) == TIM1_IT_CC3) || \
00289                                ((IT) == TIM1_IT_CC4) || \
00290                                ((IT) == TIM1_IT_COM) || \
00291                                ((IT) == TIM1_IT_TRIGGER) || \
00292                                ((IT) == TIM1_IT_BREAK))
00293
00294
00295 /** TIM1 External Trigger Prescaler */
00296 typedef enum
00297 {
00298   TIM1_EXTTRGPSC_OFF                 = ((uint8_t)0x00),
00299   TIM1_EXTTRGPSC_DIV2                = ((uint8_t)0x10),
00300   TIM1_EXTTRGPSC_DIV4                = ((uint8_t)0x20),
00301   TIM1_EXTTRGPSC_DIV8                = ((uint8_t)0x30)
00302 }TIM1_ExtTRGPSC_TypeDef;
00303
00304 #define IS_TIM1_EXT_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM1_EXTTRGPSC_OFF) || \
00305     ((PRESCALER) == TIM1_EXTTRGPSC_DIV2) || \
00306     ((PRESCALER) == TIM1_EXTTRGPSC_DIV4) || \
00307     ((PRESCALER) == TIM1_EXTTRGPSC_DIV8))
00308
00309 /** TIM1 Internal Trigger Selection */
00310 typedef enum
00311 {
00312   TIM1_TS_TIM6                       = ((uint8_t)0x00),  /*!< TRIG Input source =  TIM6 TRIG Output  */
00313   TIM1_TS_TIM5                       = ((uint8_t)0x30),  /*!< TRIG Input source =  TIM5 TRIG Output  */
00314   TIM1_TS_TI1F_ED                    = ((uint8_t)0x40),
00315   TIM1_TS_TI1FP1                     = ((uint8_t)0x50),
00316   TIM1_TS_TI2FP2                     = ((uint8_t)0x60),
00317   TIM1_TS_ETRF                       = ((uint8_t)0x70)
00318 }TIM1_TS_TypeDef;
00319
00320 #define IS_TIM1_TRIGGER_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_TS_TI1F_ED) || \
00321     ((SELECTION) == TIM1_TS_TI1FP1) || \
00322     ((SELECTION) == TIM1_TS_TI2FP2) || \
00323     ((SELECTION) == TIM1_TS_ETRF) || \
00324     ((SELECTION) == TIM1_TS_TIM5) || \
00325     ((SELECTION) == TIM1_TS_TIM6))
00326
00327
00328 #define IS_TIM1_TIX_TRIGGER_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_TS_TI1F_ED) || \
00329     ((SELECTION) == TIM1_TS_TI1FP1) || \
00330     ((SELECTION) == TIM1_TS_TI2FP2))
00331
00332 /** TIM1 TIx External Clock Source */
00333 typedef enum
00334 {
00335   TIM1_TIXEXTERNALCLK1SOURCE_TI1ED   = ((uint8_t)0x40),
00336   TIM1_TIXEXTERNALCLK1SOURCE_TI1     = ((uint8_t)0x50),
00337   TIM1_TIXEXTERNALCLK1SOURCE_TI2     = ((uint8_t)0x60)
00338 }TIM1_TIxExternalCLK1Source_TypeDef;
00339
00340 #define IS_TIM1_TIXCLK_SOURCE_OK(SOURCE)  (((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1ED) || \
00341     ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI2) || \
00342     ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1))
00343
00344 /** TIM1 External Trigger Polarity */
00345 typedef enum
00346 {
00347   TIM1_EXTTRGPOLARITY_INVERTED       = ((uint8_t)0x80),
00348   TIM1_EXTTRGPOLARITY_NONINVERTED    = ((uint8_t)0x00)
00349 }TIM1_ExtTRGPolarity_TypeDef;
00350
00351 #define IS_TIM1_EXT_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_EXTTRGPOLARITY_INVERTED) || \
00352     ((POLARITY) == TIM1_EXTTRGPOLARITY_NONINVERTED))
00353
00354 /** TIM1 Prescaler Reload Mode */
00355 typedef enum
00356 {
00357   TIM1_PSCRELOADMODE_UPDATE          = ((uint8_t)0x00),
00358   TIM1_PSCRELOADMODE_IMMEDIATE       = ((uint8_t)0x01)
00359 }TIM1_PSCReloadMode_TypeDef;
00360
00361 #define IS_TIM1_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM1_PSCRELOADMODE_UPDATE) || \
00362     ((RELOAD) == TIM1_PSCRELOADMODE_IMMEDIATE))
00363
00364 /** TIM1 Encoder Mode */
00365 typedef enum
00366 {
00367   TIM1_ENCODERMODE_TI1               = ((uint8_t)0x01),
00368   TIM1_ENCODERMODE_TI2               = ((uint8_t)0x02),
00369   TIM1_ENCODERMODE_TI12              = ((uint8_t)0x03)
00370 }TIM1_EncoderMode_TypeDef;
00371
00372 #define IS_TIM1_ENCODER_MODE_OK(MODE) (((MODE) == TIM1_ENCODERMODE_TI1) || \
00373                                        ((MODE) == TIM1_ENCODERMODE_TI2) || \
00374                                        ((MODE) == TIM1_ENCODERMODE_TI12))
00375
00376 /** TIM1 Event Source */
00377 typedef enum
00378 {
00379   TIM1_EVENTSOURCE_UPDATE            = ((uint8_t)0x01),
00380   TIM1_EVENTSOURCE_CC1               = ((uint8_t)0x02),
00381   TIM1_EVENTSOURCE_CC2               = ((uint8_t)0x04),
00382   TIM1_EVENTSOURCE_CC3               = ((uint8_t)0x08),
00383   TIM1_EVENTSOURCE_CC4               = ((uint8_t)0x10),
00384   TIM1_EVENTSOURCE_COM               = ((uint8_t)0x20),
00385   TIM1_EVENTSOURCE_TRIGGER           = ((uint8_t)0x40),
00386   TIM1_EVENTSOURCE_BREAK             = ((uint8_t)0x80)
00387 }TIM1_EventSource_TypeDef;
00388
00389 #define IS_TIM1_EVENT_SOURCE_OK(SOURCE) ((SOURCE) != 0x00)
00390
00391 /** TIM1 Update Source */
00392 typedef enum
00393 {
00394   TIM1_UPDATESOURCE_GLOBAL           = ((uint8_t)0x00),
00395   TIM1_UPDATESOURCE_REGULAR          = ((uint8_t)0x01)
00396 }TIM1_UpdateSource_TypeDef;
00397
00398 #define IS_TIM1_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM1_UPDATESOURCE_GLOBAL) || \
00399     ((SOURCE) == TIM1_UPDATESOURCE_REGULAR))
00400
00401 /** TIM1 Trigger Output Source */
00402 typedef enum
00403 {
00404   TIM1_TRGOSOURCE_RESET              = ((uint8_t)0x00),
00405   TIM1_TRGOSOURCE_ENABLE             = ((uint8_t)0x10),
00406   TIM1_TRGOSOURCE_UPDATE             = ((uint8_t)0x20),
00407   TIM1_TRGOSource_OC1                = ((uint8_t)0x30),
00408   TIM1_TRGOSOURCE_OC1REF             = ((uint8_t)0x40),
00409   TIM1_TRGOSOURCE_OC2REF             = ((uint8_t)0x50),
00410   TIM1_TRGOSOURCE_OC3REF             = ((uint8_t)0x60)
00411 }TIM1_TRGOSource_TypeDef;
00412
00413 #define IS_TIM1_TRGO_SOURCE_OK(SOURCE) (((SOURCE) == TIM1_TRGOSOURCE_RESET) || \
00414                                         ((SOURCE) == TIM1_TRGOSOURCE_ENABLE) || \
00415                                         ((SOURCE) == TIM1_TRGOSOURCE_UPDATE) || \
00416                                         ((SOURCE) == TIM1_TRGOSource_OC1)  || \
00417                                         ((SOURCE) == TIM1_TRGOSOURCE_OC1REF) || \
00418                                         ((SOURCE) == TIM1_TRGOSOURCE_OC2REF) || \
00419                                         ((SOURCE) == TIM1_TRGOSOURCE_OC3REF))
00420
00421 /** TIM1 Slave Mode */
00422 typedef enum
00423 {
00424   TIM1_SLAVEMODE_RESET               = ((uint8_t)0x04),
00425   TIM1_SLAVEMODE_GATED               = ((uint8_t)0x05),
00426   TIM1_SLAVEMODE_TRIGGER             = ((uint8_t)0x06),
00427   TIM1_SLAVEMODE_EXTERNAL1           = ((uint8_t)0x07)
00428 }TIM1_SlaveMode_TypeDef;
00429
00430 #define IS_TIM1_SLAVE_MODE_OK(MODE) (((MODE) == TIM1_SLAVEMODE_RESET) || \
00431                                      ((MODE) == TIM1_SLAVEMODE_GATED) || \
00432                                      ((MODE) == TIM1_SLAVEMODE_TRIGGER) || \
00433                                      ((MODE) == TIM1_SLAVEMODE_EXTERNAL1))
00434
00435 /** TIM1 Flags */
00436 typedef enum
00437 {
00438   TIM1_FLAG_UPDATE                   = ((uint16_t)0x0001),
00439   TIM1_FLAG_CC1                      = ((uint16_t)0x0002),
00440   TIM1_FLAG_CC2                      = ((uint16_t)0x0004),
00441   TIM1_FLAG_CC3                      = ((uint16_t)0x0008),
00442   TIM1_FLAG_CC4                      = ((uint16_t)0x0010),
00443   TIM1_FLAG_COM                      = ((uint16_t)0x0020),
00444   TIM1_FLAG_TRIGGER                  = ((uint16_t)0x0040),
00445   TIM1_FLAG_BREAK                    = ((uint16_t)0x0080),
00446   TIM1_FLAG_CC1OF                    = ((uint16_t)0x0200),
00447   TIM1_FLAG_CC2OF                    = ((uint16_t)0x0400),
00448   TIM1_FLAG_CC3OF                    = ((uint16_t)0x0800),
00449   TIM1_FLAG_CC4OF                    = ((uint16_t)0x1000)
00450 }TIM1_FLAG_TypeDef;
00451
00452 #define IS_TIM1_GET_FLAG_OK(FLAG) (((FLAG) == TIM1_FLAG_UPDATE) || \
00453                                    ((FLAG) == TIM1_FLAG_CC1) || \
00454                                    ((FLAG) == TIM1_FLAG_CC2) || \
00455                                    ((FLAG) == TIM1_FLAG_CC3) || \
00456                                    ((FLAG) == TIM1_FLAG_CC4) || \
00457                                    ((FLAG) == TIM1_FLAG_COM) || \
00458                                    ((FLAG) == TIM1_FLAG_TRIGGER) || \
00459                                    ((FLAG) == TIM1_FLAG_BREAK) || \
00460                                    ((FLAG) == TIM1_FLAG_CC1OF) || \
00461                                    ((FLAG) == TIM1_FLAG_CC2OF) || \
00462                                    ((FLAG) == TIM1_FLAG_CC3OF) || \
00463                                    ((FLAG) == TIM1_FLAG_CC4OF))
00464
00465 #define IS_TIM1_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
00466
00467 /** TIM1 Forced Action */
00468 typedef enum
00469 {
00470   TIM1_FORCEDACTION_ACTIVE           = ((uint8_t)0x50),
00471   TIM1_FORCEDACTION_INACTIVE         = ((uint8_t)0x40)
00472 }TIM1_ForcedAction_TypeDef;
00473
00474 #define IS_TIM1_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM1_FORCEDACTION_ACTIVE) || \
00475     ((ACTION) == TIM1_FORCEDACTION_INACTIVE))
00476 /**
00477   * @}
00478   */
00479
00480 /* Exported macro ------------------------------------------------------------*/
00481
00482 /* Exported functions --------------------------------------------------------*/
00483
00484 /** @addtogroup TIM1_Exported_Functions
00485   * @{
00486   */
00487
00488 void TIM1_DeInit(void);
00489 void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler,
00490                        TIM1_CounterMode_TypeDef TIM1_CounterMode,
00491                        uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter);
00492 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00493                   TIM1_OutputState_TypeDef TIM1_OutputState,
00494                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00495                   uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00496                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00497                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00498                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);
00499 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00500                   TIM1_OutputState_TypeDef TIM1_OutputState,
00501                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00502                   uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00503                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00504                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00505                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);
00506 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00507                   TIM1_OutputState_TypeDef TIM1_OutputState,
00508                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00509                   uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00510                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00511                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00512                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);
00513 void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00514                   TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse,
00515                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00516                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState);
00517 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
00518                      TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime,
00519                      TIM1_BreakState_TypeDef TIM1_Break,
00520                      TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
00521                      TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput);
00522 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
00523                  TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00524                  TIM1_ICSelection_TypeDef TIM1_ICSelection,
00525                  TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter);
00526 void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel,
00527                      TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00528                      TIM1_ICSelection_TypeDef TIM1_ICSelection,
00529                      TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter);
00530 void TIM1_Cmd(FunctionalState NewState);
00531 void TIM1_CtrlPWMOutputs(FunctionalState NewState);
00532 void TIM1_ITConfig(TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState);
00533 void TIM1_InternalClockConfig(void);
00534 void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00535                               TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00536                               uint8_t ExtTRGFilter);
00537 void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00538                               TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00539                               uint8_t ExtTRGFilter);
00540 void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00541                     TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00542                     uint8_t ExtTRGFilter);
00543 void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource,
00544                                  TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00545                                  uint8_t ICFilter);
00546 void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource);
00547 void TIM1_UpdateDisableConfig(FunctionalState NewState);
00548 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource);
00549 void TIM1_SelectHallSensor(FunctionalState NewState);
00550 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode);
00551 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource);
00552 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode);
00553 void TIM1_SelectMasterSlaveMode(FunctionalState NewState);
00554 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
00555                                  TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
00556                                  TIM1_ICPolarity_TypeDef TIM1_IC2Polarity);
00557 void TIM1_PrescalerConfig(uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode);
00558 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode);
00559 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
00560 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
00561 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
00562 void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
00563 void TIM1_ARRPreloadConfig(FunctionalState NewState);
00564 void TIM1_SelectCOM(FunctionalState NewState);
00565 void TIM1_CCPreloadControl(FunctionalState NewState);
00566 void TIM1_OC1PreloadConfig(FunctionalState NewState);
00567 void TIM1_OC2PreloadConfig(FunctionalState NewState);
00568 void TIM1_OC3PreloadConfig(FunctionalState NewState);
00569 void TIM1_OC4PreloadConfig(FunctionalState NewState);
00570 void TIM1_OC1FastConfig(FunctionalState NewState);
00571 void TIM1_OC2FastConfig(FunctionalState NewState);
00572 void TIM1_OC3FastConfig(FunctionalState NewState);
00573 void TIM1_OC4FastConfig(FunctionalState NewState);
00574 void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource);
00575 void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
00576 void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);
00577 void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
00578 void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);
00579 void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
00580 void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);
00581 void TIM1_OC4PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
00582 void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState);
00583 void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState);
00584 void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode);
00585 void TIM1_SetCounter(uint16_t Counter);
00586 void TIM1_SetAutoreload(uint16_t Autoreload);
00587 void TIM1_SetCompare1(uint16_t Compare1);
00588 void TIM1_SetCompare2(uint16_t Compare2);
00589 void TIM1_SetCompare3(uint16_t Compare3);
00590 void TIM1_SetCompare4(uint16_t Compare4);
00591 void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler);
00592 void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler);
00593 void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler);
00594 void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler);
00595 uint16_t TIM1_GetCapture1(void);
00596 uint16_t TIM1_GetCapture2(void);
00597 uint16_t TIM1_GetCapture3(void);
00598 uint16_t TIM1_GetCapture4(void);
00599 uint16_t TIM1_GetCounter(void);
00600 uint16_t TIM1_GetPrescaler(void);
00601 FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG);
00602 void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG);
00603 ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT);
00604 void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT);
00605
00606 /**
00607   * @}
00608   */
00609
00610 #endif /* __STM8S_TIM1_H */
00611
00612 /**
00613   * @}
00614   */
00615
00616 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim2.c Source File

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stm8s_tim2.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim2.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the TIM2 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_tim2.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 static void TI1_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter);
00034 static void TI2_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter);
00035 static void TI3_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter);
00036 /**
00037   * @addtogroup TIM2_Public_Functions
00038   * @{
00039   */
00040
00041 /**
00042   * @brief  Deinitializes the TIM2 peripheral registers to their default reset values.
00043   * @param  None
00044   * @retval None
00045   */
00046 void TIM2_DeInit(void)
00047 {
00048
00049     TIM2->CR1 = (uint8_t)TIM2_CR1_RESET_VALUE;
00050     TIM2->IER = (uint8_t)TIM2_IER_RESET_VALUE;
00051     TIM2->SR2 = (uint8_t)TIM2_SR2_RESET_VALUE;
00052
00053     /* Disable channels */
00054     TIM2->CCER1 = (uint8_t)TIM2_CCER1_RESET_VALUE;
00055     TIM2->CCER2 = (uint8_t)TIM2_CCER2_RESET_VALUE;
00056
00057
00058     /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
00059     TIM2->CCER1 = (uint8_t)TIM2_CCER1_RESET_VALUE;
00060     TIM2->CCER2 = (uint8_t)TIM2_CCER2_RESET_VALUE;
00061     TIM2->CCMR1 = (uint8_t)TIM2_CCMR1_RESET_VALUE;
00062     TIM2->CCMR2 = (uint8_t)TIM2_CCMR2_RESET_VALUE;
00063     TIM2->CCMR3 = (uint8_t)TIM2_CCMR3_RESET_VALUE;
00064     TIM2->CNTRH = (uint8_t)TIM2_CNTRH_RESET_VALUE;
00065     TIM2->CNTRL = (uint8_t)TIM2_CNTRL_RESET_VALUE;
00066     TIM2->PSCR = (uint8_t)TIM2_PSCR_RESET_VALUE;
00067     TIM2->ARRH  = (uint8_t)TIM2_ARRH_RESET_VALUE;
00068     TIM2->ARRL  = (uint8_t)TIM2_ARRL_RESET_VALUE;
00069     TIM2->CCR1H = (uint8_t)TIM2_CCR1H_RESET_VALUE;
00070     TIM2->CCR1L = (uint8_t)TIM2_CCR1L_RESET_VALUE;
00071     TIM2->CCR2H = (uint8_t)TIM2_CCR2H_RESET_VALUE;
00072     TIM2->CCR2L = (uint8_t)TIM2_CCR2L_RESET_VALUE;
00073     TIM2->CCR3H = (uint8_t)TIM2_CCR3H_RESET_VALUE;
00074     TIM2->CCR3L = (uint8_t)TIM2_CCR3L_RESET_VALUE;
00075     TIM2->SR1 = (uint8_t)TIM2_SR1_RESET_VALUE;
00076 }
00077
00078
00079 /**
00080   * @brief  Initializes the TIM2 Time Base Unit according to the specified parameters.
00081   * @param    TIM2_Prescaler specifies the Prescaler from TIM2_Prescaler_TypeDef.
00082   * @param    TIM2_Period specifies the Period value.
00083   * @retval None
00084   */
00085 void TIM2_TimeBaseInit( TIM2_Prescaler_TypeDef TIM2_Prescaler,
00086                         uint16_t TIM2_Period)
00087 {
00088     /* Set the Prescaler value */
00089     TIM2->PSCR = (uint8_t)(TIM2_Prescaler);
00090     /* Set the Autoreload value */
00091     TIM2->ARRH = (uint8_t)(TIM2_Period >> 8);
00092     TIM2->ARRL = (uint8_t)(TIM2_Period);
00093 }
00094
00095
00096 /**
00097   * @brief  Initializes the TIM2 Channel1 according to the specified parameters.
00098   * @param   TIM2_OCMode specifies the Output Compare mode  from @ref TIM2_OCMode_TypeDef.
00099   * @param   TIM2_OutputState specifies the Output State  from @ref TIM2_OutputState_TypeDef.
00100   * @param   TIM2_Pulse specifies the Pulse width  value.
00101   * @param   TIM2_OCPolarity specifies the Output Compare Polarity  from @ref TIM2_OCPolarity_TypeDef.
00102   * @retval None
00103   */
00104 void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode,
00105                   TIM2_OutputState_TypeDef TIM2_OutputState,
00106                   uint16_t TIM2_Pulse,
00107                   TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00108 {
00109     /* Check the parameters */
00110     assert_param(IS_TIM2_OC_MODE_OK(TIM2_OCMode));
00111     assert_param(IS_TIM2_OUTPUT_STATE_OK(TIM2_OutputState));
00112     assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00113
00114     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */
00115     TIM2->CCER1 &= (uint8_t)(~( TIM2_CCER1_CC1E | TIM2_CCER1_CC1P));
00116     /* Set the Output State &  Set the Output Polarity  */
00117     TIM2->CCER1 |= (uint8_t)((uint8_t)(TIM2_OutputState & TIM2_CCER1_CC1E ) |
00118                              (uint8_t)(TIM2_OCPolarity & TIM2_CCER1_CC1P));
00119
00120     /* Reset the Output Compare Bits  & Set the Ouput Compare Mode */
00121     TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_OCM)) |
00122                             (uint8_t)TIM2_OCMode);
00123
00124     /* Set the Pulse value */
00125     TIM2->CCR1H = (uint8_t)(TIM2_Pulse >> 8);
00126     TIM2->CCR1L = (uint8_t)(TIM2_Pulse);
00127 }
00128
00129
00130 /**
00131   * @brief  Initializes the TIM2 Channel2 according to the specified parameters.
00132   * @param   TIM2_OCMode specifies the Output Compare mode  from @ref TIM2_OCMode_TypeDef.
00133   * @param   TIM2_OutputState specifies the Output State  from @ref TIM2_OutputState_TypeDef.
00134   * @param   TIM2_Pulse specifies the Pulse width  value.
00135   * @param   TIM2_OCPolarity specifies the Output Compare Polarity  from @ref TIM2_OCPolarity_TypeDef.
00136   * @retval None
00137   */
00138 void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode,
00139                   TIM2_OutputState_TypeDef TIM2_OutputState,
00140                   uint16_t TIM2_Pulse,
00141                   TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00142 {
00143     /* Check the parameters */
00144     assert_param(IS_TIM2_OC_MODE_OK(TIM2_OCMode));
00145     assert_param(IS_TIM2_OUTPUT_STATE_OK(TIM2_OutputState));
00146     assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00147
00148
00149     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */
00150     TIM2->CCER1 &= (uint8_t)(~( TIM2_CCER1_CC2E |  TIM2_CCER1_CC2P ));
00151     /* Set the Output State & Set the Output Polarity */
00152     TIM2->CCER1 |= (uint8_t)((uint8_t)(TIM2_OutputState  & TIM2_CCER1_CC2E ) |
00153                         (uint8_t)(TIM2_OCPolarity & TIM2_CCER1_CC2P));
00154
00155
00156     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00157     TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_OCM)) |
00158                             (uint8_t)TIM2_OCMode);
00159
00160
00161     /* Set the Pulse value */
00162     TIM2->CCR2H = (uint8_t)(TIM2_Pulse >> 8);
00163     TIM2->CCR2L = (uint8_t)(TIM2_Pulse);
00164 }
00165
00166
00167 /**
00168   * @brief  Initializes the TIM2 Channel3 according to the specified parameters.
00169   * @param   TIM2_OCMode specifies the Output Compare mode from @ref TIM2_OCMode_TypeDef.
00170   * @param   TIM2_OutputState specifies the Output State from @ref TIM2_OutputState_TypeDef.
00171   * @param   TIM2_Pulse specifies the Pulse width value.
00172   * @param   TIM2_OCPolarity specifies the Output Compare Polarity  from @ref TIM2_OCPolarity_TypeDef.
00173   * @retval None
00174   */
00175 void TIM2_OC3Init(TIM2_OCMode_TypeDef TIM2_OCMode,
00176                   TIM2_OutputState_TypeDef TIM2_OutputState,
00177                   uint16_t TIM2_Pulse,
00178                   TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00179 {
00180     /* Check the parameters */
00181     assert_param(IS_TIM2_OC_MODE_OK(TIM2_OCMode));
00182     assert_param(IS_TIM2_OUTPUT_STATE_OK(TIM2_OutputState));
00183     assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00184     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */
00185     TIM2->CCER2 &= (uint8_t)(~( TIM2_CCER2_CC3E  | TIM2_CCER2_CC3P));
00186     /* Set the Output State & Set the Output Polarity */
00187     TIM2->CCER2 |= (uint8_t)((uint8_t)(TIM2_OutputState & TIM2_CCER2_CC3E) |
00188                              (uint8_t)(TIM2_OCPolarity & TIM2_CCER2_CC3P));
00189
00190     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00191     TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) |
00192                             (uint8_t)TIM2_OCMode);
00193
00194     /* Set the Pulse value */
00195     TIM2->CCR3H = (uint8_t)(TIM2_Pulse >> 8);
00196     TIM2->CCR3L = (uint8_t)(TIM2_Pulse);
00197
00198 }
00199
00200
00201 /**
00202   * @brief  Initializes the TIM2 peripheral according to the specified parameters.
00203   * @param    TIM2_Channel specifies the Input Capture Channel from @ref TIM2_Channel_TypeDef.
00204   * @param   TIM2_ICPolarity specifies the Input Capture Polarity from @ref TIM2_ICPolarity_TypeDef.
00205   * @param   TIM2_ICSelection specifies the Input Capture Selection from @ref TIM2_ICSelection_TypeDef.
00206   * @param   TIM2_ICPrescaler specifies the Input Capture Prescaler from @ref TIM2_ICPSC_TypeDef.
00207   * @param   TIM2_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00208   * @retval None
00209   */
00210 void TIM2_ICInit(TIM2_Channel_TypeDef TIM2_Channel,
00211                  TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
00212                  TIM2_ICSelection_TypeDef TIM2_ICSelection,
00213                  TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
00214                  uint8_t TIM2_ICFilter)
00215 {
00216     /* Check the parameters */
00217     assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
00218     assert_param(IS_TIM2_IC_POLARITY_OK(TIM2_ICPolarity));
00219     assert_param(IS_TIM2_IC_SELECTION_OK(TIM2_ICSelection));
00220     assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_ICPrescaler));
00221     assert_param(IS_TIM2_IC_FILTER_OK(TIM2_ICFilter));
00222
00223     if (TIM2_Channel == TIM2_CHANNEL_1)
00224     {
00225         /* TI1 Configuration */
00226         TI1_Config((uint8_t)TIM2_ICPolarity,
00227                    (uint8_t)TIM2_ICSelection,
00228                    (uint8_t)TIM2_ICFilter);
00229
00230         /* Set the Input Capture Prescaler value */
00231         TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
00232     }
00233     else if (TIM2_Channel == TIM2_CHANNEL_2)
00234     {
00235         /* TI2 Configuration */
00236         TI2_Config((uint8_t)TIM2_ICPolarity,
00237                    (uint8_t)TIM2_ICSelection,
00238                    (uint8_t)TIM2_ICFilter);
00239
00240         /* Set the Input Capture Prescaler value */
00241         TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
00242     }
00243     else
00244     {
00245         /* TI3 Configuration */
00246         TI3_Config((uint8_t)TIM2_ICPolarity,
00247                    (uint8_t)TIM2_ICSelection,
00248                    (uint8_t)TIM2_ICFilter);
00249
00250         /* Set the Input Capture Prescaler value */
00251         TIM2_SetIC3Prescaler(TIM2_ICPrescaler);
00252     }
00253 }
00254
00255
00256 /**
00257   * @brief  Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.
00258     * @param    TIM2_Channel specifies the Input Capture Channel from @ref TIM2_Channel_TypeDef.
00259   * @param   TIM2_ICPolarity specifies the Input Capture Polarity from @ref TIM2_ICPolarity_TypeDef.
00260   * @param   TIM2_ICSelection specifies the Input Capture Selection from @ref TIM2_ICSelection_TypeDef.
00261   * @param   TIM2_ICPrescaler specifies the Input Capture Prescaler from @ref TIM2_ICPSC_TypeDef.
00262   * @param   TIM2_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00263   * @retval None
00264   */
00265 void TIM2_PWMIConfig(TIM2_Channel_TypeDef TIM2_Channel,
00266                      TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
00267                      TIM2_ICSelection_TypeDef TIM2_ICSelection,
00268                      TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
00269                      uint8_t TIM2_ICFilter)
00270 {
00271     uint8_t icpolarity = (uint8_t)TIM2_ICPOLARITY_RISING;
00272     uint8_t icselection = (uint8_t)TIM2_ICSELECTION_DIRECTTI;
00273
00274     /* Check the parameters */
00275     assert_param(IS_TIM2_PWMI_CHANNEL_OK(TIM2_Channel));
00276     assert_param(IS_TIM2_IC_POLARITY_OK(TIM2_ICPolarity));
00277     assert_param(IS_TIM2_IC_SELECTION_OK(TIM2_ICSelection));
00278     assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_ICPrescaler));
00279
00280     /* Select the Opposite Input Polarity */
00281     if (TIM2_ICPolarity != TIM2_ICPOLARITY_FALLING)
00282     {
00283         icpolarity = (uint8_t)TIM2_ICPOLARITY_FALLING;
00284     }
00285     else
00286     {
00287         icpolarity = (uint8_t)TIM2_ICPOLARITY_RISING;
00288     }
00289
00290     /* Select the Opposite Input */
00291     if (TIM2_ICSelection == TIM2_ICSELECTION_DIRECTTI)
00292     {
00293         icselection = (uint8_t)TIM2_ICSELECTION_INDIRECTTI;
00294     }
00295     else
00296     {
00297         icselection = (uint8_t)TIM2_ICSELECTION_DIRECTTI;
00298     }
00299
00300     if (TIM2_Channel == TIM2_CHANNEL_1)
00301     {
00302         /* TI1 Configuration */
00303         TI1_Config((uint8_t)TIM2_ICPolarity, (uint8_t)TIM2_ICSelection,
00304                    (uint8_t)TIM2_ICFilter);
00305
00306         /* Set the Input Capture Prescaler value */
00307         TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
00308
00309         /* TI2 Configuration */
00310         TI2_Config(icpolarity, icselection, TIM2_ICFilter);
00311
00312         /* Set the Input Capture Prescaler value */
00313         TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
00314     }
00315     else
00316     {
00317         /* TI2 Configuration */
00318         TI2_Config((uint8_t)TIM2_ICPolarity, (uint8_t)TIM2_ICSelection,
00319                    (uint8_t)TIM2_ICFilter);
00320
00321         /* Set the Input Capture Prescaler value */
00322         TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
00323
00324         /* TI1 Configuration */
00325         TI1_Config((uint8_t)icpolarity, icselection, (uint8_t)TIM2_ICFilter);
00326
00327         /* Set the Input Capture Prescaler value */
00328         TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
00329     }
00330 }
00331
00332
00333 /**
00334   * @brief  Enables or disables the TIM2 peripheral.
00335   * @param   NewState new state of the TIM2 peripheral. This parameter can
00336   * be ENABLE or DISABLE.
00337   * @retval None
00338   */
00339 void TIM2_Cmd(FunctionalState NewState)
00340 {
00341     /* Check the parameters */
00342     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00343
00344     /* set or Reset the CEN Bit */
00345     if (NewState != DISABLE)
00346     {
00347         TIM2->CR1 |= (uint8_t)TIM2_CR1_CEN;
00348     }
00349     else
00350     {
00351         TIM2->CR1 &= (uint8_t)(~TIM2_CR1_CEN);
00352     }
00353 }
00354
00355
00356 /**
00357   * @brief  Enables or disables the specified TIM2 interrupts.
00358   * @param   NewState new state of the TIM2 peripheral.
00359   * This parameter can be: ENABLE or DISABLE.
00360   * @param   TIM2_IT specifies the TIM2 interrupts sources to be enabled or disabled.
00361   * This parameter can be any combination of the following values:
00362   *                       - TIM2_IT_UPDATE: TIM2 update Interrupt source
00363   *                       - TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
00364   *                       - TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
00365   *                       - TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
00366   * @param   NewState new state of the TIM2 peripheral.
00367   * @retval None
00368   */
00369 void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
00370 {
00371     /* Check the parameters */
00372     assert_param(IS_TIM2_IT_OK(TIM2_IT));
00373     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00374
00375     if (NewState != DISABLE)
00376     {
00377         /* Enable the Interrupt sources */
00378         TIM2->IER |= (uint8_t)TIM2_IT;
00379     }
00380     else
00381     {
00382         /* Disable the Interrupt sources */
00383         TIM2->IER &= (uint8_t)(~TIM2_IT);
00384     }
00385 }
00386
00387
00388 /**
00389   * @brief  Enables or Disables the TIM2 Update event.
00390   * @param   NewState new state of the TIM2 peripheral Preload register. This parameter can
00391   * be ENABLE or DISABLE.
00392   * @retval None
00393   */
00394 void TIM2_UpdateDisableConfig(FunctionalState NewState)
00395 {
00396     /* Check the parameters */
00397     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00398
00399     /* Set or Reset the UDIS Bit */
00400     if (NewState != DISABLE)
00401     {
00402         TIM2->CR1 |= (uint8_t)TIM2_CR1_UDIS;
00403     }
00404     else
00405     {
00406         TIM2->CR1 &= (uint8_t)(~TIM2_CR1_UDIS);
00407     }
00408 }
00409
00410 /**
00411   * @brief  Selects the TIM2 Update Request Interrupt source.
00412   * @param   TIM2_UpdateSource specifies the Update source.
00413   * This parameter can be one of the following values
00414   *                       - TIM2_UPDATESOURCE_REGULAR
00415   *                       - TIM2_UPDATESOURCE_GLOBAL
00416   * @retval None
00417   */
00418 void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
00419 {
00420     /* Check the parameters */
00421     assert_param(IS_TIM2_UPDATE_SOURCE_OK(TIM2_UpdateSource));
00422
00423     /* Set or Reset the URS Bit */
00424     if (TIM2_UpdateSource != TIM2_UPDATESOURCE_GLOBAL)
00425     {
00426         TIM2->CR1 |= (uint8_t)TIM2_CR1_URS;
00427     }
00428     else
00429     {
00430         TIM2->CR1 &= (uint8_t)(~TIM2_CR1_URS);
00431     }
00432 }
00433
00434
00435 /**
00436   * @brief  Selects the TIM2’s One Pulse Mode.
00437   * @param   TIM2_OPMode specifies the OPM Mode to be used.
00438   * This parameter can be one of the following values
00439   *                    - TIM2_OPMODE_SINGLE
00440   *                    - TIM2_OPMODE_REPETITIVE
00441   * @retval None
00442   */
00443 void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode)
00444 {
00445     /* Check the parameters */
00446     assert_param(IS_TIM2_OPM_MODE_OK(TIM2_OPMode));
00447
00448     /* Set or Reset the OPM Bit */
00449     if (TIM2_OPMode != TIM2_OPMODE_REPETITIVE)
00450     {
00451         TIM2->CR1 |= (uint8_t)TIM2_CR1_OPM;
00452     }
00453     else
00454     {
00455         TIM2->CR1 &= (uint8_t)(~TIM2_CR1_OPM);
00456     }
00457
00458 }
00459
00460
00461 /**
00462   * @brief  Configures the TIM2 Prescaler.
00463   * @param   Prescaler specifies the Prescaler Register value
00464   * This parameter can be one of the following values
00465   *                       -  TIM2_PRESCALER_1
00466   *                       -  TIM2_PRESCALER_2
00467   *                       -  TIM2_PRESCALER_4
00468   *                       -  TIM2_PRESCALER_8
00469   *                       -  TIM2_PRESCALER_16
00470   *                       -  TIM2_PRESCALER_32
00471   *                       -  TIM2_PRESCALER_64
00472   *                       -  TIM2_PRESCALER_128
00473   *                       -  TIM2_PRESCALER_256
00474   *                       -  TIM2_PRESCALER_512
00475   *                       -  TIM2_PRESCALER_1024
00476   *                       -  TIM2_PRESCALER_2048
00477   *                       -  TIM2_PRESCALER_4096
00478   *                       -  TIM2_PRESCALER_8192
00479   *                       -  TIM2_PRESCALER_16384
00480   *                       -  TIM2_PRESCALER_32768
00481   * @param   TIM2_PSCReloadMode specifies the TIM2 Prescaler Reload mode.
00482   * This parameter can be one of the following values
00483   *                       - TIM2_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
00484   *                         immediately.
00485   *                       - TIM2_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
00486   *                         the update event.
00487   * @retval None
00488   */
00489 void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,
00490                           TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
00491 {
00492     /* Check the parameters */
00493     assert_param(IS_TIM2_PRESCALER_RELOAD_OK(TIM2_PSCReloadMode));
00494     assert_param(IS_TIM2_PRESCALER_OK(Prescaler));
00495
00496     /* Set the Prescaler value */
00497     TIM2->PSCR = (uint8_t)Prescaler;
00498
00499     /* Set or reset the UG Bit */
00500     TIM2->EGR = (uint8_t)TIM2_PSCReloadMode;
00501 }
00502
00503 /**
00504   * @brief  Forces the TIM2 Channel1 output waveform to active or inactive level.
00505   * @param   TIM2_ForcedAction specifies the forced Action to be set to the output waveform.
00506   * This parameter can be one of the following values:
00507   *                       - TIM2_FORCEDACTION_ACTIVE: Force active level on OC1REF
00508   *                       - TIM2_FORCEDACTION_INACTIVE: Force inactive level on
00509   *                         OC1REF.
00510   * @retval None
00511   */
00512 void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
00513 {
00514     /* Check the parameters */
00515     assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
00516
00517     /* Reset the OCM Bits & Configure the Forced output Mode */
00518     TIM2->CCMR1  =  (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_OCM))
00519                               | (uint8_t)TIM2_ForcedAction);
00520 }
00521
00522 /**
00523   * @brief  Forces the TIM2 Channel2 output waveform to active or inactive level.
00524   * @param   TIM2_ForcedAction specifies the forced Action to be set to the output waveform.
00525   * This parameter can be one of the following values:
00526   *                       - TIM2_FORCEDACTION_ACTIVE: Force active level on OC2REF
00527   *                       - TIM2_FORCEDACTION_INACTIVE: Force inactive level on
00528   *                         OC2REF.
00529   * @retval None
00530   */
00531 void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
00532 {
00533     /* Check the parameters */
00534     assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
00535
00536     /* Reset the OCM Bits & Configure the Forced output Mode */
00537     TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_OCM))
00538                             | (uint8_t)TIM2_ForcedAction);
00539 }
00540
00541 /**
00542   * @brief  Forces the TIM2 Channel3 output waveform to active or inactive level.
00543   * @param   TIM2_ForcedAction specifies the forced Action to be set to the output waveform.
00544   * This parameter can be one of the following values:
00545   *                       - TIM2_FORCEDACTION_ACTIVE: Force active level on OC3REF
00546   *                       - TIM2_FORCEDACTION_INACTIVE: Force inactive level on
00547   *                         OC3REF.
00548   * @retval None
00549   */
00550 void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
00551 {
00552     /* Check the parameters */
00553     assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
00554
00555     /* Reset the OCM Bits & Configure the Forced output Mode */
00556     TIM2->CCMR3  =  (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM))
00557                               | (uint8_t)TIM2_ForcedAction);
00558 }
00559
00560
00561 /**
00562   * @brief  Enables or disables TIM2 peripheral Preload register on ARR.
00563   * @param   NewState new state of the TIM2 peripheral Preload register.
00564   * This parameter can be ENABLE or DISABLE.
00565   * @retval None
00566   */
00567 void TIM2_ARRPreloadConfig(FunctionalState NewState)
00568 {
00569     /* Check the parameters */
00570     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00571
00572     /* Set or Reset the ARPE Bit */
00573     if (NewState != DISABLE)
00574     {
00575         TIM2->CR1 |= (uint8_t)TIM2_CR1_ARPE;
00576     }
00577     else
00578     {
00579         TIM2->CR1 &= (uint8_t)(~TIM2_CR1_ARPE);
00580     }
00581 }
00582
00583
00584 /**
00585   * @brief  Enables or disables the TIM2 peripheral Preload Register on CCR1.
00586   * @param   NewState new state of the Capture Compare Preload register.
00587   * This parameter can be ENABLE or DISABLE.
00588   * @retval None
00589   */
00590 void TIM2_OC1PreloadConfig(FunctionalState NewState)
00591 {
00592     /* Check the parameters */
00593     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00594
00595     /* Set or Reset the OC1PE Bit */
00596     if (NewState != DISABLE)
00597     {
00598         TIM2->CCMR1 |= (uint8_t)TIM2_CCMR_OCxPE;
00599     }
00600     else
00601     {
00602         TIM2->CCMR1 &= (uint8_t)(~TIM2_CCMR_OCxPE);
00603     }
00604 }
00605
00606
00607 /**
00608   * @brief  Enables or disables the TIM2 peripheral Preload Register on CCR2.
00609   * @param   NewState new state of the Capture Compare Preload register.
00610   * This parameter can be ENABLE or DISABLE.
00611   * @retval None
00612   */
00613 void TIM2_OC2PreloadConfig(FunctionalState NewState)
00614 {
00615     /* Check the parameters */
00616     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00617
00618     /* Set or Reset the OC2PE Bit */
00619     if (NewState != DISABLE)
00620     {
00621         TIM2->CCMR2 |= (uint8_t)TIM2_CCMR_OCxPE;
00622     }
00623     else
00624     {
00625         TIM2->CCMR2 &= (uint8_t)(~TIM2_CCMR_OCxPE);
00626     }
00627 }
00628
00629
00630 /**
00631   * @brief  Enables or disables the TIM2 peripheral Preload Register on CCR3.
00632   * @param   NewState new state of the Capture Compare Preload register.
00633   * This parameter can be ENABLE or DISABLE.
00634   * @retval None
00635   */
00636 void TIM2_OC3PreloadConfig(FunctionalState NewState)
00637 {
00638     /* Check the parameters */
00639     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00640
00641     /* Set or Reset the OC3PE Bit */
00642     if (NewState != DISABLE)
00643     {
00644         TIM2->CCMR3 |= (uint8_t)TIM2_CCMR_OCxPE;
00645     }
00646     else
00647     {
00648         TIM2->CCMR3 &= (uint8_t)(~TIM2_CCMR_OCxPE);
00649     }
00650 }
00651
00652
00653 /**
00654   * @brief  Configures the TIM2 event to be generated by software.
00655   * @param   TIM2_EventSource specifies the event source.
00656   * This parameter can be one of the following values:
00657   *                       - TIM2_EVENTSOURCE_UPDATE: TIM2 update Event source
00658   *                       - TIM2_EVENTSOURCE_CC1: TIM2 Capture Compare 1 Event source
00659   *                       - TIM2_EVENTSOURCE_CC2: TIM2 Capture Compare 2 Event source
00660   *                       - TIM2_EVENTSOURCE_CC3: TIM2 Capture Compare 3 Event source
00661   * @retval None
00662   */
00663 void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource)
00664 {
00665     /* Check the parameters */
00666     assert_param(IS_TIM2_EVENT_SOURCE_OK(TIM2_EventSource));
00667
00668     /* Set the event sources */
00669     TIM2->EGR = (uint8_t)TIM2_EventSource;
00670 }
00671
00672
00673 /**
00674   * @brief  Configures the TIM2 Channel 1 polarity.
00675   * @param   TIM2_OCPolarity specifies the OC1 Polarity.
00676   * This parameter can be one of the following values:
00677   *                       - TIM2_OCPOLARITY_LOW: Output Compare active low
00678   *                       - TIM2_OCPOLARITY_HIGH: Output Compare active high
00679   * @retval None
00680   */
00681 void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00682 {
00683     /* Check the parameters */
00684     assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00685
00686     /* Set or Reset the CC1P Bit */
00687     if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
00688     {
00689         TIM2->CCER1 |= (uint8_t)TIM2_CCER1_CC1P;
00690     }
00691     else
00692     {
00693         TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1P);
00694     }
00695 }
00696
00697
00698 /**
00699   * @brief  Configures the TIM2 Channel 2 polarity.
00700   * @param   TIM2_OCPolarity specifies the OC2 Polarity.
00701   * This parameter can be one of the following values:
00702   *                       - TIM2_OCPOLARITY_LOW: Output Compare active low
00703   *                       - TIM2_OCPOLARITY_HIGH: Output Compare active high
00704   * @retval None
00705   */
00706 void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00707 {
00708     /* Check the parameters */
00709     assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00710
00711     /* Set or Reset the CC2P Bit */
00712     if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
00713     {
00714         TIM2->CCER1 |= TIM2_CCER1_CC2P;
00715     }
00716     else
00717     {
00718         TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2P);
00719     }
00720 }
00721
00722
00723 /**
00724   * @brief  Configures the TIM2 Channel 3 polarity.
00725   * @param   TIM2_OCPolarity specifies the OC3 Polarity.
00726   * This parameter can be one of the following values:
00727   *                       - TIM2_OCPOLARITY_LOW: Output Compare active low
00728   *                       - TIM2_OCPOLARITY_HIGH: Output Compare active high
00729   * @retval None
00730   */
00731 void TIM2_OC3PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
00732 {
00733     /* Check the parameters */
00734     assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
00735
00736     /* Set or Reset the CC3P Bit */
00737     if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
00738     {
00739         TIM2->CCER2 |= (uint8_t)TIM2_CCER2_CC3P;
00740     }
00741     else
00742     {
00743         TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3P);
00744     }
00745 }
00746
00747
00748 /**
00749   * @brief  Enables or disables the TIM2 Capture Compare Channel x.
00750   * @param   TIM2_Channel specifies the TIM2 Channel.
00751   * This parameter can be one of the following values:
00752   *                       - TIM2_CHANNEL_1: TIM2 Channel1
00753   *                       - TIM2_CHANNEL_2: TIM2 Channel2
00754   *                       - TIM2_CHANNEL_3: TIM2 Channel3
00755   * @param   NewState specifies the TIM2 Channel CCxE bit new state.
00756   * This parameter can be: ENABLE or DISABLE.
00757   * @retval None
00758   */
00759 void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
00760 {
00761     /* Check the parameters */
00762     assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
00763     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00764
00765     if (TIM2_Channel == TIM2_CHANNEL_1)
00766     {
00767         /* Set or Reset the CC1E Bit */
00768         if (NewState != DISABLE)
00769         {
00770             TIM2->CCER1 |= (uint8_t)TIM2_CCER1_CC1E;
00771         }
00772         else
00773         {
00774             TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1E);
00775         }
00776
00777     }
00778     else if (TIM2_Channel == TIM2_CHANNEL_2)
00779     {
00780         /* Set or Reset the CC2E Bit */
00781         if (NewState != DISABLE)
00782         {
00783             TIM2->CCER1 |= (uint8_t)TIM2_CCER1_CC2E;
00784         }
00785         else
00786         {
00787             TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2E);
00788         }
00789     }
00790     else
00791     {
00792         /* Set or Reset the CC3E Bit */
00793         if (NewState != DISABLE)
00794         {
00795             TIM2->CCER2 |= (uint8_t)TIM2_CCER2_CC3E;
00796         }
00797         else
00798         {
00799             TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3E);
00800         }
00801     }
00802 }
00803
00804 /**
00805   * @brief  Selects the TIM2 Output Compare Mode. This function disables the
00806   * selected channel before changing the Output Compare Mode. User has to
00807   * enable this channel using TIM2_CCxCmd and TIM2_CCxNCmd functions.
00808   * @param   TIM2_Channel specifies the TIM2 Channel.
00809   * This parameter can be one of the following values:
00810   *                       - TIM2_CHANNEL_1: TIM2 Channel1
00811   *                       - TIM2_CHANNEL_2: TIM2 Channel2
00812   *                       - TIM2_CHANNEL_3: TIM2 Channel3
00813   * @param   TIM2_OCMode specifies the TIM2 Output Compare Mode.
00814   * This paramter can be one of the following values:
00815   *                       - TIM2_OCMODE_TIMING
00816   *                       - TIM2_OCMODE_ACTIVE
00817   *                       - TIM2_OCMODE_TOGGLE
00818   *                       - TIM2_OCMODE_PWM1
00819   *                       - TIM2_OCMODE_PWM2
00820   *                       - TIM2_FORCEDACTION_ACTIVE
00821   *                       - TIM2_FORCEDACTION_INACTIVE
00822   * @retval None
00823   */
00824 void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
00825 {
00826     /* Check the parameters */
00827     assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
00828     assert_param(IS_TIM2_OCM_OK(TIM2_OCMode));
00829
00830     if (TIM2_Channel == TIM2_CHANNEL_1)
00831     {
00832         /* Disable the Channel 1: Reset the CCE Bit */
00833         TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1E);
00834
00835         /* Reset the Output Compare Bits & Set the Output Compare Mode */
00836         TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_OCM))
00837                                | (uint8_t)TIM2_OCMode);
00838     }
00839     else if (TIM2_Channel == TIM2_CHANNEL_2)
00840     {
00841         /* Disable the Channel 2: Reset the CCE Bit */
00842         TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2E);
00843
00844         /* Reset the Output Compare Bits & Set the Output Compare Mode */
00845         TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_OCM))
00846                                 | (uint8_t)TIM2_OCMode);
00847     }
00848     else
00849     {
00850         /* Disable the Channel 3: Reset the CCE Bit */
00851         TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3E);
00852
00853         /* Reset the Output Compare Bits & Set the Output Compare Mode */
00854         TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM))
00855                                 | (uint8_t)TIM2_OCMode);
00856     }
00857 }
00858
00859
00860 /**
00861   * @brief  Sets the TIM2 Counter Register value.
00862   * @param   Counter specifies the Counter register new value.
00863   * This parameter is between 0x0000 and 0xFFFF.
00864   * @retval None
00865   */
00866 void TIM2_SetCounter(uint16_t Counter)
00867 {
00868     /* Set the Counter Register value */
00869     TIM2->CNTRH = (uint8_t)(Counter >> 8);
00870     TIM2->CNTRL = (uint8_t)(Counter);
00871
00872 }
00873
00874
00875 /**
00876   * @brief  Sets the TIM2 Autoreload Register value.
00877   * @param   Autoreload specifies the Autoreload register new value.
00878   * This parameter is between 0x0000 and 0xFFFF.
00879   * @retval None
00880   */
00881 void TIM2_SetAutoreload(uint16_t Autoreload)
00882 {
00883
00884     /* Set the Autoreload Register value */
00885     TIM2->ARRH = (uint8_t)(Autoreload >> 8);
00886     TIM2->ARRL = (uint8_t)(Autoreload);
00887
00888 }
00889
00890
00891 /**
00892   * @brief  Sets the TIM2 Capture Compare1 Register value.
00893   * @param   Compare1 specifies the Capture Compare1 register new value.
00894   * This parameter is between 0x0000 and 0xFFFF.
00895   * @retval None
00896   */
00897 void TIM2_SetCompare1(uint16_t Compare1)
00898 {
00899     /* Set the Capture Compare1 Register value */
00900     TIM2->CCR1H = (uint8_t)(Compare1 >> 8);
00901     TIM2->CCR1L = (uint8_t)(Compare1);
00902
00903 }
00904
00905
00906 /**
00907   * @brief  Sets the TIM2 Capture Compare2 Register value.
00908   * @param   Compare2 specifies the Capture Compare2 register new value.
00909   * This parameter is between 0x0000 and 0xFFFF.
00910   * @retval None
00911   */
00912 void TIM2_SetCompare2(uint16_t Compare2)
00913 {
00914     /* Set the Capture Compare2 Register value */
00915     TIM2->CCR2H = (uint8_t)(Compare2 >> 8);
00916     TIM2->CCR2L = (uint8_t)(Compare2);
00917
00918 }
00919
00920
00921 /**
00922   * @brief  Sets the TIM2 Capture Compare3 Register value.
00923   * @param   Compare3 specifies the Capture Compare3 register new value.
00924   * This parameter is between 0x0000 and 0xFFFF.
00925   * @retval None
00926   */
00927 void TIM2_SetCompare3(uint16_t Compare3)
00928 {
00929     /* Set the Capture Compare3 Register value */
00930     TIM2->CCR3H = (uint8_t)(Compare3 >> 8);
00931     TIM2->CCR3L = (uint8_t)(Compare3);
00932
00933 }
00934
00935
00936 /**
00937   * @brief  Sets the TIM2 Input Capture 1 Prescaler.
00938   * @param   TIM2_IC1Prescaler specifies the Input Capture prescaler new value
00939   * This parameter can be one of the following values:
00940   *                       - TIM2_ICPSC_DIV1: no prescaler
00941   *                       - TIM2_ICPSC_DIV2: capture is done once every 2 events
00942   *                       - TIM2_ICPSC_DIV4: capture is done once every 4 events
00943   *                       - TIM2_ICPSC_DIV8: capture is done once every 8 events
00944   * @retval None
00945   */
00946 void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
00947 {
00948     /* Check the parameters */
00949     assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC1Prescaler));
00950
00951     /* Reset the IC1PSC Bits &Set the IC1PSC value */
00952     TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_ICxPSC))
00953                             | (uint8_t)TIM2_IC1Prescaler);
00954 }
00955
00956 /**
00957   * @brief  Sets the TIM2 Input Capture 2 prescaler.
00958   * @param   TIM2_IC2Prescaler specifies the Input Capture prescaler new value
00959   * This parameter can be one of the following values:
00960   *                       - TIM2_ICPSC_DIV1: no prescaler
00961   *                       - TIM2_ICPSC_DIV2: capture is done once every 2 events
00962   *                       - TIM2_ICPSC_DIV4: capture is done once every 4 events
00963   *                       - TIM2_ICPSC_DIV8: capture is done once every 8 events
00964   * @retval None
00965   */
00966 void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
00967 {
00968     /* Check the parameters */
00969     assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC2Prescaler));
00970
00971     /* Reset the IC1PSC Bits &Set the IC1PSC value */
00972     TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_ICxPSC))
00973                             | (uint8_t)TIM2_IC2Prescaler);
00974 }
00975
00976 /**
00977   * @brief  Sets the TIM2 Input Capture 3 prescaler.
00978   * @param   TIM2_IC3Prescaler specifies the Input Capture prescaler new value
00979   * This parameter can be one of the following values:
00980   *                       - TIM2_ICPSC_DIV1: no prescaler
00981   *                       - TIM2_ICPSC_DIV2: capture is done once every 2 events
00982   *                       - TIM2_ICPSC_DIV4: capture is done once every 4 events
00983   *                       - TIM2_ICPSC_DIV8: capture is done once every 8 events
00984   * @retval None
00985   */
00986 void TIM2_SetIC3Prescaler(TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
00987 {
00988
00989     /* Check the parameters */
00990     assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC3Prescaler));
00991     /* Reset the IC1PSC Bits &Set the IC1PSC value */
00992     TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_ICxPSC))
00993                             | (uint8_t)TIM2_IC3Prescaler);
00994 }
00995
00996 /**
00997   * @brief  Gets the TIM2 Input Capture 1 value.
00998   * @param  None
00999   * @retval Capture Compare 1 Register value.
01000   */
01001 uint16_t TIM2_GetCapture1(void)
01002 {
01003     /* Get the Capture 1 Register value */
01004     uint16_t tmpccr1 = 0;
01005     uint8_t tmpccr1l=0, tmpccr1h=0;
01006
01007     tmpccr1h = TIM2->CCR1H;
01008     tmpccr1l = TIM2->CCR1L;
01009
01010     tmpccr1 = (uint16_t)(tmpccr1l);
01011     tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
01012     /* Get the Capture 1 Register value */
01013     return (uint16_t)tmpccr1;
01014 }
01015
01016 /**
01017   * @brief  Gets the TIM2 Input Capture 2 value.
01018   * @param  None
01019   * @retval Capture Compare 2 Register value.
01020   */
01021 uint16_t TIM2_GetCapture2(void)
01022 {
01023     /* Get the Capture 2 Register value */
01024     uint16_t tmpccr2 = 0;
01025     uint8_t tmpccr2l=0, tmpccr2h=0;
01026
01027     tmpccr2h = TIM2->CCR2H;
01028     tmpccr2l = TIM2->CCR2L;
01029
01030     tmpccr2 = (uint16_t)(tmpccr2l);
01031     tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
01032     /* Get the Capture 2 Register value */
01033     return (uint16_t)tmpccr2;
01034 }
01035
01036 /**
01037   * @brief  Gets the TIM2 Input Capture 3 value.
01038   * @param  None
01039   * @retval Capture Compare 3 Register value.
01040   */
01041 uint16_t TIM2_GetCapture3(void)
01042 {
01043     /* Get the Capture 3 Register value */
01044     uint16_t tmpccr3 = 0;
01045     uint8_t tmpccr3l=0, tmpccr3h=0;
01046
01047     tmpccr3h = TIM2->CCR3H;
01048     tmpccr3l = TIM2->CCR3L;
01049
01050     tmpccr3 = (uint16_t)(tmpccr3l);
01051     tmpccr3 |= (uint16_t)((uint16_t)tmpccr3h << 8);
01052     /* Get the Capture 3 Register value */
01053     return (uint16_t)tmpccr3;
01054 }
01055
01056 /**
01057   * @brief  Gets the TIM2 Counter value.
01058   * @param  None
01059   * @retval Counter Register value.
01060   */
01061 uint16_t TIM2_GetCounter(void)
01062 {
01063      uint16_t tmpcntr = 0;
01064
01065     tmpcntr =  ((uint16_t)TIM2->CNTRH << 8);
01066     /* Get the Counter Register value */
01067     return (uint16_t)( tmpcntr| (uint16_t)(TIM2->CNTRL));
01068 }
01069
01070
01071 /**
01072   * @brief  Gets the TIM2 Prescaler value.
01073   * @param  None
01074   * @retval Prescaler Register configuration value  @ref TIM2_Prescaler_TypeDef.
01075   */
01076 TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void)
01077 {
01078     /* Get the Prescaler Register value */
01079     return (TIM2_Prescaler_TypeDef)(TIM2->PSCR);
01080 }
01081
01082
01083 /**
01084   * @brief  Checks whether the specified TIM2 flag is set or not.
01085   * @param   TIM2_FLAG specifies the flag to check.
01086   * This parameter can be one of the following values:
01087   *                       - TIM2_FLAG_UPDATE: TIM2 update Flag
01088   *                       - TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
01089   *                       - TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
01090   *                       - TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
01091   *                       - TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
01092   *                       - TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
01093   *                       - TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
01094   * @retval FlagStatus The new state of TIM2_FLAG (SET or RESET).
01095   */
01096 FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG)
01097 {
01098     FlagStatus bitstatus = RESET;
01099     uint8_t tim2_flag_l = 0, tim2_flag_h = 0;
01100
01101     /* Check the parameters */
01102     assert_param(IS_TIM2_GET_FLAG_OK(TIM2_FLAG));
01103
01104     tim2_flag_l = (uint8_t)(TIM2->SR1 & (uint8_t)TIM2_FLAG);
01105     tim2_flag_h = (uint8_t)((uint16_t)TIM2_FLAG >> 8);
01106
01107     if ((tim2_flag_l | (uint8_t)(TIM2->SR2 & tim2_flag_h)) != (uint8_t)RESET )
01108     {
01109         bitstatus = SET;
01110     }
01111     else
01112     {
01113         bitstatus = RESET;
01114     }
01115     return (FlagStatus)bitstatus;
01116 }
01117
01118
01119 /**
01120   * @brief  Clears the TIM2’s pending flags.
01121   * @param   TIM2_FLAG specifies the flag to clear.
01122   * This parameter can be one of the following values:
01123   *                       - TIM2_FLAG_UPDATE: TIM2 update Flag
01124   *                       - TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag
01125   *                       - TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag
01126   *                       - TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag
01127   *                       - TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag
01128   *                       - TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag
01129   *                       - TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag
01130   * @retval None.
01131   */
01132 void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG)
01133 {
01134     /* Check the parameters */
01135     assert_param(IS_TIM2_CLEAR_FLAG_OK(TIM2_FLAG));
01136
01137     /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
01138     TIM2->SR1 = (uint8_t)(~((uint8_t)(TIM2_FLAG)));
01139     TIM2->SR2 = (uint8_t)(~((uint8_t)((uint8_t)TIM2_FLAG >> 8)));
01140 }
01141
01142
01143 /**
01144   * @brief  Checks whether the TIM2 interrupt has occurred or not.
01145   * @param   TIM2_IT specifies the TIM2 interrupt source to check.
01146   * This parameter can be one of the following values:
01147   *                       - TIM2_IT_UPDATE: TIM2 update Interrupt source
01148   *                       - TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
01149   *                       - TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
01150   *                       - TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
01151   * @retval ITStatus The new state of the TIM2_IT(SET or RESET).
01152   */
01153
01154 ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT)
01155 {
01156     ITStatus bitstatus = RESET;
01157     uint8_t TIM2_itStatus = 0, TIM2_itEnable = 0;
01158
01159     /* Check the parameters */
01160     assert_param(IS_TIM2_GET_IT_OK(TIM2_IT));
01161
01162     TIM2_itStatus = (uint8_t)(TIM2->SR1 & TIM2_IT);
01163
01164     TIM2_itEnable = (uint8_t)(TIM2->IER & TIM2_IT);
01165
01166     if ((TIM2_itStatus != (uint8_t)RESET ) && (TIM2_itEnable != (uint8_t)RESET ))
01167     {
01168         bitstatus = SET;
01169     }
01170     else
01171     {
01172         bitstatus = RESET;
01173     }
01174     return (ITStatus)(bitstatus);
01175 }
01176
01177
01178 /**
01179   * @brief  Clears the TIM2's interrupt pending bits.
01180   * @param   TIM2_IT specifies the pending bit to clear.
01181   * This parameter can be one of the following values:
01182   *                       - TIM2_IT_UPDATE: TIM2 update Interrupt source
01183   *                       - TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source
01184   *                       - TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source
01185   *                       - TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source
01186   * @retval None.
01187   */
01188 void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT)
01189 {
01190     /* Check the parameters */
01191     assert_param(IS_TIM2_IT_OK(TIM2_IT));
01192
01193     /* Clear the IT pending Bit */
01194     TIM2->SR1 = (uint8_t)(~TIM2_IT);
01195 }
01196
01197
01198 /**
01199   * @brief  Configure the TI1 as Input.
01200   * @param   TIM2_ICPolarity  The Input Polarity.
01201   * This parameter can be one of the following values:
01202   *                       - TIM2_ICPOLARITY_FALLING
01203   *                       - TIM2_ICPOLARITY_RISING
01204   * @param   TIM2_ICSelection specifies the input to be used.
01205   * This parameter can be one of the following values:
01206   *                       - TIM2_ICSELECTION_DIRECTTI: TIM2 Input 1 is selected to
01207   *                         be connected to IC1.
01208   *                       - TIM2_ICSELECTION_INDIRECTTI: TIM2 Input 1 is selected to
01209   *                         be connected to IC2.
01210   * @param   TIM2_ICFilter Specifies the Input Capture Filter.
01211   * This parameter must be a value between 0x00 and 0x0F.
01212   * @retval None
01213   */
01214 static void TI1_Config(uint8_t TIM2_ICPolarity,
01215                        uint8_t TIM2_ICSelection,
01216                        uint8_t TIM2_ICFilter)
01217 {
01218     /* Disable the Channel 1: Reset the CCE Bit */
01219     TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1E);
01220
01221     /* Select the Input and set the filter */
01222     TIM2->CCMR1  = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~(uint8_t)( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF )))
01223                              | (uint8_t)(((TIM2_ICSelection)) | ((uint8_t)( TIM2_ICFilter << 4))));
01224
01225     /* Select the Polarity */
01226     if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
01227     {
01228         TIM2->CCER1 |= TIM2_CCER1_CC1P;
01229     }
01230     else
01231     {
01232         TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1P);
01233     }
01234     /* Set the CCE Bit */
01235     TIM2->CCER1 |= TIM2_CCER1_CC1E;
01236 }
01237
01238
01239 /**
01240   * @brief  Configure the TI2 as Input.
01241   * @param   TIM2_ICPolarity  The Input Polarity.
01242   * This parameter can be one of the following values:
01243   *                       - TIM2_ICPOLARITY_FALLING
01244   *                       - TIM2_ICPOLARITY_RISING
01245   * @param   TIM2_ICSelection specifies the input to be used.
01246   * This parameter can be one of the following values:
01247   *                       - TIM2_ICSELECTION_DIRECTTI: TIM2 Input 2 is selected to
01248   *                         be connected to IC2.
01249   *                       - TIM2_ICSELECTION_INDIRECTTI: TIM2 Input 2 is selected to
01250   *                         be connected to IC1.
01251   * @param   TIM2_ICFilter Specifies the Input Capture Filter.
01252   * This parameter must be a value between 0x00 and 0x0F.
01253   * @retval None
01254   */
01255 static void TI2_Config(uint8_t TIM2_ICPolarity,
01256                        uint8_t TIM2_ICSelection,
01257                        uint8_t TIM2_ICFilter)
01258 {
01259     /* Disable the Channel 2: Reset the CCE Bit */
01260     TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2E);
01261
01262     /* Select the Input and set the filter */
01263     TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~(uint8_t)( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF )))
01264                             | (uint8_t)(( (TIM2_ICSelection)) | ((uint8_t)( TIM2_ICFilter << 4))));
01265
01266
01267     /* Select the Polarity */
01268     if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
01269     {
01270         TIM2->CCER1 |= TIM2_CCER1_CC2P;
01271     }
01272     else
01273     {
01274         TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2P);
01275     }
01276
01277     /* Set the CCE Bit */
01278     TIM2->CCER1 |= TIM2_CCER1_CC2E;
01279
01280 }
01281
01282 /**
01283   * @brief  Configure the TI3 as Input.
01284   * @param   TIM2_ICPolarity  The Input Polarity.
01285   * This parameter can be one of the following values:
01286   *                       - TIM2_ICPOLARITY_FALLING
01287   *                       - TIM2_ICPOLARITY_RISING
01288   * @param   TIM2_ICSelection specifies the input to be used.
01289   * This parameter can be one of the following values:
01290   *                       - TIM2_ICSELECTION_DIRECTTI: TIM2 Input 3 is selected to
01291   *                         be connected to IC3.
01292   * @param   TIM2_ICFilter Specifies the Input Capture Filter.
01293   * This parameter must be a value between 0x00 and 0x0F.
01294   * @retval None
01295   */
01296 static void TI3_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection,
01297                        uint8_t TIM2_ICFilter)
01298 {
01299     /* Disable the Channel 3: Reset the CCE Bit */
01300     TIM2->CCER2 &=  (uint8_t)(~TIM2_CCER2_CC3E);
01301
01302     /* Select the Input and set the filter */
01303     TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF)))
01304                             | (uint8_t)(( (TIM2_ICSelection)) | ((uint8_t)( TIM2_ICFilter << 4))));
01305
01306
01307     /* Select the Polarity */
01308     if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
01309     {
01310         TIM2->CCER2 |= TIM2_CCER2_CC3P;
01311     }
01312     else
01313     {
01314         TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3P);
01315     }
01316     /* Set the CCE Bit */
01317     TIM2->CCER2 |= TIM2_CCER2_CC3E;
01318 }
01319 /**
01320   * @}
01321   */
01322
01323   /**
01324   * @}
01325   */
01326 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim2.h Source File

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stm8s_tim2.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim2.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the TIM2 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_TIM2_H
00024 #define __STM8S_TIM2_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /* Exported types ------------------------------------------------------------*/
00034
00035
00036 /** TIM2 Forced Action */
00037 typedef enum
00038 {
00039   TIM2_FORCEDACTION_ACTIVE           = ((uint8_t)0x50),
00040   TIM2_FORCEDACTION_INACTIVE         = ((uint8_t)0x40)
00041 }TIM2_ForcedAction_TypeDef;
00042
00043 #define IS_TIM2_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM2_FORCEDACTION_ACTIVE) || \
00044     ((ACTION) == TIM2_FORCEDACTION_INACTIVE))
00045
00046 /** TIM2 Prescaler */
00047 typedef enum
00048 {
00049   TIM2_PRESCALER_1  = ((uint8_t)0x00),
00050   TIM2_PRESCALER_2    = ((uint8_t)0x01),
00051   TIM2_PRESCALER_4    = ((uint8_t)0x02),
00052   TIM2_PRESCALER_8     = ((uint8_t)0x03),
00053   TIM2_PRESCALER_16   = ((uint8_t)0x04),
00054   TIM2_PRESCALER_32     = ((uint8_t)0x05),
00055   TIM2_PRESCALER_64    = ((uint8_t)0x06),
00056   TIM2_PRESCALER_128   = ((uint8_t)0x07),
00057   TIM2_PRESCALER_256   = ((uint8_t)0x08),
00058   TIM2_PRESCALER_512   = ((uint8_t)0x09),
00059   TIM2_PRESCALER_1024  = ((uint8_t)0x0A),
00060   TIM2_PRESCALER_2048 = ((uint8_t)0x0B),
00061   TIM2_PRESCALER_4096   = ((uint8_t)0x0C),
00062   TIM2_PRESCALER_8192 = ((uint8_t)0x0D),
00063   TIM2_PRESCALER_16384 = ((uint8_t)0x0E),
00064   TIM2_PRESCALER_32768 = ((uint8_t)0x0F)
00065 }TIM2_Prescaler_TypeDef;
00066
00067 #define IS_TIM2_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM2_PRESCALER_1  ) || \
00068     ((PRESCALER) == TIM2_PRESCALER_2    ) || \
00069     ((PRESCALER) == TIM2_PRESCALER_4    ) || \
00070     ((PRESCALER) == TIM2_PRESCALER_8  ) || \
00071     ((PRESCALER) == TIM2_PRESCALER_16   ) || \
00072     ((PRESCALER) == TIM2_PRESCALER_32     ) || \
00073     ((PRESCALER) == TIM2_PRESCALER_64    ) || \
00074     ((PRESCALER) == TIM2_PRESCALER_128   ) || \
00075     ((PRESCALER) == TIM2_PRESCALER_256   ) || \
00076     ((PRESCALER) == TIM2_PRESCALER_512   ) || \
00077     ((PRESCALER) == TIM2_PRESCALER_1024  ) || \
00078     ((PRESCALER) == TIM2_PRESCALER_2048 ) || \
00079     ((PRESCALER) == TIM2_PRESCALER_4096 ) || \
00080     ((PRESCALER) == TIM2_PRESCALER_8192 ) || \
00081     ((PRESCALER) == TIM2_PRESCALER_16384 ) || \
00082     ((PRESCALER) == TIM2_PRESCALER_32768 ))
00083
00084 /** TIM2 Output Compare and PWM modes */
00085 typedef enum
00086 {
00087   TIM2_OCMODE_TIMING     = ((uint8_t)0x00),
00088   TIM2_OCMODE_ACTIVE     = ((uint8_t)0x10),
00089   TIM2_OCMODE_INACTIVE   = ((uint8_t)0x20),
00090   TIM2_OCMODE_TOGGLE     = ((uint8_t)0x30),
00091   TIM2_OCMODE_PWM1       = ((uint8_t)0x60),
00092   TIM2_OCMODE_PWM2       = ((uint8_t)0x70)
00093 }TIM2_OCMode_TypeDef;
00094
00095 #define IS_TIM2_OC_MODE_OK(MODE) (((MODE) ==  TIM2_OCMODE_TIMING) || \
00096                                   ((MODE) == TIM2_OCMODE_ACTIVE) || \
00097                                   ((MODE) == TIM2_OCMODE_INACTIVE) || \
00098                                   ((MODE) == TIM2_OCMODE_TOGGLE)|| \
00099                                   ((MODE) == TIM2_OCMODE_PWM1) || \
00100                                   ((MODE) == TIM2_OCMODE_PWM2))
00101
00102 #define IS_TIM2_OCM_OK(MODE)(((MODE) ==  TIM2_OCMODE_TIMING) || \
00103                              ((MODE) == TIM2_OCMODE_ACTIVE) || \
00104                              ((MODE) == TIM2_OCMODE_INACTIVE) || \
00105                              ((MODE) == TIM2_OCMODE_TOGGLE)|| \
00106                              ((MODE) == TIM2_OCMODE_PWM1) || \
00107                              ((MODE) == TIM2_OCMODE_PWM2) || \
00108                              ((MODE) == (uint8_t)TIM2_FORCEDACTION_ACTIVE) || \
00109                              ((MODE) == (uint8_t)TIM2_FORCEDACTION_INACTIVE))
00110
00111 /** TIM2 One Pulse Mode */
00112 typedef enum
00113 {
00114   TIM2_OPMODE_SINGLE                 = ((uint8_t)0x01),
00115   TIM2_OPMODE_REPETITIVE             = ((uint8_t)0x00)
00116 }TIM2_OPMode_TypeDef;
00117
00118 #define IS_TIM2_OPM_MODE_OK(MODE) (((MODE) == TIM2_OPMODE_SINGLE) || \
00119                                    ((MODE) == TIM2_OPMODE_REPETITIVE))
00120
00121 /** TIM2 Channel */
00122 typedef enum
00123 {
00124   TIM2_CHANNEL_1                     = ((uint8_t)0x00),
00125   TIM2_CHANNEL_2                     = ((uint8_t)0x01),
00126   TIM2_CHANNEL_3                     = ((uint8_t)0x02)
00127 }TIM2_Channel_TypeDef;
00128
00129 #define IS_TIM2_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM2_CHANNEL_1) || \
00130                                      ((CHANNEL) == TIM2_CHANNEL_2) || \
00131                                      ((CHANNEL) == TIM2_CHANNEL_3))
00132
00133 #define IS_TIM2_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM2_CHANNEL_1) || \
00134     ((CHANNEL) == TIM2_CHANNEL_2))
00135
00136 /** TIM2 Output Compare Polarity */
00137 typedef enum
00138 {
00139   TIM2_OCPOLARITY_HIGH               = ((uint8_t)0x00),
00140   TIM2_OCPOLARITY_LOW                = ((uint8_t)0x22)
00141 }TIM2_OCPolarity_TypeDef;
00142
00143 #define IS_TIM2_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM2_OCPOLARITY_HIGH) || \
00144     ((POLARITY) == TIM2_OCPOLARITY_LOW))
00145
00146 /** TIM2 Output Compare states */
00147 typedef enum
00148 {
00149   TIM2_OUTPUTSTATE_DISABLE           = ((uint8_t)0x00),
00150   TIM2_OUTPUTSTATE_ENABLE            = ((uint8_t)0x11)
00151 }TIM2_OutputState_TypeDef;
00152
00153 #define IS_TIM2_OUTPUT_STATE_OK(STATE) (((STATE) == TIM2_OUTPUTSTATE_DISABLE) || \
00154                                         ((STATE) == TIM2_OUTPUTSTATE_ENABLE))
00155
00156 /** TIM2 Input Capture Polarity */
00157 typedef enum
00158 {
00159   TIM2_ICPOLARITY_RISING            = ((uint8_t)0x00),
00160   TIM2_ICPOLARITY_FALLING           = ((uint8_t)0x44)
00161 }TIM2_ICPolarity_TypeDef;
00162
00163 #define IS_TIM2_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM2_ICPOLARITY_RISING) || \
00164     ((POLARITY) == TIM2_ICPOLARITY_FALLING))
00165
00166 /** TIM2 Input Capture Selection */
00167 typedef enum
00168 {
00169   TIM2_ICSELECTION_DIRECTTI          = ((uint8_t)0x01),
00170   TIM2_ICSELECTION_INDIRECTTI        = ((uint8_t)0x02),
00171   TIM2_ICSELECTION_TRGI              = ((uint8_t)0x03)
00172 }TIM2_ICSelection_TypeDef;
00173
00174 #define IS_TIM2_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM2_ICSELECTION_DIRECTTI) || \
00175     ((SELECTION) == TIM2_ICSELECTION_INDIRECTTI) || \
00176     ((SELECTION) == TIM2_ICSELECTION_TRGI))
00177
00178 #define IS_TIM2_IC_SELECTION1_OK(SELECTION) (((SELECTION) == TIM2_ICSELECTION_DIRECTTI) || \
00179     ((SELECTION) == TIM2_ICSELECTION_TRGI))
00180
00181 /** TIM2 Input Capture Prescaler */
00182 typedef enum
00183 {
00184   TIM2_ICPSC_DIV1                    = ((uint8_t)0x00),
00185   TIM2_ICPSC_DIV2                    = ((uint8_t)0x04),
00186   TIM2_ICPSC_DIV4                    = ((uint8_t)0x08),
00187   TIM2_ICPSC_DIV8                    = ((uint8_t)0x0C)
00188 }TIM2_ICPSC_TypeDef;
00189
00190 #define IS_TIM2_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM2_ICPSC_DIV1) || \
00191     ((PRESCALER) == TIM2_ICPSC_DIV2) || \
00192     ((PRESCALER) == TIM2_ICPSC_DIV4) || \
00193     ((PRESCALER) == TIM2_ICPSC_DIV8))
00194
00195 /** TIM2 Input Capture Filer Value */
00196 #define IS_TIM2_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
00197
00198 /** TIM2 interrupt sources */
00199 typedef enum
00200 {
00201   TIM2_IT_UPDATE                     = ((uint8_t)0x01),
00202   TIM2_IT_CC1                        = ((uint8_t)0x02),
00203   TIM2_IT_CC2                        = ((uint8_t)0x04),
00204   TIM2_IT_CC3                        = ((uint8_t)0x08)
00205 }TIM2_IT_TypeDef;
00206
00207 #define IS_TIM2_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x0F))
00208
00209 #define IS_TIM2_GET_IT_OK(IT) (((IT) == TIM2_IT_UPDATE) || \
00210                                ((IT) == TIM2_IT_CC1) || \
00211                                ((IT) == TIM2_IT_CC2) || \
00212                                ((IT) == TIM2_IT_CC3))
00213
00214 /** TIM2 Prescaler Reload Mode */
00215 typedef enum
00216 {
00217   TIM2_PSCRELOADMODE_UPDATE          = ((uint8_t)0x00),
00218   TIM2_PSCRELOADMODE_IMMEDIATE       = ((uint8_t)0x01)
00219 }TIM2_PSCReloadMode_TypeDef;
00220
00221 #define IS_TIM2_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM2_PSCRELOADMODE_UPDATE) || \
00222     ((RELOAD) == TIM2_PSCRELOADMODE_IMMEDIATE))
00223
00224 /** TIM2 Event Source */
00225 typedef enum
00226 {
00227   TIM2_EVENTSOURCE_UPDATE            = ((uint8_t)0x01),
00228   TIM2_EVENTSOURCE_CC1               = ((uint8_t)0x02),
00229   TIM2_EVENTSOURCE_CC2               = ((uint8_t)0x04),
00230   TIM2_EVENTSOURCE_CC3               = ((uint8_t)0x08)
00231 }TIM2_EventSource_TypeDef;
00232
00233 #define IS_TIM2_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
00234
00235 /** TIM2 Update Source */
00236 typedef enum
00237 {
00238   TIM2_UPDATESOURCE_GLOBAL           = ((uint8_t)0x00),
00239   TIM2_UPDATESOURCE_REGULAR          = ((uint8_t)0x01)
00240 }TIM2_UpdateSource_TypeDef;
00241
00242 #define IS_TIM2_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM2_UPDATESOURCE_GLOBAL) || \
00243     ((SOURCE) == TIM2_UPDATESOURCE_REGULAR))
00244
00245 /** TIM2 Flags */
00246 typedef enum
00247 {
00248   TIM2_FLAG_UPDATE                   = ((uint16_t)0x0001),
00249   TIM2_FLAG_CC1                      = ((uint16_t)0x0002),
00250   TIM2_FLAG_CC2                      = ((uint16_t)0x0004),
00251   TIM2_FLAG_CC3                      = ((uint16_t)0x0008),
00252   TIM2_FLAG_CC1OF                    = ((uint16_t)0x0200),
00253   TIM2_FLAG_CC2OF                    = ((uint16_t)0x0400),
00254   TIM2_FLAG_CC3OF                    = ((uint16_t)0x0800)
00255 }TIM2_FLAG_TypeDef;
00256
00257 #define IS_TIM2_GET_FLAG_OK(FLAG) (((FLAG) == TIM2_FLAG_UPDATE) || \
00258                                    ((FLAG) == TIM2_FLAG_CC1) || \
00259                                    ((FLAG) == TIM2_FLAG_CC2) || \
00260                                    ((FLAG) == TIM2_FLAG_CC3) || \
00261                                    ((FLAG) == TIM2_FLAG_CC1OF) || \
00262                                    ((FLAG) == TIM2_FLAG_CC2OF) || \
00263                                    ((FLAG) == TIM2_FLAG_CC3OF))
00264
00265 #define IS_TIM2_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
00266
00267 /**
00268   * @}
00269   */
00270
00271 /* Exported macro ------------------------------------------------------------*/
00272
00273 /* Exported functions --------------------------------------------------------*/
00274
00275 /** @addtogroup TIM2_Exported_Functions
00276   * @{
00277   */
00278
00279 void TIM2_DeInit(void);
00280 void TIM2_TimeBaseInit(TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period);
00281 void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00282 void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00283 void TIM2_OC3Init(TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00284 void TIM2_ICInit(TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection,  TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter);
00285 void TIM2_PWMIConfig(TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection,  TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter);
00286 void TIM2_Cmd(FunctionalState NewState);
00287 void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState);
00288 void TIM2_InternalClockConfig(void);
00289 void TIM2_UpdateDisableConfig(FunctionalState NewState);
00290 void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource);
00291 void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode);
00292 void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode);
00293 void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
00294 void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
00295 void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
00296 void TIM2_ARRPreloadConfig(FunctionalState NewState);
00297 void TIM2_CCPreloadControl(FunctionalState NewState);
00298 void TIM2_OC1PreloadConfig(FunctionalState NewState);
00299 void TIM2_OC2PreloadConfig(FunctionalState NewState);
00300 void TIM2_OC3PreloadConfig(FunctionalState NewState);
00301 void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource);
00302 void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00303 void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00304 void TIM2_OC3PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
00305 void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState);
00306 void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode);
00307 void TIM2_SetCounter(uint16_t Counter);
00308 void TIM2_SetAutoreload(uint16_t Autoreload);
00309 void TIM2_SetCompare1(uint16_t Compare1);
00310 void TIM2_SetCompare2(uint16_t Compare2);
00311 void TIM2_SetCompare3(uint16_t Compare3);
00312 void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler);
00313 void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler);
00314 void TIM2_SetIC3Prescaler(TIM2_ICPSC_TypeDef TIM2_IC3Prescaler);
00315 uint16_t TIM2_GetCapture1(void);
00316 uint16_t TIM2_GetCapture2(void);
00317 uint16_t TIM2_GetCapture3(void);
00318 uint16_t TIM2_GetCounter(void);
00319 TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void);
00320 FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG);
00321 void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG);
00322 ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT);
00323 void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT);
00324
00325 /**
00326   * @}
00327   */
00328
00329 #endif /* __STM8S_TIM2_H */
00330
00331 /**
00332   * @}
00333   */
00334
00335 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim3.c Source File

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stm8s_tim3.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim3.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the TIM3 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_tim3.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 static void TI1_Config(uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter);
00034 static void TI2_Config(uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter);
00035 /**
00036   * @addtogroup TIM3_Public_Functions
00037   * @{
00038   */
00039
00040 /**
00041   * @brief  Deinitializes the TIM3 peripheral registers to their default reset values.
00042   * @param  None
00043   * @retval None
00044   */
00045 void TIM3_DeInit(void)
00046 {
00047
00048     TIM3->CR1 = (uint8_t)TIM3_CR1_RESET_VALUE;
00049     TIM3->IER = (uint8_t)TIM3_IER_RESET_VALUE;
00050     TIM3->SR2 = (uint8_t)TIM3_SR2_RESET_VALUE;
00051
00052     /* Disable channels */
00053     TIM3->CCER1 = (uint8_t)TIM3_CCER1_RESET_VALUE;
00054
00055     /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
00056     TIM3->CCER1 = (uint8_t)TIM3_CCER1_RESET_VALUE;
00057     TIM3->CCMR1 = (uint8_t)TIM3_CCMR1_RESET_VALUE;
00058     TIM3->CCMR2 = (uint8_t)TIM3_CCMR2_RESET_VALUE;
00059     TIM3->CNTRH = (uint8_t)TIM3_CNTRH_RESET_VALUE;
00060     TIM3->CNTRL = (uint8_t)TIM3_CNTRL_RESET_VALUE;
00061     TIM3->PSCR = (uint8_t)TIM3_PSCR_RESET_VALUE;
00062     TIM3->ARRH  = (uint8_t)TIM3_ARRH_RESET_VALUE;
00063     TIM3->ARRL  = (uint8_t)TIM3_ARRL_RESET_VALUE;
00064     TIM3->CCR1H = (uint8_t)TIM3_CCR1H_RESET_VALUE;
00065     TIM3->CCR1L = (uint8_t)TIM3_CCR1L_RESET_VALUE;
00066     TIM3->CCR2H = (uint8_t)TIM3_CCR2H_RESET_VALUE;
00067     TIM3->CCR2L = (uint8_t)TIM3_CCR2L_RESET_VALUE;
00068     TIM3->SR1 = (uint8_t)TIM3_SR1_RESET_VALUE;
00069 }
00070
00071
00072 /**
00073   * @brief  Initializes the TIM3 Time Base Unit according to the specified parameters.
00074   * @param    TIM3_Prescaler specifies the Prescaler from TIM3_Prescaler_TypeDef.
00075   * @param    TIM3_Period specifies the Period value.
00076   * @retval None
00077   */
00078 void TIM3_TimeBaseInit( TIM3_Prescaler_TypeDef TIM3_Prescaler,
00079                         uint16_t TIM3_Period)
00080 {
00081     /* Set the Prescaler value */
00082     TIM3->PSCR = (uint8_t)(TIM3_Prescaler);
00083     /* Set the Autoreload value */
00084     TIM3->ARRH = (uint8_t)(TIM3_Period >> 8);
00085     TIM3->ARRL = (uint8_t)(TIM3_Period);
00086 }
00087
00088 /**
00089   * @brief  Initializes the TIM3 Channel1 according to the specified parameters.
00090   * @param   TIM3_OCMode specifies the Output Compare mode  from @ref TIM3_OCMode_TypeDef.
00091   * @param   TIM3_OutputState specifies the Output State  from @ref TIM3_OutputState_TypeDef.
00092   * @param   TIM3_Pulse specifies the Pulse width  value.
00093   * @param   TIM3_OCPolarity specifies the Output Compare Polarity  from @ref TIM3_OCPolarity_TypeDef.
00094   * @retval None
00095   */
00096 void TIM3_OC1Init(TIM3_OCMode_TypeDef TIM3_OCMode,
00097                   TIM3_OutputState_TypeDef TIM3_OutputState,
00098                   uint16_t TIM3_Pulse,
00099                   TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
00100 {
00101     /* Check the parameters */
00102     assert_param(IS_TIM3_OC_MODE_OK(TIM3_OCMode));
00103     assert_param(IS_TIM3_OUTPUT_STATE_OK(TIM3_OutputState));
00104     assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
00105
00106     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */
00107     TIM3->CCER1 &= (uint8_t)(~( TIM3_CCER1_CC1E | TIM3_CCER1_CC1P));
00108     /* Set the Output State &  Set the Output Polarity  */
00109     TIM3->CCER1 |= (uint8_t)((uint8_t)(TIM3_OutputState  & TIM3_CCER1_CC1E   ) | (uint8_t)(TIM3_OCPolarity   & TIM3_CCER1_CC1P   ));
00110
00111     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00112     TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);
00113
00114     /* Set the Pulse value */
00115     TIM3->CCR1H = (uint8_t)(TIM3_Pulse >> 8);
00116     TIM3->CCR1L = (uint8_t)(TIM3_Pulse);
00117 }
00118
00119
00120 /**
00121   * @brief  Initializes the TIM3 Channel2 according to the specified parameters.
00122   * @param   TIM3_OCMode specifies the Output Compare mode  from @ref TIM3_OCMode_TypeDef.
00123   * @param   TIM3_OutputState specifies the Output State  from @ref TIM3_OutputState_TypeDef.
00124   * @param   TIM3_Pulse specifies the Pulse width  value.
00125   * @param   TIM3_OCPolarity specifies the Output Compare Polarity  from @ref TIM3_OCPolarity_TypeDef.
00126   * @retval None
00127   */
00128 void TIM3_OC2Init(TIM3_OCMode_TypeDef TIM3_OCMode,
00129                   TIM3_OutputState_TypeDef TIM3_OutputState,
00130                   uint16_t TIM3_Pulse,
00131                   TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
00132 {
00133     /* Check the parameters */
00134     assert_param(IS_TIM3_OC_MODE_OK(TIM3_OCMode));
00135     assert_param(IS_TIM3_OUTPUT_STATE_OK(TIM3_OutputState));
00136     assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
00137
00138
00139     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */
00140     TIM3->CCER1 &= (uint8_t)(~( TIM3_CCER1_CC2E |  TIM3_CCER1_CC2P ));
00141     /* Set the Output State & Set the Output Polarity */
00142     TIM3->CCER1 |= (uint8_t)((uint8_t)(TIM3_OutputState  & TIM3_CCER1_CC2E   ) | (uint8_t)(TIM3_OCPolarity   & TIM3_CCER1_CC2P ));
00143
00144
00145     /* Reset the Output Compare Bits & Set the Output Compare Mode */
00146     TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);
00147
00148
00149     /* Set the Pulse value */
00150     TIM3->CCR2H = (uint8_t)(TIM3_Pulse >> 8);
00151     TIM3->CCR2L = (uint8_t)(TIM3_Pulse);
00152 }
00153
00154 /**
00155   * @brief  Initializes the TIM3 peripheral according to the specified parameters.
00156   * @param    TIM3_Channel specifies the Input Capture Channel from @ref TIM3_Channel_TypeDef.
00157   * @param   TIM3_ICPolarity specifies the Input Capture Polarity from @ref TIM3_ICPolarity_TypeDef.
00158   * @param   TIM3_ICSelection specifies the Input Capture Selection from @ref TIM3_ICSelection_TypeDef.
00159   * @param   TIM3_ICPrescaler specifies the Input Capture Prescaler from @ref TIM3_ICPSC_TypeDef.
00160   * @param   TIM3_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00161   * @retval None
00162   */
00163 void TIM3_ICInit(TIM3_Channel_TypeDef TIM3_Channel,
00164                  TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
00165                  TIM3_ICSelection_TypeDef TIM3_ICSelection,
00166                  TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
00167                  uint8_t TIM3_ICFilter)
00168 {
00169     /* Check the parameters */
00170     assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
00171     assert_param(IS_TIM3_IC_POLARITY_OK(TIM3_ICPolarity));
00172     assert_param(IS_TIM3_IC_SELECTION_OK(TIM3_ICSelection));
00173     assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_ICPrescaler));
00174     assert_param(IS_TIM3_IC_FILTER_OK(TIM3_ICFilter));
00175
00176     if (TIM3_Channel != TIM3_CHANNEL_2)
00177     {
00178         /* TI1 Configuration */
00179         TI1_Config((uint8_t)TIM3_ICPolarity,
00180                    (uint8_t)TIM3_ICSelection,
00181                    (uint8_t)TIM3_ICFilter);
00182
00183         /* Set the Input Capture Prescaler value */
00184         TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
00185     }
00186     else
00187     {
00188         /* TI2 Configuration */
00189         TI2_Config((uint8_t)TIM3_ICPolarity,
00190                    (uint8_t)TIM3_ICSelection,
00191                    (uint8_t)TIM3_ICFilter);
00192
00193         /* Set the Input Capture Prescaler value */
00194         TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
00195     }
00196 }
00197 /**
00198   * @brief  Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.
00199   * @param    TIM3_Channel specifies the Input Capture Channel from @ref TIM3_Channel_TypeDef.
00200   * @param   TIM3_ICPolarity specifies the Input Capture Polarity from @ref TIM3_ICPolarity_TypeDef.
00201   * @param   TIM3_ICSelection specifies the Input Capture Selection from @ref TIM3_ICSelection_TypeDef.
00202   * @param   TIM3_ICPrescaler specifies the Input Capture Prescaler from @ref TIM3_ICPSC_TypeDef.
00203   * @param   TIM3_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00204   * @retval None
00205   */
00206 void TIM3_PWMIConfig(TIM3_Channel_TypeDef TIM3_Channel,
00207                      TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
00208                      TIM3_ICSelection_TypeDef TIM3_ICSelection,
00209                      TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
00210                      uint8_t TIM3_ICFilter)
00211 {
00212     uint8_t icpolarity = (uint8_t)TIM3_ICPOLARITY_RISING;
00213     uint8_t icselection = (uint8_t)TIM3_ICSELECTION_DIRECTTI;
00214
00215     /* Check the parameters */
00216     assert_param(IS_TIM3_PWMI_CHANNEL_OK(TIM3_Channel));
00217     assert_param(IS_TIM3_IC_POLARITY_OK(TIM3_ICPolarity));
00218     assert_param(IS_TIM3_IC_SELECTION_OK(TIM3_ICSelection));
00219     assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_ICPrescaler));
00220
00221     /* Select the Opposite Input Polarity */
00222     if (TIM3_ICPolarity != TIM3_ICPOLARITY_FALLING)
00223     {
00224         icpolarity = (uint8_t)TIM3_ICPOLARITY_FALLING;
00225     }
00226     else
00227     {
00228         icpolarity = (uint8_t)TIM3_ICPOLARITY_RISING;
00229     }
00230
00231     /* Select the Opposite Input */
00232     if (TIM3_ICSelection == TIM3_ICSELECTION_DIRECTTI)
00233     {
00234         icselection = (uint8_t)TIM3_ICSELECTION_INDIRECTTI;
00235     }
00236     else
00237     {
00238         icselection = (uint8_t)TIM3_ICSELECTION_DIRECTTI;
00239     }
00240
00241     if (TIM3_Channel != TIM3_CHANNEL_2)
00242     {
00243         /* TI1 Configuration */
00244         TI1_Config((uint8_t)TIM3_ICPolarity, (uint8_t)TIM3_ICSelection,
00245                    (uint8_t)TIM3_ICFilter);
00246
00247         /* Set the Input Capture Prescaler value */
00248         TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
00249
00250         /* TI2 Configuration */
00251         TI2_Config(icpolarity, icselection, TIM3_ICFilter);
00252
00253         /* Set the Input Capture Prescaler value */
00254         TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
00255     }
00256     else
00257     {
00258         /* TI2 Configuration */
00259         TI2_Config((uint8_t)TIM3_ICPolarity, (uint8_t)TIM3_ICSelection,
00260                    (uint8_t)TIM3_ICFilter);
00261
00262         /* Set the Input Capture Prescaler value */
00263         TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
00264
00265         /* TI1 Configuration */
00266         TI1_Config(icpolarity, icselection, TIM3_ICFilter);
00267
00268         /* Set the Input Capture Prescaler value */
00269         TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
00270     }
00271 }
00272
00273
00274 /**
00275   * @brief  Enables or disables the TIM3 peripheral.
00276   * @param   NewState new state of the TIM3 peripheral. This parameter can
00277   * be ENABLE or DISABLE.
00278   * @retval None
00279   */
00280 void TIM3_Cmd(FunctionalState NewState)
00281 {
00282     /* Check the parameters */
00283     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00284
00285     /* set or Reset the CEN Bit */
00286     if (NewState != DISABLE)
00287     {
00288         TIM3->CR1 |= (uint8_t)TIM3_CR1_CEN;
00289     }
00290     else
00291     {
00292         TIM3->CR1 &= (uint8_t)(~TIM3_CR1_CEN);
00293     }
00294 }
00295
00296
00297 /**
00298   * @brief  Enables or disables the specified TIM3 interrupts.
00299   * @param   NewState new state of the TIM3 peripheral.
00300   * This parameter can be: ENABLE or DISABLE.
00301   * @param   TIM3_IT specifies the TIM3 interrupts sources to be enabled or disabled.
00302   * This parameter can be any combination of the following values:
00303   *                       - TIM3_IT_UPDATE: TIM3 update Interrupt source
00304   *                       - TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
00305   *                       - TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
00306   *                       - TIM3_IT_CC3: TIM3 Capture Compare 3 Interrupt source
00307   * @param   NewState new state of the TIM3 peripheral.  * @retval None
00308   */
00309 void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
00310 {
00311     /* Check the parameters */
00312     assert_param(IS_TIM3_IT_OK(TIM3_IT));
00313     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00314
00315     if (NewState != DISABLE)
00316     {
00317         /* Enable the Interrupt sources */
00318         TIM3->IER |= (uint8_t)TIM3_IT;
00319     }
00320     else
00321     {
00322         /* Disable the Interrupt sources */
00323         TIM3->IER &= (uint8_t)(~TIM3_IT);
00324     }
00325 }
00326
00327
00328 /**
00329   * @brief  Enables or Disables the TIM3 Update event.
00330   * @param   NewState new state of the TIM3 peripheral Preload register. This parameter can
00331   * be ENABLE or DISABLE.
00332   * @retval None
00333   */
00334 void TIM3_UpdateDisableConfig(FunctionalState NewState)
00335 {
00336     /* Check the parameters */
00337     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00338
00339     /* Set or Reset the UDIS Bit */
00340     if (NewState != DISABLE)
00341     {
00342         TIM3->CR1 |= TIM3_CR1_UDIS;
00343     }
00344     else
00345     {
00346         TIM3->CR1 &= (uint8_t)(~TIM3_CR1_UDIS);
00347     }
00348 }
00349
00350 /**
00351   * @brief  Selects the TIM3 Update Request Interrupt source.
00352   * @param   TIM3_UpdateSource specifies the Update source.
00353   * This parameter can be one of the following values
00354   *                       - TIM3_UPDATESOURCE_REGULAR
00355   *                       - TIM3_UPDATESOURCE_GLOBAL
00356   * @retval None
00357   */
00358 void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
00359 {
00360     /* Check the parameters */
00361     assert_param(IS_TIM3_UPDATE_SOURCE_OK(TIM3_UpdateSource));
00362
00363     /* Set or Reset the URS Bit */
00364     if (TIM3_UpdateSource != TIM3_UPDATESOURCE_GLOBAL)
00365     {
00366         TIM3->CR1 |= TIM3_CR1_URS;
00367     }
00368     else
00369     {
00370         TIM3->CR1 &= (uint8_t)(~TIM3_CR1_URS);
00371     }
00372 }
00373
00374
00375 /**
00376   * @brief  Selects the TIM3’s One Pulse Mode.
00377   * @param   TIM3_OPMode specifies the OPM Mode to be used.
00378   * This parameter can be one of the following values
00379   *                    - TIM3_OPMODE_SINGLE
00380   *                    - TIM3_OPMODE_REPETITIVE
00381   * @retval None
00382   */
00383 void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode)
00384 {
00385     /* Check the parameters */
00386     assert_param(IS_TIM3_OPM_MODE_OK(TIM3_OPMode));
00387
00388     /* Set or Reset the OPM Bit */
00389     if (TIM3_OPMode != TIM3_OPMODE_REPETITIVE)
00390     {
00391         TIM3->CR1 |= TIM3_CR1_OPM;
00392     }
00393     else
00394     {
00395         TIM3->CR1 &= (uint8_t)(~TIM3_CR1_OPM);
00396     }
00397
00398 }
00399
00400
00401 /**
00402   * @brief  Configures the TIM3 Prescaler.
00403   * @param   Prescaler specifies the Prescaler Register value
00404   * This parameter can be one of the following values
00405   *                       -  TIM3_PRESCALER_1
00406   *                       -  TIM3_PRESCALER_2
00407   *                       -  TIM3_PRESCALER_4
00408   *                       -  TIM3_PRESCALER_8
00409   *                       -  TIM3_PRESCALER_16
00410   *                       -  TIM3_PRESCALER_32
00411   *                       -  TIM3_PRESCALER_64
00412   *                       -  TIM3_PRESCALER_128
00413   *                       -  TIM3_PRESCALER_256
00414   *                       -  TIM3_PRESCALER_512
00415   *                       -  TIM3_PRESCALER_1024
00416   *                       -  TIM3_PRESCALER_2048
00417   *                       -  TIM3_PRESCALER_4096
00418   *                       -  TIM3_PRESCALER_8192
00419   *                       -  TIM3_PRESCALER_16384
00420   *                       -  TIM3_PRESCALER_32768
00421   * @param   TIM3_PSCReloadMode specifies the TIM3 Prescaler Reload mode.
00422   * This parameter can be one of the following values
00423   *                       - TIM3_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
00424   *                         immediatly.
00425   *                       - TIM3_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
00426   *                         the update event.
00427   * @retval None
00428   */
00429 void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
00430                           TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
00431 {
00432     /* Check the parameters */
00433     assert_param(IS_TIM3_PRESCALER_RELOAD_OK(TIM3_PSCReloadMode));
00434     assert_param(IS_TIM3_PRESCALER_OK(Prescaler));
00435
00436     /* Set the Prescaler value */
00437     TIM3->PSCR = (uint8_t)Prescaler;
00438
00439     /* Set or reset the UG Bit */
00440     TIM3->EGR = (uint8_t)TIM3_PSCReloadMode;
00441 }
00442
00443 /**
00444   * @brief  Forces the TIM3 Channel1 output waveform to active or inactive level.
00445   * @param   TIM3_ForcedAction specifies the forced Action to be set to the output waveform.
00446   * This parameter can be one of the following values:
00447   *                       - TIM3_FORCEDACTION_ACTIVE: Force active level on OC1REF
00448   *                       - TIM3_FORCEDACTION_INACTIVE: Force inactive level on
00449   *                         OC1REF.
00450   * @retval None
00451   */
00452 void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
00453 {
00454     /* Check the parameters */
00455     assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
00456
00457     /* Reset the OCM Bits & Configure the Forced output Mode */
00458     TIM3->CCMR1 =  (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_OCM))  | (uint8_t)TIM3_ForcedAction);
00459 }
00460
00461 /**
00462   * @brief  Forces the TIM3 Channel2 output waveform to active or inactive level.
00463   * @param   TIM3_ForcedAction specifies the forced Action to be set to the output waveform.
00464   * This parameter can be one of the following values:
00465   *                       - TIM3_FORCEDACTION_ACTIVE: Force active level on OC2REF
00466   *                       - TIM3_FORCEDACTION_INACTIVE: Force inactive level on
00467   *                         OC2REF.
00468   * @retval None
00469   */
00470 void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
00471 {
00472     /* Check the parameters */
00473     assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
00474
00475     /* Reset the OCM Bits & Configure the Forced output Mode */
00476     TIM3->CCMR2 =  (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_ForcedAction);
00477 }
00478
00479
00480 /**
00481   * @brief  Enables or disables TIM3 peripheral Preload register on ARR.
00482   * @param   NewState new state of the TIM3 peripheral Preload register.
00483   * This parameter can be ENABLE or DISABLE.
00484   * @retval None
00485   */
00486 void TIM3_ARRPreloadConfig(FunctionalState NewState)
00487 {
00488     /* Check the parameters */
00489     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00490
00491     /* Set or Reset the ARPE Bit */
00492     if (NewState != DISABLE)
00493     {
00494         TIM3->CR1 |= TIM3_CR1_ARPE;
00495     }
00496     else
00497     {
00498         TIM3->CR1 &= (uint8_t)(~TIM3_CR1_ARPE);
00499     }
00500 }
00501
00502
00503 /**
00504   * @brief  Enables or disables the TIM3 peripheral Preload Register on CCR1.
00505   * @param   NewState new state of the Capture Compare Preload register.
00506   * This parameter can be ENABLE or DISABLE.
00507   * @retval None
00508   */
00509 void TIM3_OC1PreloadConfig(FunctionalState NewState)
00510 {
00511     /* Check the parameters */
00512     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00513
00514     /* Set or Reset the OC1PE Bit */
00515     if (NewState != DISABLE)
00516     {
00517         TIM3->CCMR1 |= TIM3_CCMR_OCxPE;
00518     }
00519     else
00520     {
00521         TIM3->CCMR1 &= (uint8_t)(~TIM3_CCMR_OCxPE);
00522     }
00523 }
00524
00525
00526 /**
00527   * @brief  Enables or disables the TIM3 peripheral Preload Register on CCR2.
00528   * @param   NewState new state of the Capture Compare Preload register.
00529   * This parameter can be ENABLE or DISABLE.
00530   * @retval None
00531   */
00532 void TIM3_OC2PreloadConfig(FunctionalState NewState)
00533 {
00534     /* Check the parameters */
00535     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00536
00537     /* Set or Reset the OC2PE Bit */
00538     if (NewState != DISABLE)
00539     {
00540         TIM3->CCMR2 |= TIM3_CCMR_OCxPE;
00541     }
00542     else
00543     {
00544         TIM3->CCMR2 &= (uint8_t)(~TIM3_CCMR_OCxPE);
00545     }
00546 }
00547
00548 /**
00549   * @brief  Configures the TIM3 event to be generated by software.
00550   * @param   TIM3_EventSource specifies the event source.
00551   * This parameter can be one of the following values:
00552   *                       - TIM3_EVENTSOURCE_UPDATE: TIM3 update Event source
00553   *                       - TIM3_EVENTSOURCE_CC1: TIM3 Capture Compare 1 Event source
00554   *                       - TIM3_EVENTSOURCE_CC2: TIM3 Capture Compare 2 Event source
00555   * @retval None
00556   */
00557 void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource)
00558 {
00559     /* Check the parameters */
00560     assert_param(IS_TIM3_EVENT_SOURCE_OK(TIM3_EventSource));
00561
00562     /* Set the event sources */
00563     TIM3->EGR = (uint8_t)TIM3_EventSource;
00564 }
00565
00566
00567 /**
00568   * @brief  Configures the TIM3 Channel 1 polarity.
00569   * @param   TIM3_OCPolarity specifies the OC1 Polarity.
00570   * This parameter can be one of the following values:
00571   *                       - TIM3_OCPOLARITY_LOW: Output Compare active low
00572   *                       - TIM3_OCPOLARITY_HIGH: Output Compare active high
00573   * @retval None
00574   */
00575 void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
00576 {
00577     /* Check the parameters */
00578     assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
00579
00580     /* Set or Reset the CC1P Bit */
00581     if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
00582     {
00583         TIM3->CCER1 |= TIM3_CCER1_CC1P;
00584     }
00585     else
00586     {
00587         TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1P);
00588     }
00589 }
00590
00591
00592 /**
00593   * @brief  Configures the TIM3 Channel 2 polarity.
00594   * @param   TIM3_OCPolarity specifies the OC2 Polarity.
00595   * This parameter can be one of the following values:
00596   *                       - TIM3_OCPOLARITY_LOW: Output Compare active low
00597   *                       - TIM3_OCPOLARITY_HIGH: Output Compare active high
00598   * @retval None
00599   */
00600 void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
00601 {
00602     /* Check the parameters */
00603     assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
00604
00605     /* Set or Reset the CC2P Bit */
00606     if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
00607     {
00608         TIM3->CCER1 |= TIM3_CCER1_CC2P;
00609     }
00610     else
00611     {
00612         TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2P);
00613     }
00614 }
00615
00616
00617 /**
00618   * @brief  Enables or disables the TIM3 Capture Compare Channel x.
00619   * @param   TIM3_Channel specifies the TIM3 Channel.
00620   * This parameter can be one of the following values:
00621   *                       - TIM3_CHANNEL_1: TIM3 Channel1
00622   *                       - TIM3_CHANNEL_2: TIM3 Channel2
00623   * @param   NewState specifies the TIM3 Channel CCxE bit new state.
00624   * This parameter can be: ENABLE or DISABLE.
00625   * @retval None
00626   */
00627 void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
00628 {
00629     /* Check the parameters */
00630     assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
00631     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00632
00633     if (TIM3_Channel == TIM3_CHANNEL_1)
00634     {
00635         /* Set or Reset the CC1E Bit */
00636         if (NewState != DISABLE)
00637         {
00638             TIM3->CCER1 |= TIM3_CCER1_CC1E;
00639         }
00640         else
00641         {
00642             TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1E);
00643         }
00644
00645     }
00646     else
00647     {
00648         /* Set or Reset the CC2E Bit */
00649         if (NewState != DISABLE)
00650         {
00651             TIM3->CCER1 |= TIM3_CCER1_CC2E;
00652         }
00653         else
00654         {
00655             TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2E);
00656         }
00657     }
00658
00659 }
00660
00661 /**
00662   * @brief  Selects the TIM3 Output Compare Mode. This function disables the
00663   * selected channel before changing the Output Compare Mode. User has to
00664   * enable this channel using TIM3_CCxCmd and TIM3_CCxNCmd functions.
00665   * @param   TIM3_Channel specifies the TIM3 Channel.
00666   * This parameter can be one of the following values:
00667   *                       - TIM3_CHANNEL_1: TIM3 Channel1
00668   *                       - TIM3_CHANNEL_2: TIM3 Channel2
00669   * @param   TIM3_OCMode specifies the TIM3 Output Compare Mode.
00670   * This paramter can be one of the following values:
00671   *                       - TIM3_OCMODE_TIMING
00672   *                       - TIM3_OCMODE_ACTIVE
00673   *                       - TIM3_OCMODE_TOGGLE
00674   *                       - TIM3_OCMODE_PWM1
00675   *                       - TIM3_OCMODE_PWM2
00676   *                       - TIM3_FORCEDACTION_ACTIVE
00677   *                       - TIM3_FORCEDACTION_INACTIVE
00678   * @retval None
00679   */
00680 void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
00681 {
00682     /* Check the parameters */
00683     assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
00684     assert_param(IS_TIM3_OCM_OK(TIM3_OCMode));
00685
00686     if (TIM3_Channel == TIM3_CHANNEL_1)
00687     {
00688         /* Disable the Channel 1: Reset the CCE Bit */
00689         TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1E);
00690
00691         /* Reset the Output Compare Bits & Set the Output Compare Mode */
00692         TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);
00693     }
00694     else
00695     {
00696         /* Disable the Channel 2: Reset the CCE Bit */
00697         TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2E);
00698
00699         /* Reset the Output Compare Bits & Set the Output Compare Mode */
00700         TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);
00701     }
00702 }
00703
00704
00705 /**
00706   * @brief  Sets the TIM3 Counter Register value.
00707   * @param   Counter specifies the Counter register new value.
00708   * This parameter is between 0x0000 and 0xFFFF.
00709   * @retval None
00710   */
00711 void TIM3_SetCounter(uint16_t Counter)
00712 {
00713     /* Set the Counter Register value */
00714     TIM3->CNTRH = (uint8_t)(Counter >> 8);
00715     TIM3->CNTRL = (uint8_t)(Counter);
00716
00717 }
00718
00719
00720 /**
00721   * @brief  Sets the TIM3 Autoreload Register value.
00722   * @param   Autoreload specifies the Autoreload register new value.
00723   * This parameter is between 0x0000 and 0xFFFF.
00724   * @retval None
00725   */
00726 void TIM3_SetAutoreload(uint16_t Autoreload)
00727 {
00728     /* Set the Autoreload Register value */
00729     TIM3->ARRH = (uint8_t)(Autoreload >> 8);
00730     TIM3->ARRL = (uint8_t)(Autoreload);
00731 }
00732
00733
00734 /**
00735   * @brief  Sets the TIM3 Capture Compare1 Register value.
00736   * @param   Compare1 specifies the Capture Compare1 register new value.
00737   * This parameter is between 0x0000 and 0xFFFF.
00738   * @retval None
00739   */
00740 void TIM3_SetCompare1(uint16_t Compare1)
00741 {
00742     /* Set the Capture Compare1 Register value */
00743     TIM3->CCR1H = (uint8_t)(Compare1 >> 8);
00744     TIM3->CCR1L = (uint8_t)(Compare1);
00745 }
00746
00747
00748 /**
00749   * @brief  Sets the TIM3 Capture Compare2 Register value.
00750   * @param   Compare2 specifies the Capture Compare2 register new value.
00751   * This parameter is between 0x0000 and 0xFFFF.
00752   * @retval None
00753   */
00754 void TIM3_SetCompare2(uint16_t Compare2)
00755 {
00756     /* Set the Capture Compare2 Register value */
00757     TIM3->CCR2H = (uint8_t)(Compare2 >> 8);
00758     TIM3->CCR2L = (uint8_t)(Compare2);
00759 }
00760
00761
00762 /**
00763   * @brief  Sets the TIM3 Input Capture 1 prescaler.
00764   * @param   TIM3_IC1Prescaler specifies the Input Capture prescaler new value
00765   * This parameter can be one of the following values:
00766   *                       - TIM3_ICPSC_DIV1: no prescaler
00767   *                       - TIM3_ICPSC_DIV2: capture is done once every 2 events
00768   *                       - TIM3_ICPSC_DIV4: capture is done once every 4 events
00769   *                       - TIM3_ICPSC_DIV8: capture is done once every 8 events
00770   * @retval None
00771   */
00772 void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
00773 {
00774     /* Check the parameters */
00775     assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_IC1Prescaler));
00776
00777     /* Reset the IC1PSC Bits & Set the IC1PSC value */
00778     TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_ICxPSC)) | (uint8_t)TIM3_IC1Prescaler);
00779 }
00780
00781 /**
00782   * @brief  Sets the TIM3 Input Capture 2 prescaler.
00783   * @param   TIM3_IC2Prescaler specifies the Input Capture prescaler new value
00784   * This parameter can be one of the following values:
00785   *                       - TIM3_ICPSC_DIV1: no prescaler
00786   *                       - TIM3_ICPSC_DIV2: capture is done once every 2 events
00787   *                       - TIM3_ICPSC_DIV4: capture is done once every 4 events
00788   *                       - TIM3_ICPSC_DIV8: capture is done once every 8 events
00789   * @retval None
00790   */
00791 void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
00792 {
00793     /* Check the parameters */
00794     assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_IC2Prescaler));
00795
00796     /* Reset the IC1PSC Bits & Set the IC1PSC value */
00797     TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_ICxPSC)) | (uint8_t)TIM3_IC2Prescaler);
00798 }
00799 /**
00800   * @brief  Gets the TIM3 Input Capture 1 value.
00801   * @param  None
00802   * @retval Capture Compare 1 Register value.
00803   */
00804 uint16_t TIM3_GetCapture1(void)
00805 {
00806     /* Get the Capture 1 Register value */
00807     uint16_t tmpccr1 = 0;
00808     uint8_t tmpccr1l=0, tmpccr1h=0;
00809
00810     tmpccr1h = TIM3->CCR1H;
00811     tmpccr1l = TIM3->CCR1L;
00812
00813     tmpccr1 = (uint16_t)(tmpccr1l);
00814     tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
00815     /* Get the Capture 1 Register value */
00816     return (uint16_t)tmpccr1;
00817 }
00818
00819 /**
00820   * @brief  Gets the TIM3 Input Capture 2 value.
00821   * @param  None
00822   * @retval Capture Compare 2 Register value.
00823   */
00824 uint16_t TIM3_GetCapture2(void)
00825 {
00826     /* Get the Capture 2 Register value */
00827     uint16_t tmpccr2 = 0;
00828     uint8_t tmpccr2l=0, tmpccr2h=0;
00829
00830     tmpccr2h = TIM3->CCR2H;
00831     tmpccr2l = TIM3->CCR2L;
00832
00833     tmpccr2 = (uint16_t)(tmpccr2l);
00834     tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
00835     /* Get the Capture 2 Register value */
00836     return (uint16_t)tmpccr2;
00837 }
00838
00839 /**
00840   * @brief  Gets the TIM3 Counter value.
00841   * @param  None
00842   * @retval Counter Register value.
00843   */
00844 uint16_t TIM3_GetCounter(void)
00845 {
00846    uint16_t tmpcntr = 0;
00847
00848    tmpcntr = ((uint16_t)TIM3->CNTRH << 8);
00849    /* Get the Counter Register value */
00850     return (uint16_t)( tmpcntr| (uint16_t)(TIM3->CNTRL));
00851 }
00852
00853
00854 /**
00855   * @brief  Gets the TIM3 Prescaler value.
00856   * @param  None
00857   * @retval Prescaler Register configuration value @ref TIM3_Prescaler_TypeDef.
00858   */
00859 TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void)
00860 {
00861     /* Get the Prescaler Register value */
00862     return (TIM3_Prescaler_TypeDef)(TIM3->PSCR);
00863 }
00864
00865
00866 /**
00867   * @brief  Checks whether the specified TIM3 flag is set or not.
00868   * @param   TIM3_FLAG specifies the flag to check.
00869   * This parameter can be one of the following values:
00870   *                       - TIM3_FLAG_UPDATE: TIM3 update Flag
00871   *                       - TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
00872   *                       - TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
00873   *                       - TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
00874   *                       - TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
00875   * @retval FlagStatus The new state of TIM3_FLAG (SET or RESET).
00876   */
00877 FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG)
00878 {
00879    FlagStatus bitstatus = RESET;
00880    uint8_t tim3_flag_l = 0, tim3_flag_h = 0;
00881
00882     /* Check the parameters */
00883     assert_param(IS_TIM3_GET_FLAG_OK(TIM3_FLAG));
00884
00885     tim3_flag_l = (uint8_t)(TIM3->SR1 & (uint8_t)TIM3_FLAG);
00886     tim3_flag_h = (uint8_t)((uint16_t)TIM3_FLAG >> 8);
00887
00888     if (((tim3_flag_l) | (uint8_t)(TIM3->SR2 & tim3_flag_h)) != (uint8_t)RESET )
00889     {
00890         bitstatus = SET;
00891     }
00892     else
00893     {
00894         bitstatus = RESET;
00895     }
00896     return (FlagStatus)bitstatus;
00897 }
00898
00899
00900 /**
00901   * @brief  Clears the TIM3’s pending flags.
00902   * @param   TIM3_FLAG specifies the flag to clear.
00903   * This parameter can be one of the following values:
00904   *                       - TIM3_FLAG_UPDATE: TIM3 update Flag
00905   *                       - TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag
00906   *                       - TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag
00907   *                       - TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag
00908   *                       - TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag
00909   * @retval None.
00910   */
00911 void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG)
00912 {
00913     /* Check the parameters */
00914     assert_param(IS_TIM3_CLEAR_FLAG_OK(TIM3_FLAG));
00915
00916     /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
00917     TIM3->SR1 = (uint8_t)(~((uint8_t)(TIM3_FLAG)));
00918     TIM3->SR2 = (uint8_t)(~((uint8_t)((uint16_t)TIM3_FLAG >> 8)));
00919 }
00920
00921
00922 /**
00923   * @brief  Checks whether the TIM3 interrupt has occurred or not.
00924   * @param   TIM3_IT specifies the TIM3 interrupt source to check.
00925   * This parameter can be one of the following values:
00926   *                       - TIM3_IT_UPDATE: TIM3 update Interrupt source
00927   *                       - TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
00928   *                       - TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
00929   * @retval ITStatus The new state of the TIM3_IT(SET or RESET).
00930   */
00931
00932 ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT)
00933 {
00934     ITStatus bitstatus = RESET;
00935     uint8_t TIM3_itStatus = 0, TIM3_itEnable = 0;
00936
00937     /* Check the parameters */
00938     assert_param(IS_TIM3_GET_IT_OK(TIM3_IT));
00939
00940     TIM3_itStatus = (uint8_t)(TIM3->SR1 & TIM3_IT);
00941
00942     TIM3_itEnable = (uint8_t)(TIM3->IER & TIM3_IT);
00943
00944     if ((TIM3_itStatus != (uint8_t)RESET ) && (TIM3_itEnable != (uint8_t)RESET ))
00945     {
00946         bitstatus = SET;
00947     }
00948     else
00949     {
00950         bitstatus = RESET;
00951     }
00952     return (ITStatus)(bitstatus);
00953 }
00954
00955
00956 /**
00957   * @brief  Clears the TIM3's interrupt pending bits.
00958   * @param   TIM3_IT specifies the pending bit to clear.
00959   * This parameter can be one of the following values:
00960   *                       - TIM3_IT_UPDATE: TIM3 update Interrupt source
00961   *                       - TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source
00962   *                       - TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source
00963   * @retval None.
00964   */
00965 void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT)
00966 {
00967     /* Check the parameters */
00968     assert_param(IS_TIM3_IT_OK(TIM3_IT));
00969
00970     /* Clear the IT pending Bit */
00971     TIM3->SR1 = (uint8_t)(~TIM3_IT);
00972 }
00973
00974
00975 /**
00976   * @brief  Configure the TI1 as Input.
00977   * @param   TIM3_ICPolarity  The Input Polarity.
00978   * This parameter can be one of the following values:
00979   *                       - TIM3_ICPOLARITY_FALLING
00980   *                       - TIM3_ICPOLARITY_RISING
00981   * @param   TIM3_ICSelection specifies the input to be used.
00982   * This parameter can be one of the following values:
00983   *                       - TIM3_ICSELECTION_DIRECTTI: TIM3 Input 1 is selected to
00984   *                         be connected to IC1.
00985   *                       - TIM3_ICSELECTION_INDIRECTTI: TIM3 Input 1 is selected to
00986   *                         be connected to IC2.
00987   * @param   TIM3_ICFilter Specifies the Input Capture Filter.
00988   * This parameter must be a value between 0x00 and 0x0F.
00989   * @retval None
00990   */
00991 static void TI1_Config(uint8_t TIM3_ICPolarity,
00992                        uint8_t TIM3_ICSelection,
00993                        uint8_t TIM3_ICFilter)
00994 {
00995     /* Disable the Channel 1: Reset the CCE Bit */
00996     TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1E);
00997
00998     /* Select the Input and set the filter */
00999     TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~( TIM3_CCMR_CCxS | TIM3_CCMR_ICxF))) | (uint8_t)(( (TIM3_ICSelection)) | ((uint8_t)( TIM3_ICFilter << 4))));
01000
01001     /* Select the Polarity */
01002     if (TIM3_ICPolarity != TIM3_ICPOLARITY_RISING)
01003     {
01004         TIM3->CCER1 |= TIM3_CCER1_CC1P;
01005     }
01006     else
01007     {
01008         TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1P);
01009     }
01010     /* Set the CCE Bit */
01011     TIM3->CCER1 |= TIM3_CCER1_CC1E;
01012 }
01013
01014
01015 /**
01016   * @brief  Configure the TI2 as Input.
01017   * @param   TIM3_ICPolarity  The Input Polarity.
01018   * This parameter can be one of the following values:
01019   *                       - TIM3_ICPOLARITY_FALLING
01020   *                       - TIM3_ICPOLARITY_RISING
01021   * @param   TIM3_ICSelection specifies the input to be used.
01022   * This parameter can be one of the following values:
01023   *                       - TIM3_ICSELECTION_DIRECTTI: TIM3 Input 2 is selected to
01024   *                         be connected to IC2.
01025   *                       - TIM3_ICSELECTION_INDIRECTTI: TIM3 Input 2 is selected to
01026   *                         be connected to IC1.
01027   * @param   TIM3_ICFilter Specifies the Input Capture Filter.
01028   * This parameter must be a value between 0x00 and 0x0F.
01029   * @retval None
01030   */
01031 static void TI2_Config(uint8_t TIM3_ICPolarity,
01032                        uint8_t TIM3_ICSelection,
01033                        uint8_t TIM3_ICFilter)
01034 {
01035     /* Disable the Channel 2: Reset the CCE Bit */
01036     TIM3->CCER1 &=  (uint8_t)(~TIM3_CCER1_CC2E);
01037
01038     /* Select the Input and set the filter */
01039     TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~( TIM3_CCMR_CCxS |
01040                   TIM3_CCMR_ICxF    ))) | (uint8_t)(( (TIM3_ICSelection)) |
01041                   ((uint8_t)( TIM3_ICFilter << 4))));
01042
01043     /* Select the Polarity */
01044     if (TIM3_ICPolarity != TIM3_ICPOLARITY_RISING)
01045     {
01046         TIM3->CCER1 |= TIM3_CCER1_CC2P;
01047     }
01048     else
01049     {
01050         TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2P);
01051     }
01052
01053     /* Set the CCE Bit */
01054     TIM3->CCER1 |= TIM3_CCER1_CC2E;
01055
01056 }
01057 /**
01058   * @}
01059   */
01060
01061   /**
01062   * @}
01063   */
01064
01065 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim3.h Source File

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stm8s_tim3.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim3.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief  This file contains all functions prototype and macros for the TIM3 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_TIM3_H
00024 #define __STM8S_TIM3_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /* Exported types ------------------------------------------------------------*/
00034
00035 /** @addtogroup TIM3_Exported_Types
00036   * @{
00037   */
00038
00039 /** TIM3 Forced Action */
00040 typedef enum
00041 {
00042   TIM3_FORCEDACTION_ACTIVE           = ((uint8_t)0x50),
00043   TIM3_FORCEDACTION_INACTIVE         = ((uint8_t)0x40)
00044 } TIM3_ForcedAction_TypeDef;
00045
00046 #define IS_TIM3_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM3_FORCEDACTION_ACTIVE) || \
00047     ((ACTION) == TIM3_FORCEDACTION_INACTIVE))
00048
00049 /** TIM3 Prescaler */
00050 typedef enum
00051 {
00052   TIM3_PRESCALER_1  = ((uint8_t)0x00),
00053   TIM3_PRESCALER_2    = ((uint8_t)0x01),
00054   TIM3_PRESCALER_4    = ((uint8_t)0x02),
00055   TIM3_PRESCALER_8     = ((uint8_t)0x03),
00056   TIM3_PRESCALER_16   = ((uint8_t)0x04),
00057   TIM3_PRESCALER_32     = ((uint8_t)0x05),
00058   TIM3_PRESCALER_64    = ((uint8_t)0x06),
00059   TIM3_PRESCALER_128   = ((uint8_t)0x07),
00060   TIM3_PRESCALER_256   = ((uint8_t)0x08),
00061   TIM3_PRESCALER_512   = ((uint8_t)0x09),
00062   TIM3_PRESCALER_1024  = ((uint8_t)0x0A),
00063   TIM3_PRESCALER_2048 = ((uint8_t)0x0B),
00064   TIM3_PRESCALER_4096   = ((uint8_t)0x0C),
00065   TIM3_PRESCALER_8192 = ((uint8_t)0x0D),
00066   TIM3_PRESCALER_16384 = ((uint8_t)0x0E),
00067   TIM3_PRESCALER_32768 = ((uint8_t)0x0F)
00068 } TIM3_Prescaler_TypeDef;
00069
00070 #define IS_TIM3_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM3_PRESCALER_1  ) || \
00071     ((PRESCALER) == TIM3_PRESCALER_2    ) || \
00072     ((PRESCALER) == TIM3_PRESCALER_4    ) || \
00073     ((PRESCALER) == TIM3_PRESCALER_8  ) || \
00074     ((PRESCALER) == TIM3_PRESCALER_16   ) || \
00075     ((PRESCALER) == TIM3_PRESCALER_32     ) || \
00076     ((PRESCALER) == TIM3_PRESCALER_64    ) || \
00077     ((PRESCALER) == TIM3_PRESCALER_128   ) || \
00078     ((PRESCALER) == TIM3_PRESCALER_256   ) || \
00079     ((PRESCALER) == TIM3_PRESCALER_512   ) || \
00080     ((PRESCALER) == TIM3_PRESCALER_1024  ) || \
00081     ((PRESCALER) == TIM3_PRESCALER_2048 ) || \
00082     ((PRESCALER) == TIM3_PRESCALER_4096 ) || \
00083     ((PRESCALER) == TIM3_PRESCALER_8192 ) || \
00084     ((PRESCALER) == TIM3_PRESCALER_16384 ) || \
00085     ((PRESCALER) == TIM3_PRESCALER_32768 ))
00086
00087 /** TIM3 Output Compare and PWM modes */
00088 typedef enum
00089 {
00090   TIM3_OCMODE_TIMING     = ((uint8_t)0x00),
00091   TIM3_OCMODE_ACTIVE     = ((uint8_t)0x10),
00092   TIM3_OCMODE_INACTIVE   = ((uint8_t)0x20),
00093   TIM3_OCMODE_TOGGLE     = ((uint8_t)0x30),
00094   TIM3_OCMODE_PWM1       = ((uint8_t)0x60),
00095   TIM3_OCMODE_PWM2       = ((uint8_t)0x70)
00096 } TIM3_OCMode_TypeDef;
00097
00098 #define IS_TIM3_OC_MODE_OK(MODE) (((MODE) ==  TIM3_OCMODE_TIMING) || \
00099                                   ((MODE) == TIM3_OCMODE_ACTIVE) || \
00100                                   ((MODE) == TIM3_OCMODE_INACTIVE) || \
00101                                   ((MODE) == TIM3_OCMODE_TOGGLE)|| \
00102                                   ((MODE) == TIM3_OCMODE_PWM1) || \
00103                                   ((MODE) == TIM3_OCMODE_PWM2))
00104
00105 #define IS_TIM3_OCM_OK(MODE)(((MODE) ==  TIM3_OCMODE_TIMING) || \
00106                              ((MODE) == TIM3_OCMODE_ACTIVE) || \
00107                              ((MODE) == TIM3_OCMODE_INACTIVE) || \
00108                              ((MODE) == TIM3_OCMODE_TOGGLE)|| \
00109                              ((MODE) == TIM3_OCMODE_PWM1) || \
00110                              ((MODE) == TIM3_OCMODE_PWM2) || \
00111                              ((MODE) == (uint8_t)TIM3_FORCEDACTION_ACTIVE) || \
00112                              ((MODE) == (uint8_t)TIM3_FORCEDACTION_INACTIVE))
00113
00114 /** TIM3 One Pulse Mode */
00115 typedef enum
00116 {
00117   TIM3_OPMODE_SINGLE                 = ((uint8_t)0x01),
00118   TIM3_OPMODE_REPETITIVE             = ((uint8_t)0x00)
00119 } TIM3_OPMode_TypeDef;
00120
00121 #define IS_TIM3_OPM_MODE_OK(MODE) (((MODE) == TIM3_OPMODE_SINGLE) || \
00122                                    ((MODE) == TIM3_OPMODE_REPETITIVE))
00123
00124 /** TIM3 Channel */
00125
00126 typedef enum
00127 {
00128   TIM3_CHANNEL_1                     = ((uint8_t)0x00),
00129   TIM3_CHANNEL_2                     = ((uint8_t)0x01)
00130 } TIM3_Channel_TypeDef;
00131
00132 #define IS_TIM3_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM3_CHANNEL_1) || \
00133                                      ((CHANNEL) == TIM3_CHANNEL_2))
00134
00135 #define IS_TIM3_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM3_CHANNEL_1) || \
00136     ((CHANNEL) == TIM3_CHANNEL_2))
00137
00138 /** TIM3 Output Compare Polarity */
00139 typedef enum
00140 {
00141   TIM3_OCPOLARITY_HIGH               = ((uint8_t)0x00),
00142   TIM3_OCPOLARITY_LOW                = ((uint8_t)0x22)
00143 } TIM3_OCPolarity_TypeDef;
00144
00145 #define IS_TIM3_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM3_OCPOLARITY_HIGH) || \
00146     ((POLARITY) == TIM3_OCPOLARITY_LOW))
00147
00148 /** TIM3 Output Compare states */
00149 typedef enum
00150 {
00151   TIM3_OUTPUTSTATE_DISABLE           = ((uint8_t)0x00),
00152   TIM3_OUTPUTSTATE_ENABLE            = ((uint8_t)0x11)
00153 } TIM3_OutputState_TypeDef;
00154
00155 #define IS_TIM3_OUTPUT_STATE_OK(STATE) (((STATE) == TIM3_OUTPUTSTATE_DISABLE) || \
00156                                         ((STATE) == TIM3_OUTPUTSTATE_ENABLE))
00157
00158 /** TIM3 Input Capture Polarity */
00159 typedef enum
00160 {
00161   TIM3_ICPOLARITY_RISING            = ((uint8_t)0x00),
00162   TIM3_ICPOLARITY_FALLING           = ((uint8_t)0x44)
00163 } TIM3_ICPolarity_TypeDef;
00164
00165 #define IS_TIM3_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM3_ICPOLARITY_RISING) || \
00166     ((POLARITY) == TIM3_ICPOLARITY_FALLING))
00167
00168 /** TIM3 Input Capture Selection */
00169 typedef enum
00170 {
00171   TIM3_ICSELECTION_DIRECTTI          = ((uint8_t)0x01),
00172   TIM3_ICSELECTION_INDIRECTTI        = ((uint8_t)0x02),
00173   TIM3_ICSELECTION_TRGI              = ((uint8_t)0x03)
00174 } TIM3_ICSelection_TypeDef;
00175
00176 #define IS_TIM3_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM3_ICSELECTION_DIRECTTI) || \
00177     ((SELECTION) == TIM3_ICSELECTION_INDIRECTTI) || \
00178     ((SELECTION) == TIM3_ICSELECTION_TRGI))
00179
00180 /** TIM3 Input Capture Prescaler */
00181 typedef enum
00182 {
00183   TIM3_ICPSC_DIV1                    = ((uint8_t)0x00),
00184   TIM3_ICPSC_DIV2                    = ((uint8_t)0x04),
00185   TIM3_ICPSC_DIV4                    = ((uint8_t)0x08),
00186   TIM3_ICPSC_DIV8                    = ((uint8_t)0x0C)
00187 } TIM3_ICPSC_TypeDef;
00188
00189 #define IS_TIM3_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM3_ICPSC_DIV1) || \
00190     ((PRESCALER) == TIM3_ICPSC_DIV2) || \
00191     ((PRESCALER) == TIM3_ICPSC_DIV4) || \
00192     ((PRESCALER) == TIM3_ICPSC_DIV8))
00193
00194 /** TIM3 Input Capture Filer Value */
00195 #define IS_TIM3_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
00196
00197 /** TIM3 interrupt sources */
00198 typedef enum
00199 {
00200   TIM3_IT_UPDATE                     = ((uint8_t)0x01),
00201   TIM3_IT_CC1                        = ((uint8_t)0x02),
00202   TIM3_IT_CC2                        = ((uint8_t)0x04)
00203 } TIM3_IT_TypeDef;
00204
00205 #define IS_TIM3_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x07))
00206
00207 #define IS_TIM3_GET_IT_OK(IT) (((IT) == TIM3_IT_UPDATE) || \
00208                                ((IT) == TIM3_IT_CC1) || \
00209                                ((IT) == TIM3_IT_CC2))
00210
00211 /** TIM3 Prescaler Reload Mode */
00212 typedef enum
00213 {
00214   TIM3_PSCRELOADMODE_UPDATE          = ((uint8_t)0x00),
00215   TIM3_PSCRELOADMODE_IMMEDIATE       = ((uint8_t)0x01)
00216 } TIM3_PSCReloadMode_TypeDef;
00217
00218 #define IS_TIM3_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM3_PSCRELOADMODE_UPDATE) || \
00219     ((RELOAD) == TIM3_PSCRELOADMODE_IMMEDIATE))
00220
00221 /** TIM3 Event Source */
00222 typedef enum
00223 {
00224   TIM3_EVENTSOURCE_UPDATE            = ((uint8_t)0x01),
00225   TIM3_EVENTSOURCE_CC1               = ((uint8_t)0x02),
00226   TIM3_EVENTSOURCE_CC2               = ((uint8_t)0x04)
00227 } TIM3_EventSource_TypeDef;
00228
00229 #define IS_TIM3_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
00230
00231 /** TIM3 Update Source */
00232 typedef enum
00233 {
00234   TIM3_UPDATESOURCE_GLOBAL           = ((uint8_t)0x00),
00235   TIM3_UPDATESOURCE_REGULAR          = ((uint8_t)0x01)
00236 } TIM3_UpdateSource_TypeDef;
00237
00238 #define IS_TIM3_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM3_UPDATESOURCE_GLOBAL) || \
00239     ((SOURCE) == TIM3_UPDATESOURCE_REGULAR))
00240
00241 /** TIM3 Flags */
00242 typedef enum
00243 {
00244   TIM3_FLAG_UPDATE                   = ((uint16_t)0x0001),
00245   TIM3_FLAG_CC1                      = ((uint16_t)0x0002),
00246   TIM3_FLAG_CC2                      = ((uint16_t)0x0004),
00247   TIM3_FLAG_CC1OF                    = ((uint16_t)0x0200),
00248   TIM3_FLAG_CC2OF                    = ((uint16_t)0x0400)
00249 } TIM3_FLAG_TypeDef;
00250
00251 #define IS_TIM3_GET_FLAG_OK(FLAG) (((FLAG) == TIM3_FLAG_UPDATE) || \
00252                                    ((FLAG) == TIM3_FLAG_CC1) || \
00253                                    ((FLAG) == TIM3_FLAG_CC2) || \
00254                                    ((FLAG) == TIM3_FLAG_CC1OF) || \
00255                                    ((FLAG) == TIM3_FLAG_CC2OF) )
00256
00257 #define IS_TIM3_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF9F8) == 0x0000) && ((uint16_t)(FLAG)!= 0x0000))
00258
00259 /**
00260   * @}
00261   */
00262
00263 /* Exported macro ------------------------------------------------------------*/
00264
00265 /* Exported functions --------------------------------------------------------*/
00266
00267 /** @addtogroup TIM3_Exported_Functions
00268   * @{
00269   */
00270
00271 void TIM3_DeInit(void);
00272 void TIM3_TimeBaseInit(TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period);
00273 void TIM3_OC1Init(TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
00274 void TIM3_OC2Init(TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
00275 void TIM3_ICInit(TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection,  TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter);
00276 void TIM3_PWMIConfig(TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection,  TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter);
00277 void TIM3_Cmd(FunctionalState NewState);
00278 void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState);
00279 void TIM3_InternalClockConfig(void);
00280 void TIM3_UpdateDisableConfig(FunctionalState NewState);
00281 void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource);
00282 void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode);
00283 void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode);
00284 void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);
00285 void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);
00286 void TIM3_ARRPreloadConfig(FunctionalState NewState);
00287 void TIM3_CCPreloadControl(FunctionalState NewState);
00288 void TIM3_OC1PreloadConfig(FunctionalState NewState);
00289 void TIM3_OC2PreloadConfig(FunctionalState NewState);
00290 void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource);
00291 void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
00292 void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
00293 void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState);
00294 void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode);
00295 void TIM3_SetCounter(uint16_t Counter);
00296 void TIM3_SetAutoreload(uint16_t Autoreload);
00297 void TIM3_SetCompare1(uint16_t Compare1);
00298 void TIM3_SetCompare2(uint16_t Compare2);
00299 void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler);
00300 void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler);
00301 uint16_t TIM3_GetCapture1(void);
00302 uint16_t TIM3_GetCapture2(void);
00303 uint16_t TIM3_GetCounter(void);
00304 TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void);
00305 FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG);
00306 void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG);
00307 ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT);
00308 void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT);
00309
00310 /**
00311   * @}
00312   */
00313
00314 #endif /* __STM8S_TIM3_H */
00315
00316 /**
00317   * @}
00318   */
00319
00320 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim4.c Source File

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  • STM8S_StdPeriph_Driver
  • src

stm8s_tim4.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim4.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the TIM4 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_tim4.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /**
00034   * @addtogroup TIM4_Public_Functions
00035   * @{
00036   */
00037
00038 /**
00039   * @brief  Deinitializes the TIM4 peripheral registers to their default reset values.
00040   * @param  None
00041   * @retval None
00042   */
00043 void TIM4_DeInit(void)
00044 {
00045     TIM4->CR1 = TIM4_CR1_RESET_VALUE;
00046     TIM4->IER = TIM4_IER_RESET_VALUE;
00047     TIM4->CNTR = TIM4_CNTR_RESET_VALUE;
00048     TIM4->PSCR = TIM4_PSCR_RESET_VALUE;
00049     TIM4->ARR = TIM4_ARR_RESET_VALUE;
00050     TIM4->SR1 = TIM4_SR1_RESET_VALUE;
00051 }
00052
00053 /**
00054   * @brief  Initializes the TIM4 Time Base Unit according to the specified parameters.
00055   * @param    TIM4_Prescaler specifies the Prescaler from TIM4_Prescaler_TypeDef.
00056   * @param    TIM4_Period specifies the Period value.
00057   * @retval None
00058   */
00059 void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)
00060 {
00061     /* Check TIM4 prescaler value */
00062     assert_param(IS_TIM4_PRESCALER_OK(TIM4_Prescaler));
00063     /* Set the Prescaler value */
00064     TIM4->PSCR = (uint8_t)(TIM4_Prescaler);
00065     /* Set the Autoreload value */
00066     TIM4->ARR = (uint8_t)(TIM4_Period);
00067 }
00068
00069
00070
00071 /**
00072   * @brief  Enables or disables the TIM4 peripheral.
00073   * @param   NewState new state of the TIM4 peripheral. This parameter can
00074   * be ENABLE or DISABLE.
00075   * @retval None
00076   */
00077 void TIM4_Cmd(FunctionalState NewState)
00078 {
00079     /* Check the parameters */
00080     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00081
00082     /* set or Reset the CEN Bit */
00083     if (NewState != DISABLE)
00084     {
00085         TIM4->CR1 |= TIM4_CR1_CEN;
00086     }
00087     else
00088     {
00089         TIM4->CR1 &= (uint8_t)(~TIM4_CR1_CEN);
00090     }
00091 }
00092
00093 /**
00094   * @brief  Enables or disables the specified TIM4 interrupts.
00095   * @param   NewState new state of the TIM4 peripheral.
00096   * This parameter can be: ENABLE or DISABLE.
00097   * @param   TIM4_IT specifies the TIM4 interrupts sources to be enabled or disabled.
00098   * This parameter can be any combination of the following values:
00099   * - TIM4_IT_UPDATE: TIM4 update Interrupt source
00100   * @param   NewState new state of the TIM4 peripheral.
00101   * @retval None
00102   */
00103 void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
00104 {
00105     /* Check the parameters */
00106     assert_param(IS_TIM4_IT_OK(TIM4_IT));
00107     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00108
00109     if (NewState != DISABLE)
00110     {
00111         /* Enable the Interrupt sources */
00112         TIM4->IER |= (uint8_t)TIM4_IT;
00113     }
00114     else
00115     {
00116         /* Disable the Interrupt sources */
00117         TIM4->IER &= (uint8_t)(~TIM4_IT);
00118     }
00119 }
00120
00121 /**
00122   * @brief  Enables or Disables the TIM4 Update event.
00123   * @param   NewState new state of the TIM4 peripheral Preload register. This parameter can
00124   * be ENABLE or DISABLE.
00125   * @retval None
00126   */
00127 void TIM4_UpdateDisableConfig(FunctionalState NewState)
00128 {
00129     /* Check the parameters */
00130     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00131
00132     /* Set or Reset the UDIS Bit */
00133     if (NewState != DISABLE)
00134     {
00135         TIM4->CR1 |= TIM4_CR1_UDIS;
00136     }
00137     else
00138     {
00139         TIM4->CR1 &= (uint8_t)(~TIM4_CR1_UDIS);
00140     }
00141 }
00142
00143 /**
00144   * @brief  Selects the TIM4 Update Request Interrupt source.
00145   * @param   TIM4_UpdateSource specifies the Update source.
00146   * This parameter can be one of the following values
00147   *                       - TIM4_UPDATESOURCE_REGULAR
00148   *                       - TIM4_UPDATESOURCE_GLOBAL
00149   * @retval None
00150   */
00151 void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
00152 {
00153     /* Check the parameters */
00154     assert_param(IS_TIM4_UPDATE_SOURCE_OK(TIM4_UpdateSource));
00155
00156     /* Set or Reset the URS Bit */
00157     if (TIM4_UpdateSource != TIM4_UPDATESOURCE_GLOBAL)
00158     {
00159         TIM4->CR1 |= TIM4_CR1_URS;
00160     }
00161     else
00162     {
00163         TIM4->CR1 &= (uint8_t)(~TIM4_CR1_URS);
00164     }
00165 }
00166
00167 /**
00168   * @brief  Selects the TIM4’s One Pulse Mode.
00169   * @param   TIM4_OPMode specifies the OPM Mode to be used.
00170   * This parameter can be one of the following values
00171   *                    - TIM4_OPMODE_SINGLE
00172   *                    - TIM4_OPMODE_REPETITIVE
00173   * @retval None
00174   */
00175 void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode)
00176 {
00177     /* Check the parameters */
00178     assert_param(IS_TIM4_OPM_MODE_OK(TIM4_OPMode));
00179
00180     /* Set or Reset the OPM Bit */
00181     if (TIM4_OPMode != TIM4_OPMODE_REPETITIVE)
00182     {
00183         TIM4->CR1 |= TIM4_CR1_OPM;
00184     }
00185     else
00186     {
00187         TIM4->CR1 &= (uint8_t)(~TIM4_CR1_OPM);
00188     }
00189
00190 }
00191
00192 /**
00193   * @brief  Configures the TIM4 Prescaler.
00194   * @param   Prescaler specifies the Prescaler Register value
00195   * This parameter can be one of the following values
00196   *                       -  TIM4_PRESCALER_1
00197   *                       -  TIM4_PRESCALER_2
00198   *                       -  TIM4_PRESCALER_4
00199   *                       -  TIM4_PRESCALER_8
00200   *                       -  TIM4_PRESCALER_16
00201   *                       -  TIM4_PRESCALER_32
00202   *                       -  TIM4_PRESCALER_64
00203   *                       -  TIM4_PRESCALER_128
00204   * @param   TIM4_PSCReloadMode specifies the TIM4 Prescaler Reload mode.
00205   * This parameter can be one of the following values
00206   *                       - TIM4_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
00207   *                         immediatly.
00208   *                       - TIM4_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
00209   *                         the update event.
00210   * @retval None
00211   */
00212 void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
00213 {
00214     /* Check the parameters */
00215     assert_param(IS_TIM4_PRESCALER_RELOAD_OK(TIM4_PSCReloadMode));
00216     assert_param(IS_TIM4_PRESCALER_OK(Prescaler));
00217
00218     /* Set the Prescaler value */
00219     TIM4->PSCR = (uint8_t)Prescaler;
00220
00221     /* Set or reset the UG Bit */
00222     TIM4->EGR = (uint8_t)TIM4_PSCReloadMode;
00223 }
00224
00225 /**
00226   * @brief  Enables or disables TIM4 peripheral Preload register on ARR.
00227   * @param   NewState new state of the TIM4 peripheral Preload register.
00228   * This parameter can be ENABLE or DISABLE.
00229   * @retval None
00230   */
00231 void TIM4_ARRPreloadConfig(FunctionalState NewState)
00232 {
00233     /* Check the parameters */
00234     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00235
00236     /* Set or Reset the ARPE Bit */
00237     if (NewState != DISABLE)
00238     {
00239         TIM4->CR1 |= TIM4_CR1_ARPE;
00240     }
00241     else
00242     {
00243         TIM4->CR1 &= (uint8_t)(~TIM4_CR1_ARPE);
00244     }
00245 }
00246
00247 /**
00248   * @brief  Configures the TIM4 event to be generated by software.
00249   * @param   TIM4_EventSource specifies the event source.
00250   * This parameter can be one of the following values:
00251   *                       - TIM4_EVENTSOURCE_UPDATE: TIM4 update Event source
00252   * @retval None
00253   */
00254 void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource)
00255 {
00256     /* Check the parameters */
00257     assert_param(IS_TIM4_EVENT_SOURCE_OK(TIM4_EventSource));
00258
00259     /* Set the event sources */
00260     TIM4->EGR = (uint8_t)(TIM4_EventSource);
00261 }
00262
00263
00264 /**
00265   * @brief  Sets the TIM4 Counter Register value.
00266   * @param   Counter specifies the Counter register new value.
00267   * This parameter is between 0x00 and 0xFF.
00268   * @retval None
00269   */
00270 void TIM4_SetCounter(uint8_t Counter)
00271 {
00272     /* Set the Counter Register value */
00273     TIM4->CNTR = (uint8_t)(Counter);
00274 }
00275
00276
00277 /**
00278   * @brief  Sets the TIM4 Autoreload Register value.
00279   * @param   Autoreload specifies the Autoreload register new value.
00280   * This parameter is between 0x00 and 0xFF.
00281   * @retval None
00282   */
00283 void TIM4_SetAutoreload(uint8_t Autoreload)
00284 {
00285     /* Set the Autoreload Register value */
00286     TIM4->ARR = (uint8_t)(Autoreload);
00287 }
00288
00289 /**
00290   * @brief  Gets the TIM4 Counter value.
00291   * @param  None
00292   * @retval Counter Register value.
00293   */
00294 uint8_t TIM4_GetCounter(void)
00295 {
00296     /* Get the Counter Register value */
00297     return (uint8_t)(TIM4->CNTR);
00298 }
00299
00300 /**
00301   * @brief  Gets the TIM4 Prescaler value.
00302   * @param  None
00303   * @retval Prescaler Register configuration value.
00304   */
00305 TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void)
00306 {
00307     /* Get the Prescaler Register value */
00308     return (TIM4_Prescaler_TypeDef)(TIM4->PSCR);
00309 }
00310
00311 /**
00312   * @brief  Checks whether the specified TIM4 flag is set or not.
00313   * @param   TIM4_FLAG specifies the flag to check.
00314   * This parameter can be one of the following values:
00315   *                       - TIM4_FLAG_UPDATE: TIM4 update Flag
00316   * @retval FlagStatus The new state of TIM4_FLAG (SET or RESET).
00317   */
00318 FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG)
00319 {
00320     FlagStatus bitstatus = RESET;
00321
00322     /* Check the parameters */
00323     assert_param(IS_TIM4_GET_FLAG_OK(TIM4_FLAG));
00324
00325   if ((TIM4->SR1 & (uint8_t)TIM4_FLAG)  != 0)
00326   {
00327     bitstatus = SET;
00328   }
00329   else
00330   {
00331     bitstatus = RESET;
00332   }
00333   return ((FlagStatus)bitstatus);
00334 }
00335
00336 /**
00337   * @brief  Clears the TIM4’s pending flags.
00338   * @param   TIM4_FLAG specifies the flag to clear.
00339   * This parameter can be one of the following values:
00340   *                       - TIM4_FLAG_UPDATE: TIM4 update Flag
00341   * @retval None.
00342   */
00343 void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG)
00344 {
00345     /* Check the parameters */
00346     assert_param(IS_TIM4_GET_FLAG_OK(TIM4_FLAG));
00347
00348     /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
00349     TIM4->SR1 = (uint8_t)(~TIM4_FLAG);
00350
00351 }
00352 /**
00353   * @brief  Checks whether the TIM4 interrupt has occurred or not.
00354   * @param   TIM4_IT specifies the TIM4 interrupt source to check.
00355   * This parameter can be one of the following values:
00356   *                       - TIM4_IT_UPDATE: TIM4 update Interrupt source
00357   * @retval ITStatus The new state of the TIM4_IT (SET or RESET).
00358   */
00359
00360 ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT)
00361 {
00362     ITStatus bitstatus = RESET;
00363
00364   uint8_t itstatus = 0x0, itenable = 0x0;
00365
00366   /* Check the parameters */
00367   assert_param(IS_TIM4_IT_OK(TIM4_IT));
00368
00369   itstatus = (uint8_t)(TIM4->SR1 & (uint8_t)TIM4_IT);
00370
00371   itenable = (uint8_t)(TIM4->IER & (uint8_t)TIM4_IT);
00372
00373   if ((itstatus != (uint8_t)RESET ) && (itenable != (uint8_t)RESET ))
00374   {
00375     bitstatus = (ITStatus)SET;
00376   }
00377   else
00378   {
00379     bitstatus = (ITStatus)RESET;
00380   }
00381   return ((ITStatus)bitstatus);
00382 }
00383
00384 /**
00385   * @brief  Clears the TIM4's interrupt pending bits.
00386   * @param   TIM4_IT specifies the pending bit to clear.
00387   * This parameter can be one of the following values:
00388   *                       - TIM4_IT_UPDATE: TIM4 update Interrupt source
00389   * @retval None.
00390   */
00391 void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT)
00392 {
00393     /* Check the parameters */
00394     assert_param(IS_TIM4_IT_OK(TIM4_IT));
00395
00396     /* Clear the IT pending Bit */
00397     TIM4->SR1 = (uint8_t)(~TIM4_IT);
00398 }
00399
00400 /**
00401   * @}
00402   */
00403
00404   /**
00405   * @}
00406   */
00407
00408 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim4.h Source File

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  • inc

stm8s_tim4.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim4.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the TIM4 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_TIM4_H
00024 #define __STM8S_TIM4_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /* Exported types ------------------------------------------------------------*/
00034
00035 /** @addtogroup TIM4_Exported_Types
00036   * @{
00037   */
00038
00039
00040
00041 /** TIM4 Prescaler */
00042 typedef enum
00043 {
00044   TIM4_PRESCALER_1  = ((uint8_t)0x00),
00045   TIM4_PRESCALER_2    = ((uint8_t)0x01),
00046   TIM4_PRESCALER_4    = ((uint8_t)0x02),
00047   TIM4_PRESCALER_8     = ((uint8_t)0x03),
00048   TIM4_PRESCALER_16   = ((uint8_t)0x04),
00049   TIM4_PRESCALER_32     = ((uint8_t)0x05),
00050   TIM4_PRESCALER_64    = ((uint8_t)0x06),
00051   TIM4_PRESCALER_128   = ((uint8_t)0x07)
00052 } TIM4_Prescaler_TypeDef;
00053
00054 #define IS_TIM4_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM4_PRESCALER_1  ) || \
00055     ((PRESCALER) == TIM4_PRESCALER_2    ) || \
00056     ((PRESCALER) == TIM4_PRESCALER_4    ) || \
00057     ((PRESCALER) == TIM4_PRESCALER_8  ) || \
00058     ((PRESCALER) == TIM4_PRESCALER_16   ) || \
00059     ((PRESCALER) == TIM4_PRESCALER_32     ) || \
00060     ((PRESCALER) == TIM4_PRESCALER_64    ) || \
00061     ((PRESCALER) == TIM4_PRESCALER_128   ) )
00062
00063 /** TIM4 One Pulse Mode */
00064 typedef enum
00065 {
00066   TIM4_OPMODE_SINGLE                 = ((uint8_t)0x01),
00067   TIM4_OPMODE_REPETITIVE             = ((uint8_t)0x00)
00068 } TIM4_OPMode_TypeDef;
00069
00070 #define IS_TIM4_OPM_MODE_OK(MODE) (((MODE) == TIM4_OPMODE_SINGLE) || \
00071                                    ((MODE) == TIM4_OPMODE_REPETITIVE))
00072
00073 /** TIM4 Prescaler Reload Mode */
00074 typedef enum
00075 {
00076   TIM4_PSCRELOADMODE_UPDATE          = ((uint8_t)0x00),
00077   TIM4_PSCRELOADMODE_IMMEDIATE       = ((uint8_t)0x01)
00078 } TIM4_PSCReloadMode_TypeDef;
00079
00080 #define IS_TIM4_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM4_PSCRELOADMODE_UPDATE) || \
00081     ((RELOAD) == TIM4_PSCRELOADMODE_IMMEDIATE))
00082
00083 /** TIM4 Update Source */
00084 typedef enum
00085 {
00086   TIM4_UPDATESOURCE_GLOBAL           = ((uint8_t)0x00),
00087   TIM4_UPDATESOURCE_REGULAR          = ((uint8_t)0x01)
00088 } TIM4_UpdateSource_TypeDef;
00089
00090 #define IS_TIM4_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM4_UPDATESOURCE_GLOBAL) || \
00091     ((SOURCE) == TIM4_UPDATESOURCE_REGULAR))
00092
00093 /** TIM4 Event Source */
00094 typedef enum
00095 {
00096   TIM4_EVENTSOURCE_UPDATE            = ((uint8_t)0x01)
00097 }TIM4_EventSource_TypeDef;
00098
00099 #define IS_TIM4_EVENT_SOURCE_OK(SOURCE) (((SOURCE) == 0x01))
00100
00101 /** TIM4 Flags */
00102 typedef enum
00103 {
00104   TIM4_FLAG_UPDATE                   = ((uint8_t)0x01)
00105 }TIM4_FLAG_TypeDef;
00106
00107 #define IS_TIM4_GET_FLAG_OK(FLAG) ((FLAG) == TIM4_FLAG_UPDATE)
00108
00109
00110
00111 /** TIM4 interrupt sources */
00112 typedef enum
00113 {
00114   TIM4_IT_UPDATE                     = ((uint8_t)0x01)
00115 }TIM4_IT_TypeDef;
00116
00117 #define IS_TIM4_IT_OK(IT) ((IT) == TIM4_IT_UPDATE)
00118
00119
00120
00121 /**
00122   * @}
00123   */
00124
00125 /* Exported macro ------------------------------------------------------------*/
00126
00127 /* Exported functions --------------------------------------------------------*/
00128
00129 /** @addtogroup TIM4_Exported_Functions
00130   * @{
00131   */
00132 void TIM4_DeInit(void);
00133 void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period);
00134 void TIM4_Cmd(FunctionalState NewState);
00135 void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState);
00136 void TIM4_UpdateDisableConfig(FunctionalState NewState);
00137 void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource);
00138 void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode);
00139 void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode);
00140 void TIM4_ARRPreloadConfig(FunctionalState NewState);
00141 void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource);
00142 void TIM4_SetCounter(uint8_t Counter);
00143 void TIM4_SetAutoreload(uint8_t Autoreload);
00144 uint8_t TIM4_GetCounter(void);
00145 TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void);
00146 FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG);
00147 void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG);
00148 ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT);
00149 void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT);
00150
00151
00152 /**
00153   * @}
00154   */
00155
00156 #endif /* __STM8S_TIM4_H */
00157
00158 /**
00159   * @}
00160   */
00161
00162 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim5.c Source File

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stm8s_tim5.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim5.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the TIM5 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_tim5.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 static void TI1_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter);
00034 static void TI2_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter);
00035 static void TI3_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter);
00036 /**
00037   * @addtogroup TIM5_Public_Functions
00038   * @{
00039   */
00040
00041 /**
00042   * @brief  Deinitializes the TIM5 peripheral registers to their default reset values.
00043   * @param  None
00044   * @retval None
00045   */
00046 void TIM5_DeInit(void)
00047 {
00048
00049     TIM5->CR1 = (uint8_t)TIM5_CR1_RESET_VALUE;
00050     TIM5->CR2 = TIM5_CR2_RESET_VALUE;
00051     TIM5->SMCR = TIM5_SMCR_RESET_VALUE;
00052     TIM5->IER = (uint8_t)TIM5_IER_RESET_VALUE;
00053     TIM5->SR2 = (uint8_t)TIM5_SR2_RESET_VALUE;
00054
00055     /* Disable channels */
00056     TIM5->CCER1 = (uint8_t)TIM5_CCER1_RESET_VALUE;
00057     TIM5->CCER2 = (uint8_t)TIM5_CCER2_RESET_VALUE;
00058
00059
00060     /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
00061     TIM5->CCER1 = (uint8_t)TIM5_CCER1_RESET_VALUE;
00062     TIM5->CCER2 = (uint8_t)TIM5_CCER2_RESET_VALUE;
00063     TIM5->CCMR1 = (uint8_t)TIM5_CCMR1_RESET_VALUE;
00064     TIM5->CCMR2 = (uint8_t)TIM5_CCMR2_RESET_VALUE;
00065     TIM5->CCMR3 = (uint8_t)TIM5_CCMR3_RESET_VALUE;
00066     TIM5->CNTRH = (uint8_t)TIM5_CNTRH_RESET_VALUE;
00067     TIM5->CNTRL = (uint8_t)TIM5_CNTRL_RESET_VALUE;
00068     TIM5->PSCR  = (uint8_t)TIM5_PSCR_RESET_VALUE;
00069     TIM5->ARRH  = (uint8_t)TIM5_ARRH_RESET_VALUE;
00070     TIM5->ARRL  = (uint8_t)TIM5_ARRL_RESET_VALUE;
00071     TIM5->CCR1H = (uint8_t)TIM5_CCR1H_RESET_VALUE;
00072     TIM5->CCR1L = (uint8_t)TIM5_CCR1L_RESET_VALUE;
00073     TIM5->CCR2H = (uint8_t)TIM5_CCR2H_RESET_VALUE;
00074     TIM5->CCR2L = (uint8_t)TIM5_CCR2L_RESET_VALUE;
00075     TIM5->CCR3H = (uint8_t)TIM5_CCR3H_RESET_VALUE;
00076     TIM5->CCR3L = (uint8_t)TIM5_CCR3L_RESET_VALUE;
00077     TIM5->SR1 = (uint8_t)TIM5_SR1_RESET_VALUE;
00078 }
00079
00080
00081 /**
00082   * @brief  Initializes the TIM5 Time Base Unit according to the specified parameters.
00083   * @param    TIM5_Prescaler specifies the Prescaler from TIM5_Prescaler_TypeDef.
00084   * @param    TIM5_Period specifies the Period value.
00085   * @retval None
00086   */
00087 void TIM5_TimeBaseInit( TIM5_Prescaler_TypeDef TIM5_Prescaler,
00088                         uint16_t TIM5_Period)
00089 {
00090     /* Set the Prescaler value */
00091     TIM5->PSCR = (uint8_t)(TIM5_Prescaler);
00092     /* Set the Autoreload value */
00093     TIM5->ARRH = (uint8_t)(TIM5_Period >> 8) ;
00094     TIM5->ARRL = (uint8_t)(TIM5_Period);
00095 }
00096
00097
00098 /**
00099   * @brief  Initializes the TIM5 Channel1 according to the specified parameters.
00100   * @param   TIM5_OCMode specifies the Output Compare mode  from @ref TIM5_OCMode_TypeDef.
00101   * @param   TIM5_OutputState specifies the Output State  from @ref TIM5_OutputState_TypeDef.
00102   * @param   TIM5_Pulse specifies the Pulse width  value.
00103   * @param   TIM5_OCPolarity specifies the Output Compare Polarity  from @ref TIM5_OCPolarity_TypeDef.
00104   * @retval None
00105   */
00106 void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode,
00107                   TIM5_OutputState_TypeDef TIM5_OutputState,
00108                   uint16_t TIM5_Pulse,
00109                   TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00110 {
00111     /* Check the parameters */
00112     assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode));
00113     assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState));
00114     assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00115
00116     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */
00117     TIM5->CCER1 &= (uint8_t)(~( TIM5_CCER1_CC1E | TIM5_CCER1_CC1P));
00118     /* Set the Output State &  Set the Output Polarity  */
00119     TIM5->CCER1 |= (uint8_t)((uint8_t)(TIM5_OutputState & TIM5_CCER1_CC1E )|
00120                              (uint8_t)(TIM5_OCPolarity & TIM5_CCER1_CC1P));
00121
00122     /* Reset the Output Compare Bits  & Set the Output Compare Mode */
00123     TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM)) |
00124                             (uint8_t)TIM5_OCMode);
00125
00126     /* Set the Pulse value */
00127     TIM5->CCR1H = (uint8_t)(TIM5_Pulse >> 8);
00128     TIM5->CCR1L = (uint8_t)(TIM5_Pulse);
00129 }
00130
00131
00132 /**
00133   * @brief  Initializes the TIM5 Channel2 according to the specified parameters.
00134   * @param   TIM5_OCMode specifies the Output Compare mode  from @ref TIM5_OCMode_TypeDef.
00135   * @param   TIM5_OutputState specifies the Output State  from @ref TIM5_OutputState_TypeDef.
00136   * @param   TIM5_Pulse specifies the Pulse width  value.
00137   * @param   TIM5_OCPolarity specifies the Output Compare Polarity  from @ref TIM5_OCPolarity_TypeDef.
00138   * @retval None
00139   */
00140 void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode,
00141                   TIM5_OutputState_TypeDef TIM5_OutputState,
00142                   uint16_t TIM5_Pulse,
00143                   TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00144 {
00145     /* Check the parameters */
00146     assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode));
00147     assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState));
00148     assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00149
00150
00151     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */
00152     TIM5->CCER1 &= (uint8_t)(~( TIM5_CCER1_CC2E |  TIM5_CCER1_CC2P ));
00153     /* Set the Output State & Set the Output Polarity  */
00154     TIM5->CCER1 |= (uint8_t)((uint8_t)(TIM5_OutputState  & TIM5_CCER1_CC2E )| \
00155                         (uint8_t)(TIM5_OCPolarity & TIM5_CCER1_CC2P));
00156
00157
00158     /* Reset the Output Compare Bits  & Set the Output Compare Mode */
00159     TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM)) |
00160                             (uint8_t)TIM5_OCMode);
00161
00162
00163     /* Set the Pulse value */
00164     TIM5->CCR2H = (uint8_t)(TIM5_Pulse >> 8);
00165     TIM5->CCR2L = (uint8_t)(TIM5_Pulse);
00166 }
00167
00168
00169 /**
00170   * @brief  Initializes the TIM5 Channel3 according to the specified parameters.
00171   * @param   TIM5_OCMode specifies the Output Compare mode from @ref TIM5_OCMode_TypeDef.
00172   * @param   TIM5_OutputState specifies the Output State from @ref TIM5_OutputState_TypeDef.
00173   * @param   TIM5_Pulse specifies the Pulse width value.
00174   * @param   TIM5_OCPolarity specifies the Output Compare Polarity  from @ref TIM5_OCPolarity_TypeDef.
00175   * @retval None
00176   */
00177 void TIM5_OC3Init(TIM5_OCMode_TypeDef TIM5_OCMode,
00178                   TIM5_OutputState_TypeDef TIM5_OutputState,
00179                   uint16_t TIM5_Pulse,
00180                   TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00181 {
00182     /* Check the parameters */
00183     assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode));
00184     assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState));
00185     assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00186     /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */
00187     TIM5->CCER2 &= (uint8_t)(~( TIM5_CCER2_CC3E  | TIM5_CCER2_CC3P));
00188     /* Set the Output State & Set the Output Polarity  */
00189     TIM5->CCER2 |= (uint8_t)((uint8_t)(TIM5_OutputState  & TIM5_CCER2_CC3E   )|
00190                              (uint8_t)(TIM5_OCPolarity   & TIM5_CCER2_CC3P   ));
00191
00192     /* Reset the Output Compare Bits  & Set the Output Compare Mode */
00193     TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM)) | (uint8_t)TIM5_OCMode);
00194
00195     /* Set the Pulse value */
00196     TIM5->CCR3H = (uint8_t)(TIM5_Pulse >> 8);
00197     TIM5->CCR3L = (uint8_t)(TIM5_Pulse);
00198
00199 }
00200
00201
00202 /**
00203   * @brief  Initializes the TIM5 peripheral according to the specified parameters.
00204   * @param    TIM5_Channel specifies the Input Capture Channel from @ref TIM5_Channel_TypeDef.
00205   * @param   TIM5_ICPolarity specifies the Input Capture Polarity from @ref TIM5_ICPolarity_TypeDef.
00206   * @param   TIM5_ICSelection specifies theInput Capture Selection from @ref TIM5_ICSelection_TypeDef.
00207   * @param   TIM5_ICPrescaler specifies the Input Capture Prescaler from @ref TIM5_ICPSC_TypeDef.
00208   * @param   TIM5_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00209   * @retval None
00210   */
00211 void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel,
00212                  TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
00213                  TIM5_ICSelection_TypeDef TIM5_ICSelection,
00214                  TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
00215                  uint8_t TIM5_ICFilter)
00216 {
00217     /* Check the parameters */
00218     assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel));
00219     assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_ICPolarity));
00220     assert_param(IS_TIM5_IC_SELECTION_OK(TIM5_ICSelection));
00221     assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_ICPrescaler));
00222     assert_param(IS_TIM5_IC_FILTER_OK(TIM5_ICFilter));
00223
00224     if (TIM5_Channel == TIM5_CHANNEL_1)
00225     {
00226         /* TI1 Configuration */
00227         TI1_Config((uint8_t)TIM5_ICPolarity,
00228                    (uint8_t)TIM5_ICSelection,
00229                    (uint8_t)TIM5_ICFilter);
00230
00231         /* Set the Input Capture Prescaler value */
00232         TIM5_SetIC1Prescaler(TIM5_ICPrescaler);
00233     }
00234     else if (TIM5_Channel == TIM5_CHANNEL_2)
00235     {
00236         /* TI2 Configuration */
00237         TI2_Config((uint8_t)TIM5_ICPolarity,
00238                    (uint8_t)TIM5_ICSelection,
00239                    (uint8_t)TIM5_ICFilter);
00240
00241         /* Set the Input Capture Prescaler value */
00242         TIM5_SetIC2Prescaler(TIM5_ICPrescaler);
00243     }
00244     else
00245     {
00246         /* TI3 Configuration */
00247         TI3_Config((uint8_t)TIM5_ICPolarity,
00248                    (uint8_t)TIM5_ICSelection,
00249                    (uint8_t)TIM5_ICFilter);
00250
00251         /* Set the Input Capture Prescaler value */
00252         TIM5_SetIC3Prescaler(TIM5_ICPrescaler);
00253     }
00254 }
00255
00256
00257 /**
00258   * @brief  Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.
00259     * @param    TIM5_Channel specifies the Input Capture Channel from @ref TIM5_Channel_TypeDef.
00260   * @param   TIM5_ICPolarity specifies the Input Capture Polarity from @ref TIM5_ICPolarity_TypeDef.
00261   * @param   TIM5_ICSelection specifies theInput Capture Selection from @ref TIM5_ICSelection_TypeDef.
00262   * @param   TIM5_ICPrescaler specifies the Input Capture Prescaler from @ref TIM5_ICPSC_TypeDef.
00263   * @param   TIM5_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).
00264   * @retval None
00265   */
00266 void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel,
00267                      TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
00268                      TIM5_ICSelection_TypeDef TIM5_ICSelection,
00269                      TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
00270                      uint8_t TIM5_ICFilter)
00271 {
00272     uint8_t icpolarity = (uint8_t)TIM5_ICPOLARITY_RISING;
00273     uint8_t icselection = (uint8_t)TIM5_ICSELECTION_DIRECTTI;
00274
00275     /* Check the parameters */
00276     assert_param(IS_TIM5_PWMI_CHANNEL_OK(TIM5_Channel));
00277     assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_ICPolarity));
00278     assert_param(IS_TIM5_IC_SELECTION_OK(TIM5_ICSelection));
00279     assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_ICPrescaler));
00280
00281     /* Select the Opposite Input Polarity */
00282     if (TIM5_ICPolarity != TIM5_ICPOLARITY_FALLING)
00283     {
00284         icpolarity = (uint8_t)TIM5_ICPOLARITY_FALLING;
00285     }
00286     else
00287     {
00288         icpolarity = (uint8_t)TIM5_ICPOLARITY_RISING;
00289     }
00290
00291     /* Select the Opposite Input */
00292     if (TIM5_ICSelection == TIM5_ICSELECTION_DIRECTTI)
00293     {
00294         icselection = (uint8_t)TIM5_ICSELECTION_INDIRECTTI;
00295     }
00296     else
00297     {
00298         icselection = (uint8_t)TIM5_ICSELECTION_DIRECTTI;
00299     }
00300
00301     if (TIM5_Channel == TIM5_CHANNEL_1)
00302     {
00303         /* TI1 Configuration */
00304         TI1_Config((uint8_t)TIM5_ICPolarity, (uint8_t)TIM5_ICSelection,
00305                    (uint8_t)TIM5_ICFilter);
00306
00307         /* Set the Input Capture Prescaler value */
00308         TIM5_SetIC1Prescaler(TIM5_ICPrescaler);
00309
00310         /* TI2 Configuration */
00311         TI2_Config((uint8_t)icpolarity, (uint8_t)icselection, (uint8_t)TIM5_ICFilter);
00312
00313         /* Set the Input Capture Prescaler value */
00314         TIM5_SetIC2Prescaler(TIM5_ICPrescaler);
00315     }
00316     else
00317     {
00318         /* TI2 Configuration */
00319         TI2_Config((uint8_t)TIM5_ICPolarity, (uint8_t)TIM5_ICSelection,
00320                    (uint8_t)TIM5_ICFilter);
00321
00322         /* Set the Input Capture Prescaler value */
00323         TIM5_SetIC2Prescaler(TIM5_ICPrescaler);
00324
00325         /* TI1 Configuration */
00326         TI1_Config((uint8_t)icpolarity, (uint8_t)icselection, (uint8_t)TIM5_ICFilter);
00327
00328         /* Set the Input Capture Prescaler value */
00329         TIM5_SetIC1Prescaler(TIM5_ICPrescaler);
00330     }
00331 }
00332
00333
00334 /**
00335   * @brief  Enables or disables the TIM5 peripheral.
00336   * @param   NewState new state of the TIM5 peripheral.This parameter can
00337   * be ENABLE or DISABLE.
00338   * @retval None
00339   */
00340 void TIM5_Cmd(FunctionalState NewState)
00341 {
00342     /* Check the parameters */
00343     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00344
00345     /* set or Reset the CEN Bit */
00346     if (NewState != DISABLE)
00347     {
00348         TIM5->CR1 |= TIM5_CR1_CEN ;
00349     }
00350     else
00351     {
00352         TIM5->CR1 &= (uint8_t)(~TIM5_CR1_CEN) ;
00353     }
00354 }
00355
00356
00357 /**
00358   * @brief  Enables or disables the specified TIM5 interrupts.
00359   * @param   NewState new state of the TIM5 peripheral.
00360   * This parameter can be: ENABLE or DISABLE.
00361   * @param   TIM5_IT specifies the TIM5 interrupts sources to be enabled or disabled.
00362   * This parameter can be any combination of the following values:
00363   *                       - TIM5_IT_UPDATE: TIM5 update Interrupt source
00364   *                       - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
00365   *                       - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
00366   *                       - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
00367   * @param   NewState new state of the TIM5 peripheral.
00368   * @retval None
00369   */
00370 void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
00371 {
00372     /* Check the parameters */
00373     assert_param(IS_TIM5_IT_OK(TIM5_IT));
00374     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00375
00376     if (NewState != DISABLE)
00377     {
00378         /* Enable the Interrupt sources */
00379         TIM5->IER |= (uint8_t)TIM5_IT;
00380     }
00381     else
00382     {
00383         /* Disable the Interrupt sources */
00384         TIM5->IER &= (uint8_t)(~TIM5_IT);
00385     }
00386 }
00387
00388
00389 /**
00390   * @brief  Enables or Disables the TIM5 Update event.
00391   * @param   NewState new state of the TIM5 peripheral Preload register.This parameter can
00392   * be ENABLE or DISABLE.
00393   * @retval None
00394   */
00395 void TIM5_UpdateDisableConfig(FunctionalState NewState)
00396 {
00397     /* Check the parameters */
00398     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00399
00400     /* Set or Reset the UDIS Bit */
00401     if (NewState != DISABLE)
00402     {
00403         TIM5->CR1 |= TIM5_CR1_UDIS ;
00404     }
00405     else
00406     {
00407         TIM5->CR1 &= (uint8_t)(~TIM5_CR1_UDIS) ;
00408     }
00409 }
00410
00411 /**
00412   * @brief  Selects the TIM5 Update Request Interrupt source.
00413   * @param   TIM5_UpdateSource specifies the Update source.
00414   * This parameter can be one of the following values
00415   *                       - TIM5_UPDATESOURCE_REGULAR
00416   *                       - TIM5_UPDATESOURCE_GLOBAL
00417   * @retval None
00418   */
00419 void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
00420 {
00421     /* Check the parameters */
00422     assert_param(IS_TIM5_UPDATE_SOURCE_OK(TIM5_UpdateSource));
00423
00424     /* Set or Reset the URS Bit */
00425     if (TIM5_UpdateSource != TIM5_UPDATESOURCE_GLOBAL)
00426     {
00427         TIM5->CR1 |= TIM5_CR1_URS ;
00428     }
00429     else
00430     {
00431         TIM5->CR1 &= (uint8_t)(~TIM5_CR1_URS) ;
00432     }
00433 }
00434
00435
00436 /**
00437   * @brief  Selects the TIM5’s One Pulse Mode.
00438   * @param   TIM5_OPMode specifies the OPM Mode to be used.
00439   * This parameter can be one of the following values
00440   *                    - TIM5_OPMODE_SINGLE
00441   *                    - TIM5_OPMODE_REPETITIVE
00442   * @retval None
00443   */
00444 void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode)
00445 {
00446     /* Check the parameters */
00447     assert_param(IS_TIM5_OPM_MODE_OK(TIM5_OPMode));
00448
00449     /* Set or Reset the OPM Bit */
00450     if (TIM5_OPMode != TIM5_OPMODE_REPETITIVE)
00451     {
00452         TIM5->CR1 |= TIM5_CR1_OPM ;
00453     }
00454     else
00455     {
00456         TIM5->CR1 &= (uint8_t)(~TIM5_CR1_OPM) ;
00457     }
00458
00459 }
00460
00461
00462 /**
00463   * @brief  Configures the TIM5 Prescaler.
00464   * @param   Prescaler specifies the Prescaler Register value
00465   * This parameter can be one of the following values
00466   *                       -  TIM5_PRESCALER_1
00467   *                       -  TIM5_PRESCALER_2
00468   *                       -  TIM5_PRESCALER_4
00469   *                       -  TIM5_PRESCALER_8
00470   *                       -  TIM5_PRESCALER_16
00471   *                       -  TIM5_PRESCALER_32
00472   *                       -  TIM5_PRESCALER_64
00473   *                       -  TIM5_PRESCALER_128
00474   *                       -  TIM5_PRESCALER_256
00475   *                       -  TIM5_PRESCALER_512
00476   *                       -  TIM5_PRESCALER_1024
00477   *                       -  TIM5_PRESCALER_2048
00478   *                       -  TIM5_PRESCALER_4096
00479   *                       -  TIM5_PRESCALER_8192
00480   *                       -  TIM5_PRESCALER_16384
00481   *                       -  TIM5_PRESCALER_32768
00482   * @param   TIM5_PSCReloadMode specifies the TIM5 Prescaler Reload mode.
00483   * This parameter can be one of the following values
00484   *                       - TIM5_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
00485   *                         immediatly.
00486   *                       - TIM5_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
00487   *                         the update event.
00488   * @retval None
00489   */
00490 void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler,
00491                           TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
00492 {
00493     /* Check the parameters */
00494     assert_param(IS_TIM5_PRESCALER_RELOAD_OK(TIM5_PSCReloadMode));
00495     assert_param(IS_TIM5_PRESCALER_OK(Prescaler));
00496
00497     /* Set the Prescaler value */
00498     TIM5->PSCR = (uint8_t)Prescaler;
00499
00500     /* Set or reset the UG Bit */
00501     TIM5->EGR = (uint8_t)TIM5_PSCReloadMode ;
00502 }
00503
00504 /**
00505   * @brief  Forces the TIM5 Channel1 output waveform to active or inactive level.
00506   * @param   TIM5_ForcedAction specifies the forced Action to be set to the output waveform.
00507   * This parameter can be one of the following values:
00508   *                       - TIM5_FORCEDACTION_ACTIVE: Force active level on OC1REF
00509   *                       - TIM5_FORCEDACTION_INACTIVE: Force inactive level on
00510   *                         OC1REF.
00511   * @retval None
00512   */
00513 void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
00514 {
00515     /* Check the parameters */
00516     assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));
00517
00518     /* Reset the OCM Bits */ /* Configure The Forced output Mode */
00519     TIM5->CCMR1  =  (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM))
00520                               | (uint8_t)TIM5_ForcedAction);
00521 }
00522
00523 /**
00524   * @brief  Forces the TIM5 Channel2 output waveform to active or inactive level.
00525   * @param   TIM5_ForcedAction specifies the forced Action to be set to the output waveform.
00526   * This parameter can be one of the following values:
00527   *                       - TIM5_FORCEDACTION_ACTIVE: Force active level on OC2REF
00528   *                       - TIM5_FORCEDACTION_INACTIVE: Force inactive level on
00529   *                         OC2REF.
00530   * @retval None
00531   */
00532 void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
00533 {
00534     /* Check the parameters */
00535     assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));
00536
00537     /* Reset the OCM Bits */ /* Configure The Forced output Mode */
00538     TIM5->CCMR2  =  (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM))
00539                               | (uint8_t)TIM5_ForcedAction);
00540 }
00541
00542 /**
00543   * @brief  Forces the TIM5 Channel3 output waveform to active or inactive level.
00544   * @param   TIM5_ForcedAction specifies the forced Action to be set to the output waveform.
00545   * This parameter can be one of the following values:
00546   *                       - TIM5_FORCEDACTION_ACTIVE: Force active level on OC3REF
00547   *                       - TIM5_FORCEDACTION_INACTIVE: Force inactive level on
00548   *                         OC3REF.
00549   * @retval None
00550   */
00551 void TIM5_ForcedOC3Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
00552 {
00553     /* Check the parameters */
00554     assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));
00555
00556     /* Reset the OCM Bits */ /* Configure The Forced output Mode */
00557     TIM5->CCMR3  =  (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM))
00558                               | (uint8_t)TIM5_ForcedAction);
00559 }
00560
00561
00562 /**
00563   * @brief  Enables or disables TIM5 peripheral Preload register on ARR.
00564   * @param   NewState new state of the TIM5 peripheral Preload register.
00565   * This parameter can be ENABLE or DISABLE.
00566   * @retval None
00567   */
00568 void TIM5_ARRPreloadConfig(FunctionalState NewState)
00569 {
00570     /* Check the parameters */
00571     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00572
00573     /* Set or Reset the ARPE Bit */
00574     if (NewState != DISABLE)
00575     {
00576         TIM5->CR1 |= TIM5_CR1_ARPE ;
00577     }
00578     else
00579     {
00580         TIM5->CR1 &= (uint8_t)(~TIM5_CR1_ARPE) ;
00581     }
00582 }
00583
00584
00585 /**
00586   * @brief  Enables or disables the TIM5 peripheral Preload Register on CCR1.
00587   * @param   NewState new state of the Capture Compare Preload register.
00588   * This parameter can be ENABLE or DISABLE.
00589   * @retval None
00590   */
00591 void TIM5_OC1PreloadConfig(FunctionalState NewState)
00592 {
00593     /* Check the parameters */
00594     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00595
00596     /* Set or Reset the OC1PE Bit */
00597     if (NewState != DISABLE)
00598     {
00599         TIM5->CCMR1 |= TIM5_CCMR_OCxPE ;
00600     }
00601     else
00602     {
00603         TIM5->CCMR1 &= (uint8_t)(~TIM5_CCMR_OCxPE) ;
00604     }
00605 }
00606
00607
00608 /**
00609   * @brief  Enables or disables the TIM5 peripheral Preload Register on CCR2.
00610   * @param   NewState new state of the Capture Compare Preload register.
00611   * This parameter can be ENABLE or DISABLE.
00612   * @retval None
00613   */
00614 void TIM5_OC2PreloadConfig(FunctionalState NewState)
00615 {
00616     /* Check the parameters */
00617     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00618
00619     /* Set or Reset the OC2PE Bit */
00620     if (NewState != DISABLE)
00621     {
00622         TIM5->CCMR2 |= TIM5_CCMR_OCxPE ;
00623     }
00624     else
00625     {
00626         TIM5->CCMR2 &= (uint8_t)(~TIM5_CCMR_OCxPE) ;
00627     }
00628 }
00629
00630
00631 /**
00632   * @brief  Enables or disables the TIM5 peripheral Preload Register on CCR3.
00633   * @param   NewState new state of the Capture Compare Preload register.
00634   * This parameter can be ENABLE or DISABLE.
00635   * @retval None
00636   */
00637 void TIM5_OC3PreloadConfig(FunctionalState NewState)
00638 {
00639     /* Check the parameters */
00640     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00641
00642     /* Set or Reset the OC3PE Bit */
00643     if (NewState != DISABLE)
00644     {
00645         TIM5->CCMR3 |= TIM5_CCMR_OCxPE ;
00646     }
00647     else
00648     {
00649         TIM5->CCMR3 &= (uint8_t)(~TIM5_CCMR_OCxPE) ;
00650     }
00651 }
00652
00653
00654 /**
00655   * @brief  Configures the TIM5 event to be generated by software.
00656   * @param   TIM5_EventSource specifies the event source.
00657   * This parameter can be one of the following values:
00658   *                       - TIM5_EVENTSOURCE_UPDATE: TIM5 update Event source
00659   *                       - TIM5_EVENTSOURCE_CC1: TIM5 Capture Compare 1 Event source
00660   *                       - TIM5_EVENTSOURCE_CC2: TIM5 Capture Compare 2 Event source
00661   *                       - TIM5_EVENTSOURCE_CC3: TIM5 Capture Compare 3 Event source
00662   * @retval None
00663   */
00664 void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource)
00665 {
00666     /* Check the parameters */
00667     assert_param(IS_TIM5_EVENT_SOURCE_OK(TIM5_EventSource));
00668
00669     /* Set the event sources */
00670     TIM5->EGR = (uint8_t)TIM5_EventSource;
00671 }
00672
00673
00674 /**
00675   * @brief  Configures the TIM5 Channel 1 polarity.
00676   * @param   TIM5_OCPolarity specifies the OC1 Polarity.
00677   * This parameter can be one of the following values:
00678   *                       - TIM5_OCPOLARITY_LOW: Output Compare active low
00679   *                       - TIM5_OCPOLARITY_HIGH: Output Compare active high
00680   * @retval None
00681   */
00682 void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00683 {
00684     /* Check the parameters */
00685     assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00686
00687     /* Set or Reset the CC1P Bit */
00688     if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)
00689     {
00690         TIM5->CCER1 |= TIM5_CCER1_CC1P ;
00691     }
00692     else
00693     {
00694         TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ;
00695     }
00696 }
00697
00698
00699 /**
00700   * @brief  Configures the TIM5 Channel 2 polarity.
00701   * @param   TIM5_OCPolarity specifies the OC2 Polarity.
00702   * This parameter can be one of the following values:
00703   *                       - TIM5_OCPOLARITY_LOW: Output Compare active low
00704   *                       - TIM5_OCPOLARITY_HIGH: Output Compare active high
00705   * @retval None
00706   */
00707 void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00708 {
00709     /* Check the parameters */
00710     assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00711
00712     /* Set or Reset the CC2P Bit */
00713     if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)
00714     {
00715         TIM5->CCER1 |= TIM5_CCER1_CC2P ;
00716     }
00717     else
00718     {
00719         TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ;
00720     }
00721 }
00722
00723
00724 /**
00725   * @brief  Configures the TIM5 Channel 3 polarity.
00726   * @param   TIM5_OCPolarity specifies the OC3 Polarity.
00727   * This parameter can be one of the following values:
00728   *                       - TIM5_OCPOLARITY_LOW: Output Compare active low
00729   *                       - TIM5_OCPOLARITY_HIGH: Output Compare active high
00730   * @retval None
00731   */
00732 void TIM5_OC3PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
00733 {
00734     /* Check the parameters */
00735     assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));
00736
00737     /* Set or Reset the CC3P Bit */
00738     if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)
00739     {
00740         TIM5->CCER2 |= TIM5_CCER2_CC3P ;
00741     }
00742     else
00743     {
00744         TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3P) ;
00745     }
00746 }
00747
00748
00749 /**
00750   * @brief  Enables or disables the TIM5 Capture Compare Channel x.
00751   * @param   TIM5_Channel specifies the TIM5 Channel.
00752   * This parameter can be one of the following values:
00753   *                       - TIM5_Channel1: TIM5 Channel1
00754   *                       - TIM5_Channel2: TIM5 Channel2
00755   *                       - TIM5_Channel3: TIM5 Channel3
00756   * @param   NewState specifies the TIM5 Channel CCxE bit new state.
00757   * This parameter can be: ENABLE or DISABLE.
00758   * @retval None
00759   */
00760 void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)
00761 {
00762     /* Check the parameters */
00763     assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel));
00764     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00765
00766     if (TIM5_Channel == TIM5_CHANNEL_1)
00767     {
00768         /* Set or Reset the CC1E Bit */
00769         if (NewState != DISABLE)
00770         {
00771             TIM5->CCER1 |= TIM5_CCER1_CC1E ;
00772         }
00773         else
00774         {
00775             TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E) ;
00776         }
00777
00778     }
00779     else if (TIM5_Channel == TIM5_CHANNEL_2)
00780     {
00781         /* Set or Reset the CC2E Bit */
00782         if (NewState != DISABLE)
00783         {
00784             TIM5->CCER1 |= TIM5_CCER1_CC2E;
00785         }
00786         else
00787         {
00788             TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2E) ;
00789         }
00790     }
00791     else
00792     {
00793         /* Set or Reset the CC3E Bit */
00794         if (NewState != DISABLE)
00795         {
00796             TIM5->CCER2 |= TIM5_CCER2_CC3E;
00797         }
00798         else
00799         {
00800             TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3E) ;
00801         }
00802     }
00803 }
00804
00805 /**
00806   * @brief  Selects the TIM5 Output Compare Mode. This function disables the
00807   * selected channel before changing the Output Compare Mode. User has to
00808   * enable this channel using TIM5_CCxCmd and TIM5_CCxNCmd functions.
00809   * @param   TIM5_Channel specifies the TIM5 Channel.
00810   * This parameter can be one of the following values:
00811   *                       - TIM5_Channel1: TIM5 Channel1
00812   *                       - TIM5_Channel2: TIM5 Channel2
00813   *                       - TIM5_Channel3: TIM5 Channel3
00814   * @param   TIM5_OCMode specifies the TIM5 Output Compare Mode.
00815   * This paramter can be one of the following values:
00816   *                       - TIM5_OCMODE_TIMING
00817   *                       - TIM5_OCMODE_ACTIVE
00818   *                       - TIM5_OCMODE_TOGGLE
00819   *                       - TIM5_OCMODE_PWM1
00820   *                       - TIM5_OCMODE_PWM2
00821   *                       - TIM5_FORCEDACTION_ACTIVE
00822   *                       - TIM5_FORCEDACTION_INACTIVE
00823   * @retval None
00824   */
00825 void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)
00826 {
00827     /* Check the parameters */
00828     assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel));
00829     assert_param(IS_TIM5_OCM_OK(TIM5_OCMode));
00830
00831     if (TIM5_Channel == TIM5_CHANNEL_1)
00832     {
00833         /* Disable the Channel 1: Reset the CCE Bit */
00834         TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E);
00835
00836         /* Reset the Output Compare Bits  Set the Output Compare Mode */
00837         TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM))
00838                                 | (uint8_t)TIM5_OCMode);
00839     }
00840     else if (TIM5_Channel == TIM5_CHANNEL_2)
00841     {
00842         /* Disable the Channel 2: Reset the CCE Bit */
00843         TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2E);
00844
00845         /* Reset the Output Compare Bits ** Set the Output Compare Mode */
00846         TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM))
00847                                 | (uint8_t)TIM5_OCMode);
00848     }
00849     else
00850     {
00851         /* Disable the Channel 3: Reset the CCE Bit */
00852         TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3E);
00853
00854         /* Reset the Output Compare Bits ** Set the Output Compare Mode */
00855         TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM))
00856                                 | (uint8_t)TIM5_OCMode);
00857     }
00858 }
00859
00860
00861 /**
00862   * @brief  Sets the TIM5 Counter Register value.
00863   * @param   Counter specifies the Counter register new value.
00864   * This parameter is between 0x0000 and 0xFFFF.
00865   * @retval None
00866   */
00867 void TIM5_SetCounter(uint16_t Counter)
00868 {
00869     /* Set the Counter Register value */
00870     TIM5->CNTRH = (uint8_t)(Counter >> 8);
00871     TIM5->CNTRL = (uint8_t)(Counter);
00872
00873 }
00874
00875
00876 /**
00877   * @brief  Sets the TIM5 Autoreload Register value.
00878   * @param   Autoreload specifies the Autoreload register new value.
00879   * This parameter is between 0x0000 and 0xFFFF.
00880   * @retval None
00881   */
00882 void TIM5_SetAutoreload(uint16_t Autoreload)
00883 {
00884
00885     /* Set the Autoreload Register value */
00886     TIM5->ARRH = (uint8_t)(Autoreload >> 8);
00887     TIM5->ARRL = (uint8_t)(Autoreload);
00888
00889 }
00890
00891
00892 /**
00893   * @brief  Sets the TIM5 Capture Compare1 Register value.
00894   * @param   Compare1 specifies the Capture Compare1 register new value.
00895   * This parameter is between 0x0000 and 0xFFFF.
00896   * @retval None
00897   */
00898 void TIM5_SetCompare1(uint16_t Compare1)
00899 {
00900     /* Set the Capture Compare1 Register value */
00901     TIM5->CCR1H = (uint8_t)(Compare1 >> 8);
00902     TIM5->CCR1L = (uint8_t)(Compare1);
00903
00904 }
00905
00906
00907 /**
00908   * @brief  Sets the TIM5 Capture Compare2 Register value.
00909   * @param   Compare2 specifies the Capture Compare2 register new value.
00910   * This parameter is between 0x0000 and 0xFFFF.
00911   * @retval None
00912   */
00913 void TIM5_SetCompare2(uint16_t Compare2)
00914 {
00915     /* Set the Capture Compare2 Register value */
00916     TIM5->CCR2H = (uint8_t)(Compare2 >> 8);
00917     TIM5->CCR2L = (uint8_t)(Compare2);
00918
00919 }
00920
00921
00922 /**
00923   * @brief  Sets the TIM5 Capture Compare3 Register value.
00924   * @param   Compare3 specifies the Capture Compare3 register new value.
00925   * This parameter is between 0x0000 and 0xFFFF.
00926   * @retval None
00927   */
00928 void TIM5_SetCompare3(uint16_t Compare3)
00929 {
00930     /* Set the Capture Compare3 Register value */
00931     TIM5->CCR3H = (uint8_t)(Compare3 >> 8);
00932     TIM5->CCR3L = (uint8_t)(Compare3);
00933
00934 }
00935
00936
00937 /**
00938   * @brief  Sets the TIM5 Input Capture 1 prescaler.
00939   * @param   TIM5_IC1Prescaler specifies the Input Capture prescaler new value
00940   * This parameter can be one of the following values:
00941   *                       - TIM5_ICPSC_DIV1: no prescaler
00942   *                       - TIM5_ICPSC_DIV2: capture is done once every 2 events
00943   *                       - TIM5_ICPSC_DIV4: capture is done once every 4 events
00944   *                       - TIM5_ICPSC_DIV8: capture is done once every 8 events
00945   * @retval None
00946   */
00947 void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
00948 {
00949     /* Check the parameters */
00950     assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC1Prescaler));
00951
00952     /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
00953     TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_ICxPSC))|
00954                             (uint8_t)TIM5_IC1Prescaler);
00955 }
00956
00957 /**
00958   * @brief  Sets the TIM5 Input Capture 2 prescaler.
00959   * @param   TIM5_IC2Prescaler specifies the Input Capture prescaler new value
00960   * This parameter can be one of the following values:
00961   *                       - TIM5_ICPSC_DIV1: no prescaler
00962   *                       - TIM5_ICPSC_DIV2: capture is done once every 2 events
00963   *                       - TIM5_ICPSC_DIV4: capture is done once every 4 events
00964   *                       - TIM5_ICPSC_DIV8: capture is done once every 8 events
00965   * @retval None
00966   */
00967 void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
00968 {
00969     /* Check the parameters */
00970     assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC2Prescaler));
00971
00972     /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
00973     TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_ICxPSC))
00974                             | (uint8_t)TIM5_IC2Prescaler);
00975 }
00976
00977 /**
00978   * @brief  Sets the TIM5 Input Capture 3 prescaler.
00979   * @param   TIM5_IC3Prescaler specifies the Input Capture prescaler new value
00980   * This parameter can be one of the following values:
00981   *                       - TIM5_ICPSC_DIV1: no prescaler
00982   *                       - TIM5_ICPSC_DIV2: capture is done once every 2 events
00983   *                       - TIM5_ICPSC_DIV4: capture is done once every 4 events
00984   *                       - TIM5_ICPSC_DIV8: capture is done once every 8 events
00985   * @retval None
00986   */
00987 void TIM5_SetIC3Prescaler(TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)
00988 {
00989
00990     /* Check the parameters */
00991     assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC3Prescaler));
00992     /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
00993     TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_ICxPSC)) |
00994                             (uint8_t)TIM5_IC3Prescaler);
00995 }
00996
00997 /**
00998   * @brief  Gets the TIM5 Input Capture 1 value.
00999   * @param  None
01000   * @retval Capture Compare 1 Register value.
01001   */
01002 uint16_t TIM5_GetCapture1(void)
01003 {
01004    uint16_t temp = 0;
01005
01006    temp = ((uint16_t)TIM5->CCR1H << 8);
01007
01008    /* Get the Capture 1 Register value */
01009     return (uint16_t)(temp | (uint16_t)(TIM5->CCR1L));
01010 }
01011
01012 /**
01013   * @brief  Gets the TIM5 Input Capture 2 value.
01014   * @param  None
01015   * @retval Capture Compare 2 Register value.
01016   */
01017 uint16_t TIM5_GetCapture2(void)
01018 {
01019   uint16_t temp = 0;
01020
01021    temp = ((uint16_t)TIM5->CCR2H << 8);
01022
01023   /* Get the Capture 2 Register value */
01024     return (uint16_t)(temp | (uint16_t)(TIM5->CCR2L));
01025 }
01026
01027 /**
01028   * @brief  Gets the TIM5 Input Capture 3 value.
01029   * @param  None
01030   * @retval Capture Compare 3 Register value.
01031   */
01032 uint16_t TIM5_GetCapture3(void)
01033 {
01034    uint16_t temp = 0;
01035
01036    temp = ((uint16_t)TIM5->CCR3H << 8);
01037    /* Get the Capture 1 Register value */
01038     return (uint16_t)(temp | (uint16_t)(TIM5->CCR3L));
01039 }
01040
01041 /**
01042   * @brief  Gets the TIM5 Counter value.
01043   * @param  None
01044   * @retval Counter Register value.
01045   */
01046 uint16_t TIM5_GetCounter(void)
01047 {
01048   uint16_t tmpcntr = 0;
01049
01050   tmpcntr = ((uint16_t)TIM5->CNTRH << 8);
01051   /* Get the Counter Register value */
01052     return (uint16_t)(tmpcntr | (uint16_t)(TIM5->CNTRL));
01053 }
01054
01055
01056 /**
01057   * @brief  Gets the TIM5 Prescaler value.
01058   * @param  None
01059   * @retval Prescaler Register configuration value  @ref TIM5_Prescaler_TypeDef .
01060   */
01061 TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void)
01062 {
01063     /* Get the Prescaler Register value */
01064     return (TIM5_Prescaler_TypeDef)(TIM5->PSCR);
01065 }
01066
01067
01068
01069 /**
01070   * @brief  Checks whether the specified TIM5 flag is set or not.
01071   * @param   TIM5_FLAG specifies the flag to check.
01072   * This parameter can be one of the following values:
01073   *                       - TIM5_FLAG_UPDATE: TIM5 update Flag
01074   *                       - TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
01075   *                       - TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
01076   *                       - TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
01077   *                       - TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
01078   *                       - TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
01079   *                       - TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
01080   * @retval FlagStatus The new state of TIM5_FLAG (SET or RESET).
01081   */
01082 FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG)
01083 {
01084     FlagStatus bitstatus = RESET;
01085     uint8_t tim5_flag_l, tim5_flag_h;
01086
01087     /* Check the parameters */
01088     assert_param(IS_TIM5_GET_FLAG_OK(TIM5_FLAG));
01089
01090     tim5_flag_l= (uint8_t)(TIM5->SR1 & (uint8_t)TIM5_FLAG);
01091     tim5_flag_h= (uint8_t)((uint16_t)TIM5_FLAG >> 8);
01092
01093     if (((tim5_flag_l)|(uint8_t)(TIM5->SR2 & tim5_flag_h)) != RESET )
01094     {
01095         bitstatus = SET;
01096     }
01097     else
01098     {
01099         bitstatus = RESET;
01100     }
01101     return (FlagStatus)bitstatus;
01102 }
01103
01104
01105 /**
01106   * @brief  Clears the TIM5’s pending flags.
01107   * @param   TIM5_FLAG specifies the flag to clear.
01108   * This parameter can be one of the following values:
01109   *                       - TIM5_FLAG_UPDATE: TIM5 update Flag
01110   *                       - TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag
01111   *                       - TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag
01112   *                       - TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag
01113   *                       - TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag
01114   *                       - TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag
01115   *                       - TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag
01116   * @retval None.
01117   */
01118 void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG)
01119 {
01120     /* Check the parameters */
01121     assert_param(IS_TIM5_CLEAR_FLAG_OK(TIM5_FLAG));
01122
01123     /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
01124     TIM5->SR1 = (uint8_t)(~((uint8_t)(TIM5_FLAG)));
01125     TIM5->SR2 &= (uint8_t)(~((uint8_t)((uint16_t)TIM5_FLAG >> 8)));
01126 }
01127
01128
01129 /**
01130   * @brief  Checks whether the TIM5 interrupt has occurred or not.
01131   * @param   TIM5_IT specifies the TIM5 interrupt source to check.
01132   * This parameter can be one of the following values:
01133   *                       - TIM5_IT_UPDATE: TIM5 update Interrupt source
01134   *                       - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
01135   *                       - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
01136   *                       - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
01137   * @retval ITStatus The new state of the TIM5_IT(SET or RESET).
01138   */
01139
01140 ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT)
01141 {
01142     ITStatus bitstatus = RESET;
01143     uint8_t TIM5_itStatus = 0, TIM5_itEnable = 0;
01144
01145     /* Check the parameters */
01146     assert_param(IS_TIM5_GET_IT_OK(TIM5_IT));
01147
01148     TIM5_itStatus = (uint8_t)(TIM5->SR1 & TIM5_IT);
01149
01150     TIM5_itEnable = (uint8_t)(TIM5->IER & TIM5_IT);
01151
01152     if ((TIM5_itStatus != (uint8_t)RESET ) && (TIM5_itEnable != (uint8_t)RESET ))
01153     {
01154         bitstatus = SET;
01155     }
01156     else
01157     {
01158         bitstatus = RESET;
01159     }
01160     return (ITStatus)(bitstatus);
01161 }
01162
01163
01164 /**
01165   * @brief  Clears the TIM5's interrupt pending bits.
01166   * @param   TIM5_IT specifies the pending bit to clear.
01167   * This parameter can be one of the following values:
01168   *                       - TIM5_IT_UPDATE: TIM5 update Interrupt source
01169   *                       - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source
01170   *                       - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source
01171   *                       - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source
01172   * @retval None.
01173   */
01174 void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT)
01175 {
01176     /* Check the parameters */
01177     assert_param(IS_TIM5_IT_OK(TIM5_IT));
01178
01179     /* Clear the IT pending Bit */
01180     TIM5->SR1 = (uint8_t)(~TIM5_IT);
01181 }
01182
01183
01184 /**
01185   * @brief  Configure the TI1 as Input.
01186   * @param   TIM5_ICPolarity  The Input Polarity.
01187   * This parameter can be one of the following values:
01188   *                       - TIM5_ICPOLARITY_FALLING
01189   *                       - TIM5_ICPOLARITY_RISING
01190   * @param   TIM5_ICSelection specifies the input to be used.
01191   * This parameter can be one of the following values:
01192   *                       - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 1 is selected to
01193   *                         be connected to IC1.
01194   *                       - TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 1 is selected to
01195   *                         be connected to IC2.
01196   * @param   TIM5_ICFilter Specifies the Input Capture Filter.
01197   * This parameter must be a value between 0x00 and 0x0F.
01198   * @retval None
01199   */
01200 static void TI1_Config(uint8_t TIM5_ICPolarity,
01201                        uint8_t TIM5_ICSelection,
01202                        uint8_t TIM5_ICFilter)
01203 {
01204     /* Disable the Channel 1: Reset the CCE Bit */
01205     TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E);
01206
01207     /* Select the Input and set the filter */
01208     TIM5->CCMR1  = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF )))
01209                              | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4))));
01210
01211     /* Select the Polarity */
01212     if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING)
01213     {
01214         TIM5->CCER1 |= TIM5_CCER1_CC1P ;
01215     }
01216     else
01217     {
01218         TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ;
01219     }
01220     /* Set the CCE Bit */
01221     TIM5->CCER1 |=  TIM5_CCER1_CC1E;
01222 }
01223
01224
01225 /**
01226   * @brief  Configure the TI2 as Input.
01227   * @param   TIM5_ICPolarity  The Input Polarity.
01228   * This parameter can be one of the following values:
01229   *                       - TIM5_ICPOLARITY_FALLING
01230   *                       - TIM5_ICPOLARITY_RISING
01231   * @param   TIM5_ICSelection specifies the input to be used.
01232   * This parameter can be one of the following values:
01233   *                       - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 2 is selected to
01234   *                         be connected to IC2.
01235   *                       - TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 2 is selected to
01236   *                         be connected to IC1.
01237   * @param   TIM5_ICFilter Specifies the Input Capture Filter.
01238   * This parameter must be a value between 0x00 and 0x0F.
01239   * @retval None
01240   */
01241 static void TI2_Config(uint8_t TIM5_ICPolarity,
01242                        uint8_t TIM5_ICSelection,
01243                        uint8_t TIM5_ICFilter)
01244 {
01245     /* Disable the Channel 2: Reset the CCE Bit */
01246     TIM5->CCER1 &=  (uint8_t)(~TIM5_CCER1_CC2E);
01247
01248     /* Select the Input and set the filter */
01249     TIM5->CCMR2  = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF)))
01250                              | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4))));
01251
01252
01253     /* Select the Polarity */
01254     if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING)
01255     {
01256         TIM5->CCER1 |= TIM5_CCER1_CC2P ;
01257     }
01258     else
01259     {
01260         TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ;
01261     }
01262
01263     /* Set the CCE Bit */
01264     TIM5->CCER1 |=  TIM5_CCER1_CC2E;
01265
01266 }
01267
01268 /**
01269   * @brief  Configure the TI3 as Input.
01270   * @param   TIM5_ICPolarity  The Input Polarity.
01271   * This parameter can be one of the following values:
01272   *                       - TIM5_ICPOLARITY_FALLING
01273   *                       - TIM5_ICPOLARITY_RISING
01274   * @param   TIM5_ICSelection specifies the input to be used.
01275   * This parameter can be one of the following values:
01276   *                       - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 3 is selected to
01277   *                         be connected to IC3.
01278   * @param   TIM5_ICFilter Specifies the Input Capture Filter.
01279   * This parameter must be a value between 0x00 and 0x0F.
01280   * @retval None
01281   */
01282 static void TI3_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection,
01283                        uint8_t TIM5_ICFilter)
01284 {
01285     /* Disable the Channel 3: Reset the CCE Bit */
01286     TIM5->CCER2 &=  (uint8_t)(~TIM5_CCER2_CC3E);
01287
01288     /* Select the Input and set the filter */
01289     TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF)))
01290                             | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4))));
01291
01292
01293     /* Select the Polarity */
01294     if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING)
01295     {
01296         TIM5->CCER2 |= TIM5_CCER2_CC3P ;
01297     }
01298     else
01299     {
01300         TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3P) ;
01301     }
01302     /* Set the CCE Bit */
01303     TIM5->CCER2 |=  TIM5_CCER2_CC3E;
01304 }
01305 /**
01306   * @brief  Enables the TIM5 internal Clock.
01307   * @par Parameters:
01308         * None
01309   * @retval None
01310   */
01311 void TIM5_InternalClockConfig(void)
01312 {
01313     /* Disable slave mode to clock the prescaler directly with the internal clock */
01314     TIM5->SMCR &=  (uint8_t)(~TIM5_SMCR_SMS);
01315 }
01316
01317 /**
01318   * @brief  Selects the TIM5 Trigger Output Mode.
01319   * @param   TIM5_TRGOSource : Specifies the Trigger Output source.
01320   * This parameter can be one of the @ref TIM5_TRGOSource_TypeDef enumeration.
01321   * @retval None
01322   */
01323 void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
01324 {
01325     uint8_t tmpcr2 = 0;
01326
01327     /* Check the parameters */
01328     assert_param(IS_TIM5_TRGO_SOURCE_OK(TIM5_TRGOSource));
01329
01330     tmpcr2 = TIM5->CR2;
01331
01332     /* Reset the MMS Bits */
01333     tmpcr2 &= (uint8_t)(~TIM5_CR2_MMS);
01334
01335     /* Select the TRGO source */
01336     tmpcr2 |=  (uint8_t)TIM5_TRGOSource;
01337
01338     TIM5->CR2 = tmpcr2;
01339 }
01340 /**
01341   * @brief  Selects the TIM5 Slave Mode.
01342   * @param   TIM5_SlaveMode : Specifies the TIM5 Slave Mode.
01343   * This parameter can be one of the @ref TIM5_SlaveMode_TypeDef enumeration.
01344   * @retval None
01345   */
01346 void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
01347 {
01348     uint8_t tmpsmcr = 0;
01349
01350     /* Check the parameters */
01351     assert_param(IS_TIM5_SLAVE_MODE_OK(TIM5_SlaveMode));
01352
01353     tmpsmcr = TIM5->SMCR;
01354
01355     /* Reset the SMS Bits */
01356     tmpsmcr &= (uint8_t)(~TIM5_SMCR_SMS);
01357
01358     /* Select the Slave Mode */
01359     tmpsmcr |= (uint8_t)TIM5_SlaveMode;
01360
01361     TIM5->SMCR = tmpsmcr;
01362 }
01363 /**
01364   * @brief  Selects the TIM5 Input Trigger source.
01365   * @param   TIM5_InputTriggerSource : Specifies Input Trigger source.
01366   * This parameter can be one of the @ref TIM5_TS_TypeDef enumeration.
01367   * @retval None
01368   */
01369 void TIM5_SelectInputTrigger(TIM5_TS_TypeDef TIM5_InputTriggerSource)
01370 {
01371     uint8_t tmpsmcr = 0;
01372
01373     /* Check the parameters */
01374     assert_param(IS_TIM5_TRIGGER_SELECTION_OK(TIM5_InputTriggerSource));
01375
01376     tmpsmcr = TIM5->SMCR;
01377
01378     /* Select the Tgigger Source */
01379     tmpsmcr &= (uint8_t)(~TIM5_SMCR_TS);
01380     tmpsmcr |= (uint8_t)TIM5_InputTriggerSource;
01381
01382     TIM5->SMCR = (uint8_t)tmpsmcr;
01383 }
01384 /**
01385   * @brief  Configures the TIM5 Encoder Interface.
01386   * @param   TIM5_EncoderMode : Specifies the TIM5 Encoder Mode.
01387   * This parameter can be one of the @ref TIM5_EncoderMode_TypeDef enumeration.
01388   * @param   TIM5_IC1Polarity : Specifies the IC1 Polarity.
01389   * This parameter can be one of the @ref TIM5_ICPolarity_TypeDef enumeration.
01390   * @param   TIM5_IC2Polarity : Specifies the IC2 Polarity.
01391   * This parameter can be one of the @ref TIM5_ICPolarity_TypeDef enumeration.
01392   * @retval None
01393   */
01394 void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode,
01395                                  TIM5_ICPolarity_TypeDef TIM5_IC1Polarity,
01396                                  TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
01397 {
01398     uint8_t tmpsmcr = 0;
01399     uint8_t tmpccmr1 = 0;
01400     uint8_t tmpccmr2 = 0;
01401
01402     /* Check the parameters */
01403     assert_param(IS_TIM5_ENCODER_MODE_OK(TIM5_EncoderMode));
01404     assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_IC1Polarity));
01405     assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_IC2Polarity));
01406
01407     tmpsmcr = TIM5->SMCR;
01408     tmpccmr1 = TIM5->CCMR1;
01409     tmpccmr2 = TIM5->CCMR2;
01410
01411     /* Set the encoder Mode */
01412     tmpsmcr &= (uint8_t)(TIM5_SMCR_MSM | TIM5_SMCR_TS)  ;
01413     tmpsmcr |= (uint8_t)TIM5_EncoderMode;
01414
01415     /* Select the Capture Compare 1 and the Capture Compare 2 as input */
01416     tmpccmr1 &= (uint8_t)(~TIM5_CCMR_CCxS);
01417     tmpccmr2 &= (uint8_t)(~TIM5_CCMR_CCxS);
01418     tmpccmr1 |= TIM5_CCMR_TIxDirect_Set;
01419     tmpccmr2 |= TIM5_CCMR_TIxDirect_Set;
01420
01421     /* Set the TI1 and the TI2 Polarities */
01422     if (TIM5_IC1Polarity == TIM5_ICPOLARITY_FALLING)
01423     {
01424         TIM5->CCER1 |= TIM5_CCER1_CC1P ;
01425     }
01426     else
01427     {
01428         TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ;
01429     }
01430
01431     if (TIM5_IC2Polarity == TIM5_ICPOLARITY_FALLING)
01432     {
01433         TIM5->CCER1 |= TIM5_CCER1_CC2P ;
01434     }
01435     else
01436     {
01437         TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ;
01438     }
01439
01440     TIM5->SMCR = tmpsmcr;
01441     TIM5->CCMR1 = tmpccmr1;
01442     TIM5->CCMR2 = tmpccmr2;
01443 }
01444
01445 /**
01446   * @}
01447   */
01448
01449 /**
01450   * @}
01451   */
01452 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim5.h Source File

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stm8s_tim5.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim5.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the TIM5 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_TIM5_H
00024 #define __STM8S_TIM5_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /* Exported types ------------------------------------------------------------*/
00034
00035
00036 /** TIM5 Forced Action */
00037 typedef enum
00038 {
00039     TIM5_FORCEDACTION_ACTIVE           =((uint8_t)0x50),
00040     TIM5_FORCEDACTION_INACTIVE         =((uint8_t)0x40)
00041 }TIM5_ForcedAction_TypeDef;
00042
00043 #define IS_TIM5_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM5_FORCEDACTION_ACTIVE) || \
00044                                        ((ACTION) == TIM5_FORCEDACTION_INACTIVE))
00045
00046 /** TIM5 Prescaler */
00047 typedef enum
00048 {
00049     TIM5_PRESCALER_1     =((uint8_t)0x00),
00050     TIM5_PRESCALER_2      =((uint8_t)0x01),
00051     TIM5_PRESCALER_4      =((uint8_t)0x02),
00052     TIM5_PRESCALER_8      =((uint8_t)0x03),
00053     TIM5_PRESCALER_16     =((uint8_t)0x04),
00054     TIM5_PRESCALER_32     =((uint8_t)0x05),
00055     TIM5_PRESCALER_64     =((uint8_t)0x06),
00056     TIM5_PRESCALER_128    =((uint8_t)0x07),
00057     TIM5_PRESCALER_256    =((uint8_t)0x08),
00058     TIM5_PRESCALER_512    =((uint8_t)0x09),
00059     TIM5_PRESCALER_1024   =((uint8_t)0x0A),
00060     TIM5_PRESCALER_2048   =((uint8_t)0x0B),
00061     TIM5_PRESCALER_4096   =((uint8_t)0x0C),
00062     TIM5_PRESCALER_8192   =((uint8_t)0x0D),
00063     TIM5_PRESCALER_16384  =((uint8_t)0x0E),
00064     TIM5_PRESCALER_32768  =((uint8_t)0x0F)
00065 }TIM5_Prescaler_TypeDef;
00066
00067 #define IS_TIM5_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM5_PRESCALER_1) || \
00068                  ((PRESCALER) == TIM5_PRESCALER_2     ) || \
00069                  ((PRESCALER) == TIM5_PRESCALER_4     ) || \
00070                  ((PRESCALER) == TIM5_PRESCALER_8    ) || \
00071                  ((PRESCALER) == TIM5_PRESCALER_16    ) || \
00072                  ((PRESCALER) == TIM5_PRESCALER_32      ) || \
00073                  ((PRESCALER) == TIM5_PRESCALER_64     ) || \
00074                  ((PRESCALER) == TIM5_PRESCALER_128    ) || \
00075                  ((PRESCALER) == TIM5_PRESCALER_256    ) || \
00076                  ((PRESCALER) == TIM5_PRESCALER_512    ) || \
00077                  ((PRESCALER) == TIM5_PRESCALER_1024   ) || \
00078                  ((PRESCALER) == TIM5_PRESCALER_2048  ) || \
00079                  ((PRESCALER) == TIM5_PRESCALER_4096  ) || \
00080                  ((PRESCALER) == TIM5_PRESCALER_8192  ) || \
00081                  ((PRESCALER) == TIM5_PRESCALER_16384  ) || \
00082                  ((PRESCALER) == TIM5_PRESCALER_32768  ))
00083
00084 /** TIM5 Output Compare and PWM modes */
00085 typedef enum
00086 {
00087     TIM5_OCMODE_TIMING     =((uint8_t)0x00),
00088     TIM5_OCMODE_ACTIVE     =((uint8_t)0x10),
00089     TIM5_OCMODE_INACTIVE   =((uint8_t)0x20),
00090     TIM5_OCMODE_TOGGLE     =((uint8_t)0x30),
00091     TIM5_OCMODE_PWM1       =((uint8_t)0x60),
00092     TIM5_OCMODE_PWM2       =((uint8_t)0x70)
00093 }TIM5_OCMode_TypeDef;
00094
00095 #define IS_TIM5_OC_MODE_OK(MODE) (((MODE) ==  TIM5_OCMODE_TIMING) || \
00096                                   ((MODE) == TIM5_OCMODE_ACTIVE) || \
00097                                   ((MODE) == TIM5_OCMODE_INACTIVE) || \
00098                                   ((MODE) == TIM5_OCMODE_TOGGLE)|| \
00099                                   ((MODE) == TIM5_OCMODE_PWM1) || \
00100                                   ((MODE) == TIM5_OCMODE_PWM2))
00101
00102 #define IS_TIM5_OCM_OK(MODE)(((MODE) ==  TIM5_OCMODE_TIMING) || \
00103                              ((MODE) == TIM5_OCMODE_ACTIVE) || \
00104                              ((MODE) == TIM5_OCMODE_INACTIVE) || \
00105                              ((MODE) == TIM5_OCMODE_TOGGLE)|| \
00106                              ((MODE) == TIM5_OCMODE_PWM1) || \
00107                              ((MODE) == TIM5_OCMODE_PWM2) ||  \
00108                              ((MODE) == (uint8_t)TIM5_FORCEDACTION_ACTIVE) || \
00109                              ((MODE) == (uint8_t)TIM5_FORCEDACTION_INACTIVE))
00110
00111 /** TIM5 One Pulse Mode */
00112 typedef enum
00113 {
00114     TIM5_OPMODE_SINGLE                 =((uint8_t)0x01),
00115     TIM5_OPMODE_REPETITIVE             =((uint8_t)0x00)
00116 }TIM5_OPMode_TypeDef;
00117
00118 #define IS_TIM5_OPM_MODE_OK(MODE) (((MODE) == TIM5_OPMODE_SINGLE) || \
00119                                    ((MODE) == TIM5_OPMODE_REPETITIVE))
00120
00121 /** TIM5 Channel */
00122 typedef enum
00123 {
00124     TIM5_CHANNEL_1                     =((uint8_t)0x00),
00125     TIM5_CHANNEL_2                     =((uint8_t)0x01),
00126     TIM5_CHANNEL_3                     =((uint8_t)0x02)
00127 }TIM5_Channel_TypeDef;
00128
00129 #define IS_TIM5_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM5_CHANNEL_1) || \
00130                                      ((CHANNEL) == TIM5_CHANNEL_2) || \
00131                                      ((CHANNEL) == TIM5_CHANNEL_3))
00132
00133 #define IS_TIM5_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM5_CHANNEL_1) || \
00134                                           ((CHANNEL) == TIM5_CHANNEL_2))
00135
00136 /** TIM5 Output Compare Polarity */
00137 typedef enum
00138 {
00139     TIM5_OCPOLARITY_HIGH               =((uint8_t)0x00),
00140     TIM5_OCPOLARITY_LOW                =((uint8_t)0x22)
00141 }TIM5_OCPolarity_TypeDef;
00142
00143 #define IS_TIM5_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM5_OCPOLARITY_HIGH) || \
00144                                        ((POLARITY) == TIM5_OCPOLARITY_LOW))
00145
00146 /** TIM5 Output Compare states */
00147 typedef enum
00148 {
00149     TIM5_OUTPUTSTATE_DISABLE           =((uint8_t)0x00),
00150     TIM5_OUTPUTSTATE_ENABLE            =((uint8_t)0x11)
00151 }TIM5_OutputState_TypeDef;
00152
00153 #define IS_TIM5_OUTPUT_STATE_OK(STATE) (((STATE) == TIM5_OUTPUTSTATE_DISABLE) || \
00154                                      ((STATE) == TIM5_OUTPUTSTATE_ENABLE))
00155
00156 /** TIM5 Input Capture Polarity */
00157 typedef enum
00158 {
00159     TIM5_ICPOLARITY_RISING            =((uint8_t)0x00),
00160     TIM5_ICPOLARITY_FALLING           =((uint8_t)0x44)
00161 }TIM5_ICPolarity_TypeDef;
00162
00163 #define IS_TIM5_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM5_ICPOLARITY_RISING) || \
00164                                        ((POLARITY) == TIM5_ICPOLARITY_FALLING))
00165
00166 /** TIM5 Input Capture Selection */
00167 typedef enum
00168 {
00169     TIM5_ICSELECTION_DIRECTTI          =((uint8_t)0x01),
00170     TIM5_ICSELECTION_INDIRECTTI        =((uint8_t)0x02),
00171     TIM5_ICSELECTION_TRGI              =((uint8_t)0x03)
00172 }TIM5_ICSelection_TypeDef;
00173
00174 #define IS_TIM5_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM5_ICSELECTION_DIRECTTI) || \
00175                                            ((SELECTION) == TIM5_ICSELECTION_INDIRECTTI) || \
00176                                            ((SELECTION) == TIM5_ICSELECTION_TRGI))
00177
00178 #define IS_TIM5_IC_SELECTION1_OK(SELECTION) (((SELECTION) == TIM5_ICSELECTION_DIRECTTI) || \
00179                                              ((SELECTION) == TIM5_ICSELECTION_TRGI))
00180
00181 /** TIM5 Input Capture Prescaler */
00182 typedef enum
00183 {
00184     TIM5_ICPSC_DIV1                    =((uint8_t)0x00),
00185     TIM5_ICPSC_DIV2                    =((uint8_t)0x04),
00186     TIM5_ICPSC_DIV4                    =((uint8_t)0x08),
00187     TIM5_ICPSC_DIV8                    =((uint8_t)0x0C)
00188 }TIM5_ICPSC_TypeDef;
00189
00190 #define IS_TIM5_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM5_ICPSC_DIV1) || \
00191                                          ((PRESCALER) == TIM5_ICPSC_DIV2) || \
00192                                          ((PRESCALER) == TIM5_ICPSC_DIV4) || \
00193                                          ((PRESCALER) == TIM5_ICPSC_DIV8))
00194
00195 /** TIM5 Input Capture Filer Value */
00196 #define IS_TIM5_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)
00197
00198 /** TIM5 interrupt sources */
00199 typedef enum
00200 {
00201     TIM5_IT_UPDATE                     =((uint8_t)0x01),
00202     TIM5_IT_CC1                        =((uint8_t)0x02),
00203     TIM5_IT_CC2                        =((uint8_t)0x04),
00204     TIM5_IT_CC3                        =((uint8_t)0x08),
00205     TIM5_IT_TRIGGER                    = ((uint8_t)0x40)
00206 }TIM5_IT_TypeDef;
00207
00208 #define IS_TIM5_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x4F))
00209
00210 #define IS_TIM5_GET_IT_OK(IT) (((IT) == TIM5_IT_UPDATE) || \
00211                             ((IT) == TIM5_IT_CC1) || \
00212                             ((IT) == TIM5_IT_CC2) || \
00213                             ((IT) == TIM5_IT_CC3) || \
00214                             ((IT) == TIM5_IT_TRIGGER))
00215
00216 /** TIM5 Prescaler Reload Mode */
00217 typedef enum
00218 {
00219     TIM5_PSCRELOADMODE_UPDATE          =((uint8_t)0x00),
00220     TIM5_PSCRELOADMODE_IMMEDIATE       =((uint8_t)0x01)
00221 }TIM5_PSCReloadMode_TypeDef;
00222
00223 #define IS_TIM5_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM5_PSCRELOADMODE_UPDATE) || \
00224                                           ((RELOAD) == TIM5_PSCRELOADMODE_IMMEDIATE))
00225
00226 /** TIM5 Event Source */
00227 typedef enum
00228 {
00229     TIM5_EVENTSOURCE_UPDATE            =((uint8_t)0x01),
00230     TIM5_EVENTSOURCE_CC1               =((uint8_t)0x02),
00231     TIM5_EVENTSOURCE_CC2               =((uint8_t)0x04),
00232     TIM5_EVENTSOURCE_CC3               =((uint8_t)0x08),
00233     TIM5_EVENTSOURCE_TRIGGER           = ((uint8_t)0x40)
00234 }TIM5_EventSource_TypeDef;
00235
00236 #define IS_TIM5_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))
00237
00238 /** TIM5 Update Source */
00239 typedef enum
00240 {
00241     TIM5_UPDATESOURCE_GLOBAL           =((uint8_t)0x00),
00242     TIM5_UPDATESOURCE_REGULAR          =((uint8_t)0x01)
00243 }TIM5_UpdateSource_TypeDef;
00244
00245
00246 #define IS_TIM5_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM5_UPDATESOURCE_GLOBAL) || \
00247                                        ((SOURCE) == TIM5_UPDATESOURCE_REGULAR))
00248
00249 /**
00250   * @brief  TIM5 Trigger Output Source
00251   */
00252 typedef enum
00253 {
00254     TIM5_TRGOSOURCE_RESET   = ((uint8_t)0x00),   /*!< Trigger Output source = Reset*/
00255     TIM5_TRGOSOURCE_ENABLE  = ((uint8_t)0x10),   /*!< Trigger Output source = TIM5 is enabled*/
00256     TIM5_TRGOSOURCE_UPDATE  = ((uint8_t)0x20),   /*!< Trigger Output source = Update event*/
00257     TIM5_TRGOSOURCE_OC1     = ((uint8_t)0x30),   /*!< Trigger Output source = output compare channel1  */
00258     TIM5_TRGOSOURCE_OC1REF  = ((uint8_t)0x40),   /*!< Trigger Output source = output compare channel 1 reference */
00259     TIM5_TRGOSOURCE_OC2REF  = ((uint8_t)0x50)    /*!< Trigger Output source = output compare channel 2 reference */
00260 }TIM5_TRGOSource_TypeDef;
00261
00262 /**
00263   * @brief  Macro TIM5 TRGO source
00264   */
00265 #define IS_TIM5_TRGO_SOURCE_OK(SOURCE) \
00266    (((SOURCE) == TIM5_TRGOSOURCE_RESET)  || \
00267     ((SOURCE) == TIM5_TRGOSOURCE_ENABLE) || \
00268     ((SOURCE) == TIM5_TRGOSOURCE_UPDATE) || \
00269     ((SOURCE) == TIM5_TRGOSOURCE_OC1)    || \
00270     ((SOURCE) == TIM5_TRGOSOURCE_OC1REF) || \
00271     ((SOURCE) == TIM5_TRGOSOURCE_OC2REF))
00272
00273 /** TIM5 Flags */
00274 typedef enum
00275 {
00276     TIM5_FLAG_UPDATE                   =((uint16_t)0x0001),
00277     TIM5_FLAG_CC1                      =((uint16_t)0x0002),
00278     TIM5_FLAG_CC2                      =((uint16_t)0x0004),
00279     TIM5_FLAG_CC3                      =((uint16_t)0x0008),
00280     TIM5_FLAG_TRIGGER                  = ((uint16_t)0x0040),
00281     TIM5_FLAG_CC1OF                    =((uint16_t)0x0200),
00282     TIM5_FLAG_CC2OF                    =((uint16_t)0x0400),
00283     TIM5_FLAG_CC3OF                    =((uint16_t)0x0800)
00284 }TIM5_FLAG_TypeDef;
00285
00286 #define IS_TIM5_GET_FLAG_OK(FLAG) (((FLAG) == TIM5_FLAG_UPDATE) || \
00287                                 ((FLAG) == TIM5_FLAG_CC1) || \
00288                                 ((FLAG) == TIM5_FLAG_CC2) || \
00289                                 ((FLAG) == TIM5_FLAG_CC3) || \
00290                                 ((FLAG) == TIM5_FLAG_TRIGGER) || \
00291                                 ((FLAG) == TIM5_FLAG_CC1OF) || \
00292                                 ((FLAG) == TIM5_FLAG_CC2OF) || \
00293                                 ((FLAG) == TIM5_FLAG_CC3OF))
00294
00295 #define IS_TIM5_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))
00296
00297
00298 /**
00299   * @brief  TIM5 Slave Mode
00300   */
00301 typedef enum
00302 {
00303     TIM5_SLAVEMODE_RESET      = ((uint8_t)0x04),   /*!< Slave Mode Selection  = Reset*/
00304     TIM5_SLAVEMODE_GATED      = ((uint8_t)0x05),   /*!< Slave Mode Selection  = Gated*/
00305     TIM5_SLAVEMODE_TRIGGER    = ((uint8_t)0x06),   /*!< Slave Mode Selection  = Trigger*/
00306     TIM5_SLAVEMODE_EXTERNAL1  = ((uint8_t)0x07)  /*!< Slave Mode Selection  = External 1*/
00307 }TIM5_SlaveMode_TypeDef;
00308
00309 /**
00310   * @brief  Macro TIM5 Slave mode
00311   */
00312 #define IS_TIM5_SLAVE_MODE_OK(MODE) \
00313    (((MODE) == TIM5_SLAVEMODE_RESET)   || \
00314     ((MODE) == TIM5_SLAVEMODE_GATED)   || \
00315     ((MODE) == TIM5_SLAVEMODE_TRIGGER) || \
00316     ((MODE) == TIM5_SLAVEMODE_EXTERNAL1))
00317
00318 /**
00319   * @brief  TIM5 Internal Trigger Selection
00320   */
00321 typedef enum
00322 {
00323     TIM5_TS_TIM6  = ((uint8_t)0x00), /*!< TRIG Input source =  TIM6 TRIG Output  */
00324     TIM5_TS_TIM1  = ((uint8_t)0x03) /*!< TRIG Input source =  TIM1 TRIG Output  */
00325 }TIM5_TS_TypeDef;
00326
00327 /**
00328   * @brief  Macro TIM5  Trigger Selection
00329   */
00330 #define IS_TIM5_TRIGGER_SELECTION_OK(SELECTION) \
00331    (((SELECTION) == TIM5_TS_TIM6)  || \
00332     ((SELECTION) == TIM5_TS_TIM1)  )
00333
00334
00335 #define IS_TIM5_TIX_TRIGGER_SELECTION_OK(SELECTION) \
00336    (((SELECTION) == TIM5_TS_TI1F_ED) || \
00337     ((SELECTION) == TIM5_TS_TI1FP1)  || \
00338     ((SELECTION) == TIM5_TS_TI2FP2))
00339
00340
00341 /**
00342   * @brief  TIM5 Encoder Mode
00343   */
00344 typedef enum
00345 {
00346     TIM5_ENCODERMODE_TI1    = ((uint8_t)0x01),   /*!< Encoder mode 1*/
00347     TIM5_ENCODERMODE_TI2    = ((uint8_t)0x02),   /*!< Encoder mode 2*/
00348     TIM5_ENCODERMODE_TI12   = ((uint8_t)0x03)    /*!< Encoder mode 3*/
00349 }TIM5_EncoderMode_TypeDef;
00350 /**
00351   * @brief  Macro TIM5 encoder mode
00352   */
00353 #define IS_TIM5_ENCODER_MODE_OK(MODE) \
00354    (((MODE) == TIM5_ENCODERMODE_TI1) || \
00355     ((MODE) == TIM5_ENCODERMODE_TI2) || \
00356     ((MODE) == TIM5_ENCODERMODE_TI12))
00357
00358 /**
00359   * @brief  TIM5 External Trigger Prescaler
00360   */
00361 typedef enum
00362 {
00363     TIM5_EXTTRGPSC_OFF   = ((uint8_t)0x00),   /*!< No External Trigger prescaler  */
00364     TIM5_EXTTRGPSC_DIV2  = ((uint8_t)0x10),   /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
00365     TIM5_EXTTRGPSC_DIV4  = ((uint8_t)0x20),   /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
00366     TIM5_EXTTRGPSC_DIV8  = ((uint8_t)0x30)    /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
00367 }TIM5_ExtTRGPSC_TypeDef;
00368
00369 /**
00370   * @brief  Macro TIM5 external trigger prescaler
00371   */
00372 #define IS_TIM5_EXT_PRESCALER_OK(PRESCALER) \
00373    (((PRESCALER) == TIM5_EXTTRGPSC_OFF)  || \
00374     ((PRESCALER) == TIM5_EXTTRGPSC_DIV2) || \
00375     ((PRESCALER) == TIM5_EXTTRGPSC_DIV4) || \
00376     ((PRESCALER) == TIM5_EXTTRGPSC_DIV8))
00377
00378 /**
00379   * @brief  TIM5 External Trigger Polarity
00380   */
00381 typedef enum
00382 {
00383     TIM5_EXTTRGPOLARITY_INVERTED    = ((uint8_t)0x80),   /*!< External Trigger Polarity = inverted */
00384     TIM5_EXTTRGPOLARITY_NONINVERTED  = ((uint8_t)0x00)    /*!< External Trigger Polarity = non inverted */
00385 }TIM5_ExtTRGPolarity_TypeDef;
00386
00387 /**
00388   * @brief  Macro TIM5  Trigger Polarity
00389   */
00390 #define IS_TIM5_EXT_POLARITY_OK(POLARITY) \
00391    (((POLARITY) == TIM5_EXTTRGPOLARITY_INVERTED) || \
00392     ((POLARITY) == TIM5_EXTTRGPOLARITY_NONINVERTED))
00393
00394 /**
00395   * @brief  Macro TIM5 External Trigger Filter
00396   */
00397 #define IS_TIM5_EXT_FILTER_OK(EXTFILTER) ((EXTFILTER) <= 0x0F)
00398 /**
00399   * @}
00400   */
00401
00402 /* Exported macro ------------------------------------------------------------*/
00403
00404 /* Exported functions --------------------------------------------------------*/
00405
00406 /** @addtogroup TIM5_Exported_Functions
00407   * @{
00408   */
00409
00410 void TIM5_DeInit(void);
00411 void TIM5_TimeBaseInit(TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period);
00412 void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState,uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00413 void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState,uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00414 void TIM5_OC3Init(TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState,uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00415 void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection,  TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter);
00416 void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection,  TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter);
00417 void TIM5_Cmd(FunctionalState NewState);
00418 void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState);
00419 void TIM5_InternalClockConfig(void);
00420 void TIM5_UpdateDisableConfig(FunctionalState NewState);
00421 void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource);
00422 void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode);
00423 void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode);
00424 void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource);
00425 void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
00426 void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
00427 void TIM5_ForcedOC3Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
00428 void TIM5_ARRPreloadConfig(FunctionalState NewState);
00429 void TIM5_CCPreloadControl(FunctionalState NewState);
00430 void TIM5_OC1PreloadConfig(FunctionalState NewState);
00431 void TIM5_OC2PreloadConfig(FunctionalState NewState);
00432 void TIM5_OC3PreloadConfig(FunctionalState NewState);
00433 void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource);
00434 void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00435 void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00436 void TIM5_OC3PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
00437 void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState);
00438 void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode);
00439 void TIM5_SetCounter(uint16_t Counter);
00440 void TIM5_SetAutoreload(uint16_t Autoreload);
00441 void TIM5_SetCompare1(uint16_t Compare1);
00442 void TIM5_SetCompare2(uint16_t Compare2);
00443 void TIM5_SetCompare3(uint16_t Compare3);
00444 void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler);
00445 void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler);
00446 void TIM5_SetIC3Prescaler(TIM5_ICPSC_TypeDef TIM5_IC3Prescaler);
00447 uint16_t TIM5_GetCapture1(void);
00448 uint16_t TIM5_GetCapture2(void);
00449 uint16_t TIM5_GetCapture3(void);
00450 uint16_t TIM5_GetCounter(void);
00451 TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void);
00452 FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG);
00453 void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG);
00454 ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT);
00455 void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT);
00456 void TIM5_SelectInputTrigger(TIM5_TS_TypeDef TIM5_InputTriggerSource);
00457 void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode);
00458 void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity,TIM5_ICPolarity_TypeDef TIM5_IC2Polarity);
00459
00460
00461 /**
00462   * @}
00463   */
00464
00465 #endif /* __STM8S_TIM5_H */
00466
00467 /**
00468   * @}
00469   */
00470
00471 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim6.c Source File

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stm8s_tim6.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim6.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the TIM6 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm8s_tim6.h"
00025
00026 /** @addtogroup STM8S_StdPeriph_Driver
00027   * @{
00028   */
00029 /* Private typedef -----------------------------------------------------------*/
00030 /* Private define ------------------------------------------------------------*/
00031
00032
00033 /** @addtogroup STM8S_StdPeriph_Driver
00034   * @{
00035   */
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /**
00042   * @addtogroup TIM6_Public_Functions
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  Deinitializes the TIM6 peripheral registers to their default reset values.
00048   * @param  None
00049   * @retval None
00050   */
00051 void TIM6_DeInit(void)
00052 {
00053     TIM6->CR1   = TIM6_CR1_RESET_VALUE;
00054     TIM6->CR2   = TIM6_CR2_RESET_VALUE;
00055     TIM6->SMCR  = TIM6_SMCR_RESET_VALUE;
00056     TIM6->IER   = TIM6_IER_RESET_VALUE;
00057     TIM6->CNTR  = TIM6_CNTR_RESET_VALUE;
00058     TIM6->PSCR  = TIM6_PSCR_RESET_VALUE;
00059     TIM6->ARR   = TIM6_ARR_RESET_VALUE;
00060     TIM6->SR1   = TIM6_SR1_RESET_VALUE;
00061 }
00062
00063 /**
00064   * @brief  Initializes the TIM6 Time Base Unit according to the specified
00065   * parameters.
00066   * @param   TIM6_Prescaler : This parameter can be any of the @Ref TIM5_Prescaler_TypeDef enumeration.
00067   * @param   TIM6_Period : This parameter must be a value between 0x00 and 0xFF.
00068   * @retval None
00069   */
00070 void TIM6_TimeBaseInit(TIM6_Prescaler_TypeDef TIM6_Prescaler,
00071                        uint8_t TIM6_Period)
00072 {
00073     /* Check TIM6 prescaler value */
00074     assert_param(IS_TIM6_PRESCALER_OK(TIM6_Prescaler));
00075     /* Set the Autoreload value */
00076     TIM6->ARR = (uint8_t)(TIM6_Period);
00077     /* Set the Prescaler value */
00078     TIM6->PSCR = (uint8_t)(TIM6_Prescaler);
00079 }
00080
00081 /**
00082   * @brief  Enables or disables the TIM6 peripheral.
00083   * @param   NewState : The new state of the TIM6 peripheral.
00084   * This parameter can be any of the @ref FunctionalState enumeration.
00085   * @retval None
00086   */
00087 void TIM6_Cmd(FunctionalState NewState)
00088 {
00089     /* Check the parameters */
00090     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00091
00092     /* set or Reset the CEN Bit */
00093     if (NewState == ENABLE)
00094     {
00095         TIM6->CR1 |= TIM6_CR1_CEN ;
00096     }
00097     else
00098     {
00099         TIM6->CR1 &= (uint8_t)(~TIM6_CR1_CEN) ;
00100     }
00101 }
00102
00103 /**
00104   * @brief  Enables or Disables the TIM6 Update event.
00105   * @param   NewState : The new state of the TIM6 peripheral Preload register.
00106   * This parameter can be any of the @ref FunctionalState enumeration.
00107   * @retval None
00108   */
00109 void TIM6_UpdateDisableConfig(FunctionalState NewState)
00110 {
00111     /* Check the parameters */
00112     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00113
00114     /* Set or Reset the UDIS Bit */
00115     if (NewState == ENABLE)
00116     {
00117         TIM6->CR1 |= TIM6_CR1_UDIS ;
00118     }
00119     else
00120     {
00121         TIM6->CR1 &= (uint8_t)(~TIM6_CR1_UDIS) ;
00122     }
00123 }
00124
00125 /**
00126   * @brief  Selects the TIM6 Update Request Interrupt source.
00127   * @param   TIM6_UpdateSource : Specifies the Update source.
00128   * This parameter can be one of the @ref TIM6_UpdateSource_TypeDef enumeration.
00129   * @retval None
00130   */
00131 void TIM6_UpdateRequestConfig(TIM6_UpdateSource_TypeDef TIM6_UpdateSource)
00132 {
00133     /* Check the parameters */
00134     assert_param(IS_TIM6_UPDATE_SOURCE_OK(TIM6_UpdateSource));
00135
00136     /* Set or Reset the URS Bit */
00137     if (TIM6_UpdateSource == TIM6_UPDATESOURCE_REGULAR)
00138     {
00139         TIM6->CR1 |= TIM6_CR1_URS ;
00140     }
00141     else
00142     {
00143         TIM6->CR1 &= (uint8_t)(~TIM6_CR1_URS) ;
00144     }
00145 }
00146
00147 /**
00148   * @brief  Selects the TIM6’s One Pulse Mode.
00149   * @param   TIM6_OPMode : Specifies the OPM Mode to be used.
00150   * This parameter can be one of the @ref TIM6_OPMode_TypeDef enumeration.
00151   * @retval None
00152   */
00153 void TIM6_SelectOnePulseMode(TIM6_OPMode_TypeDef TIM6_OPMode)
00154 {
00155     /* Check the parameters */
00156     assert_param(IS_TIM6_OPM_MODE_OK(TIM6_OPMode));
00157
00158     /* Set or Reset the OPM Bit */
00159     if (TIM6_OPMode == TIM6_OPMODE_SINGLE)
00160     {
00161         TIM6->CR1 |= TIM6_CR1_OPM ;
00162     }
00163     else
00164     {
00165         TIM6->CR1 &= (uint8_t)(~TIM6_CR1_OPM) ;
00166     }
00167
00168 }
00169
00170 /**
00171   * @brief  Configures the TIM6 Prescaler.
00172   * @param   Prescaler : Specifies the Prescaler Register value
00173   * This parameter can be one of the @ref TIM6_Prescaler_TypeDef enumeration.
00174   * @param   TIM6_PSCReloadMode : Specifies the TIM6 Prescaler Reload mode.
00175   * This parameter can be one of the @ref TIM6_PSCReloadMode_TypeDef enumeration.
00176   * @retval None
00177   */
00178 void TIM6_PrescalerConfig(TIM6_Prescaler_TypeDef Prescaler,
00179                           TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)
00180 {
00181     /* Check the parameters */
00182     assert_param(IS_TIM6_PRESCALER_RELOAD_OK(TIM6_PSCReloadMode));
00183     assert_param(IS_TIM6_PRESCALER_OK(Prescaler));
00184
00185     /* Set the Prescaler value */
00186     TIM6->PSCR = (uint8_t)Prescaler;
00187
00188     /* Set or reset the UG Bit */
00189     if (TIM6_PSCReloadMode == TIM6_PSCRELOADMODE_IMMEDIATE)
00190     {
00191         TIM6->EGR |= TIM6_EGR_UG ;
00192     }
00193     else
00194     {
00195         TIM6->EGR &= (uint8_t)(~TIM6_EGR_UG) ;
00196     }
00197 }
00198
00199 /**
00200   * @brief  Enables or disables TIM6 peripheral Preload register on ARR.
00201   * @param   NewState : The new state of the TIM6 peripheral Preload register.
00202   * This parameter can be any of the @ref FunctionalState enumeration.
00203   * @retval None
00204   */
00205 void TIM6_ARRPreloadConfig(FunctionalState NewState)
00206 {
00207     /* Check the parameters */
00208     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00209
00210     /* Set or Reset the ARPE Bit */
00211     if (NewState == ENABLE)
00212     {
00213         TIM6->CR1 |= TIM6_CR1_ARPE ;
00214     }
00215     else
00216     {
00217         TIM6->CR1 &= (uint8_t)(~TIM6_CR1_ARPE) ;
00218     }
00219 }
00220
00221 /**
00222   * @brief  Sets the TIM6 Counter Register value.
00223   * @param   Counter : Specifies the Counter register new value.
00224   * This parameter is between 0x00 and 0xFF.
00225   * @retval None
00226   */
00227 void TIM6_SetCounter(uint8_t Counter)
00228 {
00229     /* Set the Counter Register value */
00230     TIM6->CNTR = (uint8_t)(Counter);
00231 }
00232
00233 /**
00234   * @brief  Sets the TIM6 Autoreload Register value.
00235   * @param   Autoreload : Specifies the Autoreload register new value.
00236   * This parameter is between 0x00 and 0xFF.
00237   * @retval None
00238   */
00239 void TIM6_SetAutoreload(uint8_t Autoreload)
00240 {
00241
00242     /* Set the Autoreload Register value */
00243     TIM6->ARR = (uint8_t)(Autoreload);
00244 }
00245
00246 /**
00247   * @brief  Gets the TIM6 Counter value.
00248   * @param  None
00249   * @retval uint8_t: Counter Register value.
00250   */
00251 uint8_t TIM6_GetCounter(void)
00252 {
00253     uint8_t tmpcntr=0;
00254     tmpcntr = TIM6->CNTR;
00255     /* Get the Counter Register value */
00256     return ((uint8_t)tmpcntr);
00257 }
00258
00259 /**
00260   * @brief  Gets the TIM6 Prescaler value.
00261   * @param  None
00262   * @retval TIM6_Prescaler_TypeDef : Prescaler Register configuration value.
00263   */
00264 TIM6_Prescaler_TypeDef TIM6_GetPrescaler(void)
00265 {
00266     /* Get the Prescaler Register value */
00267     return ((TIM6_Prescaler_TypeDef)TIM6->PSCR);
00268 }
00269
00270 /**
00271   * @brief  Enables or disables the specified TIM6 interrupts.
00272   * @param   TIM6_IT : Specifies the TIM6 interrupts sources to be enabled or disabled.
00273   * This parameter can be any combination of the @ref TIM6_IT_TypeDef enumeration.
00274   * @param   NewState : The new state of the TIM6 peripheral.
00275         * This parameter can be any of the @ref FunctionalState enumeration.
00276   * @retval None
00277   * @par Required preconditions:
00278   * If QST option bit is enabled, the TIM6 Interrupt vector will be mapped on IRQ number 2 (irq0).
00279   * Otherwise, it will be mapped on IRQ number 27 (irq25).
00280   */
00281 void TIM6_ITConfig(TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)
00282 {
00283     /* Check the parameters */
00284     assert_param(IS_TIM6_IT_OK(TIM6_IT));
00285     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00286
00287     if (NewState == ENABLE)
00288     {
00289         /* Enable the Interrupt sources */
00290         TIM6->IER |= (uint8_t)TIM6_IT;
00291     }
00292     else
00293     {
00294         /* Disable the Interrupt sources */
00295         TIM6->IER &= (uint8_t)(~(uint8_t)TIM6_IT);
00296     }
00297 }
00298
00299 /**
00300   * @brief  Clears the TIM’s pending flags.
00301   * @param   TIM6_FLAG : Specifies the flag to clear.
00302   * This parameter can be one of the @ref TIM6_FLAG_TypeDef enumeration.
00303   * @retval None
00304   */
00305 void TIM6_ClearFlag(TIM6_FLAG_TypeDef TIM6_FLAG)
00306 {
00307     /* Check the parameters */
00308     assert_param(IS_TIM6_CLEAR_FLAG_OK((uint8_t)TIM6_FLAG));
00309     /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
00310     TIM6->SR1 &= (uint8_t)(~((uint8_t)TIM6_FLAG));
00311 }
00312
00313 /**
00314   * @brief  Checks whether the TIM6 interrupt has occurred or not.
00315   * @param   TIM6_IT : Specifies the TIM6 interrupt source to check.
00316   * This parameter can be one of the @ref TIM6_IT_TypeDef enumeration.
00317   * @retval ITStatus : The new state of the TIM6_IT.
00318         * This parameter can be any of the @ref ITStatus enumeration.
00319   */
00320
00321 ITStatus TIM6_GetITStatus(TIM6_IT_TypeDef TIM6_IT)
00322 {
00323     ITStatus bitstatus = RESET;
00324     uint8_t itStatus = 0, itEnable = 0;
00325
00326     /* Check the parameters */
00327     assert_param(IS_TIM6_GET_IT_OK(TIM6_IT));
00328
00329     itStatus = (uint8_t)(TIM6->SR1 & (uint8_t)TIM6_IT);
00330
00331     itEnable = (uint8_t)(TIM6->IER & (uint8_t)TIM6_IT);
00332
00333     if ((itStatus != (uint8_t)RESET ) && (itEnable != (uint8_t)RESET ))
00334     {
00335         bitstatus = (ITStatus)SET;
00336     }
00337     else
00338     {
00339         bitstatus = (ITStatus)RESET;
00340     }
00341     return ((ITStatus)bitstatus);
00342 }
00343
00344 /**
00345   * @brief  Configures the TIM6 event to be generated by software.
00346   * @param   TIM6_EventSource : Specifies the event source.
00347   * This parameter can be one of the @ref TIM6_EventSource_TypeDef enumeration.
00348   * @retval None
00349   */
00350 void TIM6_GenerateEvent(TIM6_EventSource_TypeDef TIM6_EventSource)
00351 {
00352     /* Check the parameters */
00353     assert_param(IS_TIM6_EVENT_SOURCE_OK((uint8_t)TIM6_EventSource));
00354
00355     /* Set the event sources */
00356     TIM6->EGR |= (uint8_t)TIM6_EventSource;
00357 }
00358
00359 /**
00360   * @brief  Checks whether the specified TIM6 flag is set or not.
00361   * @param   TIM6_FLAG : Specifies the flag to check.
00362   * This parameter can be one of the @ref TIM6_FLAG_TypeDef enumeration.
00363   * @retval FlagStatus : The new state of TIM6_FLAG.
00364         * This parameter can be any of the @ref FlagStatus enumeration.
00365   */
00366 FlagStatus TIM6_GetFlagStatus(TIM6_FLAG_TypeDef TIM6_FLAG)
00367 {
00368     volatile FlagStatus bitstatus = RESET;
00369
00370     /* Check the parameters */
00371     assert_param(IS_TIM6_GET_FLAG_OK(TIM6_FLAG));
00372
00373     if ((TIM6->SR1 & (uint8_t)TIM6_FLAG)  != 0)
00374     {
00375         bitstatus = SET;
00376     }
00377     else
00378     {
00379         bitstatus = RESET;
00380     }
00381     return ((FlagStatus)bitstatus);
00382 }
00383
00384 /**
00385   * @brief  Clears the TIM6's interrupt pending bits.
00386   * @param   TIM6_IT : Specifies the pending bit to clear.
00387  * This parameter can be one of the @ref TIM6_IT_TypeDef enumeration.
00388   * @retval None
00389   */
00390 void TIM6_ClearITPendingBit(TIM6_IT_TypeDef TIM6_IT)
00391 {
00392     /* Check the parameters */
00393     assert_param(IS_TIM6_IT_OK(TIM6_IT));
00394
00395     /* Clear the IT pending Bit */
00396     TIM6->SR1 &= (uint8_t)(~(uint8_t)TIM6_IT);
00397 }
00398
00399 /**
00400   * @brief  Selects the TIM6 Trigger Output Mode.
00401   * @param   TIM6_TRGOSource : Specifies the Trigger Output source.
00402   * This parameter can be one of the @ref TIM6_TRGOSource_TypeDef enumeration.
00403   * @retval None
00404   */
00405 void TIM6_SelectOutputTrigger(TIM6_TRGOSource_TypeDef TIM6_TRGOSource)
00406 {
00407     uint8_t tmpcr2 = 0;
00408
00409     /* Check the parameters */
00410     assert_param(IS_TIM6_TRGO_SOURCE_OK(TIM6_TRGOSource));
00411
00412     tmpcr2 = TIM6->CR2;
00413
00414     /* Reset the MMS Bits */
00415     tmpcr2 &= (uint8_t)(~TIM6_CR2_MMS);
00416
00417     /* Select the TRGO source */
00418     tmpcr2 |=  (uint8_t)TIM6_TRGOSource;
00419
00420     TIM6->CR2 = tmpcr2;
00421 }
00422
00423 /**
00424   * @brief  Sets or Resets the TIM6 Master/Slave Mode.
00425   * @param   NewState : The new state of the synchronization between TIM6 and its slaves (through TRGO).
00426         * This parameter can be any of the @ref FunctionalState enumeration.
00427   * @retval None
00428   */
00429
00430 void TIM6_SelectMasterSlaveMode(FunctionalState NewState)
00431 {
00432     /* Check the parameters */
00433     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00434
00435     /* Set or Reset the MSM Bit */
00436     if (NewState == ENABLE)
00437     {
00438         TIM6->SMCR |= TIM6_SMCR_MSM;
00439     }
00440     else
00441     {
00442         TIM6->SMCR &= (uint8_t)(~TIM6_SMCR_MSM);
00443     }
00444 }
00445
00446 /**
00447   * @brief  Selects the TIM6 Input Trigger source.
00448   * @param   TIM6_InputTriggerSource : Specifies Input Trigger source.
00449   * This parameter can be one of the @ref TIM6_TS_TypeDef enumeration.
00450   * @retval None
00451   */
00452 void TIM6_SelectInputTrigger(TIM6_TS_TypeDef TIM6_InputTriggerSource)
00453 {
00454     uint8_t tmpsmcr = 0;
00455
00456     /* Check the parameters */
00457     assert_param(IS_TIM6_TRIGGER_SELECTION_OK(TIM6_InputTriggerSource));
00458
00459     tmpsmcr = TIM6->SMCR;
00460
00461     /* Select the Tgigger Source */
00462     tmpsmcr &= (uint8_t)(~TIM6_SMCR_TS);
00463     tmpsmcr |= (uint8_t)TIM6_InputTriggerSource;
00464
00465     TIM6->SMCR = (uint8_t)tmpsmcr;
00466 }
00467
00468 /**
00469   * @brief  Enables the TIM6 internal Clock.
00470   * @param  None
00471   * @retval None
00472   */
00473 void TIM6_InternalClockConfig(void)
00474 {
00475     /* Disable slave mode to clock the prescaler directly with the internal clock */
00476     TIM6->SMCR &=  (uint8_t)(~TIM6_SMCR_SMS);
00477 }
00478
00479 /**
00480   * @brief  Selects the TIM6 Slave Mode.
00481   * @param   TIM6_SlaveMode : Specifies the TIM6 Slave Mode.
00482   * This parameter can be one of the @ref TIM6_SlaveMode_TypeDef enumeration.
00483   * @retval None
00484   */
00485 void TIM6_SelectSlaveMode(TIM6_SlaveMode_TypeDef TIM6_SlaveMode)
00486 {
00487     uint8_t tmpsmcr = 0;
00488
00489     /* Check the parameters */
00490     assert_param(IS_TIM6_SLAVE_MODE_OK(TIM6_SlaveMode));
00491
00492     tmpsmcr = TIM6->SMCR;
00493
00494     /* Reset the SMS Bits */
00495     tmpsmcr &= (uint8_t)(~TIM6_SMCR_SMS);
00496
00497     /* Select the Slave Mode */
00498     tmpsmcr |= (uint8_t)TIM6_SlaveMode;
00499
00500     TIM6->SMCR = tmpsmcr;
00501 }
00502
00503 /**
00504   * @}
00505   */
00506
00507 /**
00508   * @}
00509   */
00510
00511 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_tim6.h Source File

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stm8s_tim6.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim6.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the TIM6 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_TIM6_H
00024 #define __STM8S_TIM6_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /* Exported variables ------------------------------------------------------- */
00034 /* Exported types ------------------------------------------------------------*/
00035
00036 /** @addtogroup TIM6_Exported_Types
00037   * @{
00038   */
00039
00040
00041 /**
00042   * @brief  TIM6 Prescaler
00043   */
00044 typedef enum
00045 {
00046     TIM6_PRESCALER_1      = ((uint8_t)0x00),  /*!< Time base Prescaler = 1 (No effect)*/
00047     TIM6_PRESCALER_2      = ((uint8_t)0x01),  /*!< Time base Prescaler = 2 */
00048     TIM6_PRESCALER_4      = ((uint8_t)0x02),  /*!< Time base Prescaler = 4 */
00049     TIM6_PRESCALER_8      = ((uint8_t)0x03),  /*!< Time base Prescaler = 8 */
00050     TIM6_PRESCALER_16     = ((uint8_t)0x04),  /*!< Time base Prescaler = 16 */
00051     TIM6_PRESCALER_32     = ((uint8_t)0x05),  /*!< Time base Prescaler = 32 */
00052     TIM6_PRESCALER_64     = ((uint8_t)0x06),  /*!< Time base Prescaler = 64 */
00053     TIM6_PRESCALER_128    = ((uint8_t)0x07)  /*!< Time base Prescaler = 128 */
00054 }TIM6_Prescaler_TypeDef;
00055
00056 /**
00057   * @brief  TIM6 One Pulse Mode
00058   */
00059 typedef enum
00060 {
00061     TIM6_OPMODE_SINGLE      = ((uint8_t)0x01),  /*!< Single one Pulse mode (OPM Active) */
00062     TIM6_OPMODE_REPETITIVE  = ((uint8_t)0x00)   /*!< Repetitive Pulse mode (OPM inactive) */
00063 }TIM6_OPMode_TypeDef;
00064
00065 /**
00066   * @brief  TIM6 Prescaler Reload Mode
00067   */
00068 typedef enum
00069 {
00070     TIM6_PSCRELOADMODE_UPDATE      =((uint8_t)0x00),  /*!< Prescaler value is reloaded at every update*/
00071     TIM6_PSCRELOADMODE_IMMEDIATE   =((uint8_t)0x01)    /*!< Prescaler value is reloaded immediatly*/
00072 }TIM6_PSCReloadMode_TypeDef;
00073
00074 /**
00075   * @brief  TIM6 Update Source
00076   */
00077 typedef enum
00078 {
00079     TIM6_UPDATESOURCE_GLOBAL   =((uint8_t)0x00),  /*!< Global Update request source */
00080     TIM6_UPDATESOURCE_REGULAR  =((uint8_t)0x01)    /*!< Regular Update request source */
00081 }TIM6_UpdateSource_TypeDef;
00082
00083 /**
00084   * @brief  TIM6 Event Source
00085   */
00086 typedef enum
00087 {
00088     TIM6_EVENTSOURCE_UPDATE    = ((uint8_t)0x01),    /*!< Update Event*/
00089     TIM6_EVENTSOURCE_TRIGGER   = ((uint8_t)0x40)    /*!< Trigger Event*/
00090 }TIM6_EventSource_TypeDef;
00091
00092 /**
00093   * @brief  TIM6 Trigger Output Source
00094   */
00095 typedef enum
00096 {
00097     TIM6_TRGOSOURCE_RESET    = ((uint8_t)0x00),    /*!< Trigger Output source = Reset*/
00098     TIM6_TRGOSOURCE_ENABLE   = ((uint8_t)0x10),    /*!< Trigger Output source = TIM5 is enabled*/
00099     TIM6_TRGOSOURCE_UPDATE   = ((uint8_t)0x20)    /*!< Trigger Output source = Update event*/
00100 }TIM6_TRGOSource_TypeDef;
00101
00102 /**
00103   * @brief  TIM6 Slave Mode
00104   */
00105 typedef enum
00106 {
00107     TIM6_SLAVEMODE_DISABLE    = ((uint8_t)0x00),   /*!< Disable slave mode to clock the prescaler directly with the internal clock */
00108     TIM6_SLAVEMODE_RESET      = ((uint8_t)0x04),   /*!< Slave Mode Selection  = Reset*/
00109     TIM6_SLAVEMODE_GATED      = ((uint8_t)0x05),   /*!< Slave Mode Selection  = Gated*/
00110     TIM6_SLAVEMODE_TRIGGER    = ((uint8_t)0x06),    /*!< Slave Mode Selection  = Trigger*/
00111     TIM6_SLAVEMODE_EXTERNAL1  = ((uint8_t)0x07)    /*!< Slave Mode Selection  = External 1*/
00112 }TIM6_SlaveMode_TypeDef;
00113
00114 /**
00115   * @brief  TIM6 Flags
00116   */
00117 typedef enum
00118 {
00119     TIM6_FLAG_UPDATE   = ((uint8_t)0x01),    /*!< Update Flag */
00120     TIM6_FLAG_TRIGGER  = ((uint8_t)0x40)    /*!< Trigger Flag */
00121 }TIM6_FLAG_TypeDef;
00122
00123 /**
00124   * @brief  TIM6 interrupt sources
00125   */
00126 typedef enum
00127 {
00128     TIM6_IT_UPDATE   = ((uint8_t)0x01),    /*!< Update Interrupt*/
00129     TIM6_IT_TRIGGER  = ((uint8_t)0x40)    /*!< Trigger  Interrupt*/
00130 }TIM6_IT_TypeDef;
00131
00132 /**
00133   * @brief  TIM6 Internal Trigger Selection
00134   */
00135 typedef enum
00136 {
00137     TIM6_TS_TIM1  = ((uint8_t)0x20),/*!< TRIG Input source =  TIM1 TRIG Output  */
00138     TIM6_TS_TIM5  = ((uint8_t)0x30) /*!< TRIG Input source =  TIM5 TRIG Output  */
00139 }TIM6_TS_TypeDef;
00140
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported constants --------------------------------------------------------*/
00146 /* Exported macros -----------------------------------------------------------*/
00147 /* Private macros ------------------------------------------------------------*/
00148
00149 /** @addtogroup TIM6_Private_Macros
00150   * @{
00151   */
00152
00153 /**
00154   * @brief  Macro used by the assert function to check the different functions parameters.
00155   */
00156
00157 /**
00158   * @brief  Macro TIM6 Prescaler
00159   */
00160 #define IS_TIM6_PRESCALER_OK(PRESCALER)  \
00161    (((PRESCALER) == TIM6_PRESCALER_1)    || \
00162     ((PRESCALER) == TIM6_PRESCALER_2)    || \
00163     ((PRESCALER) == TIM6_PRESCALER_4)    || \
00164     ((PRESCALER) == TIM6_PRESCALER_8)    || \
00165     ((PRESCALER) == TIM6_PRESCALER_16)   || \
00166     ((PRESCALER) == TIM6_PRESCALER_32)   || \
00167     ((PRESCALER) == TIM6_PRESCALER_64)   || \
00168     ((PRESCALER) == TIM6_PRESCALER_128))
00169 /**
00170   * @brief  Macro TIM6 One Pulse Mode
00171   */
00172 #define IS_TIM6_OPM_MODE_OK(MODE)  \
00173    (((MODE) == TIM6_OPMODE_SINGLE) || \
00174     ((MODE) == TIM6_OPMODE_REPETITIVE))
00175
00176 /**
00177   * @brief  Macro TIM6 Prescaler reload
00178   */
00179 #define IS_TIM6_PRESCALER_RELOAD_OK(RELOAD) \
00180    (((RELOAD) == TIM6_PSCRELOADMODE_UPDATE) || \
00181     ((RELOAD) == TIM6_PSCRELOADMODE_IMMEDIATE))
00182 /**
00183   * @brief  Macro TIM6 Update source
00184   */
00185 #define IS_TIM6_UPDATE_SOURCE_OK(SOURCE) \
00186    (((SOURCE) == TIM6_UPDATESOURCE_GLOBAL) || \
00187     ((SOURCE) == TIM6_UPDATESOURCE_REGULAR))
00188 /**
00189   * @brief  Macro TIM6 Event source
00190   */
00191 #define IS_TIM6_EVENT_SOURCE_OK(SOURCE) \
00192    ((((SOURCE) & (uint8_t)0xBE) == 0x00) && \
00193     ((SOURCE) != 0x00))
00194
00195 /**
00196   * @brief  Macro TIM6 TRGO source
00197   */
00198 #define IS_TIM6_TRGO_SOURCE_OK(SOURCE) \
00199    (((SOURCE) == TIM6_TRGOSOURCE_RESET) || \
00200     ((SOURCE) == TIM6_TRGOSOURCE_ENABLE)|| \
00201     ((SOURCE) == TIM6_TRGOSOURCE_UPDATE))
00202 /**
00203   * @brief  Macro TIM6 Slave mode
00204   */
00205 #define IS_TIM6_SLAVE_MODE_OK(MODE) \
00206    (((MODE) == TIM6_SLAVEMODE_DISABLE) || \
00207     ((MODE) == TIM6_SLAVEMODE_RESET)   || \
00208     ((MODE) == TIM6_SLAVEMODE_GATED)   || \
00209     ((MODE) == TIM6_SLAVEMODE_TRIGGER) || \
00210     ((MODE) == TIM6_SLAVEMODE_EXTERNAL1))
00211 /**
00212   * @brief  Macro TIM6 Flags
00213   */
00214 #define IS_TIM6_GET_FLAG_OK(FLAG) \
00215    (((FLAG) == TIM6_FLAG_UPDATE) || \
00216     ((FLAG) == TIM6_FLAG_TRIGGER))
00217
00218 #define IS_TIM6_CLEAR_FLAG_OK(FLAG) \
00219    ((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))
00220 /**
00221   * @brief  Macro TIM6 interrupts
00222   */
00223 #define IS_TIM6_IT_OK(IT) \
00224    (((IT) != 0x00) && \
00225     (((IT) & (uint8_t)(~(uint8_t)(0x41)))== 0x00))
00226
00227 #define IS_TIM6_GET_IT_OK(IT) \
00228    (((IT) == TIM6_IT_UPDATE) || \
00229     ((IT) == TIM6_IT_TRIGGER))
00230 /**
00231   * @brief  Macro TIM6 Trigger selection
00232   */
00233 #define IS_TIM6_TRIGGER_SELECTION_OK(SELECTION) \
00234    (((SELECTION) == TIM6_TS_TIM5) || \
00235     ((SELECTION) == TIM6_TS_TIM1))
00236 /**
00237  * @}
00238  */
00239
00240 /* Exported functions --------------------------------------------------------*/
00241
00242 /** @addtogroup TIM6_Exported_Functions
00243   * @{
00244   */
00245
00246 void TIM6_DeInit(void);
00247 void TIM6_TimeBaseInit(TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period);
00248 void TIM6_Cmd(FunctionalState NewState);
00249 void TIM6_UpdateDisableConfig(FunctionalState NewState);
00250 void TIM6_UpdateRequestConfig(TIM6_UpdateSource_TypeDef TIM6_UpdateSource);
00251 void TIM6_SelectOnePulseMode(TIM6_OPMode_TypeDef TIM6_OPMode);
00252 void TIM6_PrescalerConfig(TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode);
00253 void TIM6_ARRPreloadConfig(FunctionalState NewState);
00254 void TIM6_SetCounter(uint8_t Counter);
00255 void TIM6_SetAutoreload(uint8_t Autoreload);
00256 uint8_t TIM6_GetCounter(void);
00257 TIM6_Prescaler_TypeDef TIM6_GetPrescaler(void);
00258 void TIM6_ITConfig(TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState);
00259 void TIM6_ClearFlag(TIM6_FLAG_TypeDef TIM6_FLAG);
00260 ITStatus TIM6_GetITStatus(TIM6_IT_TypeDef TIM6_IT);
00261 void TIM6_GenerateEvent(TIM6_EventSource_TypeDef TIM6_EventSource);
00262 FlagStatus TIM6_GetFlagStatus(TIM6_FLAG_TypeDef TIM6_FLAG);
00263 void TIM6_ClearITPendingBit(TIM6_IT_TypeDef TIM6_IT);
00264 void TIM6_SelectOutputTrigger(TIM6_TRGOSource_TypeDef TIM6_TRGOSource);
00265 void TIM6_SelectMasterSlaveMode(FunctionalState NewState);
00266 void TIM6_SelectInputTrigger(TIM6_TS_TypeDef TIM6_InputTriggerSource);
00267 void TIM6_InternalClockConfig(void);
00268 void TIM6_SelectSlaveMode(TIM6_SlaveMode_TypeDef TIM6_SlaveMode);
00269
00270 /**
00271  * @}
00272  */
00273
00274 #endif /* __STM8S_TIM6_H */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart1.c Source File

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stm8s_uart1.c

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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart1.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the UART1 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_uart1.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034 /* Public functions ----------------------------------------------------------*/
00035
00036 /** @}
00037   * @addtogroup UART1_Public_Functions
00038   * @{
00039   */
00040
00041 /**
00042   * @brief  Deinitializes the UART peripheral.
00043   * @param  None
00044   * @retval None
00045         */
00046 void UART1_DeInit(void)
00047 {
00048     /* Clear the Idle Line Detected bit in the status rerister by a read
00049        to the UART1_SR register followed by a Read to the UART1_DR register */
00050     (void)UART1->SR;
00051     (void)UART1->DR;
00052
00053     UART1->BRR2 = UART1_BRR2_RESET_VALUE;  /* Set UART1_BRR2 to reset value 0x00 */
00054     UART1->BRR1 = UART1_BRR1_RESET_VALUE;  /* Set UART1_BRR1 to reset value 0x00 */
00055
00056     UART1->CR1 = UART1_CR1_RESET_VALUE;  /* Set UART1_CR1 to reset value 0x00 */
00057     UART1->CR2 = UART1_CR2_RESET_VALUE;  /* Set UART1_CR2 to reset value 0x00 */
00058     UART1->CR3 = UART1_CR3_RESET_VALUE;  /* Set UART1_CR3 to reset value 0x00 */
00059     UART1->CR4 = UART1_CR4_RESET_VALUE;  /* Set UART1_CR4 to reset value 0x00 */
00060     UART1->CR5 = UART1_CR5_RESET_VALUE;  /* Set UART1_CR5 to reset value 0x00 */
00061
00062     UART1->GTR = UART1_GTR_RESET_VALUE;
00063     UART1->PSCR = UART1_PSCR_RESET_VALUE;
00064 }
00065
00066 /**
00067   * @brief  Initializes the UART1 according to the specified parameters.
00068   * @note   Configure in Push Pull or Open Drain mode the Tx pin by setting the
00069   *         correct I/O Port register according the product package and line
00070   *         configuration
00071   * @param  BaudRate: The baudrate.
00072   * @param  WordLength : This parameter can be any of the
00073   *         @ref UART1_WordLength_TypeDef enumeration.
00074   * @param  StopBits: This parameter can be any of the
00075   *         @ref UART1_StopBits_TypeDef enumeration.
00076   * @param  Parity: This parameter can be any of the
00077   *         @ref UART1_Parity_TypeDef enumeration.
00078   * @param  SyncMode: This parameter can be any of the
00079   *         @ref UART1_SyncMode_TypeDef values.
00080   * @param  Mode: This parameter can be any of the @ref UART1_Mode_TypeDef values
00081   * @retval None
00082   */
00083 void UART1_Init(uint32_t BaudRate, UART1_WordLength_TypeDef WordLength,
00084                 UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity,
00085                 UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
00086 {
00087     uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;
00088
00089     /* Check the parameters */
00090     assert_param(IS_UART1_BAUDRATE_OK(BaudRate));
00091     assert_param(IS_UART1_WORDLENGTH_OK(WordLength));
00092     assert_param(IS_UART1_STOPBITS_OK(StopBits));
00093     assert_param(IS_UART1_PARITY_OK(Parity));
00094     assert_param(IS_UART1_MODE_OK((uint8_t)Mode));
00095     assert_param(IS_UART1_SYNCMODE_OK((uint8_t)SyncMode));
00096
00097     /* Clear the word length bit */
00098     UART1->CR1 &= (uint8_t)(~UART1_CR1_M);
00099
00100      /* Set the word length bit according to UART1_WordLength value */
00101     UART1->CR1 |= (uint8_t)WordLength;
00102
00103     /* Clear the STOP bits */
00104     UART1->CR3 &= (uint8_t)(~UART1_CR3_STOP);
00105     /* Set the STOP bits number according to UART1_StopBits value  */
00106     UART1->CR3 |= (uint8_t)StopBits;
00107
00108     /* Clear the Parity Control bit */
00109     UART1->CR1 &= (uint8_t)(~(UART1_CR1_PCEN | UART1_CR1_PS  ));
00110     /* Set the Parity Control bit to UART1_Parity value */
00111     UART1->CR1 |= (uint8_t)Parity;
00112
00113     /* Clear the LSB mantissa of UART1DIV  */
00114     UART1->BRR1 &= (uint8_t)(~UART1_BRR1_DIVM);
00115     /* Clear the MSB mantissa of UART1DIV  */
00116     UART1->BRR2 &= (uint8_t)(~UART1_BRR2_DIVM);
00117     /* Clear the Fraction bits of UART1DIV */
00118     UART1->BRR2 &= (uint8_t)(~UART1_BRR2_DIVF);
00119
00120     /* Set the UART1 BaudRates in BRR1 and BRR2 registers according to UART1_BaudRate value */
00121     BaudRate_Mantissa    = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4));
00122     BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4));
00123     /* Set the fraction of UART1DIV  */
00124     UART1->BRR2 |= (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100)) << 4) / 100) & (uint8_t)0x0F);
00125     /* Set the MSB mantissa of UART1DIV  */
00126     UART1->BRR2 |= (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0);
00127     /* Set the LSB mantissa of UART1DIV  */
00128     UART1->BRR1 |= (uint8_t)BaudRate_Mantissa;
00129
00130     /* Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */
00131     UART1->CR2 &= (uint8_t)~(UART1_CR2_TEN | UART1_CR2_REN);
00132     /* Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
00133     UART1->CR3 &= (uint8_t)~(UART1_CR3_CPOL | UART1_CR3_CPHA | UART1_CR3_LBCL);
00134     /* Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
00135     UART1->CR3 |= (uint8_t)((uint8_t)SyncMode & (uint8_t)(UART1_CR3_CPOL |
00136                                               UART1_CR3_CPHA | UART1_CR3_LBCL));
00137
00138     if ((uint8_t)(Mode & UART1_MODE_TX_ENABLE))
00139     {
00140         /* Set the Transmitter Enable bit */
00141         UART1->CR2 |= (uint8_t)UART1_CR2_TEN;
00142     }
00143     else
00144     {
00145         /* Clear the Transmitter Disable bit */
00146         UART1->CR2 &= (uint8_t)(~UART1_CR2_TEN);
00147     }
00148     if ((uint8_t)(Mode & UART1_MODE_RX_ENABLE))
00149     {
00150         /* Set the Receiver Enable bit */
00151         UART1->CR2 |= (uint8_t)UART1_CR2_REN;
00152     }
00153     else
00154     {
00155         /* Clear the Receiver Disable bit */
00156         UART1->CR2 &= (uint8_t)(~UART1_CR2_REN);
00157     }
00158     /* Set the Clock Enable bit, lock Polarity, lock Phase and Last Bit Clock
00159            pulse bits according to UART1_Mode value */
00160     if ((uint8_t)(SyncMode & UART1_SYNCMODE_CLOCK_DISABLE))
00161     {
00162         /* Clear the Clock Enable bit */
00163         UART1->CR3 &= (uint8_t)(~UART1_CR3_CKEN);
00164     }
00165     else
00166     {
00167         UART1->CR3 |= (uint8_t)((uint8_t)SyncMode & UART1_CR3_CKEN);
00168     }
00169 }
00170
00171 /**
00172   * @brief  Enable the UART1 peripheral.
00173   * @param  NewState : The new state of the UART Communication.
00174   *         This parameter can be any of the @ref FunctionalState enumeration.
00175   * @retval None
00176   */
00177 void UART1_Cmd(FunctionalState NewState)
00178 {
00179     if (NewState != DISABLE)
00180     {
00181         /* UART1 Enable */
00182         UART1->CR1 &= (uint8_t)(~UART1_CR1_UARTD);
00183     }
00184     else
00185     {
00186         /* UART Disable */
00187         UART1->CR1 |= UART1_CR1_UARTD;
00188     }
00189 }
00190
00191 /**
00192   * @brief  Enables or disables the specified USART interrupts.
00193   * @param  UART1_IT specifies the USART interrupt sources to be enabled or disabled.
00194   *         This parameter can be one of the following values:
00195   *         - UART1_IT_TXE:  Tansmit Data Register empty interrupt
00196   *         - UART1_IT_TC:   Transmission complete interrupt
00197   *         - UART1_IT_RXNE: Receive Data register not empty interrupt
00198   *         - UART1_IT_OR: Overrun error interrupt
00199   *         - UART1_IT_IDLE: Idle line detection interrupt
00200   *         - USRT1_IT_ERR:  Error interrupt
00201   * @param  NewState new state of the specified USART interrupts.
00202   *         This parameter can be: ENABLE or DISABLE.
00203   * @retval None
00204   */
00205 void UART1_ITConfig(UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
00206 {
00207     uint8_t uartreg = 0, itpos = 0x00;
00208
00209     /* Check the parameters */
00210     assert_param(IS_UART1_CONFIG_IT_OK(UART1_IT));
00211     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00212
00213     /* Get the UART1 register index */
00214     uartreg = (uint8_t)((uint16_t)UART1_IT >> 0x08);
00215     /* Get the UART1 IT index */
00216     itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART1_IT & (uint8_t)0x0F));
00217
00218     if (NewState != DISABLE)
00219     {
00220         /**< Enable the Interrupt bits according to UART1_IT mask */
00221         if (uartreg == 0x01)
00222         {
00223             UART1->CR1 |= itpos;
00224         }
00225         else if (uartreg == 0x02)
00226         {
00227             UART1->CR2 |= itpos;
00228         }
00229         else
00230         {
00231             UART1->CR4 |= itpos;
00232         }
00233     }
00234     else
00235     {
00236         /**< Disable the interrupt bits according to UART1_IT mask */
00237         if (uartreg == 0x01)
00238         {
00239             UART1->CR1 &= (uint8_t)(~itpos);
00240         }
00241         else if (uartreg == 0x02)
00242         {
00243             UART1->CR2 &= (uint8_t)(~itpos);
00244         }
00245         else
00246         {
00247             UART1->CR4 &= (uint8_t)(~itpos);
00248         }
00249     }
00250
00251 }
00252 /**
00253   * @brief  Enables or disables the UART’s Half Duplex communication.
00254   * @param  NewState new state of the UART Communication.
00255   *         This parameter can be: ENABLE or DISABLE.
00256   * @retval None
00257   */
00258 void UART1_HalfDuplexCmd(FunctionalState NewState)
00259 {
00260     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00261
00262     if (NewState != DISABLE)
00263     {
00264         UART1->CR5 |= UART1_CR5_HDSEL;  /**< UART1 Half Duplex Enable  */
00265     }
00266     else
00267     {
00268         UART1->CR5 &= (uint8_t)~UART1_CR5_HDSEL; /**< UART1 Half Duplex Disable */
00269     }
00270 }
00271
00272 /**
00273   * @brief  Configures the UART’s IrDA interface.
00274   * @param  UART1_IrDAMode specifies the IrDA mode.
00275   *         This parameter can be any of the @ref UART1_IrDAMode_TypeDef values.
00276   * @retval None
00277   */
00278 void UART1_IrDAConfig(UART1_IrDAMode_TypeDef UART1_IrDAMode)
00279 {
00280     assert_param(IS_UART1_IRDAMODE_OK(UART1_IrDAMode));
00281
00282     if (UART1_IrDAMode != UART1_IRDAMODE_NORMAL)
00283     {
00284         UART1->CR5 |= UART1_CR5_IRLP;
00285     }
00286     else
00287     {
00288         UART1->CR5 &= ((uint8_t)~UART1_CR5_IRLP);
00289     }
00290 }
00291
00292 /**
00293   * @brief  Enables or disables the UART’s IrDA interface.
00294   * @param  NewState new state of the IrDA mode.
00295   *         This parameter can be: ENABLE or DISABLE.
00296   * @retval None
00297   */
00298 void UART1_IrDACmd(FunctionalState NewState)
00299 {
00300
00301     /* Check parameters */
00302     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00303
00304     if (NewState != DISABLE)
00305     {
00306         /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
00307         UART1->CR5 |= UART1_CR5_IREN;
00308     }
00309     else
00310     {
00311         /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
00312         UART1->CR5 &= ((uint8_t)~UART1_CR5_IREN);
00313     }
00314 }
00315
00316 /**
00317   * @brief  Sets the UART1 LIN Break detection length.
00318   * @param  UART1_LINBreakDetectionLength specifies the LIN break detection length.
00319   *         This parameter can be any of the
00320   *         @ref UART1_LINBreakDetectionLength_TypeDef values.
00321   * @retval None
00322   */
00323 void UART1_LINBreakDetectionConfig(UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
00324 {
00325     assert_param(IS_UART1_LINBREAKDETECTIONLENGTH_OK(UART1_LINBreakDetectionLength));
00326
00327     if (UART1_LINBreakDetectionLength != UART1_LINBREAKDETECTIONLENGTH_10BITS)
00328     {
00329         UART1->CR4 |= UART1_CR4_LBDL;
00330     }
00331     else
00332     {
00333         UART1->CR4 &= ((uint8_t)~UART1_CR4_LBDL);
00334     }
00335 }
00336
00337 /**
00338   * @brief  Enables or disables the UART1’s LIN mode.
00339   * @param  NewState is new state of the UART1 LIN mode.
00340   *         This parameter can be: ENABLE or DISABLE.
00341   * @retval None
00342   */
00343 void UART1_LINCmd(FunctionalState NewState)
00344 {
00345     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00346
00347     if (NewState != DISABLE)
00348     {
00349         /* Enable the LIN mode by setting the LINE bit in the CR2 register */
00350         UART1->CR3 |= UART1_CR3_LINEN;
00351     }
00352     else
00353     {
00354         /* Disable the LIN mode by clearing the LINE bit in the CR2 register */
00355         UART1->CR3 &= ((uint8_t)~UART1_CR3_LINEN);
00356     }
00357 }
00358 /**
00359   * @brief  Enables or disables the UART1 Smart Card mode.
00360   * @param  NewState: new state of the Smart Card mode.
00361   * This parameter can be: ENABLE or DISABLE.
00362   * @retval None
00363   */
00364 void UART1_SmartCardCmd(FunctionalState NewState)
00365 {
00366     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00367
00368     if (NewState != DISABLE)
00369     {
00370         /* Enable the SC mode by setting the SCEN bit in the CR5 register */
00371         UART1->CR5 |= UART1_CR5_SCEN;
00372     }
00373     else
00374     {
00375         /* Disable the SC mode by clearing the SCEN bit in the CR5 register */
00376         UART1->CR5 &= ((uint8_t)(~UART1_CR5_SCEN));
00377     }
00378 }
00379
00380 /**
00381   * @brief  Enables or disables NACK transmission.
00382   * @note   This function is valid only for UART1 because is related to SmartCard mode.
00383   * @param  NewState: new state of the Smart Card mode.
00384   *         This parameter can be: ENABLE or DISABLE.
00385   * @retval None
00386   */
00387 void UART1_SmartCardNACKCmd(FunctionalState NewState)
00388 {
00389     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00390
00391     if (NewState != DISABLE)
00392     {
00393         /* Enable the NACK transmission by setting the NACK bit in the CR5 register */
00394         UART1->CR5 |= UART1_CR5_NACK;
00395     }
00396     else
00397     {
00398         /* Disable the NACK transmission by clearing the NACK bit in the CR5 register */
00399         UART1->CR5 &= ((uint8_t)~(UART1_CR5_NACK));
00400     }
00401 }
00402
00403 /**
00404   * @brief  Selects the UART1 WakeUp method.
00405   * @param  UART1_WakeUp: specifies the UART1 wakeup method.
00406   *         This parameter can be any of the @ref UART1_WakeUp_TypeDef values.
00407   * @retval None
00408   */
00409 void UART1_WakeUpConfig(UART1_WakeUp_TypeDef UART1_WakeUp)
00410 {
00411     assert_param(IS_UART1_WAKEUP_OK(UART1_WakeUp));
00412
00413     UART1->CR1 &= ((uint8_t)~UART1_CR1_WAKE);
00414     UART1->CR1 |= (uint8_t)UART1_WakeUp;
00415 }
00416 /**
00417   * @brief  Determines if the UART1 is in mute mode or not.
00418   * @param  NewState: new state of the UART1 mode.
00419   *         This parameter can be: ENABLE or DISABLE.
00420   * @retval None
00421   */
00422 void UART1_ReceiverWakeUpCmd(FunctionalState NewState)
00423 {
00424     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00425
00426     if (NewState != DISABLE)
00427     {
00428         /* Enable the mute mode UART1 by setting the RWU bit in the CR2 register */
00429         UART1->CR2 |= UART1_CR2_RWU;
00430     }
00431     else
00432     {
00433         /* Disable the mute mode UART1 by clearing the RWU bit in the CR1 register */
00434         UART1->CR2 &= ((uint8_t)~UART1_CR2_RWU);
00435     }
00436 }
00437
00438 /**
00439   * @brief  Returns the most recent received data by the UART1 peripheral.
00440   * @param  None
00441   * @retval The received data.
00442   */
00443 uint8_t UART1_ReceiveData8(void)
00444 {
00445     return ((uint8_t)UART1->DR);
00446 }
00447
00448 /**
00449   * @brief  Returns the most recent received data by the UART1 peripheral.
00450   * @param  None
00451   * @retval The received data.
00452   */
00453 uint16_t UART1_ReceiveData9(void)
00454 {
00455   uint16_t temp = 0;
00456
00457   temp = (uint16_t)(((uint16_t)( (uint16_t)UART1->CR1 & (uint16_t)UART1_CR1_R8)) << 1);
00458   return (uint16_t)( (((uint16_t) UART1->DR) | temp ) & ((uint16_t)0x01FF));
00459 }
00460
00461 /**
00462   * @brief  Transmits 8 bit data through the UART1 peripheral.
00463   * @param  Data: The data to transmit.
00464   * @retval None
00465   */
00466 void UART1_SendData8(uint8_t Data)
00467 {
00468     /* Transmit Data */
00469     UART1->DR = Data;
00470 }
00471
00472 /**
00473   * @brief  Transmits 9 bit data through the UART peripheral.
00474   * @param  Data : The data to transmit.
00475   *         This parameter should be lower than 0x1FF.
00476   * @retval None
00477   */
00478 void UART1_SendData9(uint16_t Data)
00479 {
00480     /**< Clear the transmit data bit 8 [8]  */
00481     UART1->CR1 &= ((uint8_t)~UART1_CR1_T8);
00482     /**< Write the transmit data bit [8]  */
00483     UART1->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART1_CR1_T8);
00484     /**< Write the transmit data bit [0:7] */
00485     UART1->DR   = (uint8_t)(Data);
00486 }
00487
00488 /**
00489   * @brief  Transmits break characters.
00490   * @param  None
00491   * @retval None
00492   */
00493 void UART1_SendBreak(void)
00494 {
00495     UART1->CR2 |= UART1_CR2_SBK;
00496 }
00497
00498 /**
00499   * @brief  Sets the address of the UART1 node.
00500   * @param  UART1_Address: Indicates the address of the UART1 node.
00501   * @retval None
00502   */
00503 void UART1_SetAddress(uint8_t UART1_Address)
00504 {
00505     /*assert_param for UART1_Address*/
00506     assert_param(IS_UART1_ADDRESS_OK(UART1_Address));
00507
00508     /* Clear the UART1 address */
00509     UART1->CR4 &= ((uint8_t)~UART1_CR4_ADD);
00510     /* Set the UART1 address node */
00511     UART1->CR4 |= UART1_Address;
00512 }
00513
00514 /**
00515   * @brief  Sets the specified UART guard time.
00516   * @note   SmartCard Mode should be Enabled
00517   * @param  UART1_GuardTime: specifies the guard time.
00518   * @retval None
00519   */
00520 void UART1_SetGuardTime(uint8_t UART1_GuardTime)
00521 {
00522     /* Set the UART1 guard time */
00523     UART1->GTR = UART1_GuardTime;
00524 }
00525
00526 /**
00527   * @brief  Sets the system clock prescaler.
00528   * @note   IrDA Low Power mode or smartcard mode should be enabled
00529   * @note   This function is related to SmartCard and IrDa mode.
00530   * @param  UART1_Prescaler: specifies the prescaler clock.
00531   *         This parameter can be one of the following values:
00532   *         @par IrDA Low Power Mode
00533   *         The clock source is divided by the value given in the register (8 bits)
00534   *         - 0000 0000 Reserved
00535   *         - 0000 0001 divides the clock source by 1
00536   *         - 0000 0010 divides the clock source by 2
00537   *         - ...........................................................
00538   *        @par Smart Card Mode
00539   *        The clock source is divided by the value given in the register
00540   *        (5 significant bits) multiplied by 2
00541   *         - 0 0000 Reserved
00542   *         - 0 0001 divides the clock source by 2
00543   *         - 0 0010 divides the clock source by 4
00544   *         - 0 0011 divides the clock source by 6
00545   *         - ...........................................................
00546   * @retval None
00547   */
00548 void UART1_SetPrescaler(uint8_t UART1_Prescaler)
00549 {
00550     /* Load the UART1 prescaler value*/
00551     UART1->PSCR = UART1_Prescaler;
00552 }
00553
00554 /**
00555   * @brief  Checks whether the specified UART1 flag is set or not.
00556   * @param  UART1_FLAG specifies the flag to check.
00557   *         This parameter can be any of the @ref UART1_Flag_TypeDef enumeration.
00558   * @retval FlagStatus (SET or RESET)
00559   */
00560 FlagStatus UART1_GetFlagStatus(UART1_Flag_TypeDef UART1_FLAG)
00561 {
00562     FlagStatus status = RESET;
00563
00564     /* Check parameters */
00565     assert_param(IS_UART1_FLAG_OK(UART1_FLAG));
00566
00567
00568     /* Check the status of the specified UART1 flag*/
00569     if (UART1_FLAG == UART1_FLAG_LBDF)
00570     {
00571         if ((UART1->CR4 & (uint8_t)UART1_FLAG) != (uint8_t)0x00)
00572         {
00573             /* UART1_FLAG is set*/
00574             status = SET;
00575         }
00576         else
00577         {
00578             /* UART1_FLAG is reset*/
00579             status = RESET;
00580         }
00581     }
00582     else if (UART1_FLAG == UART1_FLAG_SBK)
00583     {
00584         if ((UART1->CR2 & (uint8_t)UART1_FLAG) != (uint8_t)0x00)
00585         {
00586             /* UART1_FLAG is set*/
00587             status = SET;
00588         }
00589         else
00590         {
00591             /* UART1_FLAG is reset*/
00592             status = RESET;
00593         }
00594     }
00595     else
00596     {
00597         if ((UART1->SR & (uint8_t)UART1_FLAG) != (uint8_t)0x00)
00598         {
00599             /* UART1_FLAG is set*/
00600             status = SET;
00601         }
00602         else
00603         {
00604             /* UART1_FLAG is reset*/
00605             status = RESET;
00606         }
00607     }
00608     /* Return the UART1_FLAG status*/
00609     return status;
00610 }
00611
00612 /**
00613   * @brief  Clears the UART1 flags.
00614   * @param  UART1_FLAG specifies the flag to clear
00615   *         This parameter can be any combination of the following values:
00616   *         - UART1_FLAG_LBDF: LIN Break detection flag.
00617   *         - UART1_FLAG_RXNE: Receive data register not empty flag.
00618   * @note
00619   *         - PE (Parity error), FE (Framing error), NE (Noise error),
00620   *         OR (OverRun error) and IDLE (Idle line detected) flags are
00621   *         cleared by software sequence: a read operation to UART1_SR register
00622   *         (UART1_GetFlagStatus())followed by a read operation to UART1_DR
00623   *         register(UART1_ReceiveData8() or UART1_ReceiveData9()).
00624   *
00625   *         - RXNE flag can be also cleared by a read to the UART1_DR register
00626   *         (UART1_ReceiveData8()or UART1_ReceiveData9()).
00627   *
00628   *         - TC flag can be also cleared by software sequence: a read operation
00629   *         to UART1_SR register (UART1_GetFlagStatus()) followed by a write
00630   *         operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).
00631   *
00632   *         - TXE flag is cleared only by a write to the UART1_DR register
00633   *         (UART1_SendData8() or UART1_SendData9()).
00634   *
00635   *         - SBK flag is cleared during the stop bit of break.
00636   * @retval None
00637   */
00638
00639 void UART1_ClearFlag(UART1_Flag_TypeDef UART1_FLAG)
00640 {
00641     assert_param(IS_UART1_CLEAR_FLAG_OK(UART1_FLAG));
00642
00643     /* Clear the Receive Register Not Empty flag */
00644     if (UART1_FLAG == UART1_FLAG_RXNE)
00645     {
00646         UART1->SR = (uint8_t)~(UART1_SR_RXNE);
00647     }
00648     /* Clear the LIN Break Detection flag */
00649     else
00650     {
00651         UART1->CR4 &= (uint8_t)~(UART1_CR4_LBDF);
00652     }
00653 }
00654
00655 /**
00656   * @brief  Checks whether the specified UART1 interrupt has occurred or not.
00657   * @param  UART1_IT: Specifies the UART1 interrupt pending bit to check.
00658   *         This parameter can be one of the following values:
00659   *         - UART1_IT_LBDF:  LIN Break detection interrupt
00660   *         - UART1_IT_TXE:  Tansmit Data Register empty interrupt
00661   *         - UART1_IT_TC:   Transmission complete interrupt
00662   *         - UART1_IT_RXNE: Receive Data register not empty interrupt
00663   *         - UART1_IT_IDLE: Idle line detection interrupt
00664   *         - UART1_IT_OR:  OverRun Error interrupt
00665   *         - UART1_IT_PE:   Parity Error interrupt
00666   * @retval The new state of UART1_IT (SET or RESET).
00667   */
00668 ITStatus UART1_GetITStatus(UART1_IT_TypeDef UART1_IT)
00669 {
00670     ITStatus pendingbitstatus = RESET;
00671     uint8_t itpos = 0;
00672     uint8_t itmask1 = 0;
00673     uint8_t itmask2 = 0;
00674     uint8_t enablestatus = 0;
00675
00676     /* Check parameters */
00677     assert_param(IS_UART1_GET_IT_OK(UART1_IT));
00678
00679     /* Get the UART1 IT index */
00680     itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART1_IT & (uint8_t)0x0F));
00681     /* Get the UART1 IT index */
00682     itmask1 = (uint8_t)((uint8_t)UART1_IT >> (uint8_t)4);
00683     /* Set the IT mask*/
00684     itmask2 = (uint8_t)((uint8_t)1 << itmask1);
00685
00686
00687     /* Check the status of the specified UART1 pending bit*/
00688     if (UART1_IT == UART1_IT_PE)
00689     {
00690         /* Get the UART1_IT enable bit status*/
00691         enablestatus = (uint8_t)((uint8_t)UART1->CR1 & itmask2);
00692         /* Check the status of the specified UART1 interrupt*/
00693
00694         if (((UART1->SR & itpos) != (uint8_t)0x00) && enablestatus)
00695         {
00696             /* Interrupt occurred*/
00697             pendingbitstatus = SET;
00698         }
00699         else
00700         {
00701             /* Interrupt not occurred*/
00702             pendingbitstatus = RESET;
00703         }
00704     }
00705
00706     else if (UART1_IT == UART1_IT_LBDF)
00707     {
00708         /* Get the UART1_IT enable bit status*/
00709         enablestatus = (uint8_t)((uint8_t)UART1->CR4 & itmask2);
00710         /* Check the status of the specified UART1 interrupt*/
00711         if (((UART1->CR4 & itpos) != (uint8_t)0x00) && enablestatus)
00712         {
00713             /* Interrupt occurred*/
00714             pendingbitstatus = SET;
00715         }
00716         else
00717         {
00718             /* Interrupt not occurred*/
00719             pendingbitstatus = RESET;
00720         }
00721     }
00722     else
00723     {
00724         /* Get the UART1_IT enable bit status*/
00725         enablestatus = (uint8_t)((uint8_t)UART1->CR2 & itmask2);
00726         /* Check the status of the specified UART1 interrupt*/
00727         if (((UART1->SR & itpos) != (uint8_t)0x00) && enablestatus)
00728         {
00729             /* Interrupt occurred*/
00730             pendingbitstatus = SET;
00731         }
00732         else
00733         {
00734             /* Interrupt not occurred*/
00735             pendingbitstatus = RESET;
00736         }
00737     }
00738
00739     /* Return the UART1_IT status*/
00740     return  pendingbitstatus;
00741 }
00742
00743 /**
00744   * @brief  Clears the UART1 pending flags.
00745   * @param  UART1_IT specifies the pending bit to clear
00746   *         This parameter can be one of the following values:
00747   *         - UART1_IT_LBDF:  LIN Break detection interrupt
00748   *         - UART1_IT_RXNE: Receive Data register not empty interrupt.
00749   * @note
00750   *         - PE (Parity error), FE (Framing error), NE (Noise error),
00751   *           OR (OverRun error) and IDLE (Idle line detected) pending bits are
00752   *           cleared by software sequence: a read operation to UART1_SR register
00753   *           (UART1_GetITStatus()) followed by a read operation to UART1_DR register
00754   *           (UART1_ReceiveData8() or UART1_ReceiveData9()).
00755   *
00756   *         - RXNE pending bit can be also cleared by a read to the UART1_DR register
00757   *           (UART1_ReceiveData8() or UART1_ReceiveData9()).
00758   *
00759   *         - TC (Transmit complete) pending bit can be cleared by software
00760   *           sequence: a read operation to UART1_SR register (UART1_GetITStatus())
00761   *           followed by a write operation to UART1_DR register (UART1_SendData8()
00762   *           or UART1_SendData9()).
00763   *
00764   *         - TXE pending bit is cleared only by a write to the UART1_DR register
00765   *           (UART1_SendData8() or UART1_SendData9()).
00766   * @retval None
00767   */
00768 void UART1_ClearITPendingBit(UART1_IT_TypeDef UART1_IT)
00769 {
00770     assert_param(IS_UART1_CLEAR_IT_OK(UART1_IT));
00771
00772     /* Clear the Receive Register Not Empty pending bit */
00773     if (UART1_IT == UART1_IT_RXNE)
00774     {
00775         UART1->SR = (uint8_t)~(UART1_SR_RXNE);
00776     }
00777     /* Clear the LIN Break Detection pending bit */
00778     else
00779     {
00780         UART1->CR4 &= (uint8_t)~(UART1_CR4_LBDF);
00781     }
00782 }
00783
00784 /**
00785   * @}
00786   */
00787
00788 /**
00789   * @}
00790   */
00791
00792 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart1.h Source File

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stm8s_uart1.h

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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart1.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototypes and macros for the UART1 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_UART1_H
00024 #define __STM8S_UART1_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /* Exported types ------------------------------------------------------------*/
00034
00035 /** @addtogroup UART1_Exported_Types
00036   * @{
00037   */
00038
00039
00040 /**
00041   * @brief  UART1 Irda Modes
00042   */
00043
00044 typedef enum { UART1_IRDAMODE_NORMAL    = (uint8_t)0x00, /**< 0x00 Irda Normal Mode   */
00045                UART1_IRDAMODE_LOWPOWER  = (uint8_t)0x01  /**< 0x01 Irda Low Power Mode */
00046              } UART1_IrDAMode_TypeDef;
00047
00048 /**
00049   * @brief  UART1 WakeUP Modes
00050   */
00051 typedef enum { UART1_WAKEUP_IDLELINE       = (uint8_t)0x00, /**< 0x01 Idle Line wake up                */
00052                UART1_WAKEUP_ADDRESSMARK    = (uint8_t)0x08  /**< 0x02 Address Mark wake up          */
00053              } UART1_WakeUp_TypeDef;
00054
00055 /**
00056   * @brief  UART1 LIN Break detection length possible values
00057   */
00058 typedef enum { UART1_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, /**< 0x01 10 bits Lin Break detection            */
00059                UART1_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01  /**< 0x02 11 bits Lin Break detection          */
00060              } UART1_LINBreakDetectionLength_TypeDef;
00061
00062 /**
00063   * @brief  UART1 stop bits possible values
00064   */
00065
00066 typedef enum { UART1_STOPBITS_1   = (uint8_t)0x00,    /**< One stop bit is  transmitted at the end of frame*/
00067                UART1_STOPBITS_0_5 = (uint8_t)0x10,    /**< Half stop bits is transmitted at the end of frame*/
00068                UART1_STOPBITS_2   = (uint8_t)0x20,    /**< Two stop bits are  transmitted at the end of frame*/
00069                UART1_STOPBITS_1_5 = (uint8_t)0x30     /**< One and half stop bits*/
00070              } UART1_StopBits_TypeDef;
00071
00072 /**
00073   * @brief  UART1 parity possible values
00074   */
00075 typedef enum { UART1_PARITY_NO     = (uint8_t)0x00,      /**< No Parity*/
00076                UART1_PARITY_EVEN   = (uint8_t)0x04,      /**< Even Parity*/
00077                UART1_PARITY_ODD    = (uint8_t)0x06       /**< Odd Parity*/
00078              } UART1_Parity_TypeDef;
00079
00080 /**
00081   * @brief  UART1 Synchrone modes
00082   */
00083 typedef enum { UART1_SYNCMODE_CLOCK_DISABLE    = (uint8_t)0x80, /**< 0x80 Sync mode Disable, SLK pin Disable */
00084                UART1_SYNCMODE_CLOCK_ENABLE     = (uint8_t)0x08, /**< 0x08 Sync mode Enable, SLK pin Enable     */
00085                UART1_SYNCMODE_CPOL_LOW         = (uint8_t)0x40, /**< 0x40 Steady low value on SCLK pin outside transmission window */
00086                UART1_SYNCMODE_CPOL_HIGH        = (uint8_t)0x04, /**< 0x04 Steady high value on SCLK pin outside transmission window */
00087                UART1_SYNCMODE_CPHA_MIDDLE      = (uint8_t)0x20, /**< 0x20 SCLK clock line activated in middle of data bit     */
00088                UART1_SYNCMODE_CPHA_BEGINING    = (uint8_t)0x02, /**< 0x02 SCLK clock line activated at beginning of data bit  */
00089                UART1_SYNCMODE_LASTBIT_DISABLE  = (uint8_t)0x10, /**< 0x10 The clock pulse of the last data bit is not output to the SCLK pin */
00090                UART1_SYNCMODE_LASTBIT_ENABLE   = (uint8_t)0x01  /**< 0x01 The clock pulse of the last data bit is output to the SCLK pin */
00091              } UART1_SyncMode_TypeDef;
00092
00093 /**
00094   * @brief  UART1 Word length possible values
00095   */
00096 typedef enum { UART1_WORDLENGTH_8D = (uint8_t)0x00,/**< 0x00 8 bits Data  */
00097                UART1_WORDLENGTH_9D = (uint8_t)0x10 /**< 0x10 9 bits Data  */
00098              } UART1_WordLength_TypeDef;
00099
00100 /**
00101   * @brief  UART1 Mode possible values
00102   */
00103 typedef enum { UART1_MODE_RX_ENABLE     = (uint8_t)0x08,  /**< 0x08 Receive Enable */
00104                UART1_MODE_TX_ENABLE     = (uint8_t)0x04,  /**< 0x04 Transmit Enable */
00105                UART1_MODE_TX_DISABLE    = (uint8_t)0x80,  /**< 0x80 Transmit Disable */
00106                UART1_MODE_RX_DISABLE    = (uint8_t)0x40,  /**< 0x40 Single-wire Half-duplex mode */
00107                UART1_MODE_TXRX_ENABLE   = (uint8_t)0x0C  /**< 0x0C Transmit Enable and Receive Enable */
00108              } UART1_Mode_TypeDef;
00109
00110 /**
00111   * @brief  UART1 Flag possible values
00112   */
00113 typedef enum { UART1_FLAG_TXE   = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */
00114                UART1_FLAG_TC    = (uint16_t)0x0040, /*!< Transmission Complete flag */
00115                UART1_FLAG_RXNE  = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */
00116                UART1_FLAG_IDLE  = (uint16_t)0x0010, /*!< Idle line detected flag */
00117                UART1_FLAG_OR    = (uint16_t)0x0008, /*!< OverRun error flag */
00118                UART1_FLAG_NF    = (uint16_t)0x0004, /*!< Noise error flag */
00119                UART1_FLAG_FE    = (uint16_t)0x0002, /*!< Framing Error flag */
00120                UART1_FLAG_PE    = (uint16_t)0x0001, /*!< Parity Error flag */
00121                UART1_FLAG_LBDF  = (uint16_t)0x0210, /*!< Line Break Detection Flag */
00122                UART1_FLAG_SBK   = (uint16_t)0x0101  /*!< Send Break characters Flag */
00123              } UART1_Flag_TypeDef;
00124
00125 /**
00126   * @brief  UART1 Interrupt definition
00127   * UART1_IT possible values
00128   * Elements values convention: 0xZYX
00129   * X: Position of the corresponding Interrupt
00130   *   - For the following values, X means the interrupt position in the CR2 register.
00131   *     UART1_IT_TXE
00132   *     UART1_IT_TC
00133   *     UART1_IT_RXNE
00134   *     UART1_IT_IDLE
00135   *     UART1_IT_OR
00136   *   - For the UART1_IT_PE value, X means the flag position in the CR1 register.
00137   *   - For the UART1_IT_LBDF value, X means the flag position in the CR4 register.
00138   * Y: Flag position
00139   *  - For the following values, Y means the flag (pending bit) position in the SR register.
00140   *     UART1_IT_TXE
00141   *     UART1_IT_TC
00142   *     UART1_IT_RXNE
00143   *     UART1_IT_IDLE
00144   *     UART1_IT_OR
00145   *     UART1_IT_PE
00146   *  - For the UART1_IT_LBDF value, Y means the flag position in the CR4 register.
00147   * Z: Register index: indicate in which register the dedicated interrupt source is:
00148   *  - 1==> CR1 register
00149   *  - 2==> CR2 register
00150   *  - 3==> CR4 register
00151   */
00152 typedef enum { UART1_IT_TXE        = (uint16_t)0x0277, /*!< Transmit interrupt */
00153                UART1_IT_TC         = (uint16_t)0x0266, /*!< Transmission Complete interrupt */
00154                UART1_IT_RXNE       = (uint16_t)0x0255, /*!< Receive interrupt */
00155                UART1_IT_IDLE       = (uint16_t)0x0244, /*!< IDLE line interrupt */
00156                UART1_IT_OR         = (uint16_t)0x0235, /*!< Overrun Error interrupt */
00157                UART1_IT_PE         = (uint16_t)0x0100, /*!< Parity Error interrupt */
00158                UART1_IT_LBDF       = (uint16_t)0x0346, /**< LIN break detection interrupt */
00159                UART1_IT_RXNE_OR    = (uint16_t)0x0205  /*!< Receive/Overrun interrupt */
00160              } UART1_IT_TypeDef;
00161
00162 /**
00163   * @}
00164   */
00165
00166 /* Exported constants --------------------------------------------------------*/
00167 /* Exported macros ------------------------------------------------------------*/
00168
00169 /* Private macros ------------------------------------------------------------*/
00170
00171 /** @addtogroup UART1_Private_Macros
00172   * @{
00173   */
00174
00175 /**
00176   * @brief  Macro used by the assert function to check the different functions parameters.
00177   */
00178
00179 /**
00180  * @brief Macro used by the assert_param function in order to check the different
00181  *        sensitivity values for the MODEs possible combination should be one of
00182  *        the following
00183  */
00184 #define IS_UART1_MODE_OK(Mode) \
00185   (((Mode) == (uint8_t)UART1_MODE_RX_ENABLE) || \
00186    ((Mode) == (uint8_t)UART1_MODE_RX_DISABLE) || \
00187    ((Mode) == (uint8_t)UART1_MODE_TX_ENABLE) || \
00188    ((Mode) == (uint8_t)UART1_MODE_TX_DISABLE) || \
00189    ((Mode) == (uint8_t)UART1_MODE_TXRX_ENABLE) || \
00190    ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_ENABLE|(uint8_t)UART1_MODE_RX_ENABLE)) || \
00191    ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_ENABLE|(uint8_t)UART1_MODE_RX_DISABLE)) || \
00192    ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_DISABLE|(uint8_t)UART1_MODE_RX_DISABLE)) || \
00193    ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_DISABLE|(uint8_t)UART1_MODE_RX_ENABLE)))
00194
00195 /**
00196  * @brief Macro used by the assert_param function in order to check the different
00197  *        sensitivity values for the WordLengths
00198  */
00199 #define IS_UART1_WORDLENGTH_OK(WordLength) \
00200   (((WordLength) == UART1_WORDLENGTH_8D) || \
00201    ((WordLength) == UART1_WORDLENGTH_9D))
00202
00203 /**
00204   * @brief  Macro used by the assert_param function in order to check the different
00205   *         sensitivity values for the SyncModes; it should exclude values such
00206   *         as  UART1_CLOCK_ENABLE|UART1_CLOCK_DISABLE
00207   */
00208 #define IS_UART1_SYNCMODE_OK(SyncMode) \
00209   (!((((SyncMode)&(((uint8_t)UART1_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART1_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART1_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART1_SYNCMODE_CLOCK_DISABLE))) \
00210     || (((SyncMode)&(((uint8_t)UART1_SYNCMODE_CPOL_LOW )|((uint8_t)UART1_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART1_SYNCMODE_CPOL_LOW )|((uint8_t)UART1_SYNCMODE_CPOL_HIGH))) \
00211     ||(((SyncMode)&(((uint8_t)UART1_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART1_SYNCMODE_CPHA_BEGINING))) ==  (((uint8_t)UART1_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART1_SYNCMODE_CPHA_BEGINING))) \
00212     || (((SyncMode)&(((uint8_t)UART1_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART1_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART1_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART1_SYNCMODE_LASTBIT_ENABLE)))))
00213
00214 /**
00215   * @brief  Macro used by the assert_param function in order to check the different
00216   *         sensitivity values for the FLAGs
00217   */
00218 #define IS_UART1_FLAG_OK(Flag) \
00219   (((Flag) == UART1_FLAG_TXE) || \
00220    ((Flag) == UART1_FLAG_TC)  || \
00221    ((Flag) == UART1_FLAG_RXNE) || \
00222    ((Flag) == UART1_FLAG_IDLE) || \
00223    ((Flag) == UART1_FLAG_OR) || \
00224    ((Flag) == UART1_FLAG_NF) || \
00225    ((Flag) == UART1_FLAG_FE) || \
00226    ((Flag) == UART1_FLAG_PE) || \
00227    ((Flag) == UART1_FLAG_SBK) || \
00228    ((Flag) == UART1_FLAG_LBDF))
00229 /**
00230   * @brief  Macro used by the assert_param function in order to check the different
00231   *         sensitivity values for the FLAGs that can be cleared by writing 0
00232   */
00233 #define IS_UART1_CLEAR_FLAG_OK(Flag) \
00234   (((Flag) == UART1_FLAG_RXNE) || \
00235    ((Flag) == UART1_FLAG_LBDF))
00236
00237
00238
00239 /**
00240   * @brief  Macro used by the assert_param function in order to check the different
00241   *         sensitivity values for the Interrupts
00242   */
00243
00244 #define IS_UART1_CONFIG_IT_OK(Interrupt) \
00245   (((Interrupt) == UART1_IT_PE) || \
00246    ((Interrupt) == UART1_IT_TXE) || \
00247    ((Interrupt) == UART1_IT_TC) || \
00248    ((Interrupt) == UART1_IT_RXNE_OR ) || \
00249    ((Interrupt) == UART1_IT_IDLE) || \
00250    ((Interrupt) == UART1_IT_LBDF))
00251
00252 /**
00253   * @brief  Macro used by the assert function in order to check the different
00254   *         sensitivity values for the pending bit
00255   */
00256 #define IS_UART1_GET_IT_OK(ITPendingBit) \
00257   (((ITPendingBit) == UART1_IT_TXE)  || \
00258    ((ITPendingBit) == UART1_IT_TC)   || \
00259    ((ITPendingBit) == UART1_IT_RXNE) || \
00260    ((ITPendingBit) == UART1_IT_IDLE) || \
00261    ((ITPendingBit) == UART1_IT_OR)  || \
00262    ((ITPendingBit) == UART1_IT_LBDF)  || \
00263    ((ITPendingBit) == UART1_IT_PE))
00264
00265 /**
00266   * @brief  Macro used by the assert function in order to check the different
00267   *         sensitivity values for the pending bit that can be cleared by writing 0
00268   */
00269 #define IS_UART1_CLEAR_IT_OK(ITPendingBit) \
00270   (((ITPendingBit) == UART1_IT_RXNE) || \
00271    ((ITPendingBit) == UART1_IT_LBDF))
00272
00273
00274 /**
00275  * @brief Macro used by the assert_param function in order to check the different
00276  *        sensitivity values for the IrDAModes
00277  */
00278 #define IS_UART1_IRDAMODE_OK(IrDAMode) \
00279   (((IrDAMode) == UART1_IRDAMODE_LOWPOWER) || \
00280    ((IrDAMode) == UART1_IRDAMODE_NORMAL))
00281
00282 /**
00283   * @brief  Macro used by the assert_param function in order to check the different
00284   *         sensitivity values for the WakeUps
00285   */
00286 #define IS_UART1_WAKEUP_OK(WakeUp) \
00287   (((WakeUp) == UART1_WAKEUP_IDLELINE) || \
00288    ((WakeUp) == UART1_WAKEUP_ADDRESSMARK))
00289
00290 /**
00291   * @brief  Macro used by the assert_param function in order to check the different
00292   *        sensitivity values for the LINBreakDetectionLengths
00293   */
00294 #define IS_UART1_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength) \
00295   (((LINBreakDetectionLength) == UART1_LINBREAKDETECTIONLENGTH_10BITS) || \
00296    ((LINBreakDetectionLength) == UART1_LINBREAKDETECTIONLENGTH_11BITS))
00297
00298 /**
00299   * @brief  Macro used by the assert_param function in order to check the different
00300   *         sensitivity values for the UART1_StopBits
00301   */
00302 #define IS_UART1_STOPBITS_OK(StopBit) (((StopBit) == UART1_STOPBITS_1) || \
00303                                        ((StopBit) == UART1_STOPBITS_0_5) || \
00304                                        ((StopBit) == UART1_STOPBITS_2) || \
00305                                        ((StopBit) == UART1_STOPBITS_1_5 ))
00306
00307 /**
00308  * @brief Macro used by the assert_param function in order to check the different
00309  *        sensitivity values for the Paritys
00310  */
00311 #define IS_UART1_PARITY_OK(Parity) (((Parity) == UART1_PARITY_NO) || \
00312                                     ((Parity) == UART1_PARITY_EVEN) || \
00313                                     ((Parity) == UART1_PARITY_ODD ))
00314
00315 /**
00316  * @brief Macro used by the assert_param function in order to check the maximum
00317  *        baudrate value
00318  */
00319 #define IS_UART1_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
00320
00321
00322 /**
00323  * @brief Macro used by the assert_param function in order to check the address
00324  *        of the UART1 or UART node
00325  */
00326 #define UART1_ADDRESS_MAX ((uint8_t)16)
00327 #define IS_UART1_ADDRESS_OK(node) ((node) < UART1_ADDRESS_MAX )
00328
00329 /**
00330   * @}
00331   */
00332
00333 /* Exported functions ------------------------------------------------------- */
00334
00335 /** @addtogroup UART1_Exported_Functions
00336   * @{
00337   */
00338
00339 void UART1_DeInit(void);
00340 void UART1_Init(uint32_t BaudRate, UART1_WordLength_TypeDef WordLength,
00341                 UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity,
00342                 UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode);
00343 void UART1_Cmd(FunctionalState NewState);
00344 void UART1_ITConfig(UART1_IT_TypeDef UART1_IT, FunctionalState NewState);
00345 void UART1_HalfDuplexCmd(FunctionalState NewState);
00346 void UART1_IrDAConfig(UART1_IrDAMode_TypeDef UART1_IrDAMode);
00347 void UART1_IrDACmd(FunctionalState NewState);
00348 void UART1_LINBreakDetectionConfig(UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength);
00349 void UART1_LINCmd(FunctionalState NewState);
00350 void UART1_SmartCardCmd(FunctionalState NewState);
00351 void UART1_SmartCardNACKCmd(FunctionalState NewState);
00352 void UART1_WakeUpConfig(UART1_WakeUp_TypeDef UART1_WakeUp);
00353 void UART1_ReceiverWakeUpCmd(FunctionalState NewState);
00354 uint8_t UART1_ReceiveData8(void);
00355 uint16_t UART1_ReceiveData9(void);
00356 void UART1_SendData8(uint8_t Data);
00357 void UART1_SendData9(uint16_t Data);
00358 void UART1_SendBreak(void);
00359 void UART1_SetAddress(uint8_t UART1_Address);
00360 void UART1_SetGuardTime(uint8_t UART1_GuardTime);
00361 void UART1_SetPrescaler(uint8_t UART1_Prescaler);
00362 FlagStatus UART1_GetFlagStatus(UART1_Flag_TypeDef UART1_FLAG);
00363 void UART1_ClearFlag(UART1_Flag_TypeDef UART1_FLAG);
00364 ITStatus UART1_GetITStatus(UART1_IT_TypeDef UART1_IT);
00365 void UART1_ClearITPendingBit(UART1_IT_TypeDef UART1_IT);
00366
00367 /**
00368   * @}
00369   */
00370
00371 #endif /* __STM8S_UART1_H */
00372
00373 /**
00374   * @}
00375   */
00376 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart2.c Source File

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stm8s_uart2.c

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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart2.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the UART2 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_uart2.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034 /* Public functions ----------------------------------------------------------*/
00035
00036 /** @}
00037   * @addtogroup UART2_Public_Functions
00038   * @{
00039   */
00040
00041 /**
00042   * @brief  Deinitializes the UART peripheral.
00043   * @param  None
00044   * @retval None
00045   */
00046
00047 void UART2_DeInit(void)
00048 {
00049     /*  Clear the Idle Line Detected bit in the status register by a read
00050        to the UART2_SR register followed by a Read to the UART2_DR register */
00051     (void) UART2->SR;
00052     (void)UART2->DR;
00053
00054     UART2->BRR2 = UART2_BRR2_RESET_VALUE;  /*  Set UART2_BRR2 to reset value 0x00 */
00055     UART2->BRR1 = UART2_BRR1_RESET_VALUE;  /*  Set UART2_BRR1 to reset value 0x00 */
00056
00057     UART2->CR1 = UART2_CR1_RESET_VALUE; /*  Set UART2_CR1 to reset value 0x00  */
00058     UART2->CR2 = UART2_CR2_RESET_VALUE; /*  Set UART2_CR2 to reset value 0x00  */
00059     UART2->CR3 = UART2_CR3_RESET_VALUE; /*  Set UART2_CR3 to reset value 0x00  */
00060     UART2->CR4 = UART2_CR4_RESET_VALUE; /*  Set UART2_CR4 to reset value 0x00  */
00061     UART2->CR5 = UART2_CR5_RESET_VALUE; /*  Set UART2_CR5 to reset value 0x00  */
00062     UART2->CR6 = UART2_CR6_RESET_VALUE; /*  Set UART2_CR6 to reset value 0x00  */
00063
00064 }
00065
00066 /**
00067   * @brief  Initializes the UART2 according to the specified parameters.
00068   * @param  BaudRate: The baudrate.
00069   * @param  WordLength : This parameter can be any of the
00070   *         @ref UART2_WordLength_TypeDef enumeration.
00071   * @param  StopBits: This parameter can be any of the
00072   *         @ref UART2_StopBits_TypeDef enumeration.
00073   * @param  Parity: This parameter can be any of the
00074   *         @ref UART2_Parity_TypeDef enumeration.
00075   * @param  SyncMode: This parameter can be any of the
00076   *         @ref UART2_SyncMode_TypeDef values.
00077   * @param  Mode: This parameter can be any of the @ref UART2_Mode_TypeDef values
00078   * @retval None
00079   */
00080 void UART2_Init(uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
00081 {
00082     uint8_t BRR2_1 = 0, BRR2_2 = 0;
00083     uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;
00084
00085     /* Check the parameters */
00086     assert_param(IS_UART2_BAUDRATE_OK(BaudRate));
00087     assert_param(IS_UART2_WORDLENGTH_OK(WordLength));
00088     assert_param(IS_UART2_STOPBITS_OK(StopBits));
00089     assert_param(IS_UART2_PARITY_OK(Parity));
00090     assert_param(IS_UART2_MODE_OK((uint8_t)Mode));
00091     assert_param(IS_UART2_SYNCMODE_OK((uint8_t)SyncMode));
00092
00093      /* Clear the word length bit */
00094     UART2->CR1 &= (uint8_t)(~UART2_CR1_M);
00095     /* Set the word length bit according to UART2_WordLength value */
00096     UART2->CR1 |= (uint8_t)WordLength;
00097
00098     /* Clear the STOP bits */
00099     UART2->CR3 &= (uint8_t)(~UART2_CR3_STOP);
00100     /* Set the STOP bits number according to UART2_StopBits value  */
00101     UART2->CR3 |= (uint8_t)StopBits;
00102
00103     /* Clear the Parity Control bit */
00104     UART2->CR1 &= (uint8_t)(~(UART2_CR1_PCEN | UART2_CR1_PS  ));
00105     /* Set the Parity Control bit to UART2_Parity value */
00106     UART2->CR1 |= (uint8_t)Parity;
00107
00108     /* Clear the LSB mantissa of UART2DIV  */
00109     UART2->BRR1 &= (uint8_t)(~UART2_BRR1_DIVM);
00110     /* Clear the MSB mantissa of UART2DIV  */
00111     UART2->BRR2 &= (uint8_t)(~UART2_BRR2_DIVM);
00112     /* Clear the Fraction bits of UART2DIV */
00113     UART2->BRR2 &= (uint8_t)(~UART2_BRR2_DIVF);
00114
00115     /* Set the UART2 BaudRates in BRR1 and BRR2 registers according to UART2_BaudRate value */
00116     BaudRate_Mantissa    = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4));
00117     BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4));
00118
00119     /* The fraction and MSB mantissa should be loaded in one step in the BRR2 register*/
00120     /* Set the fraction of UARTDIV  */
00121     BRR2_1 = (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
00122                         << 4) / 100) & (uint8_t)0x0F);
00123     BRR2_2 = (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0);
00124
00125     UART2->BRR2 = (uint8_t)(BRR2_1 | BRR2_2);
00126     /* Set the LSB mantissa of UARTDIV  */
00127     UART2->BRR1 = (uint8_t)BaudRate_Mantissa;
00128
00129     /* Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */
00130     UART2->CR2 &= (uint8_t)~(UART2_CR2_TEN | UART2_CR2_REN);
00131     /* Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
00132     UART2->CR3 &= (uint8_t)~(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL);
00133     /* Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
00134     UART2->CR3 |= (uint8_t)((uint8_t)SyncMode & (uint8_t)(UART2_CR3_CPOL | \
00135                                               UART2_CR3_CPHA | UART2_CR3_LBCL));
00136
00137     if ((uint8_t)(Mode & UART2_MODE_TX_ENABLE))
00138     {
00139         /* Set the Transmitter Enable bit */
00140         UART2->CR2 |= (uint8_t)UART2_CR2_TEN;
00141     }
00142     else
00143     {
00144         /* Clear the Transmitter Disable bit */
00145         UART2->CR2 &= (uint8_t)(~UART2_CR2_TEN);
00146     }
00147     if ((uint8_t)(Mode & UART2_MODE_RX_ENABLE))
00148     {
00149         /* Set the Receiver Enable bit */
00150         UART2->CR2 |= (uint8_t)UART2_CR2_REN;
00151     }
00152     else
00153     {
00154         /* Clear the Receiver Disable bit */
00155         UART2->CR2 &= (uint8_t)(~UART2_CR2_REN);
00156     }
00157     /* Set the Clock Enable bit, lock Polarity, lock Phase and Last Bit Clock
00158            pulse bits according to UART2_Mode value */
00159     if ((uint8_t)(SyncMode & UART2_SYNCMODE_CLOCK_DISABLE))
00160     {
00161         /* Clear the Clock Enable bit */
00162         UART2->CR3 &= (uint8_t)(~UART2_CR3_CKEN);
00163     }
00164     else
00165     {
00166         UART2->CR3 |= (uint8_t)((uint8_t)SyncMode & UART2_CR3_CKEN);
00167     }
00168 }
00169
00170 /**
00171   * @brief  Enable the UART2 peripheral.
00172   * @param  NewState : The new state of the UART Communication.
00173   *         This parameter can be any of the @ref FunctionalState enumeration.
00174   * @retval None
00175   */
00176 void UART2_Cmd(FunctionalState NewState)
00177 {
00178
00179     if (NewState != DISABLE)
00180     {
00181         /* UART2 Enable */
00182         UART2->CR1 &= (uint8_t)(~UART2_CR1_UARTD);
00183     }
00184     else
00185     {
00186         /* UART2 Disable */
00187         UART2->CR1 |= UART2_CR1_UARTD;
00188     }
00189 }
00190
00191 /**
00192   * @brief  Enables or disables the specified UART2 interrupts.
00193   * @param  UART2_IT specifies the UART2 interrupt sources to be enabled or disabled.
00194   *         This parameter can be one of the following values:
00195   *         - UART2_IT_LBDF:  LIN Break detection interrupt
00196   *         - UART2_IT_LHDF:  LIN Break detection interrupt
00197   *         - UART2_IT_TXE:  Tansmit Data Register empty interrupt
00198   *         - UART2_IT_TC:   Transmission complete interrupt
00199   *         - UART2_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
00200   *         - UART2_IT_IDLE: Idle line detection interrupt
00201   *         - UART2_IT_PE:   Parity Error interrupt
00202   * @param  NewState new state of the specified UART2 interrupts.
00203   *         This parameter can be: ENABLE or DISABLE.
00204   * @retval None
00205   */
00206 void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
00207 {
00208     uint8_t uartreg = 0, itpos = 0x00;
00209
00210     /* Check the parameters */
00211     assert_param(IS_UART2_CONFIG_IT_OK(UART2_IT));
00212     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00213
00214     /* Get the UART2 register index */
00215     uartreg = (uint8_t)((uint16_t)UART2_IT >> 0x08);
00216
00217     /* Get the UART2 IT index */
00218     itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART2_IT & (uint8_t)0x0F));
00219
00220     if (NewState != DISABLE)
00221     {
00222         /* Enable the Interrupt bits according to UART2_IT mask */
00223         if (uartreg == 0x01)
00224         {
00225             UART2->CR1 |= itpos;
00226         }
00227         else if (uartreg == 0x02)
00228         {
00229             UART2->CR2 |= itpos;
00230         }
00231         else if (uartreg == 0x03)
00232         {
00233             UART2->CR4 |= itpos;
00234         }
00235         else
00236         {
00237             UART2->CR6 |= itpos;
00238         }
00239     }
00240     else
00241     {
00242         /* Disable the interrupt bits according to UART2_IT mask */
00243         if (uartreg == 0x01)
00244         {
00245             UART2->CR1 &= (uint8_t)(~itpos);
00246         }
00247         else if (uartreg == 0x02)
00248         {
00249             UART2->CR2 &= (uint8_t)(~itpos);
00250         }
00251         else if (uartreg == 0x03)
00252         {
00253             UART2->CR4 &= (uint8_t)(~itpos);
00254         }
00255         else
00256         {
00257             UART2->CR6 &= (uint8_t)(~itpos);
00258         }
00259     }
00260 }
00261 /**
00262   * @brief  Configures the UART2’s IrDA interface.
00263   * @param  UART2_IrDAMode specifies the IrDA mode.
00264   *         This parameter can be any of the @ref UART2_IrDAMode_TypeDef values.
00265   * @retval None
00266   */
00267 void UART2_IrDAConfig(UART2_IrDAMode_TypeDef UART2_IrDAMode)
00268 {
00269     assert_param(IS_UART2_IRDAMODE_OK(UART2_IrDAMode));
00270
00271     if (UART2_IrDAMode != UART2_IRDAMODE_NORMAL)
00272     {
00273         UART2->CR5 |= UART2_CR5_IRLP;
00274     }
00275     else
00276     {
00277         UART2->CR5 &= ((uint8_t)~UART2_CR5_IRLP);
00278     }
00279 }
00280
00281 /**
00282   * @brief  Enables or disables the UART2’s IrDA interface.
00283   * @param  NewState new state of the IrDA mode.
00284   *         This parameter can be: ENABLE or DISABLE.
00285   * @retval None
00286   */
00287 void UART2_IrDACmd(FunctionalState NewState)
00288 {
00289     /* Check parameters */
00290     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00291
00292     if (NewState != DISABLE)
00293     {
00294         /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
00295         UART2->CR5 |= UART2_CR5_IREN;
00296     }
00297     else
00298     {
00299         /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
00300         UART2->CR5 &= ((uint8_t)~UART2_CR5_IREN);
00301     }
00302 }
00303
00304 /**
00305   * @brief  Sets the UART2 LIN Break detection length.
00306   * @param  UART2_LINBreakDetectionLength specifies the LIN break detection length.
00307   *         This parameter can be any of the
00308   *         @ref UART2_LINBreakDetectionLength_TypeDef values.
00309   * @retval None
00310   */
00311 void UART2_LINBreakDetectionConfig(UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
00312 {
00313     /* Check parameters */
00314     assert_param(IS_UART2_LINBREAKDETECTIONLENGTH_OK(UART2_LINBreakDetectionLength));
00315
00316     if (UART2_LINBreakDetectionLength != UART2_LINBREAKDETECTIONLENGTH_10BITS)
00317     {
00318         UART2->CR4 |= UART2_CR4_LBDL;
00319     }
00320     else
00321     {
00322         UART2->CR4 &= ((uint8_t)~UART2_CR4_LBDL);
00323     }
00324 }
00325
00326 /**
00327   * @brief  Configure the UART2 peripheral.
00328   * @param  UART2_Mode specifies the LIN mode.
00329   *         This parameter can be any of the @ref UART2_LinMode_TypeDef values.
00330   * @param  UART2_Autosync specifies the LIN automatic resynchronization mode.
00331   *         This parameter can be any of the @ref UART2_LinAutosync_TypeDef values.
00332   * @param  UART2_DivUp specifies the LIN divider update method.
00333   *         This parameter can be any of the @ref UART2_LinDivUp_TypeDef values.
00334   * @retval None
00335   */
00336 void UART2_LINConfig(UART2_LinMode_TypeDef UART2_Mode,
00337                      UART2_LinAutosync_TypeDef UART2_Autosync,
00338                      UART2_LinDivUp_TypeDef UART2_DivUp)
00339 {
00340     /* Check parameters */
00341     assert_param(IS_UART2_SLAVE_OK(UART2_Mode));
00342     assert_param(IS_UART2_AUTOSYNC_OK(UART2_Autosync));
00343     assert_param(IS_UART2_DIVUP_OK(UART2_DivUp));
00344
00345     if (UART2_Mode != UART2_LIN_MODE_MASTER)
00346     {
00347         UART2->CR6 |=  UART2_CR6_LSLV;
00348     }
00349     else
00350     {
00351         UART2->CR6 &= ((uint8_t)~UART2_CR6_LSLV);
00352     }
00353
00354     if (UART2_Autosync != UART2_LIN_AUTOSYNC_DISABLE)
00355     {
00356         UART2->CR6 |=  UART2_CR6_LASE ;
00357     }
00358     else
00359     {
00360         UART2->CR6 &= ((uint8_t)~ UART2_CR6_LASE );
00361     }
00362
00363     if (UART2_DivUp != UART2_LIN_DIVUP_LBRR1)
00364     {
00365         UART2->CR6 |=  UART2_CR6_LDUM;
00366     }
00367     else
00368     {
00369         UART2->CR6 &= ((uint8_t)~ UART2_CR6_LDUM);
00370     }
00371 }
00372
00373 /**
00374   * @brief  Enables or disables the UART2 LIN mode.
00375   * @param  NewState is new state of the UART2 LIN mode.
00376   *         This parameter can be ENABLE or DISABLE
00377   * @retval None
00378   */
00379 void UART2_LINCmd(FunctionalState NewState)
00380 {
00381     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00382
00383     if (NewState != DISABLE)
00384     {
00385         /* Enable the LIN mode by setting the LINE bit in the CR2 register */
00386         UART2->CR3 |= UART2_CR3_LINEN;
00387     }
00388     else
00389     {
00390         /* Disable the LIN mode by clearing the LINE bit in the CR2 register */
00391         UART2->CR3 &= ((uint8_t)~UART2_CR3_LINEN);
00392     }
00393 }
00394 /**
00395   * @brief  Enables or disables the UART2 Smart Card mode.
00396   * @param  NewState: new state of the Smart Card mode.
00397   *         This parameter can be: ENABLE or DISABLE.
00398   * @retval None
00399   */
00400 void UART2_SmartCardCmd(FunctionalState NewState)
00401 {
00402     /* Check parameters */
00403     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00404
00405     if (NewState != DISABLE)
00406     {
00407         /* Enable the SC mode by setting the SCEN bit in the CR5 register */
00408         UART2->CR5 |= UART2_CR5_SCEN;
00409     }
00410     else
00411     {
00412         /* Disable the SC mode by clearing the SCEN bit in the CR5 register */
00413         UART2->CR5 &= ((uint8_t)(~UART2_CR5_SCEN));
00414     }
00415 }
00416
00417 /**
00418   * @brief  Enables or disables NACK transmission.
00419   * @param  NewState: new state of the Smart Card mode.
00420   *         This parameter can be: ENABLE or DISABLE.
00421   * @retval None
00422   */
00423 void UART2_SmartCardNACKCmd(FunctionalState NewState)
00424 {
00425     /* Check parameters */
00426     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00427
00428     if (NewState != DISABLE)
00429     {
00430         /* Enable the NACK transmission by setting the NACK bit in the CR5 register */
00431         UART2->CR5 |= UART2_CR5_NACK;
00432     }
00433     else
00434     {
00435         /* Disable the NACK transmission by clearing the NACK bit in the CR5 register */
00436         UART2->CR5 &= ((uint8_t)~(UART2_CR5_NACK));
00437     }
00438 }
00439
00440 /**
00441   * @brief  Selects the UART2 WakeUp method.
00442   * @param  UART2_WakeUp: specifies the UART2 wakeup method.
00443   *         This parameter can be any of the @ref UART2_WakeUp_TypeDef values.
00444   * @retval None
00445   */
00446 void UART2_WakeUpConfig(UART2_WakeUp_TypeDef UART2_WakeUp)
00447 {
00448     assert_param(IS_UART2_WAKEUP_OK(UART2_WakeUp));
00449
00450     UART2->CR1 &= ((uint8_t)~UART2_CR1_WAKE);
00451     UART2->CR1 |= (uint8_t)UART2_WakeUp;
00452 }
00453
00454 /**
00455   * @brief  Determines if the UART2 is in mute mode or not.
00456   * @param  NewState: new state of the UART2 mode.
00457   *         This parameter can be ENABLE or DISABLE
00458   * @retval None
00459   */
00460 void UART2_ReceiverWakeUpCmd(FunctionalState NewState)
00461 {
00462     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00463
00464     if (NewState != DISABLE)
00465     {
00466         /* Enable the mute mode UART2 by setting the RWU bit in the CR2 register */
00467         UART2->CR2 |= UART2_CR2_RWU;
00468     }
00469     else
00470     {
00471         /* Disable the mute mode UART2 by clearing the RWU bit in the CR1 register */
00472         UART2->CR2 &= ((uint8_t)~UART2_CR2_RWU);
00473     }
00474 }
00475
00476 /**
00477   * @brief  Returns the most recent received data by the UART2 peripheral.
00478   * @param  None
00479   * @retval Received Data
00480   */
00481 uint8_t UART2_ReceiveData8(void)
00482 {
00483     return ((uint8_t)UART2->DR);
00484 }
00485
00486 /**
00487   * @brief  Returns the most recent received data by the UART2 peripheral.
00488   * @param  None
00489   * @retval Received Data
00490   */
00491 uint16_t UART2_ReceiveData9(void)
00492 {
00493   uint16_t temp = 0;
00494
00495   temp = ((uint16_t)(((uint16_t)((uint16_t)UART2->CR1 & (uint16_t)UART2_CR1_R8)) << 1));
00496
00497   return (uint16_t)((((uint16_t)UART2->DR) | temp) & ((uint16_t)0x01FF));
00498 }
00499
00500 /**
00501   * @brief  Transmits 8 bit data through the UART2 peripheral.
00502   * @param  Data: the data to transmit.
00503   * @retval None
00504   */
00505 void UART2_SendData8(uint8_t Data)
00506 {
00507     /* Transmit Data */
00508     UART2->DR = Data;
00509 }
00510
00511 /**
00512   * @brief  Transmits 9 bit data through the UART2 peripheral.
00513   * @param  Data: the data to transmit.
00514   * @retval None
00515   */
00516 void UART2_SendData9(uint16_t Data)
00517 {
00518     /* Clear the transmit data bit 8 */
00519     UART2->CR1 &= ((uint8_t)~UART2_CR1_T8);
00520
00521     /* Write the transmit data bit [8] */
00522     UART2->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART2_CR1_T8);
00523
00524     /* Write the transmit data bit [0:7] */
00525     UART2->DR   = (uint8_t)(Data);
00526
00527 }
00528
00529 /**
00530   * @brief  Transmits break characters.
00531   * @param  None
00532   * @retval None
00533   */
00534 void UART2_SendBreak(void)
00535 {
00536     UART2->CR2 |= UART2_CR2_SBK;
00537 }
00538
00539 /**
00540   * @brief  Sets the address of the UART2 node.
00541   * @param  UART2_Address: Indicates the address of the UART2 node.
00542   * @retval None
00543   */
00544 void UART2_SetAddress(uint8_t UART2_Address)
00545 {
00546     /*assert_param for x UART2_Address*/
00547     assert_param(IS_UART2_ADDRESS_OK(UART2_Address));
00548
00549     /* Clear the UART2 address */
00550     UART2->CR4 &= ((uint8_t)~UART2_CR4_ADD);
00551     /* Set the UART2 address node */
00552     UART2->CR4 |= UART2_Address;
00553 }
00554
00555 /**
00556   * @brief  Sets the specified UART2 guard time.
00557   * @note   SmartCard Mode should be Enabled
00558   * @param  UART2_GuardTime: specifies the guard time.
00559   * @retval None
00560   */
00561 void UART2_SetGuardTime(uint8_t UART2_GuardTime)
00562 {
00563     /* Set the UART2 guard time */
00564     UART2->GTR = UART2_GuardTime;
00565 }
00566
00567 /**
00568   * @brief  Sets the system clock prescaler.
00569   * @note   IrDA Low Power mode or smartcard mode should be enabled
00570   * @note   This function is related to SmartCard and IrDa mode.
00571   * @param  UART2_Prescaler: specifies the prescaler clock.
00572   *         This parameter can be one of the following values:
00573   *         @par IrDA Low Power Mode
00574   *         The clock source is divided by the value given in the register (8 bits)
00575   *         - 0000 0000 Reserved
00576   *         - 0000 0001 divides the clock source by 1
00577   *         - 0000 0010 divides the clock source by 2
00578   *         - ...........................................................
00579   *        @par Smart Card Mode
00580   *        The clock source is divided by the value given in the register
00581   *        (5 significant bits) multiped by 2
00582   *         - 0 0000 Reserved
00583   *         - 0 0001 divides the clock source by 2
00584   *         - 0 0010 divides the clock source by 4
00585   *         - 0 0011 divides the clock source by 6
00586   *         - ...........................................................
00587   * @retval None
00588   */
00589 void UART2_SetPrescaler(uint8_t UART2_Prescaler)
00590 {
00591     /* Load the UART2 prescaler value*/
00592     UART2->PSCR = UART2_Prescaler;
00593 }
00594
00595 /**
00596   * @brief  Checks whether the specified UART2 flag is set or not.
00597   * @param  UART2_FLAG specifies the flag to check.
00598   *         This parameter can be any of the @ref UART2_Flag_TypeDef enumeration.
00599   * @retval FlagStatus (SET or RESET)
00600   */
00601 FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG)
00602 {
00603     FlagStatus status = RESET;
00604
00605     /* Check parameters */
00606     assert_param(IS_UART2_FLAG_OK(UART2_FLAG));
00607
00608     /* Check the status of the specified UART2 flag*/
00609     if (UART2_FLAG == UART2_FLAG_LBDF)
00610     {
00611         if ((UART2->CR4 & (uint8_t)UART2_FLAG) != (uint8_t)0x00)
00612         {
00613             /* UART2_FLAG is set*/
00614             status = SET;
00615         }
00616         else
00617         {
00618             /* UART2_FLAG is reset*/
00619             status = RESET;
00620         }
00621     }
00622     else if (UART2_FLAG == UART2_FLAG_SBK)
00623     {
00624         if ((UART2->CR2 & (uint8_t)UART2_FLAG) != (uint8_t)0x00)
00625         {
00626             /* UART2_FLAG is set*/
00627             status = SET;
00628         }
00629         else
00630         {
00631             /* UART2_FLAG is reset*/
00632             status = RESET;
00633         }
00634     }
00635     else if ((UART2_FLAG == UART2_FLAG_LHDF) || (UART2_FLAG == UART2_FLAG_LSF))
00636     {
00637         if ((UART2->CR6 & (uint8_t)UART2_FLAG) != (uint8_t)0x00)
00638         {
00639             /* UART2_FLAG is set*/
00640             status = SET;
00641         }
00642         else
00643         {
00644             /* UART2_FLAG is reset*/
00645             status = RESET;
00646         }
00647     }
00648     else
00649     {
00650         if ((UART2->SR & (uint8_t)UART2_FLAG) != (uint8_t)0x00)
00651         {
00652             /* UART2_FLAG is set*/
00653             status = SET;
00654         }
00655         else
00656         {
00657             /* UART2_FLAG is reset*/
00658             status = RESET;
00659         }
00660     }
00661
00662     /* Return the UART2_FLAG status*/
00663     return  status;
00664 }
00665 /**
00666   * @brief  Clears the UART2 flags.
00667   * @param  UART2_FLAG specifies the flag to clear
00668   *         This parameter can be any combination of the following values:
00669   *         - UART2_FLAG_LBDF: LIN Break detection flag.
00670   *         - UART2_FLAG_LHDF: LIN Header detection flag.
00671   *         - UART2_FLAG_LSF: LIN synchrone field flag.
00672   *         - UART2_FLAG_RXNE: Receive data register not empty flag.
00673   * @note:
00674   *         - PE (Parity error), FE (Framing error), NE (Noise error),
00675   *           OR (OverRun error) and IDLE (Idle line detected) flags are cleared
00676   *           by software sequence: a read operation to UART2_SR register
00677   *           (UART2_GetFlagStatus())followed by a read operation to UART2_DR
00678   *           register(UART2_ReceiveData8() or UART2_ReceiveData9()).
00679   *
00680   *         - RXNE flag can be also cleared by a read to the UART2_DR register
00681   *           (UART2_ReceiveData8()or UART2_ReceiveData9()).
00682   *
00683   *         - TC flag can be also cleared by software sequence: a read operation
00684   *           to UART2_SR register (UART2_GetFlagStatus()) followed by a write
00685   *           operation to UART2_DR register (UART2_SendData8() or UART2_SendData9()).
00686   *
00687   *         - TXE flag is cleared only by a write to the UART2_DR register
00688   *           (UART2_SendData8() or UART2_SendData9()).
00689   *
00690   *         - SBK flag is cleared during the stop bit of break.
00691   * @retval None
00692   */
00693 void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG)
00694 {
00695     assert_param(IS_UART2_CLEAR_FLAG_OK(UART2_FLAG));
00696
00697     /*  Clear the Receive Register Not Empty flag */
00698     if (UART2_FLAG == UART2_FLAG_RXNE)
00699     {
00700         UART2->SR = (uint8_t)~(UART2_SR_RXNE);
00701     }
00702     /*  Clear the LIN Break Detection flag */
00703     else if (UART2_FLAG == UART2_FLAG_LBDF)
00704     {
00705         UART2->CR4 &= (uint8_t)(~UART2_CR4_LBDF);
00706     }
00707     /*  Clear the LIN Header Detection Flag */
00708     else if (UART2_FLAG == UART2_FLAG_LHDF)
00709     {
00710         UART2->CR6 &= (uint8_t)(~UART2_CR6_LHDF);
00711     }
00712     /*  Clear the LIN Synch Field flag */
00713     else
00714     {
00715         UART2->CR6 &= (uint8_t)(~UART2_CR6_LSF);
00716     }
00717 }
00718
00719 /**
00720   * @brief  Checks whether the specified UART2 interrupt has occurred or not.
00721   * @param  UART2_IT: Specifies the UART2 interrupt pending bit to check.
00722   *         This parameter can be one of the following values:
00723   *         - UART2_IT_LBDF:  LIN Break detection interrupt
00724   *         - UART2_IT_TXE:  Tansmit Data Register empty interrupt
00725   *         - UART2_IT_TC:   Transmission complete interrupt
00726   *         - UART2_IT_RXNE: Receive Data register not empty interrupt
00727   *         - UART2_IT_IDLE: Idle line detection interrupt
00728   *         - UART2_IT_OR:  OverRun Error interrupt
00729   *         - UART2_IT_PE:   Parity Error interrupt
00730   * @retval The state of UART2_IT (SET or RESET).
00731   */
00732 ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT)
00733 {
00734     ITStatus pendingbitstatus = RESET;
00735     uint8_t itpos = 0;
00736     uint8_t itmask1 = 0;
00737     uint8_t itmask2 = 0;
00738     uint8_t enablestatus = 0;
00739
00740     /* Check parameters */
00741     assert_param(IS_UART2_GET_IT_OK(UART2_IT));
00742
00743     /* Get the UART2 IT index*/
00744     itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART2_IT & (uint8_t)0x0F));
00745     /* Get the UART2 IT index*/
00746     itmask1 = (uint8_t)((uint8_t)UART2_IT >> (uint8_t)4);
00747     /* Set the IT mask*/
00748     itmask2 = (uint8_t)((uint8_t)1 << itmask1);
00749
00750     /* Check the status of the specified UART2 pending bit*/
00751     if (UART2_IT == UART2_IT_PE)
00752     {
00753         /* Get the UART2_ITPENDINGBIT enable bit status*/
00754         enablestatus = (uint8_t)((uint8_t)UART2->CR1 & itmask2);
00755         /* Check the status of the specified UART2 interrupt*/
00756
00757         if (((UART2->SR & itpos) != (uint8_t)0x00) && enablestatus)
00758         {
00759             /* Interrupt occurred*/
00760             pendingbitstatus = SET;
00761         }
00762         else
00763         {
00764             /* Interrupt not occurred*/
00765             pendingbitstatus = RESET;
00766         }
00767     }
00768     else if (UART2_IT == UART2_IT_LBDF)
00769     {
00770         /* Get the UART2_IT enable bit status*/
00771         enablestatus = (uint8_t)((uint8_t)UART2->CR4 & itmask2);
00772         /* Check the status of the specified UART2 interrupt*/
00773         if (((UART2->CR4 & itpos) != (uint8_t)0x00) && enablestatus)
00774         {
00775             /* Interrupt occurred*/
00776             pendingbitstatus = SET;
00777         }
00778         else
00779         {
00780             /* Interrupt not occurred*/
00781             pendingbitstatus = RESET;
00782         }
00783     }
00784     else if (UART2_IT == UART2_IT_LHDF)
00785     {
00786         /* Get the UART2_IT enable bit status*/
00787         enablestatus = (uint8_t)((uint8_t)UART2->CR6 & itmask2);
00788         /* Check the status of the specified UART2 interrupt*/
00789         if (((UART2->CR6 & itpos) != (uint8_t)0x00) && enablestatus)
00790         {
00791             /* Interrupt occurred*/
00792             pendingbitstatus = SET;
00793         }
00794         else
00795         {
00796             /* Interrupt not occurred*/
00797             pendingbitstatus = RESET;
00798         }
00799     }
00800     else
00801     {
00802         /* Get the UART2_IT enable bit status*/
00803         enablestatus = (uint8_t)((uint8_t)UART2->CR2 & itmask2);
00804         /* Check the status of the specified UART2 interrupt*/
00805         if (((UART2->SR & itpos) != (uint8_t)0x00) && enablestatus)
00806         {
00807             /* Interrupt occurred*/
00808             pendingbitstatus = SET;
00809         }
00810         else
00811         {
00812             /* Interrupt not occurred*/
00813             pendingbitstatus = RESET;
00814         }
00815     }
00816     /* Return the UART2_IT status*/
00817     return  pendingbitstatus;
00818 }
00819
00820 /**
00821   * @brief  Clears the UART2 pending flags.
00822   * @param  UART2_IT specifies the pending bit to clear
00823   *         This parameter can be one of the following values:
00824   *         - UART2_IT_LBDF:  LIN Break detection interrupt
00825   *         - UART2_IT_LHDF:  LIN Header detection interrupt
00826   *         - UART2_IT_RXNE: Receive Data register not empty interrupt.
00827   * @note
00828   *         - PE (Parity error), FE (Framing error), NE (Noise error),
00829   *           OR (OverRun error) and IDLE (Idle line detected) pending bits are
00830   *           cleared by software sequence: a read operation to UART2_SR register
00831   *           (UART2_GetITStatus()) followed by a read operation to UART2_DR register
00832   *           (UART2_ReceiveData8() or UART2_ReceiveData9()).
00833   *
00834   *         - RXNE pending bit can be also cleared by a read to the UART2_DR
00835   *           register (UART2_ReceiveData8() or UART2_ReceiveData9()).
00836   *
00837   *         - TC (Transmit complete) pending bit can be cleared by software
00838   *           sequence: a read operation to UART2_SR register
00839   *           (UART2_GetITStatus()) followed by a write operation to UART2_DR
00840   *           register (UART2_SendData8()or UART2_SendData9()).
00841   *
00842   *         - TXE pending bit is cleared only by a write to the UART2_DR register
00843   *           (UART2_SendData8() or UART2_SendData9()).
00844   * @retval None
00845   */
00846 void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT)
00847 {
00848     assert_param(IS_UART2_CLEAR_IT_OK(UART2_IT));
00849
00850     /*  Clear the Receive Register Not Empty pending bit */
00851     if (UART2_IT == UART2_IT_RXNE)
00852     {
00853         UART2->SR = (uint8_t)~(UART2_SR_RXNE);
00854     }
00855     /*  Clear the LIN Break Detection pending bit */
00856     else if (UART2_IT == UART2_IT_LBDF)
00857     {
00858         UART2->CR4 &= (uint8_t)~(UART2_CR4_LBDF);
00859     }
00860     /*  Clear the LIN Header Detection pending bit */
00861     else
00862     {
00863         UART2->CR6 &= (uint8_t)(~UART2_CR6_LHDF);
00864     }
00865 }
00866 /**
00867   * @}
00868   */
00869
00870 /**
00871   * @}
00872   */
00873
00874 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart2.h Source File

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stm8s_uart2.h

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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart2.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototypes and macros for the UART2 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_UART2_H
00024 #define __STM8S_UART2_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /* Exported types ------------------------------------------------------------*/
00034
00035 /** @addtogroup UART2_Exported_Types
00036   * @{
00037   */
00038
00039 /**
00040   * @brief  UART2 Irda Modes
00041   */
00042
00043 typedef enum { UART2_IRDAMODE_NORMAL     = (uint8_t)0x00, /**< 0x00 Irda Normal Mode   */
00044                UART2_IRDAMODE_LOWPOWER   = (uint8_t)0x01  /**< 0x01 Irda Low Power Mode */
00045
00046              } UART2_IrDAMode_TypeDef;
00047
00048 /**
00049   * @brief  UART2 WakeUP Modes
00050   */
00051
00052 typedef enum { UART2_WAKEUP_IDLELINE       = (uint8_t)0x00, /**< 0x01 Idle Line wake up */
00053                UART2_WAKEUP_ADDRESSMARK    = (uint8_t)0x08  /**< 0x02 Address Mark wake up */
00054              } UART2_WakeUp_TypeDef;
00055
00056
00057 /**
00058   * @brief  UART2 LIN Break detection length possible values
00059   */
00060 typedef enum { UART2_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, /**< 0x01 10 bits Lin Break detection */
00061                UART2_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01  /**< 0x02 11 bits Lin Break detection */
00062              } UART2_LINBreakDetectionLength_TypeDef;
00063
00064 /**
00065   * @brief  UART2 stop bits possible values
00066   */
00067
00068 typedef enum { UART2_STOPBITS_1   = (uint8_t)0x00,    /**< One stop bit is  transmitted at the end of frame*/
00069                UART2_STOPBITS_0_5 = (uint8_t)0x10,    /**< Half stop bits is transmitted at the end of frame*/
00070                UART2_STOPBITS_2   = (uint8_t)0x20,    /**< Two stop bits are  transmitted at the end of frame*/
00071                UART2_STOPBITS_1_5 = (uint8_t)0x30     /**< One and half stop bits*/
00072              } UART2_StopBits_TypeDef;
00073
00074
00075 /**
00076   * @brief  UART2 parity possible values
00077   */
00078 typedef enum { UART2_PARITY_NO     = (uint8_t)0x00,      /**< No Parity*/
00079                UART2_PARITY_EVEN   = (uint8_t)0x04,      /**< Even Parity*/
00080                UART2_PARITY_ODD    = (uint8_t)0x06       /**< Odd Parity*/
00081              } UART2_Parity_TypeDef;
00082 /**
00083   * @brief  UART2 Mode possible values
00084   */
00085 typedef enum { UART2_LIN_MODE_MASTER  = (uint8_t)0x00, /**<  LIN Master Mode*/
00086                UART2_LIN_MODE_SLAVE   = (uint8_t)0x01  /**<  LIN Slave Mode*/
00087              } UART2_LinMode_TypeDef;
00088 /**
00089   * @brief  UART2 automatic resynchronisation possible values
00090   */
00091 typedef enum { UART2_LIN_AUTOSYNC_DISABLE   = (uint8_t)0x00,  /**< LIN Autosynchronization Disable*/
00092                UART2_LIN_AUTOSYNC_ENABLE    = (uint8_t)0x01   /**< LIN Autosynchronization Enable*/
00093              } UART2_LinAutosync_TypeDef;
00094 /**
00095   * @brief  UART2 Divider Update Method possible values
00096   */
00097 typedef enum { UART2_LIN_DIVUP_LBRR1    = (uint8_t)0x00, /**<  LIN LDIV is updated as soon as LBRR1 is written*/
00098                UART2_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01  /**<  LIN LDIV is updated at the next received character*/
00099              } UART2_LinDivUp_TypeDef;
00100
00101 /**
00102   * @brief  UART2 Synchrone modes
00103   */
00104 typedef enum { UART2_SYNCMODE_CLOCK_DISABLE    = (uint8_t)0x80, /**< 0x80 Sync mode Disable, SLK pin Disable */
00105                UART2_SYNCMODE_CLOCK_ENABLE     = (uint8_t)0x08, /**< 0x08 Sync mode Enable, SLK pin Enable     */
00106                UART2_SYNCMODE_CPOL_LOW         = (uint8_t)0x40, /**< 0x40 Steady low value on SCLK pin outside transmission window */
00107                UART2_SYNCMODE_CPOL_HIGH        = (uint8_t)0x04, /**< 0x04 Steady high value on SCLK pin outside transmission window */
00108                UART2_SYNCMODE_CPHA_MIDDLE      = (uint8_t)0x20, /**< 0x20 SCLK clock line activated in middle of data bit     */
00109                UART2_SYNCMODE_CPHA_BEGINING    = (uint8_t)0x02, /**< 0x02 SCLK clock line activated at beginning of data bit  */
00110                UART2_SYNCMODE_LASTBIT_DISABLE  = (uint8_t)0x10, /**< 0x10 The clock pulse of the last data bit is not output to the SCLK pin */
00111                UART2_SYNCMODE_LASTBIT_ENABLE   = (uint8_t)0x01  /**< 0x01 The clock pulse of the last data bit is output to the SCLK pin */
00112              } UART2_SyncMode_TypeDef;
00113
00114 /**
00115   * @brief  UART2 Word length possible values
00116   */
00117 typedef enum { UART2_WORDLENGTH_8D = (uint8_t)0x00,/**< 0x00 8 bits Data  */
00118                UART2_WORDLENGTH_9D = (uint8_t)0x10 /**< 0x10 9 bits Data  */
00119              } UART2_WordLength_TypeDef;
00120
00121 /**
00122   * @brief  UART2 Mode possible values
00123   */
00124 typedef enum { UART2_MODE_RX_ENABLE     = (uint8_t)0x08,  /**< 0x08 Receive Enable */
00125                UART2_MODE_TX_ENABLE     = (uint8_t)0x04,  /**< 0x04 Transmit Enable */
00126                UART2_MODE_TX_DISABLE    = (uint8_t)0x80,  /**< 0x80 Transmit Disable */
00127                UART2_MODE_RX_DISABLE    = (uint8_t)0x40,  /**< 0x40 Single-wire Half-duplex mode */
00128                UART2_MODE_TXRX_ENABLE   = (uint8_t)0x0C  /**< 0x0C Transmit Enable and Receive Enable */
00129              } UART2_Mode_TypeDef;
00130 /**
00131   * @brief  UART2 Flag possible values
00132   */
00133 typedef enum
00134 {
00135   UART2_FLAG_TXE          = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */
00136   UART2_FLAG_TC           = (uint16_t)0x0040, /*!< Transmission Complete flag */
00137   UART2_FLAG_RXNE         = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */
00138   UART2_FLAG_IDLE         = (uint16_t)0x0010, /*!< Idle line detected flag */
00139   UART2_FLAG_OR_LHE       = (uint16_t)0x0008, /*!< OverRun error flag */
00140   UART2_FLAG_NF           = (uint16_t)0x0004, /*!< Noise error flag */
00141   UART2_FLAG_FE           = (uint16_t)0x0002, /*!< Framing Error flag */
00142   UART2_FLAG_PE           = (uint16_t)0x0001, /*!< Parity Error flag */
00143   UART2_FLAG_SBK          = (uint16_t)0x0101,  /**< Send Break Complete interrupt flag */
00144   UART2_FLAG_LBDF         = (uint16_t)0x0210, /**< LIN Break Detection Flag           */
00145   UART2_FLAG_LHDF         = (uint16_t)0x0302, /**< LIN Header Detection Flag*/
00146   UART2_FLAG_LSF          = (uint16_t)0x0301  /**< LIN Sync Field Flag*/
00147 } UART2_Flag_TypeDef;
00148
00149 /**
00150   * @brief  UART2 Interrupt definition
00151   * UART2_IT possible values
00152   * Elements values convention: 0xZYX
00153   * X: Position of the corresponding Interrupt
00154   *   - For the following values, X means the interrupt position in the CR2 register.
00155   *     UART2_IT_TXE
00156   *     UART2_IT_TC
00157   *     UART2_IT_RXNE
00158   *     UART2_IT_IDLE
00159   *     UART2_IT_OR
00160   *   - For the UART2_IT_PE value, X means the flag position in the CR1 register.
00161   *   - For the UART2_IT_LBDF value, X means the flag position in the CR4 register.
00162   *   - For the UART2_IT_LHDF value, X means the flag position in the CR6 register.
00163   * Y: Flag position
00164   *  - For the following values, Y means the flag (pending bit) position in the SR register.
00165   *     UART2_IT_TXE
00166   *     UART2_IT_TC
00167   *     UART2_IT_RXNE
00168   *     UART2_IT_IDLE
00169   *     UART2_IT_OR
00170   *     UART2_IT_PE
00171   *  - For the UART2_IT_LBDF value, Y means the flag position in the CR4 register.
00172   *  - For the UART2_IT_LHDF value, Y means the flag position in the CR6 register.
00173   * Z: Register index: indicate in which register the dedicated interrupt source is:
00174   *  - 1==> CR1 register
00175   *  - 2==> CR2 register
00176   *  - 3==> CR4 register
00177   *  - 4==> CR6 register
00178   */
00179 typedef enum { UART2_IT_TXE        = (uint16_t)0x0277, /**< Transmit interrupt */
00180                UART2_IT_TC         = (uint16_t)0x0266, /**< Transmission Complete interrupt */
00181                UART2_IT_RXNE       = (uint16_t)0x0255, /**< Data Register Not Empty interrupt */
00182                UART2_IT_IDLE       = (uint16_t)0x0244, /**< Idle line detected interrupt */
00183                UART2_IT_OR         = (uint16_t)0x0235, /**< OverRun error interrupt */
00184                UART2_IT_PE         = (uint16_t)0x0100, /**< Parity Error interrupt */
00185                UART2_IT_LBDF       = (uint16_t)0x0346, /**< LIN Break Detection interrupt */
00186                UART2_IT_LHDF       = (uint16_t)0x0412, /**< LIN Header Detection interrupt*/
00187                UART2_IT_RXNE_OR    = (uint16_t)0x0205  /*!< Receive/Overrun interrupt */
00188              } UART2_IT_TypeDef;
00189
00190 /**
00191   * @}
00192   */
00193
00194 /* Exported constants --------------------------------------------------------*/
00195 /* Exported macros ------------------------------------------------------------*/
00196
00197 /* Private macros ------------------------------------------------------------*/
00198
00199 /** @addtogroup UART2_Private_Macros
00200   * @{
00201   */
00202
00203 /**
00204   * @brief  Macro used by the assert function to check the different functions parameters.
00205   */
00206
00207 /**
00208  * @brief Macro used by the assert_param function in order to check the different
00209  *        sensitivity values for the MODEs possible combination should be one of
00210  *        the following.
00211  */
00212
00213 #define IS_UART2_MODE_OK(Mode) \
00214   (((Mode) == (uint8_t)UART2_MODE_RX_ENABLE) || \
00215    ((Mode) == (uint8_t)UART2_MODE_RX_DISABLE) || \
00216    ((Mode) == (uint8_t)UART2_MODE_TX_ENABLE) || \
00217    ((Mode) == (uint8_t)UART2_MODE_TX_DISABLE) || \
00218    ((Mode) == (uint8_t)UART2_MODE_TXRX_ENABLE) || \
00219    ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_ENABLE|(uint8_t)UART2_MODE_RX_ENABLE)) || \
00220    ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_ENABLE|(uint8_t)UART2_MODE_RX_DISABLE)) || \
00221    ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_DISABLE|(uint8_t)UART2_MODE_RX_DISABLE)) || \
00222    ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_DISABLE|(uint8_t)UART2_MODE_RX_ENABLE)))
00223
00224 /**
00225  * @brief Macro used by the assert_param function in order to check the different
00226  *        sensitivity values for the WordLengths
00227  */
00228 #define IS_UART2_WORDLENGTH_OK(WordLength) \
00229   (((WordLength) == UART2_WORDLENGTH_8D) || \
00230    ((WordLength) == UART2_WORDLENGTH_9D))
00231
00232 /**
00233   * @brief  Macro used by the assert_param function in order to check the different
00234   *         sensitivity values for the SyncModes; it should exclude values such
00235   *         as  UART2_CLOCK_ENABLE|UART2_CLOCK_DISABLE
00236   */
00237 #define IS_UART2_SYNCMODE_OK(SyncMode) \
00238   (!((((SyncMode)&(((uint8_t)UART2_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART2_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART2_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART2_SYNCMODE_CLOCK_DISABLE))) || \
00239      (((SyncMode)&(((uint8_t)UART2_SYNCMODE_CPOL_LOW )|((uint8_t)UART2_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART2_SYNCMODE_CPOL_LOW )|((uint8_t)UART2_SYNCMODE_CPOL_HIGH))) || \
00240      (((SyncMode)&(((uint8_t)UART2_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART2_SYNCMODE_CPHA_BEGINING))) == (((uint8_t)UART2_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART2_SYNCMODE_CPHA_BEGINING))) || \
00241      (((SyncMode)&(((uint8_t)UART2_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART2_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART2_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART2_SYNCMODE_LASTBIT_ENABLE)))))
00242
00243 /**
00244   * @brief  Macro used by the assert_param function in order to check the
00245   *         different sensitivity values for the FLAGs
00246   */
00247 #define IS_UART2_FLAG_OK(Flag) \
00248   (((Flag) == UART2_FLAG_TXE) || \
00249    ((Flag) == UART2_FLAG_TC)  || \
00250    ((Flag) == UART2_FLAG_RXNE) || \
00251    ((Flag) == UART2_FLAG_IDLE) || \
00252    ((Flag) == UART2_FLAG_OR_LHE) || \
00253    ((Flag) == UART2_FLAG_NF) || \
00254    ((Flag) == UART2_FLAG_FE) || \
00255    ((Flag) == UART2_FLAG_PE) || \
00256    ((Flag) == UART2_FLAG_SBK) || \
00257    ((Flag) == UART2_FLAG_LSF) || \
00258    ((Flag) == UART2_FLAG_LHDF) || \
00259    ((Flag) == UART2_FLAG_LBDF))
00260
00261
00262 /**
00263   * @brief  Macro used by the assert_param function in order to check the
00264   *         different sensitivity values for the FLAGs that can be cleared by writing 0
00265   */
00266 #define IS_UART2_CLEAR_FLAG_OK(Flag) \
00267   (((Flag) == UART2_FLAG_RXNE) || \
00268    ((Flag) == UART2_FLAG_LHDF) || \
00269    ((Flag) == UART2_FLAG_LSF) || \
00270    ((Flag) == UART2_FLAG_LBDF))
00271
00272 /**
00273   * @brief  Macro used by the assert_param function in order to check
00274   *         the different sensitivity values for the Interrupts
00275   */
00276
00277 #define IS_UART2_CONFIG_IT_OK(Interrupt) \
00278   (((Interrupt) == UART2_IT_PE) || \
00279    ((Interrupt) == UART2_IT_TXE) || \
00280    ((Interrupt) == UART2_IT_TC) || \
00281    ((Interrupt) == UART2_IT_RXNE_OR ) || \
00282    ((Interrupt) == UART2_IT_IDLE) || \
00283    ((Interrupt) == UART2_IT_LHDF) || \
00284    ((Interrupt) == UART2_IT_LBDF))
00285
00286 /**
00287   * @brief  Macro used by the assert function in order to check the different
00288   *         sensitivity values for the pending bit
00289   */
00290 #define IS_UART2_GET_IT_OK(ITPendingBit) \
00291   (((ITPendingBit) == UART2_IT_TXE)  || \
00292    ((ITPendingBit) == UART2_IT_TC)   || \
00293    ((ITPendingBit) == UART2_IT_RXNE) || \
00294    ((ITPendingBit) == UART2_IT_IDLE) || \
00295    ((ITPendingBit) == UART2_IT_OR)  || \
00296    ((ITPendingBit) == UART2_IT_LBDF)  || \
00297    ((ITPendingBit) == UART2_IT_LHDF)  || \
00298    ((ITPendingBit) == UART2_IT_PE))
00299
00300 /**
00301   * @brief  Macro used by the assert function in order to check the different
00302   *         sensitivity values for the pending bit that can be cleared by writing 0
00303   */
00304 #define IS_UART2_CLEAR_IT_OK(ITPendingBit) \
00305   (((ITPendingBit) == UART2_IT_RXNE) || \
00306    ((ITPendingBit) == UART2_IT_LHDF) || \
00307    ((ITPendingBit) == UART2_IT_LBDF))
00308
00309
00310 /**
00311  * @brief Macro used by the assert_param function in order to check the different
00312  *        sensitivity values for the IrDAModes
00313  */
00314 #define IS_UART2_IRDAMODE_OK(IrDAMode) \
00315   (((IrDAMode) == UART2_IRDAMODE_LOWPOWER) || \
00316    ((IrDAMode) == UART2_IRDAMODE_NORMAL))
00317
00318 /**
00319   * @brief  Macro used by the assert_param function in order to check the different
00320   *         sensitivity values for the WakeUps
00321   */
00322 #define IS_UART2_WAKEUP_OK(WakeUp) \
00323   (((WakeUp) == UART2_WAKEUP_IDLELINE) || \
00324    ((WakeUp) == UART2_WAKEUP_ADDRESSMARK))
00325
00326 /**
00327   * @brief  Macro used by the assert_param function in order to check the different
00328   *         sensitivity values for the LINBreakDetectionLengths
00329   */
00330 #define IS_UART2_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength) \
00331   (((LINBreakDetectionLength) == UART2_LINBREAKDETECTIONLENGTH_10BITS) || \
00332    ((LINBreakDetectionLength) == UART2_LINBREAKDETECTIONLENGTH_11BITS))
00333
00334 /**
00335   * @brief  Macro used by the assert_param function in order to check the different
00336   *         sensitivity values for the UART2_StopBits
00337   */
00338 #define IS_UART2_STOPBITS_OK(StopBit) (((StopBit) == UART2_STOPBITS_1) || \
00339                                        ((StopBit) == UART2_STOPBITS_0_5) || \
00340                                        ((StopBit) == UART2_STOPBITS_2) || \
00341                                        ((StopBit) == UART2_STOPBITS_1_5 ))
00342
00343 /**
00344  * @brief Macro used by the assert_param function in order to check the different
00345  *        sensitivity values for the Paritys
00346  */
00347 #define IS_UART2_PARITY_OK(Parity) (((Parity) == UART2_PARITY_NO) || \
00348                                     ((Parity) == UART2_PARITY_EVEN) || \
00349                                     ((Parity) == UART2_PARITY_ODD ))
00350
00351 /**
00352  * @brief Macro used by the assert_param function in order to check the maximum
00353  *        baudrate value
00354  */
00355 #define IS_UART2_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
00356
00357
00358 /**
00359  * @brief Macro used by the assert_param function in order to check the address
00360  *        of the UART2 or UART node
00361  */
00362 #define UART2_ADDRESS_MAX ((uint8_t)16)
00363 #define IS_UART2_ADDRESS_OK(node) ((node) < UART2_ADDRESS_MAX )
00364
00365 /**
00366  * @brief Macro used by the assert_param function in order to check the LIN mode
00367  */
00368 #define IS_UART2_SLAVE_OK(Mode) \
00369   (((Mode) == UART2_LIN_MODE_MASTER) || \
00370    ((Mode) == UART2_LIN_MODE_SLAVE))
00371
00372 /**
00373  * @brief Macro used by the assert_param function in order to check the LIN
00374  *        automatic resynchronization mode
00375  */
00376 #define IS_UART2_AUTOSYNC_OK(AutosyncMode) \
00377   (((AutosyncMode) ==  UART2_LIN_AUTOSYNC_ENABLE) || \
00378    ((AutosyncMode) == UART2_LIN_AUTOSYNC_DISABLE))
00379
00380 /**
00381  * @brief Macro used by the assert_param function in order to check the LIN divider update method
00382  */
00383 #define IS_UART2_DIVUP_OK(DivupMethode) \
00384   (((DivupMethode) == UART2_LIN_DIVUP_LBRR1) || \
00385    ((DivupMethode) == UART2_LIN_DIVUP_NEXTRXNE))
00386
00387
00388 /**
00389   * @}
00390   */
00391
00392 /* Exported functions ------------------------------------------------------- */
00393
00394 /** @addtogroup UART2_Exported_Functions
00395   * @{
00396   */
00397
00398 void UART2_DeInit(void);
00399 void UART2_Init(uint32_t BaudRate, UART2_WordLength_TypeDef WordLength,
00400                 UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity,
00401                 UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode);
00402 void UART2_Cmd(FunctionalState NewState);
00403 void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState);
00404 void UART2_HalfDuplexCmd(FunctionalState NewState);
00405 void UART2_IrDAConfig(UART2_IrDAMode_TypeDef UART2_IrDAMode);
00406 void UART2_IrDACmd(FunctionalState NewState);
00407 void UART2_LINBreakDetectionConfig(UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength);
00408 void UART2_LINConfig(UART2_LinMode_TypeDef UART2_Mode,
00409                      UART2_LinAutosync_TypeDef UART2_Autosync,
00410                      UART2_LinDivUp_TypeDef UART2_DivUp);
00411 void UART2_LINCmd(FunctionalState NewState);
00412 void UART2_SmartCardCmd(FunctionalState NewState);
00413 void UART2_SmartCardNACKCmd(FunctionalState NewState);
00414 void UART2_WakeUpConfig(UART2_WakeUp_TypeDef UART2_WakeUp);
00415 void UART2_ReceiverWakeUpCmd(FunctionalState NewState);
00416 uint8_t UART2_ReceiveData8(void);
00417 uint16_t UART2_ReceiveData9(void);
00418 void UART2_SendData8(uint8_t Data);
00419 void UART2_SendData9(uint16_t Data);
00420 void UART2_SendBreak(void);
00421 void UART2_SetAddress(uint8_t UART2_Address);
00422 void UART2_SetGuardTime(uint8_t UART2_GuardTime);
00423 void UART2_SetPrescaler(uint8_t UART2_Prescaler);
00424 FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG);
00425 void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG);
00426 ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT);
00427 void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT);
00428
00429
00430 /**
00431   * @}
00432   */
00433
00434 #endif /* __STM8S_UART2_H */
00435
00436 /**
00437   * @}
00438   */
00439
00440 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart3.c Source File

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stm8s_uart3.c

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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart3.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the uart3 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_uart3.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private typedef -----------------------------------------------------------*/
00029 /* Private define ------------------------------------------------------------*/
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033
00034 /* Private functions ---------------------------------------------------------*/
00035 /* Public functions ----------------------------------------------------------*/
00036
00037 /** @}
00038   * @addtogroup UART3_Public_Functions
00039   * @{
00040   */
00041
00042 /**
00043   * @brief  Deinitializes the UART peripheral.
00044   * @param  None
00045   * @retval None
00046   */
00047
00048 void UART3_DeInit(void)
00049 {
00050     /* Clear the Idle Line Detected bit in the status rerister by a read
00051        to the UART3_SR register followed by a Read to the UART3_DR register */
00052     (void) UART3->SR;
00053     (void) UART3->DR;
00054
00055     UART3->BRR2 = UART3_BRR2_RESET_VALUE; /*Set UART3_BRR2 to reset value 0x00 */
00056     UART3->BRR1 = UART3_BRR1_RESET_VALUE; /*Set UART3_BRR1 to reset value 0x00 */
00057
00058     UART3->CR1 = UART3_CR1_RESET_VALUE;  /*Set UART3_CR1 to reset value 0x00  */
00059     UART3->CR2 = UART3_CR2_RESET_VALUE;  /*Set UART3_CR2 to reset value 0x00  */
00060     UART3->CR3 = UART3_CR3_RESET_VALUE;  /*Set UART3_CR3 to reset value 0x00  */
00061     UART3->CR4 = UART3_CR4_RESET_VALUE;  /*Set UART3_CR4 to reset value 0x00  */
00062     UART3->CR6 = UART3_CR6_RESET_VALUE;  /*Set UART3_CR6 to reset value 0x00  */
00063
00064 }
00065
00066 /**
00067   * @brief  Initializes the UART3 according to the specified parameters.
00068   * @param  BaudRate: The baudrate.
00069   * @param  WordLength : This parameter can be any of
00070   *         the @ref UART3_WordLength_TypeDef enumeration.
00071   * @param  StopBits: This parameter can be any of the
00072   *         @ref UART3_StopBits_TypeDef enumeration.
00073   * @param  Parity: This parameter can be any of the
00074   *         @ref UART3_Parity_TypeDef enumeration.
00075   * @param  Mode: This parameter can be any of the @ref UART3_Mode_TypeDef values
00076   * @retval None
00077   */
00078 void UART3_Init(uint32_t BaudRate, UART3_WordLength_TypeDef WordLength,
00079                 UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity,
00080                 UART3_Mode_TypeDef Mode)
00081 {
00082     uint8_t BRR2_1 = 0, BRR2_2 = 0;
00083     uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;
00084
00085         /* Check the parameters */
00086     assert_param(IS_UART3_WORDLENGTH_OK(WordLength));
00087     assert_param(IS_UART3_STOPBITS_OK(StopBits));
00088     assert_param(IS_UART3_PARITY_OK(Parity));
00089     assert_param(IS_UART3_BAUDRATE_OK(BaudRate));
00090     assert_param(IS_UART3_MODE_OK((uint8_t)Mode));
00091
00092     /* Clear the word length bit */
00093     UART3->CR1 &= (uint8_t)(~UART3_CR1_M);
00094     /* Set the word length bit according to UART3_WordLength value */
00095     UART3->CR1 |= (uint8_t)WordLength;
00096
00097     /* Clear the STOP bits */
00098     UART3->CR3 &= (uint8_t)(~UART3_CR3_STOP);
00099     /* Set the STOP bits number according to UART3_StopBits value  */
00100     UART3->CR3 |= (uint8_t)StopBits;
00101
00102     /* Clear the Parity Control bit */
00103     UART3->CR1 &= (uint8_t)(~(UART3_CR1_PCEN | UART3_CR1_PS));
00104     /* Set the Parity Control bit to UART3_Parity value */
00105     UART3->CR1 |= (uint8_t)Parity;
00106
00107     /* Clear the LSB mantissa of UART3DIV  */
00108     UART3->BRR1 &= (uint8_t)(~UART3_BRR1_DIVM);
00109     /* Clear the MSB mantissa of UART3DIV  */
00110     UART3->BRR2 &= (uint8_t)(~UART3_BRR2_DIVM);
00111     /* Clear the Fraction bits of UART3DIV */
00112     UART3->BRR2 &= (uint8_t)(~UART3_BRR2_DIVF);
00113
00114     /* Set the UART3 BaudRates in BRR1 and BRR2 registers according to UART3_BaudRate value */
00115     BaudRate_Mantissa    = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4));
00116     BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4));
00117     /* The fraction and MSB mantissa should be loaded in one step in the BRR2 register */
00118     /* Set the fraction of UART3DIV  */
00119     BRR2_1 = (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
00120                         << 4) / 100) & (uint8_t)0x0F);
00121     BRR2_2 = (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0);
00122
00123     UART3->BRR2 = (uint8_t)(BRR2_1 | BRR2_2);
00124     /* Set the LSB mantissa of UART3DIV  */
00125     UART3->BRR1 = (uint8_t)BaudRate_Mantissa;
00126
00127     if ((uint8_t)(Mode & UART3_MODE_TX_ENABLE))
00128     {
00129         /* Set the Transmitter Enable bit */
00130         UART3->CR2 |= UART3_CR2_TEN;
00131     }
00132     else
00133     {
00134         /* Clear the Transmitter Disable bit */
00135         UART3->CR2 &= (uint8_t)(~UART3_CR2_TEN);
00136     }
00137     if ((uint8_t)(Mode & UART3_MODE_RX_ENABLE))
00138     {
00139         /* Set the Receiver Enable bit */
00140         UART3->CR2 |= UART3_CR2_REN;
00141     }
00142     else
00143     {
00144         /* Clear the Receiver Disable bit */
00145         UART3->CR2 &= (uint8_t)(~UART3_CR2_REN);
00146     }
00147 }
00148
00149 /**
00150   * @brief  Enable the UART1 peripheral.
00151   * @param  NewState : The new state of the UART Communication.
00152   *         This parameter can be any of the @ref FunctionalState enumeration.
00153   * @retval None
00154   */
00155 void UART3_Cmd(FunctionalState NewState)
00156 {
00157
00158     if (NewState != DISABLE)
00159     {
00160         /* UART3 Enable */
00161         UART3->CR1 &= (uint8_t)(~UART3_CR1_UARTD);
00162     }
00163     else
00164     {
00165         /* UART3 Disable */
00166         UART3->CR1 |= UART3_CR1_UARTD;
00167     }
00168 }
00169
00170 /**
00171   * @brief  Enables or disables the specified UART3 interrupts.
00172   * @param  UART3_IT specifies the UART3 interrupt sources to be enabled or disabled.
00173   *         This parameter can be one of the following values:
00174   *         - UART3_IT_LBDF:  LIN Break detection interrupt
00175   *         - UART3_IT_LHDF:  LIN Break detection interrupt
00176   *         - UART3_IT_TXE:  Tansmit Data Register empty interrupt
00177   *         - UART3_IT_TC:   Transmission complete interrupt
00178   *         - UART3_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt
00179   *         - UART3_IT_IDLE: Idle line detection interrupt
00180   *         - UART3_IT_PE:   Parity Error interrupt
00181   * @param  NewState new state of the specified UART3 interrupts.
00182   *         This parameter can be: ENABLE or DISABLE.
00183   * @retval None
00184   */
00185 void UART3_ITConfig(UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
00186 {
00187     uint8_t uartreg = 0, itpos = 0x00;
00188
00189     /* Check the parameters */
00190     assert_param(IS_UART3_CONFIG_IT_OK(UART3_IT));
00191     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00192
00193     /* Get the UART3 register index */
00194     uartreg = (uint8_t)((uint16_t)UART3_IT >> 0x08);
00195
00196     /* Get the UART3 IT index */
00197     itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART3_IT & (uint8_t)0x0F));
00198
00199     if (NewState != DISABLE)
00200     {
00201         /* Enable the Interrupt bits according to UART3_IT mask */
00202         if (uartreg == 0x01)
00203         {
00204             UART3->CR1 |= itpos;
00205         }
00206         else if (uartreg == 0x02)
00207         {
00208             UART3->CR2 |= itpos;
00209         }
00210         else if (uartreg == 0x03)
00211         {
00212             UART3->CR4 |= itpos;
00213         }
00214         else
00215         {
00216             UART3->CR6 |= itpos;
00217         }
00218     }
00219     else
00220     {
00221         /* Disable the interrupt bits according to UART3_IT mask */
00222         if (uartreg == 0x01)
00223         {
00224             UART3->CR1 &= (uint8_t)(~itpos);
00225         }
00226         else if (uartreg == 0x02)
00227         {
00228             UART3->CR2 &= (uint8_t)(~itpos);
00229         }
00230         else if (uartreg == 0x03)
00231         {
00232             UART3->CR4 &= (uint8_t)(~itpos);
00233         }
00234         else
00235         {
00236             UART3->CR6 &= (uint8_t)(~itpos);
00237         }
00238     }
00239 }
00240
00241 /**
00242   * @brief  Sets the UART3 LIN Break detection length.
00243   * @param  UART3_LINBreakDetectionLength specifies the LIN break detection length.
00244   *         This parameter can be any of the
00245   *         @ref UART3_LINBreakDetectionLength_TypeDef values.
00246   * @retval None
00247   */
00248 void UART3_LINBreakDetectionConfig(UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)
00249 {
00250     /* Check the parameters */
00251     assert_param(IS_UART3_LINBREAKDETECTIONLENGTH_OK(UART3_LINBreakDetectionLength));
00252
00253     if (UART3_LINBreakDetectionLength != UART3_LINBREAKDETECTIONLENGTH_10BITS)
00254     {
00255         UART3->CR4 |= UART3_CR4_LBDL;
00256     }
00257     else
00258     {
00259         UART3->CR4 &= ((uint8_t)~UART3_CR4_LBDL);
00260     }
00261 }
00262
00263 /**
00264   * @brief  Configure the UART3 peripheral.
00265   * @param  UART3_Mode specifies the LIN mode.
00266   *         This parameter can be any of the @ref UART3_LinMode_TypeDef values.
00267   * @param  UART3_Autosync specifies the LIN automatic resynchronization mode.
00268   *         This parameter can be any of the @ref UART3_LinAutosync_TypeDef values.
00269   * @param  UART3_DivUp specifies the LIN divider update method.
00270   *         This parameter can be any of the @ref UART3_LinDivUp_TypeDef values.
00271   * @retval None
00272   */
00273 void UART3_LINConfig(UART3_LinMode_TypeDef UART3_Mode,
00274                      UART3_LinAutosync_TypeDef UART3_Autosync,
00275                      UART3_LinDivUp_TypeDef UART3_DivUp)
00276 {
00277     /* Check the parameters */
00278     assert_param(IS_UART3_SLAVE_OK(UART3_Mode));
00279     assert_param(IS_UART3_AUTOSYNC_OK(UART3_Autosync));
00280     assert_param(IS_UART3_DIVUP_OK(UART3_DivUp));
00281
00282     if (UART3_Mode != UART3_LIN_MODE_MASTER)
00283     {
00284         UART3->CR6 |=  UART3_CR6_LSLV;
00285     }
00286     else
00287     {
00288         UART3->CR6 &= ((uint8_t)~UART3_CR6_LSLV);
00289     }
00290
00291     if (UART3_Autosync != UART3_LIN_AUTOSYNC_DISABLE)
00292     {
00293         UART3->CR6 |=  UART3_CR6_LASE ;
00294     }
00295     else
00296     {
00297         UART3->CR6 &= ((uint8_t)~ UART3_CR6_LASE );
00298     }
00299
00300     if (UART3_DivUp != UART3_LIN_DIVUP_LBRR1)
00301     {
00302         UART3->CR6 |=  UART3_CR6_LDUM;
00303     }
00304     else
00305     {
00306         UART3->CR6 &= ((uint8_t)~ UART3_CR6_LDUM);
00307     }
00308 }
00309
00310 /**
00311   * @brief  Enables or disables the UART3 LIN mode.
00312   * @param  NewState is new state of the UART3 LIN mode.
00313   *         This parameter can be ENABLE or DISABLE
00314   * @retval None
00315   */
00316 void UART3_LINCmd(FunctionalState NewState)
00317 {
00318     /* Check the parameters */
00319     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00320
00321     if (NewState != DISABLE)
00322     {
00323         /* Enable the LIN mode by setting the LINE bit in the CR2 register */
00324         UART3->CR3 |= UART3_CR3_LINEN;
00325     }
00326     else
00327     {
00328         /* Disable the LIN mode by clearing the LINE bit in the CR2 register */
00329         UART3->CR3 &= ((uint8_t)~UART3_CR3_LINEN);
00330     }
00331 }
00332
00333 /**
00334   * @brief  Selects the UART3 WakeUp method.
00335   * @param  UART3_WakeUp: specifies the UART3 wakeup method.
00336   *         This parameter can be any of the @ref UART3_WakeUp_TypeDef values.
00337   * @retval None
00338   */
00339 void UART3_WakeUpConfig(UART3_WakeUp_TypeDef UART3_WakeUp)
00340 {
00341     /* Check the parameters */
00342     assert_param(IS_UART3_WAKEUP_OK(UART3_WakeUp));
00343
00344     UART3->CR1 &= ((uint8_t)~UART3_CR1_WAKE);
00345     UART3->CR1 |= (uint8_t)UART3_WakeUp;
00346 }
00347
00348 /**
00349   * @brief  Determines if the UART3 is in mute mode or not.
00350   * @param  NewState: new state of the UART3 mode.
00351   *         This parameter can be ENABLE or DISABLE
00352   * @retval None
00353   */
00354 void UART3_ReceiverWakeUpCmd(FunctionalState NewState)
00355 {
00356     /* Check the parameters */
00357     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00358
00359     if (NewState != DISABLE)
00360     {
00361         /* Enable the mute mode UART3 by setting the RWU bit in the CR2 register */
00362         UART3->CR2 |= UART3_CR2_RWU;
00363     }
00364     else
00365     {
00366         /* Disable the mute mode UART3 by clearing the RWU bit in the CR1 register */
00367         UART3->CR2 &= ((uint8_t)~UART3_CR2_RWU);
00368     }
00369 }
00370
00371 /**
00372   * @brief  Returns the most recent received data by the UART3 peripheral.
00373   * @param  None
00374   * @retval Received Data
00375   */
00376 uint8_t UART3_ReceiveData8(void)
00377 {
00378     return ((uint8_t)UART3->DR);
00379 }
00380
00381 /**
00382   * @brief  Returns the most recent received data by the UART3 peripheral.
00383   * @param  None
00384   * @retval Received Data
00385   */
00386 uint16_t UART3_ReceiveData9(void)
00387 {
00388   uint16_t temp = 0;
00389
00390  temp = (uint16_t)(((uint16_t)((uint16_t)UART3->CR1 & (uint16_t)UART3_CR1_R8)) << 1);
00391   return (uint16_t)((((uint16_t)UART3->DR) | temp) & ((uint16_t)0x01FF));
00392 }
00393
00394 /**
00395   * @brief  Transmits 8 bit data through the UART3 peripheral.
00396   * @param  Data the data to transmit.
00397   * @retval None
00398   */
00399 void UART3_SendData8(uint8_t Data)
00400 {
00401     /* Transmit Data */
00402     UART3->DR = Data;
00403 }
00404
00405 /**
00406   * @brief  Transmits 9 bit data through the UART3 peripheral.
00407   * @param   Data: the data to transmit.
00408   * @retval None
00409   */
00410 void UART3_SendData9(uint16_t Data)
00411 {
00412     /* Clear the transmit data bit 8 */
00413     UART3->CR1 &= ((uint8_t)~UART3_CR1_T8);
00414
00415     /* Write the transmit data bit [8] */
00416     UART3->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART3_CR1_T8);
00417
00418     /* Write the transmit data bit [0:7] */
00419     UART3->DR   = (uint8_t)(Data);
00420 }
00421
00422 /**
00423   * @brief  Transmits break characters.
00424   * @param  None
00425   * @retval None
00426   */
00427 void UART3_SendBreak(void)
00428 {
00429     UART3->CR2 |= UART3_CR2_SBK;
00430 }
00431
00432 /**
00433   * @brief  Sets the address of the UART3 node.
00434   * @param  UART3_Address: Indicates the address of the UART3 node.
00435   * @retval None
00436   */
00437 void UART3_SetAddress(uint8_t UART3_Address)
00438 {
00439     /* Check the parameters */
00440     assert_param(IS_UART3_ADDRESS_OK(UART3_Address));
00441
00442     /* Clear the UART3 address */
00443     UART3->CR4 &= ((uint8_t)~UART3_CR4_ADD);
00444     /* Set the UART3 address node */
00445     UART3->CR4 |= UART3_Address;
00446 }
00447
00448 /**
00449   * @brief  Checks whether the specified UART3 flag is set or not.
00450   * @param  UART3_FLAG specifies the flag to check.
00451   *         This parameter can be any of the @ref UART3_Flag_TypeDef enumeration.
00452   * @retval FlagStatus (SET or RESET)
00453   */
00454 FlagStatus UART3_GetFlagStatus(UART3_Flag_TypeDef UART3_FLAG)
00455 {
00456     FlagStatus status = RESET;
00457
00458     /* Check parameters */
00459     assert_param(IS_UART3_FLAG_OK(UART3_FLAG));
00460
00461     /* Check the status of the specified UART3 flag*/
00462     if (UART3_FLAG == UART3_FLAG_LBDF)
00463     {
00464         if ((UART3->CR4 & (uint8_t)UART3_FLAG) != (uint8_t)0x00)
00465         {
00466             /* UART3_FLAG is set*/
00467             status = SET;
00468         }
00469         else
00470         {
00471             /* UART3_FLAG is reset*/
00472             status = RESET;
00473         }
00474     }
00475     else if (UART3_FLAG == UART3_FLAG_SBK)
00476     {
00477         if ((UART3->CR2 & (uint8_t)UART3_FLAG) != (uint8_t)0x00)
00478         {
00479             /* UART3_FLAG is set*/
00480             status = SET;
00481         }
00482         else
00483         {
00484             /* UART3_FLAG is reset*/
00485             status = RESET;
00486         }
00487     }
00488     else if ((UART3_FLAG == UART3_FLAG_LHDF) || (UART3_FLAG == UART3_FLAG_LSF))
00489     {
00490         if ((UART3->CR6 & (uint8_t)UART3_FLAG) != (uint8_t)0x00)
00491         {
00492             /* UART3_FLAG is set*/
00493             status = SET;
00494         }
00495         else
00496         {
00497             /* UART3_FLAG is reset*/
00498             status = RESET;
00499         }
00500     }
00501     else
00502     {
00503         if ((UART3->SR & (uint8_t)UART3_FLAG) != (uint8_t)0x00)
00504         {
00505             /* UART3_FLAG is set*/
00506             status = SET;
00507         }
00508         else
00509         {
00510             /* UART3_FLAG is reset*/
00511             status = RESET;
00512         }
00513     }
00514
00515     /* Return the UART3_FLAG status*/
00516     return  status;
00517 }
00518 /**
00519   * @brief  Clears the UART3 flags.
00520   * @param  UART3_FLAG specifies the flag to clear
00521   *         This parameter can be any combination of the following values:
00522   *         - UART3_FLAG_LBDF: LIN Break detection flag.
00523   *         - UART3_FLAG_LHDF: LIN Header detection flag.
00524   *         - UART3_FLAG_LSF: LIN synchrone field flag.
00525   *         - UART3_FLAG_RXNE: Receive data register not empty flag.
00526   * @note
00527   *         - PE (Parity error), FE (Framing error), NF (Noise error),
00528   *           OR (OverRun error) and IDLE (Idle line detected) flags are cleared
00529   *           by software sequence: a read operation to UART3_SR register
00530   *           (UART3_GetFlagStatus())followed by a read operation to UART3_DR
00531   *           register(UART3_ReceiveData8() or UART3_ReceiveData9()).
00532   *
00533   *         - RXNE flag can be also cleared by a read to the UART3_DR register
00534   *           (UART3_ReceiveData8()or UART3_ReceiveData9()).
00535   *
00536   *         - TC flag can be also cleared by software sequence: a read operation
00537   *           to UART3_SR register (UART3_GetFlagStatus()) followed by a write
00538   *           operation to UART3_DR register (UART3_SendData8() or UART3_SendData9()).
00539   *
00540   *         - TXE flag is cleared only by a write to the UART3_DR register
00541   *           (UART3_SendData8() or UART3_SendData9()).
00542   *
00543   *         - SBK flag is cleared during the stop bit of break.
00544   * @retval None
00545   */
00546 void UART3_ClearFlag(UART3_Flag_TypeDef UART3_FLAG)
00547 {
00548     /* Check the parameters */
00549     assert_param(IS_UART3_CLEAR_FLAG_OK(UART3_FLAG));
00550
00551     /*Clear the Receive Register Not Empty flag */
00552     if (UART3_FLAG == UART3_FLAG_RXNE)
00553     {
00554         UART3->SR = (uint8_t)~(UART3_SR_RXNE);
00555     }
00556     /*Clear the LIN Break Detection flag */
00557     else if (UART3_FLAG == UART3_FLAG_LBDF)
00558     {
00559         UART3->CR4 &= (uint8_t)(~UART3_CR4_LBDF);
00560     }
00561     /*Clear the LIN Header Detection Flag */
00562     else if (UART3_FLAG == UART3_FLAG_LHDF)
00563     {
00564         UART3->CR6 &= (uint8_t)(~UART3_CR6_LHDF);
00565     }
00566     /*Clear the LIN Synch Field flag */
00567     else
00568     {
00569         UART3->CR6 &= (uint8_t)(~UART3_CR6_LSF);
00570     }
00571 }
00572
00573 /**
00574   * @brief  Checks whether the specified UART3 interrupt has occurred or not.
00575   * @param  UART3_IT: Specifies the UART3 interrupt pending bit to check.
00576   *         This parameter can be one of the following values:
00577   *         - UART3_IT_LBDF:  LIN Break detection interrupt
00578   *         - UART3_IT_TXE:  Tansmit Data Register empty interrupt
00579   *         - UART3_IT_TC:   Transmission complete interrupt
00580   *         - UART3_IT_RXNE: Receive Data register not empty interrupt
00581   *         - UART3_IT_IDLE: Idle line detection interrupt
00582   *         - UART3_IT_OR:  OverRun Error interrupt
00583   *         - UART3_IT_PE:   Parity Error interrupt
00584   * @retval The state of UART3_IT (SET or RESET).
00585   */
00586 ITStatus UART3_GetITStatus(UART3_IT_TypeDef UART3_IT)
00587 {
00588     ITStatus pendingbitstatus = RESET;
00589     uint8_t itpos = 0;
00590     uint8_t itmask1 = 0;
00591     uint8_t itmask2 = 0;
00592     uint8_t enablestatus = 0;
00593
00594     /* Check parameters */
00595     assert_param(IS_UART3_GET_IT_OK(UART3_IT));
00596
00597     /* Get the UART3 IT index*/
00598     itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART3_IT & (uint8_t)0x0F));
00599     /* Get the UART3 IT index*/
00600     itmask1 = (uint8_t)((uint8_t)UART3_IT >> (uint8_t)4);
00601     /* Set the IT mask*/
00602     itmask2 = (uint8_t)((uint8_t)1 << itmask1);
00603
00604     /* Check the status of the specified UART3 pending bit*/
00605     if (UART3_IT == UART3_IT_PE)
00606     {
00607         /* Get the UART3_ITPENDINGBIT enable bit status*/
00608         enablestatus = (uint8_t)((uint8_t)UART3->CR1 & itmask2);
00609         /* Check the status of the specified UART3 interrupt*/
00610
00611         if (((UART3->SR & itpos) != (uint8_t)0x00) && enablestatus)
00612         {
00613             /* Interrupt occurred*/
00614             pendingbitstatus = SET;
00615         }
00616         else
00617         {
00618             /* Interrupt not occurred*/
00619             pendingbitstatus = RESET;
00620         }
00621     }
00622     else if (UART3_IT == UART3_IT_LBDF)
00623     {
00624         /* Get the UART3_IT enable bit status*/
00625         enablestatus = (uint8_t)((uint8_t)UART3->CR4 & itmask2);
00626         /* Check the status of the specified UART3 interrupt*/
00627         if (((UART3->CR4 & itpos) != (uint8_t)0x00) && enablestatus)
00628         {
00629             /* Interrupt occurred*/
00630             pendingbitstatus = SET;
00631         }
00632         else
00633         {
00634             /* Interrupt not occurred*/
00635             pendingbitstatus = RESET;
00636         }
00637     }
00638     else if (UART3_IT == UART3_IT_LHDF)
00639     {
00640         /* Get the UART3_IT enable bit status*/
00641         enablestatus = (uint8_t)((uint8_t)UART3->CR6 & itmask2);
00642         /* Check the status of the specified UART3 interrupt*/
00643         if (((UART3->CR6 & itpos) != (uint8_t)0x00) && enablestatus)
00644         {
00645             /* Interrupt occurred*/
00646             pendingbitstatus = SET;
00647         }
00648         else
00649         {
00650             /* Interrupt not occurred*/
00651             pendingbitstatus = RESET;
00652         }
00653     }
00654     else
00655     {
00656         /* Get the UART3_IT enable bit status*/
00657         enablestatus = (uint8_t)((uint8_t)UART3->CR2 & itmask2);
00658         /* Check the status of the specified UART3 interrupt*/
00659         if (((UART3->SR & itpos) != (uint8_t)0x00) && enablestatus)
00660         {
00661             /* Interrupt occurred*/
00662             pendingbitstatus = SET;
00663         }
00664         else
00665         {
00666             /* Interrupt not occurred*/
00667             pendingbitstatus = RESET;
00668         }
00669     }
00670     /* Return the UART3_IT status*/
00671     return  pendingbitstatus;
00672 }
00673
00674 /**
00675   * @brief  Clears the UART3 pending flags.
00676   * @param  UART3_IT specifies the pending bit to clear
00677   *         This parameter can be one of the following values:
00678   *         - UART3_IT_LBDF:  LIN Break detection interrupt
00679   *         - UART3_IT_LHDF:  LIN Header detection interrupt
00680   *         - UART3_IT_RXNE: Receive Data register not empty interrupt.
00681   *
00682   * @note
00683   *         - PE (Parity error), FE (Framing error), NF (Noise error),
00684   *           OR (OverRun error) and IDLE (Idle line detected) pending bits are
00685   *           cleared by software sequence: a read operation to UART3_SR register
00686   *           (UART3_GetITStatus()) followed by a read operation to UART3_DR register
00687   *           (UART3_ReceiveData8() or UART3_ReceiveData9()).
00688   *
00689   *         - RXNE pending bit can be also cleared by a read to the UART3_DR register
00690   *           (UART3_ReceiveData8() or UART3_ReceiveData9() ).
00691   *
00692   *         - TC (Transmit complete) pending bit can be cleared by software
00693   *           sequence: a read operation to UART3_SR register (UART3_GetITStatus())
00694   *           followed by a write operation to UART3_DR register
00695   *           (UART3_SendData8()or UART3_SendData9()).
00696   *
00697   *         - TXE pending bit is cleared only by a write to the UART3_DR register
00698   *           (UART3_SendData8() or UART3_SendData9()).
00699   * @retval None
00700   */
00701 void UART3_ClearITPendingBit(UART3_IT_TypeDef UART3_IT)
00702 {
00703     /* Check the parameters */
00704     assert_param(IS_UART3_CLEAR_IT_OK(UART3_IT));
00705
00706     /*Clear the Receive Register Not Empty pending bit */
00707     if (UART3_IT == UART3_IT_RXNE)
00708     {
00709         UART3->SR = (uint8_t)~(UART3_SR_RXNE);
00710     }
00711     /*Clear the LIN Break Detection pending bit */
00712     else if (UART3_IT == UART3_IT_LBDF)
00713     {
00714         UART3->CR4 &= (uint8_t)~(UART3_CR4_LBDF);
00715     }
00716     /*Clear the LIN Header Detection pending bit */
00717     else
00718     {
00719         UART3->CR6 &= (uint8_t)(~UART3_CR6_LHDF);
00720     }
00721 }
00722 /**
00723   * @}
00724   */
00725
00726 /**
00727   * @}
00728   */
00729
00730 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_uart3.h Source File

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  • STM8S_StdPeriph_Driver
  • inc

stm8s_uart3.h

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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_uart3.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototypes and macros for the UART3 peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_UART3_H
00024 #define __STM8S_UART3_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /* Exported types ------------------------------------------------------------*/
00034
00035 /** @addtogroup UART3_Exported_Types
00036   * @{
00037   */
00038
00039 /**
00040   * @brief  UART3 WakeUP Modes
00041   */
00042 typedef enum { UART3_WAKEUP_IDLELINE      = (uint8_t)0x00,  /**< 0x01 Idle Line wake up*/
00043                UART3_WAKEUP_ADDRESSMARK   = (uint8_t)0x08   /**< 0x02 Address Mark wake up*/
00044              } UART3_WakeUp_TypeDef;
00045
00046 /**
00047   * @brief  UART3 LIN Break detection length possible values
00048   */
00049 typedef enum { UART3_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, /**< 10 bits Lin Break detection */
00050                UART3_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01  /**< 11 bits Lin Break detection */
00051              } UART3_LINBreakDetectionLength_TypeDef;
00052
00053
00054 /**
00055   * @brief  UART3 stop bits possible values
00056   */
00057 typedef enum { UART3_STOPBITS_1  = (uint8_t)0x00,  /**< One stop bit is  transmitted at the end of frame*/
00058                UART3_STOPBITS_2  = (uint8_t)0x20   /**< Two stop bits are  transmitted at the end of frame*/
00059              } UART3_StopBits_TypeDef;
00060
00061 /**
00062   * @brief  UART3 parity possible values
00063   */
00064 typedef enum { UART3_PARITY_NO    = (uint8_t)0x00,    /**< No Parity*/
00065                UART3_PARITY_EVEN  = (uint8_t)0x04,    /**< Even Parity*/
00066                UART3_PARITY_ODD   = (uint8_t)0x06     /**< Odd Parity*/
00067              } UART3_Parity_TypeDef;
00068
00069 /**
00070   * @brief  UART3 Word length possible values
00071   */
00072 typedef enum { UART3_WORDLENGTH_8D = (uint8_t)0x00,    /**< 0x00 8 bits Data*/
00073                UART3_WORDLENGTH_9D = (uint8_t)0x10     /**< 0x10 9 bits Data*/
00074              } UART3_WordLength_TypeDef;
00075
00076 /**
00077   * @brief  UART3 Mode Transmit/Receive possible values
00078   */
00079 typedef enum { UART3_MODE_RX_ENABLE    = (uint8_t)0x08,  /**< 0x08 Receive Enable*/
00080                UART3_MODE_TX_ENABLE    = (uint8_t)0x04,  /**< 0x04 Transmit Enable*/
00081                UART3_MODE_TX_DISABLE   = (uint8_t)0x80,  /**< 0x80 Receive Enable*/
00082                UART3_MODE_RX_DISABLE   = (uint8_t)0x40,  /**< 0x40 Single-wire Half-duplex mode*/
00083                UART3_MODE_TXRX_ENABLE  = (uint8_t)0x0C   /**< 0x0C Receive Enable and Transmit enable*/
00084              } UART3_Mode_TypeDef;
00085
00086 /**
00087   * @brief  UART3 Mode possible values
00088   */
00089 typedef enum { UART3_LIN_MODE_MASTER  = (uint8_t)0x00, /**<  LIN Master Mode*/
00090                UART3_LIN_MODE_SLAVE   = (uint8_t)0x01  /**<  LIN Slave Mode*/
00091              } UART3_LinMode_TypeDef;
00092 /**
00093   * @brief  UART3 automatic resynchronisation possible values
00094   */
00095 typedef enum { UART3_LIN_AUTOSYNC_DISABLE   = (uint8_t)0x00,  /**< LIN Autosynchronization Disable*/
00096                UART3_LIN_AUTOSYNC_ENABLE    = (uint8_t)0x01   /**< LIN Autosynchronization Enable*/
00097              } UART3_LinAutosync_TypeDef;
00098 /**
00099   * @brief  UART3 Divider Update Method possible values
00100   */
00101 typedef enum { UART3_LIN_DIVUP_LBRR1    = (uint8_t)0x00, /**<  LIN LDIV is updated as soon as LBRR1 is written*/
00102                UART3_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01  /**<  LIN LDIV is updated at the next received character*/
00103              } UART3_LinDivUp_TypeDef;
00104
00105
00106 /**
00107   * @brief  UART3 Flag possible values
00108   */
00109 typedef enum
00110 {
00111   UART3_FLAG_TXE         = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */
00112   UART3_FLAG_TC          = (uint16_t)0x0040, /*!< Transmission Complete flag */
00113   UART3_FLAG_RXNE        = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */
00114   UART3_FLAG_IDLE        = (uint16_t)0x0010, /*!< Idle line detected flag */
00115   UART3_FLAG_OR_LHE      = (uint16_t)0x0008, /*!< OverRun error flag */
00116   UART3_FLAG_NF          = (uint16_t)0x0004, /*!< Noise error flag */
00117   UART3_FLAG_FE          = (uint16_t)0x0002, /*!< Framing Error flag */
00118   UART3_FLAG_PE          = (uint16_t)0x0001, /*!< Parity Error flag */
00119   UART3_FLAG_SBK         = (uint16_t)0x0101,  /**< Send Break Complete interrupt flag */
00120   UART3_FLAG_LBDF        = (uint16_t)0x0210, /**< LIN Break Detection Flag           */
00121   UART3_FLAG_LHDF        = (uint16_t)0x0302, /**< LIN Header Detection Flag*/
00122   UART3_FLAG_LSF         = (uint16_t)0x0301  /**< LIN Sync Field Flag*/
00123 } UART3_Flag_TypeDef;
00124
00125 /**
00126   * @brief  UART3 Interrupt definition
00127   * UART3_IT possible values
00128   * Elements values convention: 0xZYX
00129   * X: Position of the corresponding Interrupt
00130   *   - For the following values, X means the interrupt position in the CR2 register.
00131   *     UART3_IT_TXE
00132   *     UART3_IT_TC
00133   *     UART3_IT_RXNE
00134   *     UART3_IT_IDLE
00135   *     UART3_IT_OR
00136   *   - For the UART3_IT_PE value, X means the flag position in the CR1 register.
00137   *   - For the UART3_IT_LBDF value, X means the flag position in the CR4 register.
00138   *   - For the UART3_IT_LHDF value, X means the flag position in the CR6 register.
00139   * Y: Flag position
00140   *  - For the following values, Y means the flag (pending bit) position in the SR register.
00141   *     UART3_IT_TXE
00142   *     UART3_IT_TC
00143   *     UART3_IT_RXNE
00144   *     UART3_IT_IDLE
00145   *     UART3_IT_OR
00146   *     UART3_IT_PE
00147   *  - For the UART3_IT_LBDF value, Y means the flag position in the CR4 register.
00148   *  - For the UART3_IT_LHDF value, Y means the flag position in the CR6 register.
00149   * Z: Register index: indicate in which register the dedicated interrupt source is:
00150   *  - 1==> CR1 register
00151   *  - 2==> CR2 register
00152   *  - 3==> CR4 register
00153   *  - 4==> CR6 register
00154   */
00155 typedef enum { UART3_IT_TXE        = (uint16_t)0x0277, /**< Transmit interrupt */
00156                UART3_IT_TC         = (uint16_t)0x0266, /**< Transmission Complete interrupt */
00157                UART3_IT_RXNE       = (uint16_t)0x0255, /**< Data Register Not Empty interrupt */
00158                UART3_IT_IDLE       = (uint16_t)0x0244, /**< Idle line detected interrupt */
00159                UART3_IT_OR         = (uint16_t)0x0235, /**< OverRun error interrupt */
00160                UART3_IT_PE         = (uint16_t)0x0100, /**< Parity Error interrupt */
00161                UART3_IT_LBDF       = (uint16_t)0x0346, /**< LIN Break Detection interrupt */
00162                UART3_IT_LHDF       = (uint16_t)0x0412, /**< LIN Header Detection interrupt*/
00163                UART3_IT_RXNE_OR    = (uint16_t)0x0205  /*!< Receive/Overrun interrupt */
00164              } UART3_IT_TypeDef;
00165
00166
00167 /**
00168   * @}
00169   */
00170
00171 /* Exported constants --------------------------------------------------------*/
00172 /* Exported macros ------------------------------------------------------------*/
00173
00174 /* Private macros ------------------------------------------------------------*/
00175
00176 /** @addtogroup UART3_Private_Macros
00177   * @{
00178   */
00179
00180 /**
00181   * @brief  Macro used by the assert_param function in order to check the
00182   *         different sensitivity values for the FLAGs
00183   */
00184 #define IS_UART3_FLAG_OK(Flag) \
00185   (((Flag) == UART3_FLAG_TXE) || \
00186    ((Flag) == UART3_FLAG_TC)  || \
00187    ((Flag) == UART3_FLAG_RXNE) || \
00188    ((Flag) == UART3_FLAG_IDLE) || \
00189    ((Flag) == UART3_FLAG_OR_LHE) || \
00190    ((Flag) == UART3_FLAG_NF) || \
00191    ((Flag) == UART3_FLAG_FE) || \
00192    ((Flag) == UART3_FLAG_PE) || \
00193    ((Flag) == UART3_FLAG_SBK) || \
00194    ((Flag) == UART3_FLAG_LSF) || \
00195    ((Flag) == UART3_FLAG_LHDF) || \
00196    ((Flag) == UART3_FLAG_LBDF))
00197
00198
00199 /**
00200   * @brief  Macro used by the assert_param function in order to check the
00201   *         different sensitivity values for the FLAGs that can be cleared by writing 0
00202   */
00203 #define IS_UART3_CLEAR_FLAG_OK(Flag) \
00204   (((Flag) == UART3_FLAG_RXNE) || \
00205    ((Flag) == UART3_FLAG_LHDF) || \
00206    ((Flag) == UART3_FLAG_LSF) || \
00207    ((Flag) == UART3_FLAG_LBDF))
00208
00209 /**
00210   * @brief  Macro used by the assert_param function in order to check the
00211   *         different sensitivity values for the Interrupts
00212   */
00213
00214 #define IS_UART3_CONFIG_IT_OK(Interrupt) \
00215   (((Interrupt) == UART3_IT_PE) || \
00216    ((Interrupt) == UART3_IT_TXE) || \
00217    ((Interrupt) == UART3_IT_TC) || \
00218    ((Interrupt) == UART3_IT_RXNE_OR ) || \
00219    ((Interrupt) == UART3_IT_IDLE) || \
00220    ((Interrupt) == UART3_IT_LHDF) || \
00221    ((Interrupt) == UART3_IT_LBDF))
00222
00223 /**
00224   * @brief  Macro used by the assert function in order to check the different
00225   *         sensitivity values for the pending bit
00226   */
00227 #define IS_UART3_GET_IT_OK(ITPendingBit) \
00228   (((ITPendingBit) == UART3_IT_TXE)  || \
00229    ((ITPendingBit) == UART3_IT_TC)   || \
00230    ((ITPendingBit) == UART3_IT_RXNE) || \
00231    ((ITPendingBit) == UART3_IT_IDLE) || \
00232    ((ITPendingBit) == UART3_IT_OR)  || \
00233    ((ITPendingBit) == UART3_IT_LBDF)  || \
00234    ((ITPendingBit) == UART3_IT_LHDF)  || \
00235    ((ITPendingBit) == UART3_IT_PE))
00236
00237 /**
00238   * @brief  Macro used by the assert function in order to check the different
00239   *         sensitivity values for the pending bit that can be cleared by writing 0
00240   */
00241 #define IS_UART3_CLEAR_IT_OK(ITPendingBit) \
00242   (((ITPendingBit) == UART3_IT_RXNE) || \
00243    ((ITPendingBit) == UART3_IT_LHDF) || \
00244    ((ITPendingBit) == UART3_IT_LBDF))
00245
00246 /**
00247  * @brief Macro used by the assert_param function in order to check the different
00248  *        sensitivity values for the MODEs
00249  */
00250 #define IS_UART3_MODE_OK(Mode) \
00251   (((Mode) == (uint8_t)UART3_MODE_RX_ENABLE) || \
00252    ((Mode) == (uint8_t)UART3_MODE_RX_DISABLE) || \
00253    ((Mode) == (uint8_t)UART3_MODE_TX_ENABLE) || \
00254    ((Mode) == (uint8_t)UART3_MODE_TX_DISABLE) || \
00255    ((Mode) == (uint8_t)UART3_MODE_TXRX_ENABLE) || \
00256    ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_ENABLE|(uint8_t)UART3_MODE_RX_ENABLE)) || \
00257    ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_ENABLE|(uint8_t)UART3_MODE_RX_DISABLE)) || \
00258    ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_DISABLE|(uint8_t)UART3_MODE_RX_DISABLE)) || \
00259    ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_DISABLE|(uint8_t)UART3_MODE_RX_ENABLE)))
00260
00261 /**
00262  * @brief Macro used by the assert_param function in order to check the different
00263  *        sensitivity values for the WordLengths
00264  */
00265 #define IS_UART3_WORDLENGTH_OK(WordLength) \
00266   (((WordLength) == UART3_WORDLENGTH_8D) || \
00267    ((WordLength) == UART3_WORDLENGTH_9D))
00268
00269
00270 /**
00271   * @brief  Macro used by the assert_param function in order to check the different
00272   *         sensitivity values for the WakeUps
00273   */
00274 #define IS_UART3_WAKEUP_OK(WakeUpMode) \
00275   (((WakeUpMode) == UART3_WAKEUP_IDLELINE) || \
00276    ((WakeUpMode) == UART3_WAKEUP_ADDRESSMARK))
00277
00278 /**
00279   * @brief  Macro used by the assert_param function in order to check the different
00280   *         sensitivity values for the LINBreakDetectionLengths
00281   */
00282 #define IS_UART3_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLengths) \
00283   (((LINBreakDetectionLengths) == UART3_LINBREAKDETECTIONLENGTH_10BITS) || \
00284    ((LINBreakDetectionLengths) == UART3_LINBREAKDETECTIONLENGTH_11BITS))
00285
00286 /**
00287   * @brief  Macro used by the assert_param function in order to check the different
00288   *         sensitivity values for the UART3_StopBits
00289   */
00290 #define IS_UART3_STOPBITS_OK(StopBit) \
00291   (((StopBit) == UART3_STOPBITS_1) || \
00292    ((StopBit) == UART3_STOPBITS_2))
00293
00294 /**
00295  * @brief Macro used by the assert_param function in order to check the different
00296  *        sensitivity values for the Parity
00297  */
00298 #define IS_UART3_PARITY_OK(Parity) \
00299   (((Parity) == UART3_PARITY_NO) || \
00300    ((Parity) == UART3_PARITY_EVEN) || \
00301    ((Parity) == UART3_PARITY_ODD ))
00302
00303 /**
00304  * @brief Macro used by the assert_param function in order to check the maximum
00305  *        baudrate value
00306  */
00307 #define IS_UART3_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)
00308
00309 /**
00310  * @brief Macro used by the assert_param function in order to check the address
00311  *        of the UART3 or UART node
00312  */
00313 #define UART3_ADDRESS_MAX ((uint8_t)16)
00314 #define IS_UART3_ADDRESS_OK(Node) ((Node) < UART3_ADDRESS_MAX)
00315
00316 /**
00317  * @brief Macro used by the assert_param function in order to check the LIN mode
00318  */
00319 #define IS_UART3_SLAVE_OK(Mode) \
00320   (((Mode) == UART3_LIN_MODE_MASTER) || \
00321    ((Mode) == UART3_LIN_MODE_SLAVE))
00322
00323 /**
00324  * @brief Macro used by the assert_param function in order to check the LIN
00325  *        automatic resynchronization mode
00326  */
00327 #define IS_UART3_AUTOSYNC_OK(AutosyncMode) \
00328   (((AutosyncMode) ==  UART3_LIN_AUTOSYNC_ENABLE) || \
00329    ((AutosyncMode) == UART3_LIN_AUTOSYNC_DISABLE))
00330
00331 /**
00332  * @brief Macro used by the assert_param function in order to check the LIN
00333  *        divider update method
00334  */
00335 #define IS_UART3_DIVUP_OK(DivupMethode) \
00336   (((DivupMethode) == UART3_LIN_DIVUP_LBRR1) || \
00337    ((DivupMethode) == UART3_LIN_DIVUP_NEXTRXNE))
00338
00339 /**
00340   * @}
00341   */
00342
00343 /* Exported functions ------------------------------------------------------- */
00344
00345 /** @addtogroup UART3_Exported_Functions
00346   * @{
00347   */
00348
00349 void UART3_DeInit(void);
00350 void UART3_Init(uint32_t BaudRate, UART3_WordLength_TypeDef WordLength,
00351                 UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity,
00352                 UART3_Mode_TypeDef Mode);
00353 void UART3_Cmd(FunctionalState NewState);
00354 void UART3_ITConfig(UART3_IT_TypeDef UART3_IT, FunctionalState NewState);
00355 void UART3_LINBreakDetectionConfig(UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength);
00356 void UART3_LINConfig(UART3_LinMode_TypeDef UART3_Mode,
00357                      UART3_LinAutosync_TypeDef UART3_Autosync,
00358                      UART3_LinDivUp_TypeDef UART3_DivUp);
00359 void UART3_LINCmd(FunctionalState NewState);
00360 void UART3_ReceiverWakeUpCmd(FunctionalState NewState);
00361 void UART3_WakeUpConfig( UART3_WakeUp_TypeDef UART3_WakeUp);
00362 uint8_t UART3_ReceiveData8(void);
00363 uint16_t UART3_ReceiveData9(void);
00364 void UART3_SendData8(uint8_t Data);
00365 void UART3_SendData9(uint16_t Data);
00366 void UART3_SendBreak(void);
00367 void UART3_SetAddress(uint8_t UART3_Address);
00368 FlagStatus UART3_GetFlagStatus(UART3_Flag_TypeDef UART3_FLAG);
00369 void UART3_ClearFlag(UART3_Flag_TypeDef UART3_FLAG);
00370 ITStatus UART3_GetITStatus(UART3_IT_TypeDef UART3_IT);
00371 void UART3_ClearITPendingBit(UART3_IT_TypeDef UART3_IT);
00372 /**
00373   * @}
00374   */
00375
00376 #endif /* __STM8S_UART3_H */
00377
00378 /**
00379   * @}
00380   */
00381
00382 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_wwdg.c Source File

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  • STM8S_StdPeriph_Driver
  • src

stm8s_wwdg.c

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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_wwdg.c
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all the functions for the WWDG peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm8s_wwdg.h"
00024
00025 /** @addtogroup STM8S_StdPeriph_Driver
00026   * @{
00027   */
00028 /* Private define ------------------------------------------------------------*/
00029 #define BIT_MASK          ((uint8_t)0x7F)
00030 /* Private macro -------------------------------------------------------------*/
00031 /* Private variables ---------------------------------------------------------*/
00032 /* Private function prototypes -----------------------------------------------*/
00033 /* Private functions ---------------------------------------------------------*/
00034
00035 /** @addtogroup WWDG_Public_Functions
00036   * @{
00037   */
00038
00039 /**
00040   * @brief  Initializes the WWDG peripheral.
00041   *         This function set Window Register = WindowValue, Counter Register
00042   *         according to Counter and \b ENABLE \b WWDG
00043   * @param  Counter : WWDG counter value
00044   * @param  WindowValue : specifies the WWDG Window Register, range is 0x00 to 0x7F.
00045   * @retval None
00046   */
00047 void WWDG_Init(uint8_t Counter, uint8_t WindowValue)
00048 {
00049     /* Check the parameters */
00050     assert_param(IS_WWDG_WINDOWLIMITVALUE_OK(WindowValue));
00051
00052     WWDG->WR = WWDG_WR_RESET_VALUE;
00053     WWDG->CR = (uint8_t)((uint8_t)(WWDG_CR_WDGA | WWDG_CR_T6) | (uint8_t)Counter);
00054     WWDG->WR = (uint8_t)((uint8_t)(~WWDG_CR_WDGA) & (uint8_t)(WWDG_CR_T6 | WindowValue));
00055 }
00056
00057 /**
00058   * @brief  Refreshes the WWDG peripheral.
00059   * @param  Counter :  WWDG Counter Value
00060   *         This parameter must be a number between 0x40 and 0x7F.
00061   * @retval None
00062   */
00063 void WWDG_SetCounter(uint8_t Counter)
00064 {
00065
00066     /* Check the parameters */
00067     assert_param(IS_WWDG_COUNTERVALUE_OK(Counter));
00068
00069    /* Write to T[6:0] bits to configure the counter value, no need to do
00070      a read-modify-write; writing a 0 to WDGA bit does nothing */
00071   WWDG->CR = (uint8_t)(Counter & (uint8_t)BIT_MASK);
00072
00073 }
00074
00075 /**
00076   * @brief Gets the WWDG Counter Value.
00077   *        This value could be used to check if WWDG is in the window, where
00078   *        refresh is allowed.
00079   * @param  None
00080   * @retval WWDG Counter Value
00081   */
00082 uint8_t WWDG_GetCounter(void)
00083 {
00084     return(WWDG->CR);
00085 }
00086
00087 /**
00088   * @brief  Generates immediate WWDG RESET.
00089   * @param  None
00090   * @retval None
00091   */
00092 void WWDG_SWReset(void)
00093 {
00094     WWDG->CR = WWDG_CR_WDGA; /* Activate WWDG, with clearing T6 */
00095 }
00096
00097 /**
00098   * @brief  Sets the WWDG window value.
00099   * @param  WindowValue: specifies the window value to be compared to the
00100   *         downcounter.
00101   *         This parameter value must be lower than 0x80.
00102   * @retval None
00103   */
00104 void WWDG_SetWindowValue(uint8_t WindowValue)
00105 {
00106     /* Check the parameters */
00107     assert_param(IS_WWDG_WINDOWLIMITVALUE_OK(WindowValue));
00108
00109     WWDG->WR = (uint8_t)((uint8_t)(~WWDG_CR_WDGA) & (uint8_t)(WWDG_CR_T6 | WindowValue));
00110 }
00111 /**
00112   * @}
00113   */
00114
00115 /**
00116   * @}
00117   */
00118
00119 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM8S/A Standard Peripherals Drivers: stm8s_wwdg.h Source File

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stm8s_wwdg.h

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00001 /**
00002   ********************************************************************************
00003   * @file    stm8s_wwdg.h
00004   * @author  MCD Application Team
00005   * @version V2.1.0
00006   * @date    18-November-2011
00007   * @brief   This file contains all functions prototype and macros for the WWDG peripheral.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM8S_WWDG_H
00024 #define __STM8S_WWDG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm8s.h"
00028
00029 /** @addtogroup STM8S_StdPeriph_Driver
00030   * @{
00031   */
00032
00033 /* Private macros ------------------------------------------------------------*/
00034
00035 /** @addtogroup WWDG_Private_Macros
00036   * @{
00037   */
00038
00039 /**
00040   * @brief  Macro used by the assert function in order to check the
00041   * values of the window register.
00042   */
00043 #define IS_WWDG_WINDOWLIMITVALUE_OK(WindowLimitValue) ((WindowLimitValue) <= 0x7F)
00044
00045 /**
00046   * @brief  Macro used by the assert function in order to check the different
00047   * values of the counter register.
00048   */
00049 #define IS_WWDG_COUNTERVALUE_OK(CounterValue) ((CounterValue) <= 0x7F)
00050
00051 /**
00052   * @}
00053   */
00054
00055 /* Exported types ------------------------------------------------------------*/
00056
00057 /* Exported functions ------------------------------------------------------- */
00058
00059 /** @addtogroup WWDG_Exported_Functions
00060   * @{
00061   */
00062
00063 void WWDG_Init(uint8_t Counter, uint8_t WindowValue);
00064 void WWDG_SetCounter(uint8_t Counter);
00065 uint8_t WWDG_GetCounter(void);
00066 void WWDG_SWReset(void);
00067 void WWDG_SetWindowValue(uint8_t WindowValue);
00068
00069
00070 /**
00071   * @}
00072   */
00073
00074 #endif /* __STM8S_WWDG_H */
00075
00076 /**
00077   * @}
00078   */
00079
00080 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/